; -------------------------------------------------------------------------------- ; @Title: S32K38x On-Chip Peripherals ; @Props: Released ; @Author: JDU, KRZ, NEJ ; @Changelog: 2023-04-14 JDU ; 2023-10-19 KRZ ; 2023-11-07 NEJ ; @Manufacturer: NXP - NXP Semiconductors ; @Doc: Generated (TRACE32, build: 164352.), based on: S32K388_M7.svd (Ver. 1.3) ; @Core: Cortex-M7F, Cortex-M0+ ; @Chip: S32K388-M0+-HSE, S32K388-M7, S32K388LS-M0+-HSE, S32K388LS-M7 ; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: pers32k38x.per 16929 2023-11-07 12:03:15Z kwisniewski $ AUTOINDENT.ON CENTER TREE ENUMDELIMITER "," base ad:0x0 sif (CORENAME()=="CORTEXM0+") tree.close "Core Registers (Cortex-M0+)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 0x8 if (CORENAME()=="CORTEXM1") group.long 0x10++0x0b line.long 0x00 "STCSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock" textline " " bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick" bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled" line.long 0x04 "STRVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0" line.long 0x08 "STCVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter" else group.long 0x10++0x0b line.long 0x00 "STCSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock" textline " " bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick" bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled" line.long 0x04 "STRVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0" line.long 0x08 "STCVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter" endif if (CORENAME()=="CORTEXM1") rgroup.long 0x1c++0x03 line.long 0x00 "STCR,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1" bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known" else rgroup.long 0x1c++0x03 line.long 0x00 "STCR,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors" endif rgroup.long 0xd00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code" hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number" textline " " hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family" hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number" group.long 0xd04++0x03 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending" bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending" textline " " bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending" bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending" textline " " bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending" bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service" textline " " bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt" hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field" textline " " hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field" if (CORENAME()=="CORTEXM0+") group.long 0xd08++0x03 line.long 0x00 "VTOR,Vector Table Offset Register" hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address" else textline " " endif group.long 0xd0c++0x03 line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key" bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian" textline " " bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset" bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear" group.long 0xd10++0x03 line.long 0x00 "SCR,System Control Register" bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" textline " " bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" rgroup.long 0xd14++0x03 line.long 0x00 "CCR,Configuration and Control Register" bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned" bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped" group.long 0xd1c++0x0b line.long 0x00 "SHPR2,System Handler Priority Register 2" bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11" line.long 0x04 "SHPR3,System Handler Priority Register 3" bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11" bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11" line.long 0x08 "SHCSR,System Handler Control and State Register" bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending" if (CORENAME()=="CORTEXM0+") hgroup.long 0x08++0x03 hide.long 0x00 "ACTLR,Auxiliary Control Register" else textline " " endif else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit (MPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..." group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller (NVIC)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. tree "Interrupt Enable Registers" group.long 0x100++0x03 line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" tree.end tree "Interrupt Pending Registers" group.long 0x200++0x03 line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" tree.end width 6. tree "Interrupt Priority Registers" group.long 0x400++0x1F line.long 0x00 "INT0,Interrupt Priority Register" bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3" bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3" bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3" bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3" line.long 0x04 "INT1,Interrupt Priority Register" bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3" bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3" bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3" bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3" line.long 0x08 "INT2,Interrupt Priority Register" bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3" bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3" bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3" bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3" line.long 0x0C "INT3,Interrupt Priority Register" bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3" bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3" bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3" bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3" line.long 0x10 "INT4,Interrupt Priority Register" bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3" bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3" bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3" bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3" line.long 0x14 "INT5,Interrupt Priority Register" bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3" bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3" bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3" bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3" line.long 0x18 "INT6,Interrupt Priority Register" bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3" bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3" bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3" bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3" line.long 0x1C "INT7,Interrupt Priority Register" bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3" bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3" bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3" bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 0xA group.long 0xD30++0x03 line.long 0x00 "DFSR,Data Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred" eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred" textline " " eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match" textline " " eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match" eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request" if (CORENAME()=="CORTEXM1") if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00) group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " textline " " textfld " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" else group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif else if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00) group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " textline " " textfld " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" else group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif endif wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Selector Register" bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write" bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..." group.long 0xDF8++0x07 line.long 0x00 "DCRDR,Debug Core Register Data Register" hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor" line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled" bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error" textline " " bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset" width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Breakpoint Unit (BPU)" sif COMPonent.AVAILABLE("BPU") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1)) width 8. group.long 0x00++0x03 line.long 0x00 "BP_CTRL,Breakpoint Control Register" bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. " KEY ,Key field" "No write,Write" bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled" group.long 0x8++0x03 line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled" group.long 0xC++0x03 line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled" group.long 0x10++0x03 line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled" group.long 0x14++0x03 line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled" else newline textline "BPU component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 14. rgroup.long 0x00++0x03 line.long 0x00 "DW_CTRL,DW Control Register " bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x1c++0x03 line.long 0x00 "DW_PCSR,DW Program Counter Sample Register" hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF" group.long 0x20++0x0b line.long 0x00 "DW_COMP0,DW Comparator Register 0" hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address" line.long 0x04 "DW_MASK0,DW Mask Register 0" hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP" line.long 0x08 "DW_FUNCTION0,DW Function Register 0" bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match" bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..." group.long 0x30++0x0b line.long 0x00 "DW_COMP1,DW Comparator Register 1" hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address" line.long 0x04 "DW_MASK1,DW Mask Register 1 " hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP" line.long 0x08 "DW_FUNCTION1,DW Function Register 1" bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match" bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..." else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end endif sif (CORENAME()=="CORTEXM7F") tree.close "Core Registers (Cortex-M7F)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. group.long 0x08++0x03 line.long 0x00 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 28. " DISFPUISSOPT ,DISFPUISSOPT" "No,Yes" bitfld.long 0x00 27. " DISCRITAXIRUW ,Disables critical AXI read-under-write" "No,Yes" bitfld.long 0x00 26. " DISDYNADD ,Disables dynamic allocation of ADD and SUB instructions" "No,Yes" textline " " bitfld.long 0x00 21.--25. " DISISSCH1 ,DISISSCH1" "Normal,Not issued in ch1,,,,,,,,,,,,,,,,,,,,Direct branches,Indirect branches,Loaded to PC,Integer MAC and MUL,VFP,?..." bitfld.long 0x00 16.--20. " DISDI ,DISDI" "Normal,ch1,,,,,,,,,,,,,,,Direct branches,Indirect branches,Loaded to PC,Integer MAC and MUL,VFP,?..." bitfld.long 0x00 15. " DISCRITAXIRUR ,Disables critical AXI read-under-read" "No,Yes" textline " " bitfld.long 0x00 14. " DISBTACALLOC ,DISBTACALLOC" "No,Yes" bitfld.long 0x00 13. " DISBTACREAD ,DISBTACREAD" "No,Yes" bitfld.long 0x00 12. " DISITMATBFLUSH ,Disables ITM and DWT ATB flush" "No,Yes" textline " " bitfld.long 0x00 11. " DISRAMODE ,Disables dynamic read allocate mode for Write-Back Write-Allocate memory regions" "No,Yes" bitfld.long 0x00 10. " FPEXCODIS ,Disables FPU exception outputs" "No,Yes" bitfld.long 0x00 2. " DISFOLD ,Disables dual-issue functionality" "No,Yes" textline "" group.long 0x10++0x03 line.long 0x00 "SYST_CSR,SysTick Control and Status Register" rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted" bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core" bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick" textline " " bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled" group.long 0x14++0x07 line.long 0x00 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x00 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0" line.long 0x04 "SYST_CVR,SysTick Current Value Register" rgroup.long 0x1C++0x03 line.long 0x00 "SYST_CALIB,SysTick Calibration value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing" rgroup.long 0xD00++0x03 line.long 0x00 "CPUID,CPUID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Indicates implementer" bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,Revision 1,?..." bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number" bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "Patch 0,Patch 1,Patch 2,?..." group.long 0xD04++0x23 line.long 0x00 "ICSR,Interrupt Control and State Register" bitfld.long 0x00 31. " NMIPENDSET ,On writes, makes the NMI exception active. On reads, indicates the state of the exception" "Inactive,Active" setclrfld.long 0x00 28. 0x00 28. 0x00 27. " PENDSVSET ,On writes, sets the PendSV exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x00 25. " PENDSTSET ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending" textline " " rbitfld.long 0x00 23. " ISRPREEMPT ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled" rbitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending" hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,The exception number of the highest priority pending and enabled interrupt" textline " " rbitfld.long 0x00 11. " RETTOBASE ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent" hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception" line.long 0x04 "VTOR,Vector Table Offset Register" hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Bits[31:7] of the vector table address" line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT ,Vector Key" rbitfld.long 0x08 15. " ENDIANNESS ,Indicates the memory system endianness" "Little endian,Big endian" bitfld.long 0x08 8.--10. " PRIGROUP ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" textline " " bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested" bitfld.long 0x08 1. " VECTCLRACTIVE ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear" bitfld.long 0x08 0. " VECTRESET ,Writing 1 to this bit causes a local system reset" "No effect,Reset" line.long 0x0C "SCR,System Control Register" bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" line.long 0x10 "CCR,Configuration and Control Register" bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled" bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled" textline " " bitfld.long 0x10 9. " STKALIGN ,Determines whether the exception entry sequence guarantees 8-byte stack frame alignment, adjusting the SP if necessary before saving state" "4-byte/no adjustment,8-byte/adjustment" bitfld.long 0x10 8. " BFHFNMIGN ,Determines the effect of precise data access faults on handlers running at priority -1 or priority -2" "Lockup,Ignored" bitfld.long 0x10 4. " DIV_0_TRP ,Controls the trap on divide by 0" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " UNALIGN_TRP ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled" bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled" bitfld.long 0x10 0. " NONBASETHRDENA ,Controls whether the processor can enter Thread mode at an execution priority level other than base level" "Disabled,Enabled" line.long 0x14 "SHPR1,SSystem Handler Priority Register 1" hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7" hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)" hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)" textline " " hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)" line.long 0x18 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)" hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10" hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9" textline " " hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8" line.long 0x1C "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)" hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)" hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13" textline " " hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)" line.long 0x20 "SHCSR,System Handler Control and State Register" bitfld.long 0x20 18. " USGFAULTENA ,UsageFault" "Disabled,Enabled" bitfld.long 0x20 17. " BUSFAULTENA ,BusFault" "Disabled,Enabled" bitfld.long 0x20 16. " MEMFAULTENA ,MemManage" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " SVCALLPENDED ,SVCall status" "Not pending,Pending" bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault status" "Not pending,Pending" bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage status" "Not pending,Pending" textline " " bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault status" "Not pending,Pending" bitfld.long 0x20 11. " SYSTICKACT ,SysTick status" "Not active,Active" bitfld.long 0x20 10. " PENDSVACT ,PendSV status" "Not active,Active" textline " " bitfld.long 0x20 8. " MONITORACT ,Monitor status" "Not active,Active" bitfld.long 0x20 7. " SVCALLACT ,SVCall status" "Not active,Active" bitfld.long 0x20 3. " USGFAULTACT ,UsageFault status" "Not active,Active" textline " " bitfld.long 0x20 1. " BUSFAULTACT ,BusFault status" "Not active,Active" bitfld.long 0x20 0. " MEMFAULTACT ,MemManage status" "Not active,Active" group.byte 0xD28++0x1 line.byte 0x00 "MMFSR,MemManage Status Register" bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred" bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred" line.byte 0x01 "BFSR,Bus Fault Status Register" bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred" textline " " bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred" bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred" bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred" textline " " bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred" group.word 0xD2A++0x1 line.word 0x00 "USAFAULT,Usage Fault Status Register" bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error" bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error" bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error" textline " " bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error" bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error" bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error" group.long 0xD2C++0x13 line.long 0x00 "HFSR,HardFault Status Register" eventfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred" eventfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority has been escalated to a HardFault exception" "Not occurred,Occurred" eventfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred" line.long 0x04 "DFSR,Debug Fault Status Register" eventfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not occurred,Occurred" eventfld.long 0x04 3. " VCATCH ,Indicates triggering of a Vector catch" "Not occurred,Occurred" eventfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred" textline " " eventfld.long 0x04 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not occurred,Occurred" eventfld.long 0x04 0. " HALTED ,Indicates a debug event generated by a C_HALT or C_STEP request or a step request triggered by setting DEMCR.MON_STEP to 1" "Not occurred,Occurred" line.long 0x08 "MMFAR,MemManage Fault Address Register" line.long 0x0C "BFAR,BusFault Address Register" line.long 0x10 "AFSR,Auxiliary Fault Status Register" group.long 0xD88++0x03 line.long 0x00 "CPACR,Coprocessor Access Control Register" bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Denied,Privileged,,Full" bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Denied,Privileged,,Full" bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Denied,Privileged,,Full" textline " " bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Denied,Privileged,,Full" bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Denied,Privileged,,Full" bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Denied,Privileged,,Full" textline " " bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Denied,Privileged,,Full" bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Denied,Privileged,,Full" bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Denied,Privileged,,Full" textline " " bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Denied,Privileged,,Full" wgroup.long 0xF00++0x03 line.long 0x00 "STIR,Software Triggered Interrupt Register" hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered" tree "Memory System" width 10. rgroup.long 0xD78++0x0B line.long 0x00 "CLIDR,Cache Level ID Register" bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "Level 1,level 2,?..." bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,level 2,?..." bitfld.long 0x00 18.--20. " CL7 ,Cache type field level 7" "No cache,?..." textline " " bitfld.long 0x00 15.--17. " CL6 ,Cache type field level 6" "No cache,?..." bitfld.long 0x00 12.--14. " CL5 ,Cache type field level 5" "No cache,?..." bitfld.long 0x00 9.--11. " CL4 ,Cache type field level 4" "No cache,?..." textline " " bitfld.long 0x00 6.--8. " CL3 ,Cache type field level 3" "No cache,?..." bitfld.long 0x00 3.--5. " CL2 ,Cache type field level 2" "No cache,?..." bitfld.long 0x00 0.--2. " CL1 ,Cache type field level 1" "No cache,Instr. only,Data only,Data and Instr.,?..." line.long 0x04 "CTR,Cache Type Register" bitfld.long 0x04 29.--31. " FORMAT ,Indicates the implemented CTR format" ",,,,ARMv7,?..." bitfld.long 0x04 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x04 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,?..." textline " " bitfld.long 0x04 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "CCSIDR,Cache Size ID Register" bitfld.long 0x08 31. " WT ,Indicates support available for Write-Through" "Not supported,Supported" bitfld.long 0x08 30. " WB ,Indicates support available for Write-Back" "Not supported,Supported" bitfld.long 0x08 29. " RA ,Indicates support available for read allocation" "Not supported,Supported" textline " " bitfld.long 0x08 28. " WA ,Indicates support available for write allocation" "Not supported,Supported" hexmask.long.word 0x08 13.--27. 1. " NUMSETS ,Indicates the number of sets as (number of sets) - 1" hexmask.long.word 0x08 3.--12. 1. " ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1" textline " " bitfld.long 0x08 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512" group.long 0xD84++0x03 line.long 0x00 "CSSELR,Cache Size Selection Register" bitfld.long 0x00 1.--3. " LEVEL ,Identifies which cache level to select" "Level 1,?..." bitfld.long 0x00 0. " IND ,Identifies instruction or data cache to use" "Data,Instruction" wgroup.long 0xF50++0x03 line.long 0x00 "ICIALLU,Instruction cache invalidate all to Point of Unification" wgroup.long 0xF58++0x1F line.long 0x00 "ICIMVAU,Instruction cache invalidate by address to PoU" line.long 0x04 "DCIMVAC,Data cache invalidate by address to Point of Coherency (PoC)" line.long 0x08 "DCISW,Data cache invalidate by set/way" line.long 0x0C "DCCMVAU,Data cache by address to PoU" line.long 0x10 "DCCMVAC,Data cache clean by address to PoC" line.long 0x14 "DCCSW,Data cache clean by set/way" line.long 0x18 "DCCIMVAC,Data cache clean and invalidate by address to PoC" line.long 0x1C "DCCISW,Data cache clean and invalidate by set/way" group.long 0xF90++0x13 line.long 0x00 "ITCMCR,Instruction Tightly-Coupled Memory Control Register" bitfld.long 0x00 3.--6. " SZ ,TCM size" "Not implemented,,,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB" bitfld.long 0x00 2. " RETEN ,Retry phase enable" "Disabled,Enabled" bitfld.long 0x00 1. " RMW ,Read-Modify-Write enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " EN ,TCM enable" "Disabled,Enabled" line.long 0x04 "DTCMCR,Data Tightly-Coupled Memory Control Register" bitfld.long 0x04 3.--6. " SZ ,TCM size" "Not implemented,,,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB" bitfld.long 0x04 2. " RETEN ,Retry phase enable" "Disabled,Enabled" bitfld.long 0x04 1. " RMW ,Read-Modify-Write enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " EN ,TCM enable" "Disabled,Enabled" line.long 0x08 "AHBPCR,AHBP control register" bitfld.long 0x08 1.--3. " SZ ,AHBP size" "AHBP disabled,64 MB,128 MB,256 MB,512 MB,?..." bitfld.long 0x08 0. " EN ,AHBP enable" "Disabled,Enabled" line.long 0x0C "CACR,L1 Cache Control Register" bitfld.long 0x0C 2. " FORCEWT ,Enables Force Write-through in the data cache" "Disabled,Enabled" bitfld.long 0x0C 1. " ECCDIS ,Disables ECC in the instruction and data cache" "No,Yes" bitfld.long 0x0C 0. " SIWT ,Enables limited cache coherency usage" "Disabled,Enabled" line.long 0x10 "AHBSCR,AHB Slave Control Register" bitfld.long 0x10 11.--15. " INITCOUNT ,Fairness counter initialization value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x10 2.--10. 1. " TPRI ,Threshold execution priority for AHBS traffic demotion" bitfld.long 0x10 0.--1. " CTL ,AHBS prioritization control" "AHBS,Software,AHBSCR.INITCOUNT,AHBSPRI" group.long 0xFA8++0x03 line.long 0x00 "ABFSR,Auxiliary Bus Fault Status Register" bitfld.long 0x00 8.--9. " AXIMTYPE ,Indicates the type of fault on the AXIM interface" "OKAY,EXOKAY,SLVERR,DECERR" bitfld.long 0x00 4. " EPPB ,Asynchronous fault on EPPB interface" "Not occurred,Occurred" bitfld.long 0x00 3. " AXIM ,Asynchronous fault on AXIM interface" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " AHBP ,Asynchronous fault on AHBP interface" "Not occurred,Occurred" bitfld.long 0x00 1. " DTCM ,Asynchronous fault on DTCM interface" "Not occurred,Occurred" bitfld.long 0x00 0. " ITCM ,Asynchronous fault on ITCM interface" "Not occurred,Occurred" group.long 0xFB0++0x03 line.long 0x00 "IEBR0,Instruction Error bank Register 0" bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3" bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable" bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data" textline " " hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM" bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked" bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid" group.long 0xFB4++0x03 line.long 0x00 "IEBR1,Instruction Error bank Register 1" bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3" bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable" bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data" textline " " hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM" bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked" bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid" group.long 0xFB8++0x03 line.long 0x00 "DEBR0,Data Error bank Register 0" bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3" bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable" bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data" textline " " hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM" bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked" bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid" group.long 0xFBC++0x03 line.long 0x00 "DEBR1,Data Error bank Register 1" bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3" bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable" bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data" textline " " hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM" bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked" bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid" tree.end tree "Feature Registers" width 10. rgroup.long 0xD40++0x0B line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..." line.long 0x04 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..." line.long 0x08 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..." hgroup.long 0xD4C++0x03 hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long 0xD50++0x03 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..." bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..." textline " " bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored" bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..." hgroup.long 0xD54++0x03 hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" rgroup.long 0xD58++0x03 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..." rgroup.long 0xD60++0x13 line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..." bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..." bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..." textline " " bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..." line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..." bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..." bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..." textline " " bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..." line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..." bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..." bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..." bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..." bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..." textline " " bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..." line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..." bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..." bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..." textline " " bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..." bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..." textline " " bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..." line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..." bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..." textline " " bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..." bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..." bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..." tree.end tree "CoreSight Identification Registers" width 6. rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0C "CID3,Component ID3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit (MPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported" group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8 group.long 0xD9C++0x03 "Region 8" saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 8 (not implemented)" saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9 group.long 0xD9C++0x03 "Region 9" saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 9 (not implemented)" saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA group.long 0xD9C++0x03 "Region 10" saveout 0xD98 %l 0xA line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xA line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 10 (not implemented)" saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB group.long 0xD9C++0x03 "Region 11" saveout 0xD98 %l 0xB line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xB line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 11 (not implemented)" saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC group.long 0xD9C++0x03 "Region 12" saveout 0xD98 %l 0xC line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xC line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 12 (not implemented)" saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD group.long 0xD9C++0x03 "Region 13" saveout 0xD98 %l 0xD line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xD line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 13 (not implemented)" saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE group.long 0xD9C++0x03 "Region 14" saveout 0xD98 %l 0xE line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xE line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 14 (not implemented)" saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF group.long 0xD9C++0x03 "Region 15" saveout 0xD98 %l 0xF line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xF line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 15 (not implemented)" saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" textline " " textline " " endif tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller (NVIC)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 6. rgroup.long 0x04++0x03 line.long 0x00 "ICTR,Interrupt Controller Type Register" bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..." tree "Interrupt Enable Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x100++0x03 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x100++0x7 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x100++0x0B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x100++0x0F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x100++0x13 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x100++0x17 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x100++0x1B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x100++0x1F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x100++0x1F hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" endif tree.end tree "Interrupt Pending Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x200++0x03 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x200++0x07 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x200++0x0B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x200++0x0F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x200++0x13 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x200++0x17 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x200++0x1B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x200++0x1F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x200++0x1F hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" endif tree.end tree "Interrupt Active Bit Registers" width 9. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) rgroup.long 0x300++0x03 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) rgroup.long 0x300++0x07 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) rgroup.long 0x300++0x0B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) rgroup.long 0x300++0x0F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) rgroup.long 0x300++0x13 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) rgroup.long 0x300++0x17 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) rgroup.long 0x300++0x1B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) rgroup.long 0x300++0x1F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" line.long 0x1c "ACTIVE8,Active Bit Register 8" bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x300++0x1F hide.long 0x00 "ACTIVE1,Active Bit Register 1" hide.long 0x04 "ACTIVE2,Active Bit Register 2" hide.long 0x08 "ACTIVE3,Active Bit Register 3" hide.long 0x0c "ACTIVE4,Active Bit Register 4" hide.long 0x10 "ACTIVE5,Active Bit Register 5" hide.long 0x14 "ACTIVE6,Active Bit Register 6" hide.long 0x18 "ACTIVE7,Active Bit Register 7" hide.long 0x1c "ACTIVE8,Active Bit Register 8" endif tree.end tree "Interrupt Priority Registers" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x400++0x1F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x400++0x3F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x400++0x5F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x400++0x7F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x400++0x9F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x400++0xBF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x400++0xDF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x400++0xEF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" line.long 0xE0 "IPR56,Interrupt Priority Register" hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority" hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority" hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority" hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority" line.long 0xE4 "IPR57,Interrupt Priority Register" hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority" hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority" hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority" hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority" line.long 0xE8 "IPR58,Interrupt Priority Register" hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority" hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority" hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority" hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority" line.long 0xEC "IPR59,Interrupt Priority Register" hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority" hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority" hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority" hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority" else hgroup.long 0x400++0xEF hide.long 0x0 "IPR0,Interrupt Priority Register" hide.long 0x4 "IPR1,Interrupt Priority Register" hide.long 0x8 "IPR2,Interrupt Priority Register" hide.long 0xC "IPR3,Interrupt Priority Register" hide.long 0x10 "IPR4,Interrupt Priority Register" hide.long 0x14 "IPR5,Interrupt Priority Register" hide.long 0x18 "IPR6,Interrupt Priority Register" hide.long 0x1C "IPR7,Interrupt Priority Register" hide.long 0x20 "IPR8,Interrupt Priority Register" hide.long 0x24 "IPR9,Interrupt Priority Register" hide.long 0x28 "IPR10,Interrupt Priority Register" hide.long 0x2C "IPR11,Interrupt Priority Register" hide.long 0x30 "IPR12,Interrupt Priority Register" hide.long 0x34 "IPR13,Interrupt Priority Register" hide.long 0x38 "IPR14,Interrupt Priority Register" hide.long 0x3C "IPR15,Interrupt Priority Register" hide.long 0x40 "IPR16,Interrupt Priority Register" hide.long 0x44 "IPR17,Interrupt Priority Register" hide.long 0x48 "IPR18,Interrupt Priority Register" hide.long 0x4C "IPR19,Interrupt Priority Register" hide.long 0x50 "IPR20,Interrupt Priority Register" hide.long 0x54 "IPR21,Interrupt Priority Register" hide.long 0x58 "IPR22,Interrupt Priority Register" hide.long 0x5C "IPR23,Interrupt Priority Register" hide.long 0x60 "IPR24,Interrupt Priority Register" hide.long 0x64 "IPR25,Interrupt Priority Register" hide.long 0x68 "IPR26,Interrupt Priority Register" hide.long 0x6C "IPR27,Interrupt Priority Register" hide.long 0x70 "IPR28,Interrupt Priority Register" hide.long 0x74 "IPR29,Interrupt Priority Register" hide.long 0x78 "IPR30,Interrupt Priority Register" hide.long 0x7C "IPR31,Interrupt Priority Register" hide.long 0x80 "IPR32,Interrupt Priority Register" hide.long 0x84 "IPR33,Interrupt Priority Register" hide.long 0x88 "IPR34,Interrupt Priority Register" hide.long 0x8C "IPR35,Interrupt Priority Register" hide.long 0x90 "IPR36,Interrupt Priority Register" hide.long 0x94 "IPR37,Interrupt Priority Register" hide.long 0x98 "IPR38,Interrupt Priority Register" hide.long 0x9C "IPR39,Interrupt Priority Register" hide.long 0xA0 "IPR40,Interrupt Priority Register" hide.long 0xA4 "IPR41,Interrupt Priority Register" hide.long 0xA8 "IPR42,Interrupt Priority Register" hide.long 0xAC "IPR43,Interrupt Priority Register" hide.long 0xB0 "IPR44,Interrupt Priority Register" hide.long 0xB4 "IPR45,Interrupt Priority Register" hide.long 0xB8 "IPR46,Interrupt Priority Register" hide.long 0xBC "IPR47,Interrupt Priority Register" hide.long 0xC0 "IPR48,Interrupt Priority Register" hide.long 0xC4 "IPR49,Interrupt Priority Register" hide.long 0xC8 "IPR50,Interrupt Priority Register" hide.long 0xCC "IPR51,Interrupt Priority Register" hide.long 0xD0 "IPR52,Interrupt Priority Register" hide.long 0xD4 "IPR53,Interrupt Priority Register" hide.long 0xD8 "IPR54,Interrupt Priority Register" hide.long 0xDC "IPR55,Interrupt Priority Register" hide.long 0xE0 "IPR56,Interrupt Priority Register" hide.long 0xE4 "IPR57,Interrupt Priority Register" hide.long 0xE8 "IPR58,Interrupt Priority Register" hide.long 0xEC "IPR59,Interrupt Priority Register" endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end sif CORENAME()=="CORTEXM7F" tree "Floating-point Unit (FPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 8. group.long 0xF34++0x0B line.long 0x00 "FPCCR,Floating-Point Context Control Register" bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled" bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled" bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able" newline bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able" bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able" bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able" newline bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread" bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged" bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active" line.long 0x04 "FPCAR,Floating-Point Context Address Register" hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame" line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register" bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative" bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation" bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode" newline bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero" rgroup.long 0xF40++0x0B line.long 0x00 "MVFR0,Media and FP Feature Register 0" bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..." bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..." bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..." newline bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..." bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..." bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..." newline bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..." bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..." line.long 0x04 "MVFR1,Media and FP Feature Register 1" bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..." bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..." newline bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..." bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..." line.long 0x08 "MVFR2,Media and FP Feature Register 2" bitfld.long 0x08 4.--7. " VFP_MISC ,Indicates the hardware support for FP miscellaneous features" "Not supported,,,,Supported,?..." width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end endif tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 7. group.long 0xD30++0x03 line.long 0x00 "DFSR,Debug Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated" eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered" eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated" newline eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated" eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated" newline hgroup.long 0xDF0++0x03 hide.long 0x00 "DHCSR,Debug Halting Control and Status Register" in newline wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Register Selector Register" bitfld.long 0x00 16. " REGWNR ,Specifies the access type for the transfer" "Read,Write" hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register, special-purpose register or Floating-point extension register" group.long 0xDF8++0x03 line.long 0x00 "DCRDR,Debug Core Register Data Register" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000) group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" else group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" endif width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Flash Patch and Breakpoint Unit (FPB)" sif COMPonent.AVAILABLE("FPB") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1)) width 10. group.long 0x00++0x03 line.long 0x00 "FP_CTRL,Flash Patch Control Register" bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..." rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127" bitfld.long 0x00 1. " KEY ,Key Field" "Low,High" bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled" newline if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0C "CID3,Component ID3" tree.end else newline textline "FPB component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 15. group.long 0x00++0x1B line.long 0x00 "DWT_CTRL,Control Register" rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported" rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported" newline rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported" rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported" bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled" newline bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled" bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled" newline bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled" bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled" newline bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled" bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]" bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]" newline bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled" line.long 0x04 "DWT_CYCCNT,Cycle Count register" line.long 0x08 "DWT_CPICNT,CPI Count register" hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter" line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register" hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter" line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register" hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter" line.long 0x14 "DWT_LSUCNT,LSU Count Register" hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter" line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count register" hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter" rgroup.long 0x1C++0x03 line.long 0x00 "DWT_PCSR,Program Counter Sample register" newline group.long 0x20++0x07 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" line.long 0x04 "DWT_MASK0,DWT Mask Registers 0" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" else group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x30)++0x07 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" line.long 0x04 "DWT_MASK1,DWT Mask Registers 1" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x40)++0x07 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" line.long 0x04 "DWT_MASK2,DWT Mask Registers 2" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x50)++0x07 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" line.long 0x04 "DWT_MASK3,DWT Mask Registers 3" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0x0B else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end endif tree "ACE" base ad:0x0 tree "ACE__AHB (AHB: ACE SFR memory map)" wgroup.quad 0x0++0xF line.quad 0x0 "INIT_VEC,Initial Value" hexmask.quad 0x0 0.--63. 1. "DATA,Some AES modes require an initialization vector or nonce for CTR mode" line.quad 0x8 "DATA_IN,Data Input" hexmask.quad 0x8 0.--63. 1. "DATA,This field is loaded with 64 bits of data at a time" tree.end tree "ACE__AHB2 (AHB2: ACE SFR memory map)" rgroup.quad 0x100++0x7 line.quad 0x0 "STATUS,Status" bitfld.quad 0x0 25. "KP_CRC_ERR,Key Property CRC Error (Safety error)" "0: Key properties CRC check is successful on..,1: Key properties CRC error on selected key" bitfld.quad 0x0 24. "DMA2_DID_ERR,DMA2 DID error (Safety error)" "0,1" newline bitfld.quad 0x0 23. "DMA1_DID_ERR,DMA1 DID error (Safety error)" "0,1" bitfld.quad 0x0 22. "ECC_ERR,ECC error (Safety error)" "0,1" newline bitfld.quad 0x0 21. "DMA_ERR,DMA error (Functional Error)" "0,1" bitfld.quad 0x0 20. "VERIFY_ERR,Verify error" "0: Verify successful,1: When running a verify command the comparison.." newline bitfld.quad 0x0 19. "KP_ERR,Key property check error (Functional error)" "0: Key property check is successful,1: Key properties are violated. This includes.." bitfld.quad 0x0 18. "KD_ERR,Key digest error (Functional error)" "0: Key digest checks successful or AES has no Key..,1: Key digest checks failed" newline bitfld.quad 0x0 17. "CMP_ERR,Secure comparison error (Safety error)" "0: Secure comparison is successful,1: Secure comparison has failed" bitfld.quad 0x0 16. "K_ERR,AES Internal error (Functional error)" "0: No error,1: AES has reported an internal error" newline bitfld.quad 0x0 2.--4. "ERROR,Error" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 1. "BUSY,Busy" "0: Idle,1: Calculation or key property check is running" group.quad 0x108++0x7 line.quad 0x0 "CONTROL,Control" hexmask.quad.byte 0x0 2.--8. 1. "MASK,Result mask" bitfld.quad 0x0 1. "RESET,Reset" "0,1" newline bitfld.quad 0x0 0. "ENABLE,Enable" "0,1" group.quad 0x118++0xF line.quad 0x0 "RESULT,Result" hexmask.quad 0x0 0.--63. 1. "DATA,Result data" line.quad 0x8 "AUTH_TAG,Auth Tag Output" hexmask.quad 0x8 0.--63. 1. "DATA,Auth tag result data" rgroup.quad 0x128++0x7 line.quad 0x0 "VERSION,ACE Version" bitfld.quad 0x0 16.--17. "MILESTONE,ACE version milestone" "0: Pre-release,1: Bronze,2: Silver,3: Gold" hexmask.quad.byte 0x0 12.--15. 1. "MAJOR_REV,Major revision number" newline hexmask.quad.byte 0x0 8.--11. 1. "MINOR_REV1,Minor revision number 1" hexmask.quad.byte 0x0 4.--7. 1. "MINOR_REV2,Minor revision number 2" newline hexmask.quad.byte 0x0 0.--3. 1. "EXT_REV,Extended revision" tree.end tree.end tree "ADC (Analog-to-Digital Converter)" base ad:0x0 tree "ADC_0" base ad:0x400A0000 group.long 0x0++0x3 line.long 0x0 "MCR,Main Configuration" bitfld.long 0x0 31. "OWREN,Overwrite Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "WLSIDE,Write Left-Aligned" "0: Right aligned,1: Left-aligned" newline bitfld.long 0x0 29. "MODE,Normal Conversion Mode" "0: Single conversion,1: Continuous conversion" bitfld.long 0x0 27. "TRGEN,External Trigger Enable" "0: Normal trigger input does not start a conversion,1: Normal trigger input starts a conversion" newline bitfld.long 0x0 26. "EDGE,External Trigger Edge Selection" "0: Falling edge,1: Rising edge" bitfld.long 0x0 25. "XSTRTEN,Auxiliary External Start Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 24. "NSTART,Start Normal Conversion" "0: No effect,1: Starts conversion" bitfld.long 0x0 22. "JTRGEN,Injection Trigger Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 21. "JEDGE,Injected Trigger Edge Selection" "0: Falling edge,1: Rising edge" bitfld.long 0x0 20. "JSTART,Injected Start" "0: Injected conversion can be started,1: Starts an injected conversion" newline bitfld.long 0x0 17. "BCTUEN,Body Cross Trigger Unit Enable" "0: Disable,1: Enable" bitfld.long 0x0 16. "BCTU_MODE,Body Cross Trigger Unit Mode Select" "0: Only BCTU can trigger conversion,1: All trigger sources can trigger conversion" newline eventfld.long 0x0 15. "STCL,Self-Test Configuration Lock" "0: Registers are writeable,1: Registers are read-only" bitfld.long 0x0 11. "AVGEN,Averaging Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 9.--10. "AVGS,Averaging Select" "0: 4 conversions,1: 8 conversions,2: 16 conversions,3: 32 conversions" eventfld.long 0x0 7. "ABORTCHAIN,Abort Chain" "0: Undefined,1: Conversion aborted" newline eventfld.long 0x0 6. "ABORT,Abort Conversion" "0: Undefined,1: Conversion aborted" bitfld.long 0x0 5. "ACKO,Auto Clock Off" "0: Clock always active,1: Clock gated" newline bitfld.long 0x0 1.--2. "ADCLKSEL,Conversion Clock (AD_clk) Frequency Selection" "0: Module clock frequency,1: Module clock frequency / 2,2: Module clock frequency / 4,3: Module clock frequency / 8" bitfld.long 0x0 0. "PWDN,Power Down" "0: ADC enters a functional state,1: ADC enters Power Down state" rgroup.long 0x4++0x3 line.long 0x0 "MSR,Main Status" bitfld.long 0x0 31. "CALIBRTD,Calibration Status" "0: Uncalibrated or calibration unsuccessful,1: Calibrated" bitfld.long 0x0 24. "NSTART,Normal Conversion Started" "0: Not in progress,1: In progress" newline bitfld.long 0x0 23. "JABORT,Injected Conversion Aborted" "0: Not aborted,1: Aborted" bitfld.long 0x0 20. "JSTART,Injected Conversion Started" "0: Not an injected conversion,1: Injected conversion" newline bitfld.long 0x0 18. "SELF_TEST_S,Indicates whether an ongoing conversion is for self-test." "0: Not self-test,1: Self-test" bitfld.long 0x0 16. "BCTUSTART,BCTU Conversion Started" "0: Conversion was not triggered by BCTU,1: Ongoing conversion was triggered by BCTU" newline hexmask.long.byte 0x0 9.--15. 1. "CHADDR,Input Under Measure" bitfld.long 0x0 5. "ACKO,Auto Clock-Off On" "0: Inactive,1: Active" newline bitfld.long 0x0 0.--2. "ADCSTATUS,ADC State" "0: Idle,1: Power Down,2: Wait,3: Calibrate,4: Convert,?,6: Done,?" group.long 0x10++0x27 line.long 0x0 "ISR,Interrupt Status" eventfld.long 0x0 4. "EOBCTU,End Of BCTU Conversion" "0: No EOBCTU interrupt generated,1: EOBCTU interrupt generated" eventfld.long 0x0 3. "JEOC,End Of Injected Conversion" "0: No JEOC interrupt generated,1: JEOC interrupt generated" newline eventfld.long 0x0 2. "JECH,End Of Injected Chain Conversion" "0: No JECH interrupt generated,1: JECH interrupt generated" eventfld.long 0x0 1. "EOC,End Of Conversion" "0: No EOC interrupt generated,1: Interrupt generated" newline eventfld.long 0x0 0. "ECH,End Of Chain Conversion" "0: Indicates no ECH interrupt generated,1: Indicates an ECH interrupt has been generated" line.long 0x4 "CEOCFR0,Channel End Of Conversion Flag For Precision Inputs" eventfld.long 0x4 7. "PIEOCF7,Precision Input End Of Conversion Flag 7" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x4 6. "PIEOCF6,Precision Input End Of Conversion Flag 6" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x4 5. "PIEOCF5,Precision Input End Of Conversion Flag 5" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x4 4. "PIEOCF4,Precision Input End Of Conversion Flag 4" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x4 3. "PIEOCF3,Precision Input End Of Conversion Flag 3" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x4 2. "PIEOCF2,Precision Input End Of Conversion Flag 2" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x4 1. "PIEOCF1,Precision Input End Of Conversion Flag 1" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x4 0. "PIEOCF0,Precision Input End Of Conversion Flag 0" "0: Conversion not complete,1: Conversion complete" line.long 0x8 "CEOCFR1,Channel End Of Conversion Flag For Standard Inputs" eventfld.long 0x8 23. "SIEOCF23,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 22. "SIEOCF22,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 21. "SIEOCF21,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 20. "SIEOCF20,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 19. "SIEOCF19,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 18. "SIEOCF18,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 17. "SIEOCF17,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 16. "SIEOCF16,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 15. "SIEOCF15,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 14. "SIEOCF14,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 13. "SIEOCF13,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 12. "SIEOCF12,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 11. "SIEOCF11,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 10. "SIEOCF10,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 9. "SIEOCF9,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 8. "SIEOCF8,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 7. "SIEOCF7,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 6. "SIEOCF6,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 5. "SIEOCF5,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 4. "SIEOCF4,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 3. "SIEOCF3,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 2. "SIEOCF2,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 1. "SIEOCF1,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 0. "SIEOCF0,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" line.long 0xC "CEOCFR2,Channel End Of Conversion Flag For External Inputs" eventfld.long 0xC 31. "EIEOCF31,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0xC 30. "EIEOCF30,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0xC 29. "EIEOCF29,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0xC 28. "EIEOCF28,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0xC 27. "EIEOCF27,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0xC 26. "EIEOCF26,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0xC 25. "EIEOCF25,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0xC 24. "EIEOCF24,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0xC 23. "EIEOCF23,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0xC 22. "EIEOCF22,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0xC 21. "EIEOCF21,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0xC 20. "EIEOCF20,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0xC 19. "EIEOCF19,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0xC 18. "EIEOCF18,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0xC 17. "EIEOCF17,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0xC 16. "EIEOCF16,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0xC 15. "EIEOCF15,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0xC 14. "EIEOCF14,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0xC 13. "EIEOCF13,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0xC 12. "EIEOCF12,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0xC 11. "EIEOCF11,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0xC 10. "EIEOCF10,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0xC 9. "EIEOCF9,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0xC 8. "EIEOCF8,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0xC 7. "EIEOCF7,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0xC 6. "EIEOCF6,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0xC 5. "EIEOCF5,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0xC 4. "EIEOCF4,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0xC 3. "EIEOCF3,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0xC 2. "EIEOCF2,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0xC 1. "EIEOCF1,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0xC 0. "EIEOCF0,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" line.long 0x10 "IMR,Interrupt Mask" bitfld.long 0x10 4. "MSKEOBCTU,EOBCTU Interrupt Flag Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x10 3. "MSKJEOC,JEOC Interrupt Flag Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x10 2. "MSKJECH,JECH Interrupt Flag Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x10 1. "MSKEOC,EOC Interrupt Flag Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x10 0. "MSKECH,ECH Interrupt Flag Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" line.long 0x14 "CIMR0,EOC Interrupt Enable For Precision Inputs" bitfld.long 0x14 7. "PIEOCIEN7,Precision Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x14 6. "PIEOCIEN6,Precision Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x14 5. "PIEOCIEN5,Precision Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x14 4. "PIEOCIEN4,Precision Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x14 3. "PIEOCIEN3,Precision Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x14 2. "PIEOCIEN2,Precision Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x14 1. "PIEOCIEN1,Precision Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x14 0. "PIEOCIEN0,Precision Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" line.long 0x18 "CIMR1,EOC Interrupt Enable For Standard Inputs" bitfld.long 0x18 23. "SIEOCIEN23,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x18 22. "SIEOCIEN22,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x18 21. "SIEOCIEN21,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x18 20. "SIEOCIEN20,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x18 19. "SIEOCIEN19,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x18 18. "SIEOCIEN18,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x18 17. "SIEOCIEN17,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x18 16. "SIEOCIEN16,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x18 15. "SIEOCIEN15,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x18 14. "SIEOCIEN14,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x18 13. "SIEOCIEN13,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x18 12. "SIEOCIEN12,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x18 11. "SIEOCIEN11,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x18 10. "SIEOCIEN10,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x18 9. "SIEOCIEN9,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x18 8. "SIEOCIEN8,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x18 7. "SIEOCIEN7,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x18 6. "SIEOCIEN6,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x18 5. "SIEOCIEN5,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x18 4. "SIEOCIEN4,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x18 3. "SIEOCIEN3,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x18 2. "SIEOCIEN2,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x18 1. "SIEOCIEN1,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x18 0. "SIEOCIEN0,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" line.long 0x1C "CIMR2,EOC Interrupt Enable For External Inputs" bitfld.long 0x1C 31. "EIEOCIEN31,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x1C 30. "EIEOCIEN30,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x1C 29. "EIEOCIEN29,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x1C 28. "EIEOCIEN28,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x1C 27. "EIEOCIEN27,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x1C 26. "EIEOCIEN26,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x1C 25. "EIEOCIEN25,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x1C 24. "EIEOCIEN24,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x1C 23. "EIEOCIEN23,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x1C 22. "EIEOCIEN22,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x1C 21. "EIEOCIEN21,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x1C 20. "EIEOCIEN20,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x1C 19. "EIEOCIEN19,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x1C 18. "EIEOCIEN18,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x1C 17. "EIEOCIEN17,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x1C 16. "EIEOCIEN16,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x1C 15. "EIEOCIEN15,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x1C 14. "EIEOCIEN14,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x1C 13. "EIEOCIEN13,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x1C 12. "EIEOCIEN12,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x1C 11. "EIEOCIEN11,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x1C 10. "EIEOCIEN10,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x1C 9. "EIEOCIEN9,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x1C 8. "EIEOCIEN8,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x1C 7. "EIEOCIEN7,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x1C 6. "EIEOCIEN6,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x1C 5. "EIEOCIEN5,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x1C 4. "EIEOCIEN4,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x1C 3. "EIEOCIEN3,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x1C 2. "EIEOCIEN2,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x1C 1. "EIEOCIEN1,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x1C 0. "EIEOCIEN0,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" line.long 0x20 "WTISR,Analog Watchdog Threshold Interrupt Status" eventfld.long 0x20 31. "HAWIF16,High Analog Watchdog Interrupt Flag 16" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x20 30. "LAWIF16,Low Analog Watchdog Interrupt Flag 16" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x20 29. "HAWIF15,High Analog Watchdog Interrupt Flag 15" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x20 28. "LAWIF15,Low Analog Watchdog Interrupt Flag 15" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x20 27. "HAWIF14,High Analog Watchdog Interrupt Flag 14" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x20 26. "LAWIF14,Low Analog Watchdog Interrupt Flag 14" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x20 25. "HAWIF13,High Analog Watchdog Interrupt Flag 13" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x20 24. "LAWIF13,Low Analog Watchdog Interrupt Flag 13" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x20 23. "HAWIF12,High Analog Watchdog Interrupt Flag 12" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x20 22. "LAWIF12,Low Analog Watchdog Interrupt Flag 12" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x20 21. "HAWIF11,High Analog Watchdog Interrupt Flag 11" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x20 20. "LAWIF11,Low Analog Watchdog Interrupt Flag 11" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x20 19. "HAWIF10,High Analog Watchdog Interrupt Flag 10" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x20 18. "LAWIF10,Low Analog Watchdog Interrupt Flag 10" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x20 17. "HAWIF9,High Analog Watchdog Interrupt Flag 9" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x20 16. "LAWIF9,Low Analog Watchdog Interrupt Flag 9" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x20 15. "HAWIF8,High Analog Watchdog Interrupt Flag 8" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x20 14. "LAWIF8,Low Analog Watchdog Interrupt Flag 8" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x20 13. "HAWIF7,High Analog Watchdog Interrupt Flag 7" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x20 12. "LAWIF7,Low Analog Watchdog Interrupt Flag 7" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x20 11. "HAWIF6,High Analog Watchdog Interrupt Flag 6" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x20 10. "LAWIF6,Low Analog Watchdog Interrupt Flag 6" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x20 9. "HAWIF5,High Analog Watchdog Interrupt Flag 5" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x20 8. "LAWIF5,Low Analog Watchdog Interrupt Flag 5" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x20 7. "HAWIF4,High Analog Watchdog Interrupt Flag 4" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x20 6. "LAWIF4,Low Analog Watchdog Interrupt Flag 4" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x20 5. "HAWIF3,High Analog Watchdog Interrupt Flag 3" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x20 4. "LAWIF3,Low Analog Watchdog Interrupt Flag 3" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x20 3. "HAWIF2,High Analog Watchdog Interrupt Flag 2" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x20 2. "LAWIF2,Low Analog Watchdog Interrupt Flag 2" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x20 1. "HAWIF1,High Analog Watchdog Interrupt Flag 1" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x20 0. "LAWIF1,Low Analog Watchdog Interrupt Flag 1" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." line.long 0x24 "WTIMR,Analog Watchdog Threshold Interrupt Enable" bitfld.long 0x24 7. "HDWIFEN4,High Data Watchdog Interrupt Flag Enable n" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x24 6. "LAWIFEN4,Low Analog Watchdog Interrupt Flag Enable n" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x24 5. "HDWIFEN3,High Data Watchdog Interrupt Flag Enable n" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x24 4. "LAWIFEN3,Low Analog Watchdog Interrupt Flag Enable n" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x24 3. "HDWIFEN2,High Data Watchdog Interrupt Flag Enable n" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x24 2. "LAWIFEN2,Low Analog Watchdog Interrupt Flag Enable n" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x24 1. "HDWIFEN1,High Data Watchdog Interrupt Flag Enable n" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x24 0. "LAWIFEN1,Low Analog Watchdog Interrupt Flag Enable n" "0: Interrupt is not flagged,1: Interrupt is flagged" group.long 0x40++0xF line.long 0x0 "DMAE,Direct Memory Access Configuration" bitfld.long 0x0 1. "DCLR,DMA Clear Request" "0: DMA controller acknowledges the request,1: Conversion data register is read" bitfld.long 0x0 0. "DMAEN,DMA Enable" "0: Disable,1: Enable" line.long 0x4 "DMAR0,DMA Request Enable For Precision Inputs" bitfld.long 0x4 7. "PIDMAREN7,Precision Input DMA Request Enable 7" "0: Not triggered,1: Triggered" bitfld.long 0x4 6. "PIDMAREN6,Precision Input DMA Request Enable 6" "0: Not triggered,1: Triggered" newline bitfld.long 0x4 5. "PIDMAREN5,Precision Input DMA Request Enable 5" "0: Not triggered,1: Triggered" bitfld.long 0x4 4. "PIDMAREN4,Precision Input DMA Request Enable 4" "0: Not triggered,1: Triggered" newline bitfld.long 0x4 3. "PIDMAREN3,Precision Input DMA Request Enable 3" "0: Not triggered,1: Triggered" bitfld.long 0x4 2. "PIDMAREN2,Precision Input DMA Request Enable 2" "0: Not triggered,1: Triggered" newline bitfld.long 0x4 1. "PIDMAREN1,Precision Input DMA Request Enable 1" "0: Not triggered,1: Triggered" bitfld.long 0x4 0. "PIDMAREN0,Precision Input DMA Request Enable 0" "0: Not triggered,1: Triggered" line.long 0x8 "DMAR1,DMA Request Enable For Standard Inputs" bitfld.long 0x8 23. "SIDMAREN23,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" bitfld.long 0x8 22. "SIDMAREN22,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" newline bitfld.long 0x8 21. "SIDMAREN21,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" bitfld.long 0x8 20. "SIDMAREN20,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" newline bitfld.long 0x8 19. "SIDMAREN19,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" bitfld.long 0x8 18. "SIDMAREN18,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" newline bitfld.long 0x8 17. "SIDMAREN17,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" bitfld.long 0x8 16. "SIDMAREN16,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" newline bitfld.long 0x8 15. "SIDMAREN15,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" bitfld.long 0x8 14. "SIDMAREN14,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" newline bitfld.long 0x8 13. "SIDMAREN13,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" bitfld.long 0x8 12. "SIDMAREN12,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" newline bitfld.long 0x8 11. "SIDMAREN11,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" bitfld.long 0x8 10. "SIDMAREN10,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" newline bitfld.long 0x8 9. "SIDMAREN9,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" bitfld.long 0x8 8. "SIDMAREN8,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" newline bitfld.long 0x8 7. "SIDMAREN7,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" bitfld.long 0x8 6. "SIDMAREN6,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" newline bitfld.long 0x8 5. "SIDMAREN5,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" bitfld.long 0x8 4. "SIDMAREN4,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" newline bitfld.long 0x8 3. "SIDMAREN3,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" bitfld.long 0x8 2. "SIDMAREN2,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" newline bitfld.long 0x8 1. "SIDMAREN1,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" bitfld.long 0x8 0. "SIDMAREN0,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" line.long 0xC "DMAR2,DMA Request Enable For External Inputs" bitfld.long 0xC 31. "EIDMAREN31,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" bitfld.long 0xC 30. "EIDMAREN30,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" newline bitfld.long 0xC 29. "EIDMAREN29,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" bitfld.long 0xC 28. "EIDMAREN28,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" newline bitfld.long 0xC 27. "EIDMAREN27,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" bitfld.long 0xC 26. "EIDMAREN26,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" newline bitfld.long 0xC 25. "EIDMAREN25,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" bitfld.long 0xC 24. "EIDMAREN24,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" newline bitfld.long 0xC 23. "EIDMAREN23,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" bitfld.long 0xC 22. "EIDMAREN22,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" newline bitfld.long 0xC 21. "EIDMAREN21,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" bitfld.long 0xC 20. "EIDMAREN20,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" newline bitfld.long 0xC 19. "EIDMAREN19,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" bitfld.long 0xC 18. "EIDMAREN18,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" newline bitfld.long 0xC 17. "EIDMAREN17,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" bitfld.long 0xC 16. "EIDMAREN16,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" newline bitfld.long 0xC 15. "EIDMAREN15,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" bitfld.long 0xC 14. "EIDMAREN14,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" newline bitfld.long 0xC 13. "EIDMAREN13,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" bitfld.long 0xC 12. "EIDMAREN12,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" newline bitfld.long 0xC 11. "EIDMAREN11,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" bitfld.long 0xC 10. "EIDMAREN10,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" newline bitfld.long 0xC 9. "EIDMAREN9,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" bitfld.long 0xC 8. "EIDMAREN8,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" newline bitfld.long 0xC 7. "EIDMAREN7,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" bitfld.long 0xC 6. "EIDMAREN6,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" newline bitfld.long 0xC 5. "EIDMAREN5,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" bitfld.long 0xC 4. "EIDMAREN4,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" newline bitfld.long 0xC 3. "EIDMAREN3,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" bitfld.long 0xC 2. "EIDMAREN2,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" newline bitfld.long 0xC 1. "EIDMAREN1,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" bitfld.long 0xC 0. "EIDMAREN0,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x60)++0x3 line.long 0x0 "THRHLR[$1],Analog Watchdog Threshold Values" hexmask.long.word 0x0 16.--30. 1. "THRH,High Threshold Value" hexmask.long.word 0x0 0.--14. 1. "THRL,Low Threshold Value" repeat.end group.long 0x80++0xF line.long 0x0 "PSCR,Presampling Control" bitfld.long 0x0 5. "PREVAL2,Presampling Voltage Select For External Inputs" "0: VREFL,1: VREFH" bitfld.long 0x0 3. "PREVAL1,Presampling Voltage Select For Standard Inputs" "0: VREFL,1: VREFH" newline bitfld.long 0x0 1. "PREVAL0,Presampling Voltage Select For Precision Inputs" "0: VREFL,1: VREFH" bitfld.long 0x0 0. "PRECONV,Convert Presampled Value" "0: No conversion after presampling,1: Presampling is followed by conversion" line.long 0x4 "PSR0,Presampling Enable For Precision Inputs" bitfld.long 0x4 7. "PRES7,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x4 6. "PRES6,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x4 5. "PRES5,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x4 4. "PRES4,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x4 3. "PRES3,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x4 2. "PRES2,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x4 1. "PRES1,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x4 0. "PRES0,Presampling Enable n" "0: Disable,1: Enable" line.long 0x8 "PSR1,Presampling Enable For Standard Inputs" bitfld.long 0x8 23. "PRES23,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x8 22. "PRES22,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x8 21. "PRES21,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x8 20. "PRES20,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x8 19. "PRES19,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x8 18. "PRES18,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x8 17. "PRES17,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x8 16. "PRES16,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x8 15. "PRES15,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x8 14. "PRES14,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x8 13. "PRES13,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x8 12. "PRES12,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x8 11. "PRES11,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x8 10. "PRES10,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x8 9. "PRES9,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x8 8. "PRES8,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x8 7. "PRES7,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x8 6. "PRES6,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x8 5. "PRES5,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x8 4. "PRES4,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x8 3. "PRES3,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x8 2. "PRES2,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x8 1. "PRES1,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x8 0. "PRES0,Presampling Enable n" "0: Disable,1: Enable" line.long 0xC "PSR2,Presampling Enable For External Inputs" bitfld.long 0xC 31. "PRES31,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0xC 30. "PRES30,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0xC 29. "PRES29,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0xC 28. "PRES28,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0xC 27. "PRES27,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0xC 26. "PRES26,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0xC 25. "PRES25,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0xC 24. "PRES24,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0xC 23. "PRES23,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0xC 22. "PRES22,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0xC 21. "PRES21,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0xC 20. "PRES20,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0xC 19. "PRES19,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0xC 18. "PRES18,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0xC 17. "PRES17,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0xC 16. "PRES16,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0xC 15. "PRES15,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0xC 14. "PRES14,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0xC 13. "PRES13,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0xC 12. "PRES12,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0xC 11. "PRES11,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0xC 10. "PRES10,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0xC 9. "PRES9,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0xC 8. "PRES8,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0xC 7. "PRES7,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0xC 6. "PRES6,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0xC 5. "PRES5,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0xC 4. "PRES4,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0xC 3. "PRES3,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0xC 2. "PRES2,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0xC 1. "PRES1,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0xC 0. "PRES0,Presampling Enable n" "0: Disable,1: Enable" group.long 0x94++0xB line.long 0x0 "CTR0,Conversion Timing For Precision Inputs" hexmask.long.byte 0x0 0.--7. 1. "INPSAMP,Input Sample Cycles" line.long 0x4 "CTR1,Conversion Timing For Standard Inputs" hexmask.long.byte 0x4 1.--7. 1. "INPSAMP,Specifies the sample duration in terms of conversion clock cycles" bitfld.long 0x4 0. "TSENSOR_SEL,Temperature Sensor Voltage Select" "0: Selects temperature sensor source 0,1: Selects temperature sensor source 1" line.long 0x8 "CTR2,Conversion Timing For External Inputs" hexmask.long.byte 0x8 0.--7. 1. "INPSAMP,Input Sample Cycles" group.long 0xA4++0xB line.long 0x0 "NCMR0,Normal Conversion Enable For Precision Inputs" bitfld.long 0x0 7. "CH7,Precision Input To Be Converted" "0: Input is not selected,1: Input is selected" bitfld.long 0x0 6. "CH6,Precision Input To Be Converted" "0: Input is not selected,1: Input is selected" newline bitfld.long 0x0 5. "CH5,Precision Input To Be Converted" "0: Input is not selected,1: Input is selected" bitfld.long 0x0 4. "CH4,Precision Input To Be Converted" "0: Input is not selected,1: Input is selected" newline bitfld.long 0x0 3. "CH3,Precision Input To Be Converted" "0: Input is not selected,1: Input is selected" bitfld.long 0x0 2. "CH2,Precision Input To Be Converted" "0: Input is not selected,1: Input is selected" newline bitfld.long 0x0 1. "CH1,Precision Input To Be Converted" "0: Input is not selected,1: Input is selected" bitfld.long 0x0 0. "CH0,Precision Input To Be Converted" "0: Input is not selected,1: Input is selected" line.long 0x4 "NCMR1,Normal Conversion Enable For Standard Inputs" bitfld.long 0x4 23. "CH55,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 22. "CH54,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 21. "CH53,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 20. "CH52,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 19. "CH51,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 18. "CH50,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 17. "CH49,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 16. "CH48,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 15. "CH47,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 14. "CH46,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 13. "CH45,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 12. "CH44,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 11. "CH43,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 10. "CH42,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 9. "CH41,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 8. "CH40,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 7. "CH39,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 6. "CH38,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 5. "CH37,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 4. "CH36,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 3. "CH35,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 2. "CH34,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 1. "CH33,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 0. "CH32,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" line.long 0x8 "NCMR2,Normal Conversion Enable For External Inputs" bitfld.long 0x8 31. "CH95,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 30. "CH94,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 29. "CH93,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 28. "CH92,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 27. "CH91,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 26. "CH90,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 25. "CH89,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 24. "CH88,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 23. "CH87,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 22. "CH86,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 21. "CH85,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 20. "CH84,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 19. "CH83,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 18. "CH82,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 17. "CH81,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 16. "CH80,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 15. "CH79,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 14. "CH78,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 13. "CH77,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 12. "CH76,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 11. "CH75,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 10. "CH74,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 9. "CH73,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 8. "CH72,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 7. "CH71,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 6. "CH70,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 5. "CH69,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 4. "CH68,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 3. "CH67,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 2. "CH66,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 1. "CH65,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 0. "CH64,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" group.long 0xB4++0xB line.long 0x0 "JCMR0,Injected Conversion Enable For Precision Inputs" bitfld.long 0x0 7. "CH7,Precision Input To Be Converted" "0: Input 7 is not selected,1: Input 7 is selected" bitfld.long 0x0 6. "CH6,Precision Input To Be Converted" "0: Input 6 is not selected,1: Input 6 is selected" newline bitfld.long 0x0 5. "CH5,Precision Input To Be Converted" "0: Input 5 is not selected,1: Input 5 is selected" bitfld.long 0x0 4. "CH4,Precision Input To Be Converted" "0: Input 4 is not selected,1: Input 4 is selected" newline bitfld.long 0x0 3. "CH3,Precision Input To Be Converted" "0: Input 3 is not selected,1: Input 3 is selected" bitfld.long 0x0 2. "CH2,Precision Input To Be Converted" "0: Input 2 is not selected,1: Input 2 is selected" newline bitfld.long 0x0 1. "CH1,Precision Input To Be Converted" "0: Input 1 is not selected,1: Input 1 is selected" bitfld.long 0x0 0. "CH0,Precision Input To Be Converted" "0: Input 0 is not selected,1: Input 0 is selected" line.long 0x4 "JCMR1,Injected Conversion Enable For Standard Inputs" bitfld.long 0x4 23. "CH55,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 22. "CH54,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 21. "CH53,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 20. "CH52,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 19. "CH51,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 18. "CH50,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 17. "CH49,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 16. "CH48,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 15. "CH47,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 14. "CH46,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 13. "CH45,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 12. "CH44,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 11. "CH43,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 10. "CH42,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 9. "CH41,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 8. "CH40,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 7. "CH39,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 6. "CH38,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 5. "CH37,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 4. "CH36,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 3. "CH35,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 2. "CH34,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 1. "CH33,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 0. "CH32,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" line.long 0x8 "JCMR2,Injected Conversion Enable For External Inputs" bitfld.long 0x8 31. "CH95,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 30. "CH94,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 29. "CH93,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 28. "CH92,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 27. "CH91,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 26. "CH90,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 25. "CH89,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 24. "CH88,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 23. "CH87,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 22. "CH86,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 21. "CH85,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 20. "CH84,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 19. "CH83,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 18. "CH82,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 17. "CH81,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 16. "CH80,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 15. "CH79,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 14. "CH78,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 13. "CH77,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 12. "CH76,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 11. "CH75,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 10. "CH74,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 9. "CH73,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 8. "CH72,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 7. "CH71,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 6. "CH70,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 5. "CH69,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 4. "CH68,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 3. "CH67,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 2. "CH66,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 1. "CH65,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 0. "CH64,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" group.long 0xC4++0x7 line.long 0x0 "DSDR,Delay Start Of Data Conversion" hexmask.long.word 0x0 0.--15. 1. "DSD,Delay" line.long 0x4 "PDEDR,Power Down Exit Delay" hexmask.long.byte 0x4 0.--7. 1. "PDED,Delay" rgroup.long 0x100++0x1F line.long 0x0 "PCDR0,Precision Input n Conversion Data" bitfld.long 0x0 19. "VALID,Conversion Data Available" "0: No unread conversion data,1: Unread conversion data is available" bitfld.long 0x0 18. "OVERW,Overwrite Status Flag" "0: No unread data is overwritten,1: Unread data is overwritten" newline bitfld.long 0x0 16.--17. "RESULT,Conversion Data Type" "0: Normal trigger,1: Injected trigger,2: BCTU trigger,?" hexmask.long.word 0x0 0.--15. 1. "CDATA,Conversion Data" line.long 0x4 "PCDR1,Precision Input n Conversion Data" bitfld.long 0x4 19. "VALID,Conversion Data Available" "0: No unread conversion data,1: Unread conversion data is available" bitfld.long 0x4 18. "OVERW,Overwrite Status Flag" "0: No unread data is overwritten,1: Unread data is overwritten" newline bitfld.long 0x4 16.--17. "RESULT,Conversion Data Type" "0: Normal trigger,1: Injected trigger,2: BCTU trigger,?" hexmask.long.word 0x4 0.--15. 1. "CDATA,Conversion Data" line.long 0x8 "PCDR2,Precision Input n Conversion Data" bitfld.long 0x8 19. "VALID,Conversion Data Available" "0: No unread conversion data,1: Unread conversion data is available" bitfld.long 0x8 18. "OVERW,Overwrite Status Flag" "0: No unread data is overwritten,1: Unread data is overwritten" newline bitfld.long 0x8 16.--17. "RESULT,Conversion Data Type" "0: Normal trigger,1: Injected trigger,2: BCTU trigger,?" hexmask.long.word 0x8 0.--15. 1. "CDATA,Conversion Data" line.long 0xC "PCDR3,Precision Input n Conversion Data" bitfld.long 0xC 19. "VALID,Conversion Data Available" "0: No unread conversion data,1: Unread conversion data is available" bitfld.long 0xC 18. "OVERW,Overwrite Status Flag" "0: No unread data is overwritten,1: Unread data is overwritten" newline bitfld.long 0xC 16.--17. "RESULT,Conversion Data Type" "0: Normal trigger,1: Injected trigger,2: BCTU trigger,?" hexmask.long.word 0xC 0.--15. 1. "CDATA,Conversion Data" line.long 0x10 "PCDR4,Precision Input n Conversion Data" bitfld.long 0x10 19. "VALID,Conversion Data Available" "0: No unread conversion data,1: Unread conversion data is available" bitfld.long 0x10 18. "OVERW,Overwrite Status Flag" "0: No unread data is overwritten,1: Unread data is overwritten" newline bitfld.long 0x10 16.--17. "RESULT,Conversion Data Type" "0: Normal trigger,1: Injected trigger,2: BCTU trigger,?" hexmask.long.word 0x10 0.--15. 1. "CDATA,Conversion Data" line.long 0x14 "PCDR5,Precision Input n Conversion Data" bitfld.long 0x14 19. "VALID,Conversion Data Available" "0: No unread conversion data,1: Unread conversion data is available" bitfld.long 0x14 18. "OVERW,Overwrite Status Flag" "0: No unread data is overwritten,1: Unread data is overwritten" newline bitfld.long 0x14 16.--17. "RESULT,Conversion Data Type" "0: Normal trigger,1: Injected trigger,2: BCTU trigger,?" hexmask.long.word 0x14 0.--15. 1. "CDATA,Conversion Data" line.long 0x18 "PCDR6,Precision Input n Conversion Data" bitfld.long 0x18 19. "VALID,Conversion Data Available" "0: No unread conversion data,1: Unread conversion data is available" bitfld.long 0x18 18. "OVERW,Overwrite Status Flag" "0: No unread data is overwritten,1: Unread data is overwritten" newline bitfld.long 0x18 16.--17. "RESULT,Conversion Data Type" "0: Normal trigger,1: Injected trigger,2: BCTU trigger,?" hexmask.long.word 0x18 0.--15. 1. "CDATA,Conversion Data" line.long 0x1C "PCDR7,Precision Input n Conversion Data" bitfld.long 0x1C 19. "VALID,Conversion Data Available" "0: No unread conversion data,1: Unread conversion data is available" bitfld.long 0x1C 18. "OVERW,Overwrite Status Flag" "0: No unread data is overwritten,1: Unread data is overwritten" newline bitfld.long 0x1C 16.--17. "RESULT,Conversion Data Type" "0: Normal trigger,1: Injected trigger,2: BCTU trigger,?" hexmask.long.word 0x1C 0.--15. 1. "CDATA,Conversion Data" repeat 24. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x180)++0x3 line.long 0x0 "ICDR[$1],Standard Input n Conversion Data" bitfld.long 0x0 19. "VALID,Conversion Data Available" "0: No unread conversion data,1: Unread conversion data is available" bitfld.long 0x0 18. "OVERW,Overwrite Status Flag" "0: No unread data is overwritten,1: Unread data is overwritten" newline bitfld.long 0x0 16.--17. "RESULT,Conversion Data Type" "0: Normal trigger,1: Injected trigger,2: BCTU trigger,?" hexmask.long.word 0x0 0.--15. 1. "CDATA,Conversion Data" repeat.end repeat 32. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x200)++0x3 line.long 0x0 "ECDR[$1],External Input n Conversion Data" bitfld.long 0x0 19. "VALID,Conversion Data Available" "0: No unread conversion data,1: Unread conversion data is available" bitfld.long 0x0 18. "OVERW,Overwrite Status Flag" "0: No unread data is overwritten,1: Unread data is overwritten" newline bitfld.long 0x0 16.--17. "RESULT,Conversion Data Type" "0: Normal trigger,1: Injected trigger,2: BCTU trigger,?" hexmask.long.word 0x0 0.--15. 1. "CDATA,Conversion Data" repeat.end group.long 0x2B0++0x3 line.long 0x0 "CWSELRPI0,Channel Analog Watchdog Select For Precision Inputs" bitfld.long 0x0 28.--29. "WSEL_SI0_7,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x0 24.--25. "WSEL_SI0_6,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x0 20.--21. "WSEL_SI0_5,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x0 16.--17. "WSEL_SI0_4,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x0 12.--13. "WSEL_SI0_3,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x0 8.--9. "WSEL_SI0_2,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x0 4.--5. "WSEL_SI0_1,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x0 0.--1. "WSEL_SI0_0,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" rgroup.long 0x2B4++0x3 line.long 0x0 "CWSELRPI1,Channel Analog Watchdog Select For Precision Inputs" group.long 0x2C0++0xB line.long 0x0 "CWSELRSI0,Channel Analog Watchdog Select For Standard Inputs" bitfld.long 0x0 28.--29. "WSEL_SI7_0,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x0 24.--25. "WSEL_SI6_0,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x0 20.--21. "WSEL_SI5_0,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x0 16.--17. "WSEL_SI4_0,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x0 12.--13. "WSEL_SI3_0,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x0 8.--9. "WSEL_SI2_0,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x0 4.--5. "WSEL_SI1_0,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x0 0.--1. "WSEL_SI0_0,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" line.long 0x4 "CWSELRSI1,Channel Analog Watchdog Select For Standard Inputs" bitfld.long 0x4 28.--29. "WSEL_SI7_1,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x4 24.--25. "WSEL_SI6_1,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x4 20.--21. "WSEL_SI5_1,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x4 16.--17. "WSEL_SI4_1,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x4 12.--13. "WSEL_SI3_1,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x4 8.--9. "WSEL_SI2_1,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x4 4.--5. "WSEL_SI1_1,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x4 0.--1. "WSEL_SI0_1,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" line.long 0x8 "CWSELRSI2,Channel Analog Watchdog Select For Standard Inputs" bitfld.long 0x8 28.--29. "WSEL_SI7_2,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x8 24.--25. "WSEL_SI6_2,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x8 20.--21. "WSEL_SI5_2,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x8 16.--17. "WSEL_SI4_2,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x8 12.--13. "WSEL_SI3_2,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x8 8.--9. "WSEL_SI2_2,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x8 4.--5. "WSEL_SI1_2,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x8 0.--1. "WSEL_SI0_2,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" group.long 0x2D0++0x1B line.long 0x0 "CWSELREI0,Channel Analog Watchdog Select For External inputs" bitfld.long 0x0 28.--29. "WSEL_SI0_7,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x0 24.--25. "WSEL_SI0_6,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x0 20.--21. "WSEL_SI0_5,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x0 16.--17. "WSEL_SI0_4,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x0 12.--13. "WSEL_SI0_3,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x0 8.--9. "WSEL_SI0_2,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x0 4.--5. "WSEL_SI0_1,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x0 0.--1. "WSEL_SI0_0,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" line.long 0x4 "CWSELREI1,Channel Analog Watchdog Select For External inputs" bitfld.long 0x4 28.--29. "WSEL_SI1_15,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x4 24.--25. "WSEL_SI1_14,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x4 20.--21. "WSEL_SI1_13,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x4 16.--17. "WSEL_SI1_12,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x4 12.--13. "WSEL_SI1_11,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x4 8.--9. "WSEL_SI1_10,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x4 4.--5. "WSEL_SI1_9,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x4 0.--1. "WSEL_SI1_8,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" line.long 0x8 "CWSELREI2,Channel Analog Watchdog Select For External inputs" bitfld.long 0x8 28.--29. "WSEL_SI2_23,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x8 24.--25. "WSEL_SI2_22,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x8 20.--21. "WSEL_SI2_21,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x8 16.--17. "WSEL_SI2_20,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x8 12.--13. "WSEL_SI2_19,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x8 8.--9. "WSEL_SI2_18,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x8 4.--5. "WSEL_SI2_17,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x8 0.--1. "WSEL_SI2_16,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" line.long 0xC "CWSELREI3,Channel Analog Watchdog Select For External inputs" bitfld.long 0xC 28.--29. "WSEL_SI3_31,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0xC 24.--25. "WSEL_SI3_30,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0xC 20.--21. "WSEL_SI3_29,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0xC 16.--17. "WSEL_SI3_28,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0xC 12.--13. "WSEL_SI3_27,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0xC 8.--9. "WSEL_SI3_26,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0xC 4.--5. "WSEL_SI3_25,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0xC 0.--1. "WSEL_SI3_24,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" line.long 0x10 "CWENR0,Channel Watchdog Enable For Precision Inputs" bitfld.long 0x10 7. "CWEN7,Channel Analog Watchdog Enable 7" "0: Disable,1: Enable" bitfld.long 0x10 6. "CWEN6,Channel Analog Watchdog Enable 6" "0: Disable,1: Enable" newline bitfld.long 0x10 5. "CWEN5,Channel Analog Watchdog Enable 5" "0: Disable,1: Enable" bitfld.long 0x10 4. "CWEN4,Channel Analog Watchdog Enable 4" "0: Disable,1: Enable" newline bitfld.long 0x10 3. "CWEN3,Channel Analog Watchdog Enable 3" "0: Disable,1: Enable" bitfld.long 0x10 2. "CWEN2,Channel Analog Watchdog Enable 2" "0: Disable,1: Enable" newline bitfld.long 0x10 1. "CWEN1,Channel Analog Watchdog Enable 1" "0: Disable,1: Enable" bitfld.long 0x10 0. "CWEN0,Channel Analog Watchdog Enable 0" "0: Disable,1: Enable" line.long 0x14 "CWENR1,Channel Watchdog Enable For Standard Inputs" bitfld.long 0x14 23. "CWEN55,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" bitfld.long 0x14 22. "CWEN54,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" newline bitfld.long 0x14 21. "CWEN53,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" bitfld.long 0x14 20. "CWEN52,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" newline bitfld.long 0x14 19. "CWEN51,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" bitfld.long 0x14 18. "CWEN50,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" newline bitfld.long 0x14 17. "CWEN49,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" bitfld.long 0x14 16. "CWEN48,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" newline bitfld.long 0x14 15. "CWEN47,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" bitfld.long 0x14 14. "CWEN46,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" newline bitfld.long 0x14 13. "CWEN45,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" bitfld.long 0x14 12. "CWEN44,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" newline bitfld.long 0x14 11. "CWEN43,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" bitfld.long 0x14 10. "CWEN42,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" newline bitfld.long 0x14 9. "CWEN41,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" bitfld.long 0x14 8. "CWEN40,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" newline bitfld.long 0x14 7. "CWEN39,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" bitfld.long 0x14 6. "CWEN38,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" newline bitfld.long 0x14 5. "CWEN37,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" bitfld.long 0x14 4. "CWEN36,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" newline bitfld.long 0x14 3. "CWEN35,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" bitfld.long 0x14 2. "CWEN34,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" newline bitfld.long 0x14 1. "CWEN33,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" bitfld.long 0x14 0. "CWEN32,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" line.long 0x18 "CWENR2,Channel Watchdog Enable For External Inputs" bitfld.long 0x18 31. "CWEN95,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" bitfld.long 0x18 30. "CWEN94,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" newline bitfld.long 0x18 29. "CWEN93,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" bitfld.long 0x18 28. "CWEN92,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" newline bitfld.long 0x18 27. "CWEN91,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" bitfld.long 0x18 26. "CWEN90,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" newline bitfld.long 0x18 25. "CWEN89,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" bitfld.long 0x18 24. "CWEN88,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" newline bitfld.long 0x18 23. "CWEN87,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" bitfld.long 0x18 22. "CWEN86,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" newline bitfld.long 0x18 21. "CWEN85,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" bitfld.long 0x18 20. "CWEN84,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" newline bitfld.long 0x18 19. "CWEN83,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" bitfld.long 0x18 18. "CWEN82,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" newline bitfld.long 0x18 17. "CWEN81,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" bitfld.long 0x18 16. "CWEN80,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" newline bitfld.long 0x18 15. "CWEN79,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" bitfld.long 0x18 14. "CWEN78,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" newline bitfld.long 0x18 13. "CWEN77,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" bitfld.long 0x18 12. "CWEN76,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" newline bitfld.long 0x18 11. "CWEN75,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" bitfld.long 0x18 10. "CWEN74,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" newline bitfld.long 0x18 9. "CWEN73,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" bitfld.long 0x18 8. "CWEN72,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" newline bitfld.long 0x18 7. "CWEN71,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" bitfld.long 0x18 6. "CWEN70,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" newline bitfld.long 0x18 5. "CWEN69,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" bitfld.long 0x18 4. "CWEN68,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" newline bitfld.long 0x18 3. "CWEN67,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" bitfld.long 0x18 2. "CWEN66,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" newline bitfld.long 0x18 1. "CWEN65,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" bitfld.long 0x18 0. "CWEN64,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" group.long 0x2F0++0xB line.long 0x0 "AWORR0,Analog Watchdog Out Of Range For Precision Inputs" eventfld.long 0x0 7. "AWOR_CH7,Analog Watchdog Out Of Range For Precision Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x0 6. "AWOR_CH6,Analog Watchdog Out Of Range For Precision Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x0 5. "AWOR_CH5,Analog Watchdog Out Of Range For Precision Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x0 4. "AWOR_CH4,Analog Watchdog Out Of Range For Precision Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x0 3. "AWOR_CH3,Analog Watchdog Out Of Range For Precision Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x0 2. "AWOR_CH2,Analog Watchdog Out Of Range For Precision Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x0 1. "AWOR_CH1,Analog Watchdog Out Of Range For Precision Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x0 0. "AWOR_CH0,Analog Watchdog Out Of Range For Precision Inputs" "0: Conversion is within limits,1: Conversion is not within limits" line.long 0x4 "AWORR1,Analog Watchdog Out Of Range For Standard Inputs" eventfld.long 0x4 23. "AWOR_CH23,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x4 22. "AWOR_CH22,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x4 21. "AWOR_CH21,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x4 20. "AWOR_CH20,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x4 19. "AWOR_CH19,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x4 18. "AWOR_CH18,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x4 17. "AWOR_CH17,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x4 16. "AWOR_CH16,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x4 15. "AWOR_CH15,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x4 14. "AWOR_CH14,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x4 13. "AWOR_CH13,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x4 12. "AWOR_CH12,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x4 11. "AWOR_CH11,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x4 10. "AWOR_CH10,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x4 9. "AWOR_CH9,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x4 8. "AWOR_CH8,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x4 7. "AWOR_CH7,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x4 6. "AWOR_CH6,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x4 5. "AWOR_CH5,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x4 4. "AWOR_CH4,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x4 3. "AWOR_CH3,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x4 2. "AWOR_CH2,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x4 1. "AWOR_CH1,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x4 0. "AWOR_CH0,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" line.long 0x8 "AWORR2,Analog Watchdog Out Of Range For External Inputs" eventfld.long 0x8 31. "AWOR_CH31,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x8 30. "AWOR_CH30,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x8 29. "AWOR_CH29,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x8 28. "AWOR_CH28,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x8 27. "AWOR_CH27,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x8 26. "AWOR_CH26,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x8 25. "AWOR_CH25,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x8 24. "AWOR_CH24,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x8 23. "AWOR_CH23,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x8 22. "AWOR_CH22,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x8 21. "AWOR_CH21,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x8 20. "AWOR_CH20,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x8 19. "AWOR_CH19,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x8 18. "AWOR_CH18,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x8 17. "AWOR_CH17,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x8 16. "AWOR_CH16,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x8 15. "AWOR_CH15,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x8 14. "AWOR_CH14,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x8 13. "AWOR_CH13,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x8 12. "AWOR_CH12,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x8 11. "AWOR_CH11,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x8 10. "AWOR_CH10,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x8 9. "AWOR_CH9,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x8 8. "AWOR_CH8,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x8 7. "AWOR_CH7,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x8 6. "AWOR_CH6,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x8 5. "AWOR_CH5,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x8 4. "AWOR_CH4,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x8 3. "AWOR_CH3,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x8 2. "AWOR_CH2,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x8 1. "AWOR_CH1,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x8 0. "AWOR_CH0,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" group.long 0x340++0x13 line.long 0x0 "STCR1,Self-Test Configuration 1" hexmask.long.byte 0x0 24.--31. 1. "INPSAMP_C,Input Sampling Time Algorithm C" hexmask.long.byte 0x0 8.--15. 1. "INPSAMP_S,Input Sampling Time Algorithm S" line.long 0x4 "STCR2,Self-Test Configuration 2" bitfld.long 0x4 27. "MSKWDSERR,Mask Interrupt Self-Test Watchdog Sequence Error" "0: No interrupt is generated,1: Interrupt is generated" eventfld.long 0x4 26. "SERR,Self-Test Error Injection" "0: Error can be injected,1: Error is being injected" newline bitfld.long 0x4 25. "MSKWDTERR,Mask Interrupt Self-Test Watchdog Timer Error" "0: No interrupt is generated,1: Interrupt is generated" bitfld.long 0x4 23. "MSKST_EOC,Mask Interrupt Self-Test End Of Conversion" "0: No interrupt is generated,1: Interrupt is generated" newline bitfld.long 0x4 18. "MSKWDG_EOA_C,Mask Error Interrupt End Of Algorithm C" "0: No interrupt is generated,1: Interrupt is generated" bitfld.long 0x4 16. "MSKWDG_EOA_S,Mask Error Interrupt End Of Algorithm S" "0: No interrupt is generated,1: Interrupt is generated" newline bitfld.long 0x4 15. "MSKERR_C,Mask Error Interrupt Algorithm C" "0: No interrupt is generated,1: Interrupt is generated" bitfld.long 0x4 13. "MSKERR_S2,Mask Error Interrupt Algorithm S2" "0: No interrupt is generated,1: Interrupt is generated" newline bitfld.long 0x4 12. "MSKERR_S1,Mask Error Interrupt Algorithm S1" "0: No interrupt is generated,1: Interrupt is generated" bitfld.long 0x4 11. "MSKERR_S0,Mask Error Interrupt Algorithm S0" "0: No interrupt is generated,1: Interrupt is generated" newline bitfld.long 0x4 7. "EN,Self-Test Enable" "0: Disable,1: Enable" bitfld.long 0x4 4. "FMA_WDSERR,Fault Mapping Self-Test Watchdog Sequence Error" "0: Noncritical fault line,1: Critical fault line" newline bitfld.long 0x4 3. "FMA_WDTERR,Fault Mapping Self-Test Watchdog Timer Error" "0: Noncritical fault line,1: Critical fault line" bitfld.long 0x4 2. "FMA_C,Fault Mapping Algorithm C" "0: Noncritical fault line,1: Critical fault line" newline bitfld.long 0x4 0. "FMA_S,Fault Mapping Algorithm S" "0: Noncritical fault line,1: Critical fault line" line.long 0x8 "STCR3,Self-Test Configuration 3" bitfld.long 0x8 8.--9. "ALG,Algorithm Selection" "0,1,2,3" hexmask.long.byte 0x8 0.--4. 1. "MSTEP,Algorithm Step" line.long 0xC "STBRR,Self-Test Baud Rate" bitfld.long 0xC 16.--18. "WDT,Self-Test Watchdog Timer" "0: 8192 conversion clock cycles (~0.1 ms at 80 MHz),1: 39 936 conversion clock cycles (~0.5 ms at 80 MHz),2: 79 872 conversion clock cycles (~1 ms at 80 MHz),3: 159 744 conversion clock cycles (~2 ms at 80 MHz),4: 400 384 conversion clock cycles (~5 ms at 80 MHz),5: 799 744 conversion clock cycles (~10 ms at 80 MHz),6: 1 599 488 conversion clock cycles (~20 ms at 80..,7: 3 999 744 conversion clock cycles (~50 ms at 80.." hexmask.long.byte 0xC 0.--7. 1. "BR,Baud Rate" line.long 0x10 "STSR1,Self-Test Status 1" eventfld.long 0x10 27. "WDSERR,Self-Test Watchdog Sequence Error" "0: Algorithm executed in correct sequence,1: Algorithm did not execute in correct sequence" eventfld.long 0x10 25. "WDTERR,Self-Test Watchdog Timer Error" "0: Algorithm finished within the safe time period..,1: Algorithm did not finish within safe time period." newline eventfld.long 0x10 24. "OVERWR,Self-Test Error Status Overwrite" "0: No self-test error status flag overwritten,1: Self-test error status flag overwritten" eventfld.long 0x10 23. "ST_EOC,Self-Test End Of Conversion" "0: Not complete,1: Complete" newline eventfld.long 0x10 18. "WDG_EOA_C,Self-Test Watchdog End Of Algorithm C" "0: Not complete,1: Complete" eventfld.long 0x10 16. "WDG_EOA_S,Self-Test Watchdog End Of Algorithm S" "0: Not complete,1: Complete" newline eventfld.long 0x10 15. "ERR_C,Error Algorithm C" "0: No error,1: Error" eventfld.long 0x10 13. "ERR_S2,Error Algorithm S Step 2" "0: No error,1: Error" newline eventfld.long 0x10 12. "ERR_S1,Error Algorithm S Step 1" "0: No error,1: Error" eventfld.long 0x10 11. "ERR_S0,Error Algorithm S Step 0" "0: No error,1: Error" newline hexmask.long.byte 0x10 5.--9. 1. "STEP_C,Step Of Algorithm C" rgroup.long 0x354++0xB line.long 0x0 "STSR2,Self-Test Status 2" hexmask.long.word 0x0 0.--14. 1. "DATA0,Conversion Data ERR_S1" line.long 0x4 "STSR3,Self-Test Status 3" hexmask.long.word 0x4 16.--30. 1. "DATA1,Conversion Data ERR_S2" hexmask.long.word 0x4 0.--14. 1. "DATA0,Conversion Data ERR_S0" line.long 0x8 "STSR4,Self-Test Status 4" hexmask.long.word 0x8 16.--30. 1. "DATA1,Conversion Data ERR_C" rgroup.long 0x370++0x3 line.long 0x0 "STDR1,Self-Test Conversion Data 1" bitfld.long 0x0 19. "VALID,Valid Conversion Data" "0: No unread conversion data,1: Unread conversion data is available" bitfld.long 0x0 18. "OWERWR,Conversion Data Overwrite Status" "0: Current conversion data not overwritten,1: Current conversion data was overwritten" newline hexmask.long.word 0x0 0.--14. 1. "TCDATA,Test Channel Conversion Data" group.long 0x380++0x3 line.long 0x0 "STAW0R,Self-Test Analog Watchdog S0" bitfld.long 0x0 31. "AWDE,Self-Test Watchdog Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "WDTE,Self-Test Watchdog Timer Enable" "0: Disable,1: Enable" newline hexmask.long.word 0x0 16.--29. 1. "THRH,Higher Threshold Value" hexmask.long.word 0x0 0.--14. 1. "THRL,Lower Threshold Value" group.long 0x388++0x7 line.long 0x0 "STAW1R,Self-Test Analog Watchdog S1" bitfld.long 0x0 31. "AWDE,Self-Test Watchdog Enable" "0: Disable,1: Enable" hexmask.long.word 0x0 0.--14. 1. "THRL,Lower Threshold Value" line.long 0x4 "STAW2R,Self-Test Analog Watchdog S2" bitfld.long 0x4 31. "AWDE,Self-Test Watchdog Enable" "0: Disable,1: Enable" hexmask.long.word 0x4 0.--14. 1. "THRL,Lower Threshold Value" group.long 0x394++0xF line.long 0x0 "STAW4R,Self-Test Analog Watchdog C0" bitfld.long 0x0 31. "AWDE,Self-Test Watchdog Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "WDTE,Self-Test Watchdog Timer Enable" "0: Disable,1: Enable" newline hexmask.long.word 0x0 16.--29. 1. "THRH,Higher Threshold Value" hexmask.long.word 0x0 0.--14. 1. "THRL,Lower Threshold Value" line.long 0x4 "STAW5R,Self-Test Analog Watchdog C" hexmask.long.word 0x4 16.--30. 1. "THRH,Higher Threshold Value" hexmask.long.word 0x4 0.--14. 1. "THRL,Lower Threshold Value" line.long 0x8 "AMSIO,Analog Miscellaneous In/Out register" bitfld.long 0x8 17.--18. "HSEN,High-Speed Enable" "0,1,2,3" bitfld.long 0x8 16. "CMPCTRL0,Compare Control 0" "0,1" line.long 0xC "CALBISTREG,Control And Calibration Status" bitfld.long 0xC 29.--31. "RESN,Conversion Resolution" "0: 14-bit resolution,1: 12-bit resolution,2: 10-bit resolution,3: 8-bit resolution,?,?,?,?" bitfld.long 0xC 27.--28. "TSAMP,Sample Period In Calibration" "0: 22 conversion clock cycles,1: 8 conversion clock cycles,2: 16 conversion clock cycles,3: 32 conversion clock cycles" newline rbitfld.long 0xC 15. "C_T_BUSY,Calibration Busy" "0: Calibration can be started,1: Calibration is in progress" bitfld.long 0xC 14. "CALSTFUL,Calibration And Self-Test Full Range Comparison" "0: Lowest 11 bits are compared.,1: All 15 bits are compared." newline bitfld.long 0xC 5.--6. "NR_SMPL,Calibration Averaging Number" "0: 4 samples,1: 8 samples,2: 16 samples,3: 32 samples" bitfld.long 0xC 4. "AVG_EN,Calibration Averaging Enable" "0: Disable,1: Enable" newline eventfld.long 0xC 3. "TEST_FAIL,Calibration Status" "0: Calibration finished successfully or has not..,1: Calibration did not finish successfully" bitfld.long 0xC 0. "TEST_EN,Calibration Enable" "0: Wait to start a calibration,1: Start calibration" group.long 0x3A8++0x3 line.long 0x0 "OFSGNUSR,Offset And Gain User" hexmask.long.word 0x0 16.--25. 1. "GAIN_USER,Gain User" hexmask.long.byte 0x0 0.--7. 1. "OFFSET_USER,Offset User" group.long 0x3B4++0x3 line.long 0x0 "CAL2,Calibration Value 2" bitfld.long 0x0 15. "ENX,Enable X" "0: Disable,1: Enable" tree.end tree "ADC_1" base ad:0x400A4000 group.long 0x0++0x3 line.long 0x0 "MCR,Main Configuration" bitfld.long 0x0 31. "OWREN,Overwrite Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "WLSIDE,Write Left-Aligned" "0: Right aligned,1: Left-aligned" newline bitfld.long 0x0 29. "MODE,Normal Conversion Mode" "0: Single conversion,1: Continuous conversion" bitfld.long 0x0 27. "TRGEN,External Trigger Enable" "0: Normal trigger input does not start a conversion,1: Normal trigger input starts a conversion" newline bitfld.long 0x0 26. "EDGE,External Trigger Edge Selection" "0: Falling edge,1: Rising edge" bitfld.long 0x0 25. "XSTRTEN,Auxiliary External Start Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 24. "NSTART,Start Normal Conversion" "0: No effect,1: Starts conversion" bitfld.long 0x0 22. "JTRGEN,Injection Trigger Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 21. "JEDGE,Injected Trigger Edge Selection" "0: Falling edge,1: Rising edge" bitfld.long 0x0 20. "JSTART,Injected Start" "0: Injected conversion can be started,1: Starts an injected conversion" newline bitfld.long 0x0 17. "BCTUEN,Body Cross Trigger Unit Enable" "0: Disable,1: Enable" bitfld.long 0x0 16. "BCTU_MODE,Body Cross Trigger Unit Mode Select" "0: Only BCTU can trigger conversion,1: All trigger sources can trigger conversion" newline eventfld.long 0x0 15. "STCL,Self-Test Configuration Lock" "0: Registers are writeable,1: Registers are read-only" bitfld.long 0x0 11. "AVGEN,Averaging Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 9.--10. "AVGS,Averaging Select" "0: 4 conversions,1: 8 conversions,2: 16 conversions,3: 32 conversions" eventfld.long 0x0 7. "ABORTCHAIN,Abort Chain" "0: Undefined,1: Conversion aborted" newline eventfld.long 0x0 6. "ABORT,Abort Conversion" "0: Undefined,1: Conversion aborted" bitfld.long 0x0 5. "ACKO,Auto Clock Off" "0: Clock always active,1: Clock gated" newline bitfld.long 0x0 1.--2. "ADCLKSEL,Conversion Clock (AD_clk) Frequency Selection" "0: Module clock frequency,1: Module clock frequency / 2,2: Module clock frequency / 4,3: Module clock frequency / 8" bitfld.long 0x0 0. "PWDN,Power Down" "0: ADC enters a functional state,1: ADC enters Power Down state" rgroup.long 0x4++0x3 line.long 0x0 "MSR,Main Status" bitfld.long 0x0 31. "CALIBRTD,Calibration Status" "0: Uncalibrated or calibration unsuccessful,1: Calibrated" bitfld.long 0x0 24. "NSTART,Normal Conversion Started" "0: Not in progress,1: In progress" newline bitfld.long 0x0 23. "JABORT,Injected Conversion Aborted" "0: Not aborted,1: Aborted" bitfld.long 0x0 20. "JSTART,Injected Conversion Started" "0: Not an injected conversion,1: Injected conversion" newline bitfld.long 0x0 18. "SELF_TEST_S,Indicates whether an ongoing conversion is for self-test." "0: Not self-test,1: Self-test" bitfld.long 0x0 16. "BCTUSTART,BCTU Conversion Started" "0: Conversion was not triggered by BCTU,1: Ongoing conversion was triggered by BCTU" newline hexmask.long.byte 0x0 9.--15. 1. "CHADDR,Input Under Measure" bitfld.long 0x0 5. "ACKO,Auto Clock-Off On" "0: Inactive,1: Active" newline bitfld.long 0x0 0.--2. "ADCSTATUS,ADC State" "0: Idle,1: Power Down,2: Wait,3: Calibrate,4: Convert,?,6: Done,?" group.long 0x10++0x27 line.long 0x0 "ISR,Interrupt Status" eventfld.long 0x0 4. "EOBCTU,End Of BCTU Conversion" "0: No EOBCTU interrupt generated,1: EOBCTU interrupt generated" eventfld.long 0x0 3. "JEOC,End Of Injected Conversion" "0: No JEOC interrupt generated,1: JEOC interrupt generated" newline eventfld.long 0x0 2. "JECH,End Of Injected Chain Conversion" "0: No JECH interrupt generated,1: JECH interrupt generated" eventfld.long 0x0 1. "EOC,End Of Conversion" "0: No EOC interrupt generated,1: Interrupt generated" newline eventfld.long 0x0 0. "ECH,End Of Chain Conversion" "0: Indicates no ECH interrupt generated,1: Indicates an ECH interrupt has been generated" line.long 0x4 "CEOCFR0,Channel End Of Conversion Flag For Precision Inputs" eventfld.long 0x4 7. "PIEOCF7,Precision Input End Of Conversion Flag 7" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x4 6. "PIEOCF6,Precision Input End Of Conversion Flag 6" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x4 5. "PIEOCF5,Precision Input End Of Conversion Flag 5" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x4 4. "PIEOCF4,Precision Input End Of Conversion Flag 4" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x4 3. "PIEOCF3,Precision Input End Of Conversion Flag 3" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x4 2. "PIEOCF2,Precision Input End Of Conversion Flag 2" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x4 1. "PIEOCF1,Precision Input End Of Conversion Flag 1" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x4 0. "PIEOCF0,Precision Input End Of Conversion Flag 0" "0: Conversion not complete,1: Conversion complete" line.long 0x8 "CEOCFR1,Channel End Of Conversion Flag For Standard Inputs" eventfld.long 0x8 23. "SIEOCF23,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 22. "SIEOCF22,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 21. "SIEOCF21,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 20. "SIEOCF20,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 19. "SIEOCF19,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 18. "SIEOCF18,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 17. "SIEOCF17,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 16. "SIEOCF16,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 15. "SIEOCF15,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 14. "SIEOCF14,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 13. "SIEOCF13,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 12. "SIEOCF12,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 11. "SIEOCF11,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 10. "SIEOCF10,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 9. "SIEOCF9,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 8. "SIEOCF8,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 7. "SIEOCF7,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 6. "SIEOCF6,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 5. "SIEOCF5,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 4. "SIEOCF4,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 3. "SIEOCF3,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 2. "SIEOCF2,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 1. "SIEOCF1,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 0. "SIEOCF0,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" line.long 0xC "CEOCFR2,Channel End Of Conversion Flag For External Inputs" eventfld.long 0xC 31. "EIEOCF31,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0xC 30. "EIEOCF30,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0xC 29. "EIEOCF29,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0xC 28. "EIEOCF28,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0xC 27. "EIEOCF27,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0xC 26. "EIEOCF26,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0xC 25. "EIEOCF25,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0xC 24. "EIEOCF24,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0xC 23. "EIEOCF23,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0xC 22. "EIEOCF22,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0xC 21. "EIEOCF21,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0xC 20. "EIEOCF20,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0xC 19. "EIEOCF19,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0xC 18. "EIEOCF18,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0xC 17. "EIEOCF17,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0xC 16. "EIEOCF16,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0xC 15. "EIEOCF15,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0xC 14. "EIEOCF14,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0xC 13. "EIEOCF13,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0xC 12. "EIEOCF12,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0xC 11. "EIEOCF11,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0xC 10. "EIEOCF10,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0xC 9. "EIEOCF9,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0xC 8. "EIEOCF8,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0xC 7. "EIEOCF7,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0xC 6. "EIEOCF6,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0xC 5. "EIEOCF5,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0xC 4. "EIEOCF4,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0xC 3. "EIEOCF3,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0xC 2. "EIEOCF2,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0xC 1. "EIEOCF1,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0xC 0. "EIEOCF0,External Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" line.long 0x10 "IMR,Interrupt Mask" bitfld.long 0x10 4. "MSKEOBCTU,EOBCTU Interrupt Flag Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x10 3. "MSKJEOC,JEOC Interrupt Flag Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x10 2. "MSKJECH,JECH Interrupt Flag Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x10 1. "MSKEOC,EOC Interrupt Flag Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x10 0. "MSKECH,ECH Interrupt Flag Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" line.long 0x14 "CIMR0,EOC Interrupt Enable For Precision Inputs" bitfld.long 0x14 7. "PIEOCIEN7,Precision Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x14 6. "PIEOCIEN6,Precision Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x14 5. "PIEOCIEN5,Precision Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x14 4. "PIEOCIEN4,Precision Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x14 3. "PIEOCIEN3,Precision Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x14 2. "PIEOCIEN2,Precision Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x14 1. "PIEOCIEN1,Precision Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x14 0. "PIEOCIEN0,Precision Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" line.long 0x18 "CIMR1,EOC Interrupt Enable For Standard Inputs" bitfld.long 0x18 23. "SIEOCIEN23,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x18 22. "SIEOCIEN22,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x18 21. "SIEOCIEN21,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x18 20. "SIEOCIEN20,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x18 19. "SIEOCIEN19,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x18 18. "SIEOCIEN18,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x18 17. "SIEOCIEN17,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x18 16. "SIEOCIEN16,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x18 15. "SIEOCIEN15,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x18 14. "SIEOCIEN14,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x18 13. "SIEOCIEN13,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x18 12. "SIEOCIEN12,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x18 11. "SIEOCIEN11,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x18 10. "SIEOCIEN10,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x18 9. "SIEOCIEN9,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x18 8. "SIEOCIEN8,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x18 7. "SIEOCIEN7,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x18 6. "SIEOCIEN6,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x18 5. "SIEOCIEN5,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x18 4. "SIEOCIEN4,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x18 3. "SIEOCIEN3,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x18 2. "SIEOCIEN2,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x18 1. "SIEOCIEN1,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x18 0. "SIEOCIEN0,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" line.long 0x1C "CIMR2,EOC Interrupt Enable For External Inputs" bitfld.long 0x1C 31. "EIEOCIEN31,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x1C 30. "EIEOCIEN30,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x1C 29. "EIEOCIEN29,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x1C 28. "EIEOCIEN28,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x1C 27. "EIEOCIEN27,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x1C 26. "EIEOCIEN26,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x1C 25. "EIEOCIEN25,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x1C 24. "EIEOCIEN24,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x1C 23. "EIEOCIEN23,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x1C 22. "EIEOCIEN22,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x1C 21. "EIEOCIEN21,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x1C 20. "EIEOCIEN20,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x1C 19. "EIEOCIEN19,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x1C 18. "EIEOCIEN18,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x1C 17. "EIEOCIEN17,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x1C 16. "EIEOCIEN16,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x1C 15. "EIEOCIEN15,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x1C 14. "EIEOCIEN14,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x1C 13. "EIEOCIEN13,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x1C 12. "EIEOCIEN12,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x1C 11. "EIEOCIEN11,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x1C 10. "EIEOCIEN10,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x1C 9. "EIEOCIEN9,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x1C 8. "EIEOCIEN8,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x1C 7. "EIEOCIEN7,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x1C 6. "EIEOCIEN6,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x1C 5. "EIEOCIEN5,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x1C 4. "EIEOCIEN4,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x1C 3. "EIEOCIEN3,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x1C 2. "EIEOCIEN2,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x1C 1. "EIEOCIEN1,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x1C 0. "EIEOCIEN0,External Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" line.long 0x20 "WTISR,Analog Watchdog Threshold Interrupt Status" eventfld.long 0x20 31. "HAWIF16,High Analog Watchdog Interrupt Flag 16" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x20 30. "LAWIF16,Low Analog Watchdog Interrupt Flag 16" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x20 29. "HAWIF15,High Analog Watchdog Interrupt Flag 15" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x20 28. "LAWIF15,Low Analog Watchdog Interrupt Flag 15" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x20 27. "HAWIF14,High Analog Watchdog Interrupt Flag 14" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x20 26. "LAWIF14,Low Analog Watchdog Interrupt Flag 14" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x20 25. "HAWIF13,High Analog Watchdog Interrupt Flag 13" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x20 24. "LAWIF13,Low Analog Watchdog Interrupt Flag 13" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x20 23. "HAWIF12,High Analog Watchdog Interrupt Flag 12" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x20 22. "LAWIF12,Low Analog Watchdog Interrupt Flag 12" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x20 21. "HAWIF11,High Analog Watchdog Interrupt Flag 11" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x20 20. "LAWIF11,Low Analog Watchdog Interrupt Flag 11" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x20 19. "HAWIF10,High Analog Watchdog Interrupt Flag 10" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x20 18. "LAWIF10,Low Analog Watchdog Interrupt Flag 10" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x20 17. "HAWIF9,High Analog Watchdog Interrupt Flag 9" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x20 16. "LAWIF9,Low Analog Watchdog Interrupt Flag 9" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x20 15. "HAWIF8,High Analog Watchdog Interrupt Flag 8" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x20 14. "LAWIF8,Low Analog Watchdog Interrupt Flag 8" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x20 13. "HAWIF7,High Analog Watchdog Interrupt Flag 7" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x20 12. "LAWIF7,Low Analog Watchdog Interrupt Flag 7" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x20 11. "HAWIF6,High Analog Watchdog Interrupt Flag 6" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x20 10. "LAWIF6,Low Analog Watchdog Interrupt Flag 6" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x20 9. "HAWIF5,High Analog Watchdog Interrupt Flag 5" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x20 8. "LAWIF5,Low Analog Watchdog Interrupt Flag 5" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x20 7. "HAWIF4,High Analog Watchdog Interrupt Flag 4" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x20 6. "LAWIF4,Low Analog Watchdog Interrupt Flag 4" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x20 5. "HAWIF3,High Analog Watchdog Interrupt Flag 3" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x20 4. "LAWIF3,Low Analog Watchdog Interrupt Flag 3" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x20 3. "HAWIF2,High Analog Watchdog Interrupt Flag 2" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x20 2. "LAWIF2,Low Analog Watchdog Interrupt Flag 2" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x20 1. "HAWIF1,High Analog Watchdog Interrupt Flag 1" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x20 0. "LAWIF1,Low Analog Watchdog Interrupt Flag 1" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." line.long 0x24 "WTIMR,Analog Watchdog Threshold Interrupt Enable" bitfld.long 0x24 7. "HDWIFEN4,High Data Watchdog Interrupt Flag Enable n" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x24 6. "LAWIFEN4,Low Analog Watchdog Interrupt Flag Enable n" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x24 5. "HDWIFEN3,High Data Watchdog Interrupt Flag Enable n" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x24 4. "LAWIFEN3,Low Analog Watchdog Interrupt Flag Enable n" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x24 3. "HDWIFEN2,High Data Watchdog Interrupt Flag Enable n" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x24 2. "LAWIFEN2,Low Analog Watchdog Interrupt Flag Enable n" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x24 1. "HDWIFEN1,High Data Watchdog Interrupt Flag Enable n" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x24 0. "LAWIFEN1,Low Analog Watchdog Interrupt Flag Enable n" "0: Interrupt is not flagged,1: Interrupt is flagged" group.long 0x40++0xF line.long 0x0 "DMAE,Direct Memory Access Configuration" bitfld.long 0x0 1. "DCLR,DMA Clear Request" "0: DMA controller acknowledges the request,1: Conversion data register is read" bitfld.long 0x0 0. "DMAEN,DMA Enable" "0: Disable,1: Enable" line.long 0x4 "DMAR0,DMA Request Enable For Precision Inputs" bitfld.long 0x4 7. "PIDMAREN7,Precision Input DMA Request Enable 7" "0: Not triggered,1: Triggered" bitfld.long 0x4 6. "PIDMAREN6,Precision Input DMA Request Enable 6" "0: Not triggered,1: Triggered" newline bitfld.long 0x4 5. "PIDMAREN5,Precision Input DMA Request Enable 5" "0: Not triggered,1: Triggered" bitfld.long 0x4 4. "PIDMAREN4,Precision Input DMA Request Enable 4" "0: Not triggered,1: Triggered" newline bitfld.long 0x4 3. "PIDMAREN3,Precision Input DMA Request Enable 3" "0: Not triggered,1: Triggered" bitfld.long 0x4 2. "PIDMAREN2,Precision Input DMA Request Enable 2" "0: Not triggered,1: Triggered" newline bitfld.long 0x4 1. "PIDMAREN1,Precision Input DMA Request Enable 1" "0: Not triggered,1: Triggered" bitfld.long 0x4 0. "PIDMAREN0,Precision Input DMA Request Enable 0" "0: Not triggered,1: Triggered" line.long 0x8 "DMAR1,DMA Request Enable For Standard Inputs" bitfld.long 0x8 23. "SIDMAREN23,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" bitfld.long 0x8 22. "SIDMAREN22,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" newline bitfld.long 0x8 21. "SIDMAREN21,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" bitfld.long 0x8 20. "SIDMAREN20,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" newline bitfld.long 0x8 19. "SIDMAREN19,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" bitfld.long 0x8 18. "SIDMAREN18,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" newline bitfld.long 0x8 17. "SIDMAREN17,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" bitfld.long 0x8 16. "SIDMAREN16,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" newline bitfld.long 0x8 15. "SIDMAREN15,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" bitfld.long 0x8 14. "SIDMAREN14,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" newline bitfld.long 0x8 13. "SIDMAREN13,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" bitfld.long 0x8 12. "SIDMAREN12,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" newline bitfld.long 0x8 11. "SIDMAREN11,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" bitfld.long 0x8 10. "SIDMAREN10,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" newline bitfld.long 0x8 9. "SIDMAREN9,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" bitfld.long 0x8 8. "SIDMAREN8,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" newline bitfld.long 0x8 7. "SIDMAREN7,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" bitfld.long 0x8 6. "SIDMAREN6,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" newline bitfld.long 0x8 5. "SIDMAREN5,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" bitfld.long 0x8 4. "SIDMAREN4,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" newline bitfld.long 0x8 3. "SIDMAREN3,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" bitfld.long 0x8 2. "SIDMAREN2,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" newline bitfld.long 0x8 1. "SIDMAREN1,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" bitfld.long 0x8 0. "SIDMAREN0,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" line.long 0xC "DMAR2,DMA Request Enable For External Inputs" bitfld.long 0xC 31. "EIDMAREN31,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" bitfld.long 0xC 30. "EIDMAREN30,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" newline bitfld.long 0xC 29. "EIDMAREN29,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" bitfld.long 0xC 28. "EIDMAREN28,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" newline bitfld.long 0xC 27. "EIDMAREN27,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" bitfld.long 0xC 26. "EIDMAREN26,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" newline bitfld.long 0xC 25. "EIDMAREN25,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" bitfld.long 0xC 24. "EIDMAREN24,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" newline bitfld.long 0xC 23. "EIDMAREN23,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" bitfld.long 0xC 22. "EIDMAREN22,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" newline bitfld.long 0xC 21. "EIDMAREN21,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" bitfld.long 0xC 20. "EIDMAREN20,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" newline bitfld.long 0xC 19. "EIDMAREN19,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" bitfld.long 0xC 18. "EIDMAREN18,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" newline bitfld.long 0xC 17. "EIDMAREN17,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" bitfld.long 0xC 16. "EIDMAREN16,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" newline bitfld.long 0xC 15. "EIDMAREN15,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" bitfld.long 0xC 14. "EIDMAREN14,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" newline bitfld.long 0xC 13. "EIDMAREN13,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" bitfld.long 0xC 12. "EIDMAREN12,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" newline bitfld.long 0xC 11. "EIDMAREN11,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" bitfld.long 0xC 10. "EIDMAREN10,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" newline bitfld.long 0xC 9. "EIDMAREN9,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" bitfld.long 0xC 8. "EIDMAREN8,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" newline bitfld.long 0xC 7. "EIDMAREN7,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" bitfld.long 0xC 6. "EIDMAREN6,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" newline bitfld.long 0xC 5. "EIDMAREN5,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" bitfld.long 0xC 4. "EIDMAREN4,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" newline bitfld.long 0xC 3. "EIDMAREN3,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" bitfld.long 0xC 2. "EIDMAREN2,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" newline bitfld.long 0xC 1. "EIDMAREN1,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" bitfld.long 0xC 0. "EIDMAREN0,External Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA request is triggered" repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x60)++0x3 line.long 0x0 "THRHLR[$1],Analog Watchdog Threshold Values" hexmask.long.word 0x0 16.--30. 1. "THRH,High Threshold Value" hexmask.long.word 0x0 0.--14. 1. "THRL,Low Threshold Value" repeat.end group.long 0x80++0xF line.long 0x0 "PSCR,Presampling Control" bitfld.long 0x0 5. "PREVAL2,Presampling Voltage Select For External Inputs" "0: VREFL,1: VREFH" bitfld.long 0x0 3. "PREVAL1,Presampling Voltage Select For Standard Inputs" "0: VREFL,1: VREFH" newline bitfld.long 0x0 1. "PREVAL0,Presampling Voltage Select For Precision Inputs" "0: VREFL,1: VREFH" bitfld.long 0x0 0. "PRECONV,Convert Presampled Value" "0: No conversion after presampling,1: Presampling is followed by conversion" line.long 0x4 "PSR0,Presampling Enable For Precision Inputs" bitfld.long 0x4 7. "PRES7,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x4 6. "PRES6,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x4 5. "PRES5,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x4 4. "PRES4,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x4 3. "PRES3,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x4 2. "PRES2,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x4 1. "PRES1,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x4 0. "PRES0,Presampling Enable n" "0: Disable,1: Enable" line.long 0x8 "PSR1,Presampling Enable For Standard Inputs" bitfld.long 0x8 23. "PRES23,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x8 22. "PRES22,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x8 21. "PRES21,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x8 20. "PRES20,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x8 19. "PRES19,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x8 18. "PRES18,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x8 17. "PRES17,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x8 16. "PRES16,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x8 15. "PRES15,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x8 14. "PRES14,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x8 13. "PRES13,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x8 12. "PRES12,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x8 11. "PRES11,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x8 10. "PRES10,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x8 9. "PRES9,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x8 8. "PRES8,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x8 7. "PRES7,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x8 6. "PRES6,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x8 5. "PRES5,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x8 4. "PRES4,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x8 3. "PRES3,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x8 2. "PRES2,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x8 1. "PRES1,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x8 0. "PRES0,Presampling Enable n" "0: Disable,1: Enable" line.long 0xC "PSR2,Presampling Enable For External Inputs" bitfld.long 0xC 31. "PRES31,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0xC 30. "PRES30,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0xC 29. "PRES29,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0xC 28. "PRES28,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0xC 27. "PRES27,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0xC 26. "PRES26,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0xC 25. "PRES25,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0xC 24. "PRES24,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0xC 23. "PRES23,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0xC 22. "PRES22,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0xC 21. "PRES21,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0xC 20. "PRES20,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0xC 19. "PRES19,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0xC 18. "PRES18,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0xC 17. "PRES17,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0xC 16. "PRES16,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0xC 15. "PRES15,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0xC 14. "PRES14,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0xC 13. "PRES13,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0xC 12. "PRES12,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0xC 11. "PRES11,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0xC 10. "PRES10,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0xC 9. "PRES9,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0xC 8. "PRES8,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0xC 7. "PRES7,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0xC 6. "PRES6,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0xC 5. "PRES5,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0xC 4. "PRES4,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0xC 3. "PRES3,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0xC 2. "PRES2,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0xC 1. "PRES1,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0xC 0. "PRES0,Presampling Enable n" "0: Disable,1: Enable" group.long 0x94++0xB line.long 0x0 "CTR0,Conversion Timing For Precision Inputs" hexmask.long.byte 0x0 0.--7. 1. "INPSAMP,Input Sample Cycles" line.long 0x4 "CTR1,Conversion Timing For Standard Inputs" hexmask.long.byte 0x4 1.--7. 1. "INPSAMP,Specifies the sample duration in terms of conversion clock cycles" bitfld.long 0x4 0. "TSENSOR_SEL,Temperature Sensor Voltage Select" "0: Selects temperature sensor source 0,1: Selects temperature sensor source 1" line.long 0x8 "CTR2,Conversion Timing For External Inputs" hexmask.long.byte 0x8 0.--7. 1. "INPSAMP,Input Sample Cycles" group.long 0xA4++0xB line.long 0x0 "NCMR0,Normal Conversion Enable For Precision Inputs" bitfld.long 0x0 7. "CH7,Precision Input To Be Converted" "0: Input is not selected,1: Input is selected" bitfld.long 0x0 6. "CH6,Precision Input To Be Converted" "0: Input is not selected,1: Input is selected" newline bitfld.long 0x0 5. "CH5,Precision Input To Be Converted" "0: Input is not selected,1: Input is selected" bitfld.long 0x0 4. "CH4,Precision Input To Be Converted" "0: Input is not selected,1: Input is selected" newline bitfld.long 0x0 3. "CH3,Precision Input To Be Converted" "0: Input is not selected,1: Input is selected" bitfld.long 0x0 2. "CH2,Precision Input To Be Converted" "0: Input is not selected,1: Input is selected" newline bitfld.long 0x0 1. "CH1,Precision Input To Be Converted" "0: Input is not selected,1: Input is selected" bitfld.long 0x0 0. "CH0,Precision Input To Be Converted" "0: Input is not selected,1: Input is selected" line.long 0x4 "NCMR1,Normal Conversion Enable For Standard Inputs" bitfld.long 0x4 23. "CH55,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 22. "CH54,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 21. "CH53,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 20. "CH52,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 19. "CH51,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 18. "CH50,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 17. "CH49,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 16. "CH48,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 15. "CH47,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 14. "CH46,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 13. "CH45,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 12. "CH44,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 11. "CH43,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 10. "CH42,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 9. "CH41,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 8. "CH40,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 7. "CH39,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 6. "CH38,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 5. "CH37,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 4. "CH36,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 3. "CH35,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 2. "CH34,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 1. "CH33,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 0. "CH32,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" line.long 0x8 "NCMR2,Normal Conversion Enable For External Inputs" bitfld.long 0x8 31. "CH95,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 30. "CH94,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 29. "CH93,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 28. "CH92,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 27. "CH91,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 26. "CH90,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 25. "CH89,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 24. "CH88,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 23. "CH87,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 22. "CH86,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 21. "CH85,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 20. "CH84,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 19. "CH83,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 18. "CH82,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 17. "CH81,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 16. "CH80,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 15. "CH79,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 14. "CH78,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 13. "CH77,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 12. "CH76,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 11. "CH75,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 10. "CH74,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 9. "CH73,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 8. "CH72,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 7. "CH71,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 6. "CH70,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 5. "CH69,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 4. "CH68,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 3. "CH67,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 2. "CH66,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 1. "CH65,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 0. "CH64,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" group.long 0xB4++0xB line.long 0x0 "JCMR0,Injected Conversion Enable For Precision Inputs" bitfld.long 0x0 7. "CH7,Precision Input To Be Converted" "0: Input 7 is not selected,1: Input 7 is selected" bitfld.long 0x0 6. "CH6,Precision Input To Be Converted" "0: Input 6 is not selected,1: Input 6 is selected" newline bitfld.long 0x0 5. "CH5,Precision Input To Be Converted" "0: Input 5 is not selected,1: Input 5 is selected" bitfld.long 0x0 4. "CH4,Precision Input To Be Converted" "0: Input 4 is not selected,1: Input 4 is selected" newline bitfld.long 0x0 3. "CH3,Precision Input To Be Converted" "0: Input 3 is not selected,1: Input 3 is selected" bitfld.long 0x0 2. "CH2,Precision Input To Be Converted" "0: Input 2 is not selected,1: Input 2 is selected" newline bitfld.long 0x0 1. "CH1,Precision Input To Be Converted" "0: Input 1 is not selected,1: Input 1 is selected" bitfld.long 0x0 0. "CH0,Precision Input To Be Converted" "0: Input 0 is not selected,1: Input 0 is selected" line.long 0x4 "JCMR1,Injected Conversion Enable For Standard Inputs" bitfld.long 0x4 23. "CH55,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 22. "CH54,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 21. "CH53,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 20. "CH52,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 19. "CH51,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 18. "CH50,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 17. "CH49,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 16. "CH48,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 15. "CH47,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 14. "CH46,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 13. "CH45,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 12. "CH44,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 11. "CH43,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 10. "CH42,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 9. "CH41,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 8. "CH40,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 7. "CH39,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 6. "CH38,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 5. "CH37,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 4. "CH36,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 3. "CH35,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 2. "CH34,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 1. "CH33,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 0. "CH32,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" line.long 0x8 "JCMR2,Injected Conversion Enable For External Inputs" bitfld.long 0x8 31. "CH95,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 30. "CH94,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 29. "CH93,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 28. "CH92,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 27. "CH91,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 26. "CH90,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 25. "CH89,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 24. "CH88,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 23. "CH87,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 22. "CH86,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 21. "CH85,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 20. "CH84,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 19. "CH83,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 18. "CH82,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 17. "CH81,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 16. "CH80,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 15. "CH79,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 14. "CH78,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 13. "CH77,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 12. "CH76,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 11. "CH75,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 10. "CH74,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 9. "CH73,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 8. "CH72,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 7. "CH71,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 6. "CH70,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 5. "CH69,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 4. "CH68,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 3. "CH67,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 2. "CH66,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x8 1. "CH65,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x8 0. "CH64,External Input To Be Converted" "0: Input n is not selected,1: Input n is selected" group.long 0xC4++0x7 line.long 0x0 "DSDR,Delay Start Of Data Conversion" hexmask.long.word 0x0 0.--15. 1. "DSD,Delay" line.long 0x4 "PDEDR,Power Down Exit Delay" hexmask.long.byte 0x4 0.--7. 1. "PDED,Delay" rgroup.long 0x100++0x1F line.long 0x0 "PCDR0,Precision Input n Conversion Data" bitfld.long 0x0 19. "VALID,Conversion Data Available" "0: No unread conversion data,1: Unread conversion data is available" bitfld.long 0x0 18. "OVERW,Overwrite Status Flag" "0: No unread data is overwritten,1: Unread data is overwritten" newline bitfld.long 0x0 16.--17. "RESULT,Conversion Data Type" "0: Normal trigger,1: Injected trigger,2: BCTU trigger,?" hexmask.long.word 0x0 0.--15. 1. "CDATA,Conversion Data" line.long 0x4 "PCDR1,Precision Input n Conversion Data" bitfld.long 0x4 19. "VALID,Conversion Data Available" "0: No unread conversion data,1: Unread conversion data is available" bitfld.long 0x4 18. "OVERW,Overwrite Status Flag" "0: No unread data is overwritten,1: Unread data is overwritten" newline bitfld.long 0x4 16.--17. "RESULT,Conversion Data Type" "0: Normal trigger,1: Injected trigger,2: BCTU trigger,?" hexmask.long.word 0x4 0.--15. 1. "CDATA,Conversion Data" line.long 0x8 "PCDR2,Precision Input n Conversion Data" bitfld.long 0x8 19. "VALID,Conversion Data Available" "0: No unread conversion data,1: Unread conversion data is available" bitfld.long 0x8 18. "OVERW,Overwrite Status Flag" "0: No unread data is overwritten,1: Unread data is overwritten" newline bitfld.long 0x8 16.--17. "RESULT,Conversion Data Type" "0: Normal trigger,1: Injected trigger,2: BCTU trigger,?" hexmask.long.word 0x8 0.--15. 1. "CDATA,Conversion Data" line.long 0xC "PCDR3,Precision Input n Conversion Data" bitfld.long 0xC 19. "VALID,Conversion Data Available" "0: No unread conversion data,1: Unread conversion data is available" bitfld.long 0xC 18. "OVERW,Overwrite Status Flag" "0: No unread data is overwritten,1: Unread data is overwritten" newline bitfld.long 0xC 16.--17. "RESULT,Conversion Data Type" "0: Normal trigger,1: Injected trigger,2: BCTU trigger,?" hexmask.long.word 0xC 0.--15. 1. "CDATA,Conversion Data" line.long 0x10 "PCDR4,Precision Input n Conversion Data" bitfld.long 0x10 19. "VALID,Conversion Data Available" "0: No unread conversion data,1: Unread conversion data is available" bitfld.long 0x10 18. "OVERW,Overwrite Status Flag" "0: No unread data is overwritten,1: Unread data is overwritten" newline bitfld.long 0x10 16.--17. "RESULT,Conversion Data Type" "0: Normal trigger,1: Injected trigger,2: BCTU trigger,?" hexmask.long.word 0x10 0.--15. 1. "CDATA,Conversion Data" line.long 0x14 "PCDR5,Precision Input n Conversion Data" bitfld.long 0x14 19. "VALID,Conversion Data Available" "0: No unread conversion data,1: Unread conversion data is available" bitfld.long 0x14 18. "OVERW,Overwrite Status Flag" "0: No unread data is overwritten,1: Unread data is overwritten" newline bitfld.long 0x14 16.--17. "RESULT,Conversion Data Type" "0: Normal trigger,1: Injected trigger,2: BCTU trigger,?" hexmask.long.word 0x14 0.--15. 1. "CDATA,Conversion Data" line.long 0x18 "PCDR6,Precision Input n Conversion Data" bitfld.long 0x18 19. "VALID,Conversion Data Available" "0: No unread conversion data,1: Unread conversion data is available" bitfld.long 0x18 18. "OVERW,Overwrite Status Flag" "0: No unread data is overwritten,1: Unread data is overwritten" newline bitfld.long 0x18 16.--17. "RESULT,Conversion Data Type" "0: Normal trigger,1: Injected trigger,2: BCTU trigger,?" hexmask.long.word 0x18 0.--15. 1. "CDATA,Conversion Data" line.long 0x1C "PCDR7,Precision Input n Conversion Data" bitfld.long 0x1C 19. "VALID,Conversion Data Available" "0: No unread conversion data,1: Unread conversion data is available" bitfld.long 0x1C 18. "OVERW,Overwrite Status Flag" "0: No unread data is overwritten,1: Unread data is overwritten" newline bitfld.long 0x1C 16.--17. "RESULT,Conversion Data Type" "0: Normal trigger,1: Injected trigger,2: BCTU trigger,?" hexmask.long.word 0x1C 0.--15. 1. "CDATA,Conversion Data" repeat 24. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x180)++0x3 line.long 0x0 "ICDR[$1],Standard Input n Conversion Data" bitfld.long 0x0 19. "VALID,Conversion Data Available" "0: No unread conversion data,1: Unread conversion data is available" bitfld.long 0x0 18. "OVERW,Overwrite Status Flag" "0: No unread data is overwritten,1: Unread data is overwritten" newline bitfld.long 0x0 16.--17. "RESULT,Conversion Data Type" "0: Normal trigger,1: Injected trigger,2: BCTU trigger,?" hexmask.long.word 0x0 0.--15. 1. "CDATA,Conversion Data" repeat.end repeat 32. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x200)++0x3 line.long 0x0 "ECDR[$1],External Input n Conversion Data" bitfld.long 0x0 19. "VALID,Conversion Data Available" "0: No unread conversion data,1: Unread conversion data is available" bitfld.long 0x0 18. "OVERW,Overwrite Status Flag" "0: No unread data is overwritten,1: Unread data is overwritten" newline bitfld.long 0x0 16.--17. "RESULT,Conversion Data Type" "0: Normal trigger,1: Injected trigger,2: BCTU trigger,?" hexmask.long.word 0x0 0.--15. 1. "CDATA,Conversion Data" repeat.end group.long 0x2B0++0x3 line.long 0x0 "CWSELRPI0,Channel Analog Watchdog Select For Precision Inputs" bitfld.long 0x0 28.--29. "WSEL_SI0_7,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x0 24.--25. "WSEL_SI0_6,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x0 20.--21. "WSEL_SI0_5,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x0 16.--17. "WSEL_SI0_4,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x0 12.--13. "WSEL_SI0_3,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x0 8.--9. "WSEL_SI0_2,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x0 4.--5. "WSEL_SI0_1,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x0 0.--1. "WSEL_SI0_0,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" rgroup.long 0x2B4++0x3 line.long 0x0 "CWSELRPI1,Channel Analog Watchdog Select For Precision Inputs" group.long 0x2C0++0xB line.long 0x0 "CWSELRSI0,Channel Analog Watchdog Select For Standard Inputs" bitfld.long 0x0 28.--29. "WSEL_SI7_0,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x0 24.--25. "WSEL_SI6_0,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x0 20.--21. "WSEL_SI5_0,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x0 16.--17. "WSEL_SI4_0,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x0 12.--13. "WSEL_SI3_0,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x0 8.--9. "WSEL_SI2_0,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x0 4.--5. "WSEL_SI1_0,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x0 0.--1. "WSEL_SI0_0,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" line.long 0x4 "CWSELRSI1,Channel Analog Watchdog Select For Standard Inputs" bitfld.long 0x4 28.--29. "WSEL_SI7_1,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x4 24.--25. "WSEL_SI6_1,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x4 20.--21. "WSEL_SI5_1,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x4 16.--17. "WSEL_SI4_1,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x4 12.--13. "WSEL_SI3_1,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x4 8.--9. "WSEL_SI2_1,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x4 4.--5. "WSEL_SI1_1,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x4 0.--1. "WSEL_SI0_1,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" line.long 0x8 "CWSELRSI2,Channel Analog Watchdog Select For Standard Inputs" bitfld.long 0x8 28.--29. "WSEL_SI7_2,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x8 24.--25. "WSEL_SI6_2,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x8 20.--21. "WSEL_SI5_2,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x8 16.--17. "WSEL_SI4_2,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x8 12.--13. "WSEL_SI3_2,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x8 8.--9. "WSEL_SI2_2,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x8 4.--5. "WSEL_SI1_2,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x8 0.--1. "WSEL_SI0_2,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" group.long 0x2D0++0x1B line.long 0x0 "CWSELREI0,Channel Analog Watchdog Select For External inputs" bitfld.long 0x0 28.--29. "WSEL_SI0_7,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x0 24.--25. "WSEL_SI0_6,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x0 20.--21. "WSEL_SI0_5,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x0 16.--17. "WSEL_SI0_4,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x0 12.--13. "WSEL_SI0_3,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x0 8.--9. "WSEL_SI0_2,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x0 4.--5. "WSEL_SI0_1,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x0 0.--1. "WSEL_SI0_0,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" line.long 0x4 "CWSELREI1,Channel Analog Watchdog Select For External inputs" bitfld.long 0x4 28.--29. "WSEL_SI1_15,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x4 24.--25. "WSEL_SI1_14,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x4 20.--21. "WSEL_SI1_13,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x4 16.--17. "WSEL_SI1_12,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x4 12.--13. "WSEL_SI1_11,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x4 8.--9. "WSEL_SI1_10,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x4 4.--5. "WSEL_SI1_9,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x4 0.--1. "WSEL_SI1_8,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" line.long 0x8 "CWSELREI2,Channel Analog Watchdog Select For External inputs" bitfld.long 0x8 28.--29. "WSEL_SI2_23,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x8 24.--25. "WSEL_SI2_22,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x8 20.--21. "WSEL_SI2_21,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x8 16.--17. "WSEL_SI2_20,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x8 12.--13. "WSEL_SI2_19,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x8 8.--9. "WSEL_SI2_18,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x8 4.--5. "WSEL_SI2_17,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x8 0.--1. "WSEL_SI2_16,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" line.long 0xC "CWSELREI3,Channel Analog Watchdog Select For External inputs" bitfld.long 0xC 28.--29. "WSEL_SI3_31,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0xC 24.--25. "WSEL_SI3_30,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0xC 20.--21. "WSEL_SI3_29,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0xC 16.--17. "WSEL_SI3_28,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0xC 12.--13. "WSEL_SI3_27,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0xC 8.--9. "WSEL_SI3_26,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0xC 4.--5. "WSEL_SI3_25,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0xC 0.--1. "WSEL_SI3_24,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" line.long 0x10 "CWENR0,Channel Watchdog Enable For Precision Inputs" bitfld.long 0x10 7. "CWEN7,Channel Analog Watchdog Enable 7" "0: Disable,1: Enable" bitfld.long 0x10 6. "CWEN6,Channel Analog Watchdog Enable 6" "0: Disable,1: Enable" newline bitfld.long 0x10 5. "CWEN5,Channel Analog Watchdog Enable 5" "0: Disable,1: Enable" bitfld.long 0x10 4. "CWEN4,Channel Analog Watchdog Enable 4" "0: Disable,1: Enable" newline bitfld.long 0x10 3. "CWEN3,Channel Analog Watchdog Enable 3" "0: Disable,1: Enable" bitfld.long 0x10 2. "CWEN2,Channel Analog Watchdog Enable 2" "0: Disable,1: Enable" newline bitfld.long 0x10 1. "CWEN1,Channel Analog Watchdog Enable 1" "0: Disable,1: Enable" bitfld.long 0x10 0. "CWEN0,Channel Analog Watchdog Enable 0" "0: Disable,1: Enable" line.long 0x14 "CWENR1,Channel Watchdog Enable For Standard Inputs" bitfld.long 0x14 23. "CWEN55,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" bitfld.long 0x14 22. "CWEN54,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" newline bitfld.long 0x14 21. "CWEN53,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" bitfld.long 0x14 20. "CWEN52,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" newline bitfld.long 0x14 19. "CWEN51,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" bitfld.long 0x14 18. "CWEN50,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" newline bitfld.long 0x14 17. "CWEN49,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" bitfld.long 0x14 16. "CWEN48,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" newline bitfld.long 0x14 15. "CWEN47,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" bitfld.long 0x14 14. "CWEN46,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" newline bitfld.long 0x14 13. "CWEN45,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" bitfld.long 0x14 12. "CWEN44,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" newline bitfld.long 0x14 11. "CWEN43,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" bitfld.long 0x14 10. "CWEN42,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" newline bitfld.long 0x14 9. "CWEN41,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" bitfld.long 0x14 8. "CWEN40,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" newline bitfld.long 0x14 7. "CWEN39,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" bitfld.long 0x14 6. "CWEN38,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" newline bitfld.long 0x14 5. "CWEN37,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" bitfld.long 0x14 4. "CWEN36,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" newline bitfld.long 0x14 3. "CWEN35,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" bitfld.long 0x14 2. "CWEN34,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" newline bitfld.long 0x14 1. "CWEN33,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" bitfld.long 0x14 0. "CWEN32,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" line.long 0x18 "CWENR2,Channel Watchdog Enable For External Inputs" bitfld.long 0x18 31. "CWEN95,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" bitfld.long 0x18 30. "CWEN94,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" newline bitfld.long 0x18 29. "CWEN93,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" bitfld.long 0x18 28. "CWEN92,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" newline bitfld.long 0x18 27. "CWEN91,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" bitfld.long 0x18 26. "CWEN90,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" newline bitfld.long 0x18 25. "CWEN89,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" bitfld.long 0x18 24. "CWEN88,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" newline bitfld.long 0x18 23. "CWEN87,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" bitfld.long 0x18 22. "CWEN86,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" newline bitfld.long 0x18 21. "CWEN85,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" bitfld.long 0x18 20. "CWEN84,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" newline bitfld.long 0x18 19. "CWEN83,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" bitfld.long 0x18 18. "CWEN82,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" newline bitfld.long 0x18 17. "CWEN81,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" bitfld.long 0x18 16. "CWEN80,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" newline bitfld.long 0x18 15. "CWEN79,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" bitfld.long 0x18 14. "CWEN78,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" newline bitfld.long 0x18 13. "CWEN77,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" bitfld.long 0x18 12. "CWEN76,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" newline bitfld.long 0x18 11. "CWEN75,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" bitfld.long 0x18 10. "CWEN74,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" newline bitfld.long 0x18 9. "CWEN73,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" bitfld.long 0x18 8. "CWEN72,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" newline bitfld.long 0x18 7. "CWEN71,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" bitfld.long 0x18 6. "CWEN70,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" newline bitfld.long 0x18 5. "CWEN69,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" bitfld.long 0x18 4. "CWEN68,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" newline bitfld.long 0x18 3. "CWEN67,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" bitfld.long 0x18 2. "CWEN66,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" newline bitfld.long 0x18 1. "CWEN65,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" bitfld.long 0x18 0. "CWEN64,Channel Analog Watchdog Enable For External Inputs" "0: Disable,1: Enable" group.long 0x2F0++0xB line.long 0x0 "AWORR0,Analog Watchdog Out Of Range For Precision Inputs" eventfld.long 0x0 7. "AWOR_CH7,Analog Watchdog Out Of Range For Precision Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x0 6. "AWOR_CH6,Analog Watchdog Out Of Range For Precision Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x0 5. "AWOR_CH5,Analog Watchdog Out Of Range For Precision Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x0 4. "AWOR_CH4,Analog Watchdog Out Of Range For Precision Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x0 3. "AWOR_CH3,Analog Watchdog Out Of Range For Precision Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x0 2. "AWOR_CH2,Analog Watchdog Out Of Range For Precision Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x0 1. "AWOR_CH1,Analog Watchdog Out Of Range For Precision Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x0 0. "AWOR_CH0,Analog Watchdog Out Of Range For Precision Inputs" "0: Conversion is within limits,1: Conversion is not within limits" line.long 0x4 "AWORR1,Analog Watchdog Out Of Range For Standard Inputs" eventfld.long 0x4 23. "AWOR_CH23,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x4 22. "AWOR_CH22,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x4 21. "AWOR_CH21,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x4 20. "AWOR_CH20,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x4 19. "AWOR_CH19,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x4 18. "AWOR_CH18,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x4 17. "AWOR_CH17,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x4 16. "AWOR_CH16,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x4 15. "AWOR_CH15,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x4 14. "AWOR_CH14,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x4 13. "AWOR_CH13,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x4 12. "AWOR_CH12,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x4 11. "AWOR_CH11,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x4 10. "AWOR_CH10,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x4 9. "AWOR_CH9,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x4 8. "AWOR_CH8,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x4 7. "AWOR_CH7,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x4 6. "AWOR_CH6,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x4 5. "AWOR_CH5,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x4 4. "AWOR_CH4,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x4 3. "AWOR_CH3,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x4 2. "AWOR_CH2,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x4 1. "AWOR_CH1,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x4 0. "AWOR_CH0,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" line.long 0x8 "AWORR2,Analog Watchdog Out Of Range For External Inputs" eventfld.long 0x8 31. "AWOR_CH31,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x8 30. "AWOR_CH30,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x8 29. "AWOR_CH29,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x8 28. "AWOR_CH28,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x8 27. "AWOR_CH27,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x8 26. "AWOR_CH26,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x8 25. "AWOR_CH25,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x8 24. "AWOR_CH24,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x8 23. "AWOR_CH23,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x8 22. "AWOR_CH22,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x8 21. "AWOR_CH21,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x8 20. "AWOR_CH20,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x8 19. "AWOR_CH19,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x8 18. "AWOR_CH18,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x8 17. "AWOR_CH17,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x8 16. "AWOR_CH16,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x8 15. "AWOR_CH15,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x8 14. "AWOR_CH14,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x8 13. "AWOR_CH13,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x8 12. "AWOR_CH12,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x8 11. "AWOR_CH11,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x8 10. "AWOR_CH10,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x8 9. "AWOR_CH9,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x8 8. "AWOR_CH8,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x8 7. "AWOR_CH7,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x8 6. "AWOR_CH6,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x8 5. "AWOR_CH5,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x8 4. "AWOR_CH4,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x8 3. "AWOR_CH3,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x8 2. "AWOR_CH2,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x8 1. "AWOR_CH1,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x8 0. "AWOR_CH0,Analog Watchdog Out Of Range For External Inputs" "0: Conversion is within limits,1: Conversion is not within limits" group.long 0x340++0x13 line.long 0x0 "STCR1,Self-Test Configuration 1" hexmask.long.byte 0x0 24.--31. 1. "INPSAMP_C,Input Sampling Time Algorithm C" hexmask.long.byte 0x0 8.--15. 1. "INPSAMP_S,Input Sampling Time Algorithm S" line.long 0x4 "STCR2,Self-Test Configuration 2" bitfld.long 0x4 27. "MSKWDSERR,Mask Interrupt Self-Test Watchdog Sequence Error" "0: No interrupt is generated,1: Interrupt is generated" eventfld.long 0x4 26. "SERR,Self-Test Error Injection" "0: Error can be injected,1: Error is being injected" newline bitfld.long 0x4 25. "MSKWDTERR,Mask Interrupt Self-Test Watchdog Timer Error" "0: No interrupt is generated,1: Interrupt is generated" bitfld.long 0x4 23. "MSKST_EOC,Mask Interrupt Self-Test End Of Conversion" "0: No interrupt is generated,1: Interrupt is generated" newline bitfld.long 0x4 18. "MSKWDG_EOA_C,Mask Error Interrupt End Of Algorithm C" "0: No interrupt is generated,1: Interrupt is generated" bitfld.long 0x4 16. "MSKWDG_EOA_S,Mask Error Interrupt End Of Algorithm S" "0: No interrupt is generated,1: Interrupt is generated" newline bitfld.long 0x4 15. "MSKERR_C,Mask Error Interrupt Algorithm C" "0: No interrupt is generated,1: Interrupt is generated" bitfld.long 0x4 13. "MSKERR_S2,Mask Error Interrupt Algorithm S2" "0: No interrupt is generated,1: Interrupt is generated" newline bitfld.long 0x4 12. "MSKERR_S1,Mask Error Interrupt Algorithm S1" "0: No interrupt is generated,1: Interrupt is generated" bitfld.long 0x4 11. "MSKERR_S0,Mask Error Interrupt Algorithm S0" "0: No interrupt is generated,1: Interrupt is generated" newline bitfld.long 0x4 7. "EN,Self-Test Enable" "0: Disable,1: Enable" bitfld.long 0x4 4. "FMA_WDSERR,Fault Mapping Self-Test Watchdog Sequence Error" "0: Noncritical fault line,1: Critical fault line" newline bitfld.long 0x4 3. "FMA_WDTERR,Fault Mapping Self-Test Watchdog Timer Error" "0: Noncritical fault line,1: Critical fault line" bitfld.long 0x4 2. "FMA_C,Fault Mapping Algorithm C" "0: Noncritical fault line,1: Critical fault line" newline bitfld.long 0x4 0. "FMA_S,Fault Mapping Algorithm S" "0: Noncritical fault line,1: Critical fault line" line.long 0x8 "STCR3,Self-Test Configuration 3" bitfld.long 0x8 8.--9. "ALG,Algorithm Selection" "0,1,2,3" hexmask.long.byte 0x8 0.--4. 1. "MSTEP,Algorithm Step" line.long 0xC "STBRR,Self-Test Baud Rate" bitfld.long 0xC 16.--18. "WDT,Self-Test Watchdog Timer" "0: 8192 conversion clock cycles (~0.1 ms at 80 MHz),1: 39 936 conversion clock cycles (~0.5 ms at 80 MHz),2: 79 872 conversion clock cycles (~1 ms at 80 MHz),3: 159 744 conversion clock cycles (~2 ms at 80 MHz),4: 400 384 conversion clock cycles (~5 ms at 80 MHz),5: 799 744 conversion clock cycles (~10 ms at 80 MHz),6: 1 599 488 conversion clock cycles (~20 ms at 80..,7: 3 999 744 conversion clock cycles (~50 ms at 80.." hexmask.long.byte 0xC 0.--7. 1. "BR,Baud Rate" line.long 0x10 "STSR1,Self-Test Status 1" eventfld.long 0x10 27. "WDSERR,Self-Test Watchdog Sequence Error" "0: Algorithm executed in correct sequence,1: Algorithm did not execute in correct sequence" eventfld.long 0x10 25. "WDTERR,Self-Test Watchdog Timer Error" "0: Algorithm finished within the safe time period..,1: Algorithm did not finish within safe time period." newline eventfld.long 0x10 24. "OVERWR,Self-Test Error Status Overwrite" "0: No self-test error status flag overwritten,1: Self-test error status flag overwritten" eventfld.long 0x10 23. "ST_EOC,Self-Test End Of Conversion" "0: Not complete,1: Complete" newline eventfld.long 0x10 18. "WDG_EOA_C,Self-Test Watchdog End Of Algorithm C" "0: Not complete,1: Complete" eventfld.long 0x10 16. "WDG_EOA_S,Self-Test Watchdog End Of Algorithm S" "0: Not complete,1: Complete" newline eventfld.long 0x10 15. "ERR_C,Error Algorithm C" "0: No error,1: Error" eventfld.long 0x10 13. "ERR_S2,Error Algorithm S Step 2" "0: No error,1: Error" newline eventfld.long 0x10 12. "ERR_S1,Error Algorithm S Step 1" "0: No error,1: Error" eventfld.long 0x10 11. "ERR_S0,Error Algorithm S Step 0" "0: No error,1: Error" newline hexmask.long.byte 0x10 5.--9. 1. "STEP_C,Step Of Algorithm C" rgroup.long 0x354++0xB line.long 0x0 "STSR2,Self-Test Status 2" hexmask.long.word 0x0 0.--14. 1. "DATA0,Conversion Data ERR_S1" line.long 0x4 "STSR3,Self-Test Status 3" hexmask.long.word 0x4 16.--30. 1. "DATA1,Conversion Data ERR_S2" hexmask.long.word 0x4 0.--14. 1. "DATA0,Conversion Data ERR_S0" line.long 0x8 "STSR4,Self-Test Status 4" hexmask.long.word 0x8 16.--30. 1. "DATA1,Conversion Data ERR_C" rgroup.long 0x370++0x3 line.long 0x0 "STDR1,Self-Test Conversion Data 1" bitfld.long 0x0 19. "VALID,Valid Conversion Data" "0: No unread conversion data,1: Unread conversion data is available" bitfld.long 0x0 18. "OWERWR,Conversion Data Overwrite Status" "0: Current conversion data not overwritten,1: Current conversion data was overwritten" newline hexmask.long.word 0x0 0.--14. 1. "TCDATA,Test Channel Conversion Data" group.long 0x380++0x3 line.long 0x0 "STAW0R,Self-Test Analog Watchdog S0" bitfld.long 0x0 31. "AWDE,Self-Test Watchdog Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "WDTE,Self-Test Watchdog Timer Enable" "0: Disable,1: Enable" newline hexmask.long.word 0x0 16.--29. 1. "THRH,Higher Threshold Value" hexmask.long.word 0x0 0.--14. 1. "THRL,Lower Threshold Value" group.long 0x388++0x7 line.long 0x0 "STAW1R,Self-Test Analog Watchdog S1" bitfld.long 0x0 31. "AWDE,Self-Test Watchdog Enable" "0: Disable,1: Enable" hexmask.long.word 0x0 0.--14. 1. "THRL,Lower Threshold Value" line.long 0x4 "STAW2R,Self-Test Analog Watchdog S2" bitfld.long 0x4 31. "AWDE,Self-Test Watchdog Enable" "0: Disable,1: Enable" hexmask.long.word 0x4 0.--14. 1. "THRL,Lower Threshold Value" group.long 0x394++0xF line.long 0x0 "STAW4R,Self-Test Analog Watchdog C0" bitfld.long 0x0 31. "AWDE,Self-Test Watchdog Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "WDTE,Self-Test Watchdog Timer Enable" "0: Disable,1: Enable" newline hexmask.long.word 0x0 16.--29. 1. "THRH,Higher Threshold Value" hexmask.long.word 0x0 0.--14. 1. "THRL,Lower Threshold Value" line.long 0x4 "STAW5R,Self-Test Analog Watchdog C" hexmask.long.word 0x4 16.--30. 1. "THRH,Higher Threshold Value" hexmask.long.word 0x4 0.--14. 1. "THRL,Lower Threshold Value" line.long 0x8 "AMSIO,Analog Miscellaneous In/Out register" bitfld.long 0x8 17.--18. "HSEN,High-Speed Enable" "0,1,2,3" bitfld.long 0x8 16. "CMPCTRL0,Compare Control 0" "0,1" line.long 0xC "CALBISTREG,Control And Calibration Status" bitfld.long 0xC 29.--31. "RESN,Conversion Resolution" "0: 14-bit resolution,1: 12-bit resolution,2: 10-bit resolution,3: 8-bit resolution,?,?,?,?" bitfld.long 0xC 27.--28. "TSAMP,Sample Period In Calibration" "0: 22 conversion clock cycles,1: 8 conversion clock cycles,2: 16 conversion clock cycles,3: 32 conversion clock cycles" newline rbitfld.long 0xC 15. "C_T_BUSY,Calibration Busy" "0: Calibration can be started,1: Calibration is in progress" bitfld.long 0xC 14. "CALSTFUL,Calibration And Self-Test Full Range Comparison" "0: Lowest 11 bits are compared.,1: All 15 bits are compared." newline bitfld.long 0xC 5.--6. "NR_SMPL,Calibration Averaging Number" "0: 4 samples,1: 8 samples,2: 16 samples,3: 32 samples" bitfld.long 0xC 4. "AVG_EN,Calibration Averaging Enable" "0: Disable,1: Enable" newline eventfld.long 0xC 3. "TEST_FAIL,Calibration Status" "0: Calibration finished successfully or has not..,1: Calibration did not finish successfully" bitfld.long 0xC 0. "TEST_EN,Calibration Enable" "0: Wait to start a calibration,1: Start calibration" group.long 0x3A8++0x3 line.long 0x0 "OFSGNUSR,Offset And Gain User" hexmask.long.word 0x0 16.--25. 1. "GAIN_USER,Gain User" hexmask.long.byte 0x0 0.--7. 1. "OFFSET_USER,Offset User" group.long 0x3B4++0x3 line.long 0x0 "CAL2,Calibration Value 2" bitfld.long 0x0 15. "ENX,Enable X" "0: Disable,1: Enable" tree.end tree "ADC_2" base ad:0x400A8000 group.long 0x0++0x3 line.long 0x0 "MCR,Main Configuration" bitfld.long 0x0 31. "OWREN,Overwrite Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "WLSIDE,Write Left-Aligned" "0: Right aligned,1: Left-aligned" newline bitfld.long 0x0 29. "MODE,Normal Conversion Mode" "0: Single conversion,1: Continuous conversion" bitfld.long 0x0 27. "TRGEN,External Trigger Enable" "0: Normal trigger input does not start a conversion,1: Normal trigger input starts a conversion" newline bitfld.long 0x0 26. "EDGE,External Trigger Edge Selection" "0: Falling edge,1: Rising edge" bitfld.long 0x0 25. "XSTRTEN,Auxiliary External Start Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 24. "NSTART,Start Normal Conversion" "0: No effect,1: Starts conversion" bitfld.long 0x0 22. "JTRGEN,Injection Trigger Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 21. "JEDGE,Injected Trigger Edge Selection" "0: Falling edge,1: Rising edge" bitfld.long 0x0 20. "JSTART,Injected Start" "0: Injected conversion can be started,1: Starts an injected conversion" newline bitfld.long 0x0 17. "BCTUEN,Body Cross Trigger Unit Enable" "0: Disable,1: Enable" bitfld.long 0x0 16. "BCTU_MODE,Body Cross Trigger Unit Mode Select" "0: Only BCTU can trigger conversion,1: All trigger sources can trigger conversion" newline eventfld.long 0x0 15. "STCL,Self-Test Configuration Lock" "0: Registers are writeable,1: Registers are read-only" bitfld.long 0x0 11. "AVGEN,Averaging Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 9.--10. "AVGS,Averaging Select" "0: 4 conversions,1: 8 conversions,2: 16 conversions,3: 32 conversions" eventfld.long 0x0 7. "ABORTCHAIN,Abort Chain" "0: Undefined,1: Conversion aborted" newline eventfld.long 0x0 6. "ABORT,Abort Conversion" "0: Undefined,1: Conversion aborted" bitfld.long 0x0 5. "ACKO,Auto Clock Off" "0: Clock always active,1: Clock gated" newline bitfld.long 0x0 1.--2. "ADCLKSEL,Conversion Clock (AD_clk) Frequency Selection" "0: Module clock frequency,1: Module clock frequency / 2,2: Module clock frequency / 4,3: Module clock frequency / 8" bitfld.long 0x0 0. "PWDN,Power Down" "0: ADC enters a functional state,1: ADC enters Power Down state" rgroup.long 0x4++0x3 line.long 0x0 "MSR,Main Status" bitfld.long 0x0 31. "CALIBRTD,Calibration Status" "0: Uncalibrated or calibration unsuccessful,1: Calibrated" bitfld.long 0x0 24. "NSTART,Normal Conversion Started" "0: Not in progress,1: In progress" newline bitfld.long 0x0 23. "JABORT,Injected Conversion Aborted" "0: Not aborted,1: Aborted" bitfld.long 0x0 20. "JSTART,Injected Conversion Started" "0: Not an injected conversion,1: Injected conversion" newline bitfld.long 0x0 18. "SELF_TEST_S,Indicates whether an ongoing conversion is for self-test." "0: Not self-test,1: Self-test" bitfld.long 0x0 16. "BCTUSTART,BCTU Conversion Started" "0: Conversion was not triggered by BCTU,1: Ongoing conversion was triggered by BCTU" newline hexmask.long.byte 0x0 9.--15. 1. "CHADDR,Input Under Measure" bitfld.long 0x0 5. "ACKO,Auto Clock-Off On" "0: Inactive,1: Active" newline bitfld.long 0x0 0.--2. "ADCSTATUS,ADC State" "0: Idle,1: Power Down,2: Wait,3: Calibrate,4: Convert,?,6: Done,?" group.long 0x10++0xB line.long 0x0 "ISR,Interrupt Status" eventfld.long 0x0 4. "EOBCTU,End Of BCTU Conversion" "0: No EOBCTU interrupt generated,1: EOBCTU interrupt generated" eventfld.long 0x0 3. "JEOC,End Of Injected Conversion" "0: No JEOC interrupt generated,1: JEOC interrupt generated" newline eventfld.long 0x0 2. "JECH,End Of Injected Chain Conversion" "0: No JECH interrupt generated,1: JECH interrupt generated" eventfld.long 0x0 1. "EOC,End Of Conversion" "0: No EOC interrupt generated,1: Interrupt generated" newline eventfld.long 0x0 0. "ECH,End Of Chain Conversion" "0: Indicates no ECH interrupt generated,1: Indicates an ECH interrupt has been generated" line.long 0x4 "CEOCFR0,Channel End Of Conversion Flag For Precision Inputs" eventfld.long 0x4 7. "PIEOCF7,Precision Input End Of Conversion Flag 7" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x4 6. "PIEOCF6,Precision Input End Of Conversion Flag 6" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x4 5. "PIEOCF5,Precision Input End Of Conversion Flag 5" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x4 4. "PIEOCF4,Precision Input End Of Conversion Flag 4" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x4 3. "PIEOCF3,Precision Input End Of Conversion Flag 3" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x4 2. "PIEOCF2,Precision Input End Of Conversion Flag 2" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x4 1. "PIEOCF1,Precision Input End Of Conversion Flag 1" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x4 0. "PIEOCF0,Precision Input End Of Conversion Flag 0" "0: Conversion not complete,1: Conversion complete" line.long 0x8 "CEOCFR1,Channel End Of Conversion Flag For Standard Inputs" eventfld.long 0x8 23. "SIEOCF23,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 22. "SIEOCF22,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 21. "SIEOCF21,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 20. "SIEOCF20,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 19. "SIEOCF19,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 18. "SIEOCF18,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 17. "SIEOCF17,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 16. "SIEOCF16,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 15. "SIEOCF15,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 14. "SIEOCF14,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 13. "SIEOCF13,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 12. "SIEOCF12,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 11. "SIEOCF11,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 10. "SIEOCF10,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 9. "SIEOCF9,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 8. "SIEOCF8,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 7. "SIEOCF7,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 6. "SIEOCF6,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 5. "SIEOCF5,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 4. "SIEOCF4,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 3. "SIEOCF3,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 2. "SIEOCF2,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" newline eventfld.long 0x8 1. "SIEOCF1,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" eventfld.long 0x8 0. "SIEOCF0,Standard Input End Of Conversion Flag" "0: Conversion not complete,1: Conversion complete" group.long 0x20++0xB line.long 0x0 "IMR,Interrupt Mask" bitfld.long 0x0 4. "MSKEOBCTU,EOBCTU Interrupt Flag Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x0 3. "MSKJEOC,JEOC Interrupt Flag Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x0 2. "MSKJECH,JECH Interrupt Flag Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x0 1. "MSKEOC,EOC Interrupt Flag Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x0 0. "MSKECH,ECH Interrupt Flag Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" line.long 0x4 "CIMR0,EOC Interrupt Enable For Precision Inputs" bitfld.long 0x4 7. "PIEOCIEN7,Precision Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x4 6. "PIEOCIEN6,Precision Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x4 5. "PIEOCIEN5,Precision Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x4 4. "PIEOCIEN4,Precision Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x4 3. "PIEOCIEN3,Precision Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x4 2. "PIEOCIEN2,Precision Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x4 1. "PIEOCIEN1,Precision Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x4 0. "PIEOCIEN0,Precision Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" line.long 0x8 "CIMR1,EOC Interrupt Enable For Standard Inputs" bitfld.long 0x8 23. "SIEOCIEN23,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x8 22. "SIEOCIEN22,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x8 21. "SIEOCIEN21,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x8 20. "SIEOCIEN20,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x8 19. "SIEOCIEN19,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x8 18. "SIEOCIEN18,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x8 17. "SIEOCIEN17,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x8 16. "SIEOCIEN16,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x8 15. "SIEOCIEN15,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x8 14. "SIEOCIEN14,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x8 13. "SIEOCIEN13,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x8 12. "SIEOCIEN12,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x8 11. "SIEOCIEN11,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x8 10. "SIEOCIEN10,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x8 9. "SIEOCIEN9,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x8 8. "SIEOCIEN8,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x8 7. "SIEOCIEN7,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x8 6. "SIEOCIEN6,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x8 5. "SIEOCIEN5,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x8 4. "SIEOCIEN4,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x8 3. "SIEOCIEN3,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x8 2. "SIEOCIEN2,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x8 1. "SIEOCIEN1,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x8 0. "SIEOCIEN0,Standard Input EOC Interrupt Enable" "0: Interrupt is not flagged,1: Interrupt is flagged" group.long 0x30++0x7 line.long 0x0 "WTISR,Analog Watchdog Threshold Interrupt Status" eventfld.long 0x0 31. "HAWIF16,High Analog Watchdog Interrupt Flag 16" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x0 30. "LAWIF16,Low Analog Watchdog Interrupt Flag 16" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x0 29. "HAWIF15,High Analog Watchdog Interrupt Flag 15" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x0 28. "LAWIF15,Low Analog Watchdog Interrupt Flag 15" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x0 27. "HAWIF14,High Analog Watchdog Interrupt Flag 14" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x0 26. "LAWIF14,Low Analog Watchdog Interrupt Flag 14" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x0 25. "HAWIF13,High Analog Watchdog Interrupt Flag 13" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x0 24. "LAWIF13,Low Analog Watchdog Interrupt Flag 13" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x0 23. "HAWIF12,High Analog Watchdog Interrupt Flag 12" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x0 22. "LAWIF12,Low Analog Watchdog Interrupt Flag 12" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x0 21. "HAWIF11,High Analog Watchdog Interrupt Flag 11" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x0 20. "LAWIF11,Low Analog Watchdog Interrupt Flag 11" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x0 19. "HAWIF10,High Analog Watchdog Interrupt Flag 10" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x0 18. "LAWIF10,Low Analog Watchdog Interrupt Flag 10" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x0 17. "HAWIF9,High Analog Watchdog Interrupt Flag 9" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x0 16. "LAWIF9,Low Analog Watchdog Interrupt Flag 9" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x0 15. "HAWIF8,High Analog Watchdog Interrupt Flag 8" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x0 14. "LAWIF8,Low Analog Watchdog Interrupt Flag 8" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x0 13. "HAWIF7,High Analog Watchdog Interrupt Flag 7" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x0 12. "LAWIF7,Low Analog Watchdog Interrupt Flag 7" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x0 11. "HAWIF6,High Analog Watchdog Interrupt Flag 6" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x0 10. "LAWIF6,Low Analog Watchdog Interrupt Flag 6" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x0 9. "HAWIF5,High Analog Watchdog Interrupt Flag 5" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x0 8. "LAWIF5,Low Analog Watchdog Interrupt Flag 5" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x0 7. "HAWIF4,High Analog Watchdog Interrupt Flag 4" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x0 6. "LAWIF4,Low Analog Watchdog Interrupt Flag 4" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x0 5. "HAWIF3,High Analog Watchdog Interrupt Flag 3" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x0 4. "LAWIF3,Low Analog Watchdog Interrupt Flag 3" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x0 3. "HAWIF2,High Analog Watchdog Interrupt Flag 2" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x0 2. "LAWIF2,Low Analog Watchdog Interrupt Flag 2" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." newline eventfld.long 0x0 1. "HAWIF1,High Analog Watchdog Interrupt Flag 1" "0: Conversion result is lower than the specified..,1: Conversion result is higher than the specified.." eventfld.long 0x0 0. "LAWIF1,Low Analog Watchdog Interrupt Flag 1" "0: Conversion result is greater than the specified..,1: Conversion result is lower than the specified.." line.long 0x4 "WTIMR,Analog Watchdog Threshold Interrupt Enable" bitfld.long 0x4 7. "HDWIFEN4,High Data Watchdog Interrupt Flag Enable n" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x4 6. "LAWIFEN4,Low Analog Watchdog Interrupt Flag Enable n" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x4 5. "HDWIFEN3,High Data Watchdog Interrupt Flag Enable n" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x4 4. "LAWIFEN3,Low Analog Watchdog Interrupt Flag Enable n" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x4 3. "HDWIFEN2,High Data Watchdog Interrupt Flag Enable n" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x4 2. "LAWIFEN2,Low Analog Watchdog Interrupt Flag Enable n" "0: Interrupt is not flagged,1: Interrupt is flagged" newline bitfld.long 0x4 1. "HDWIFEN1,High Data Watchdog Interrupt Flag Enable n" "0: Interrupt is not flagged,1: Interrupt is flagged" bitfld.long 0x4 0. "LAWIFEN1,Low Analog Watchdog Interrupt Flag Enable n" "0: Interrupt is not flagged,1: Interrupt is flagged" group.long 0x40++0xB line.long 0x0 "DMAE,Direct Memory Access Configuration" bitfld.long 0x0 1. "DCLR,DMA Clear Request" "0: DMA controller acknowledges the request,1: Conversion data register is read" bitfld.long 0x0 0. "DMAEN,DMA Enable" "0: Disable,1: Enable" line.long 0x4 "DMAR0,DMA Request Enable For Precision Inputs" bitfld.long 0x4 7. "PIDMAREN7,Precision Input DMA Request Enable 7" "0: Not triggered,1: Triggered" bitfld.long 0x4 6. "PIDMAREN6,Precision Input DMA Request Enable 6" "0: Not triggered,1: Triggered" newline bitfld.long 0x4 5. "PIDMAREN5,Precision Input DMA Request Enable 5" "0: Not triggered,1: Triggered" bitfld.long 0x4 4. "PIDMAREN4,Precision Input DMA Request Enable 4" "0: Not triggered,1: Triggered" newline bitfld.long 0x4 3. "PIDMAREN3,Precision Input DMA Request Enable 3" "0: Not triggered,1: Triggered" bitfld.long 0x4 2. "PIDMAREN2,Precision Input DMA Request Enable 2" "0: Not triggered,1: Triggered" newline bitfld.long 0x4 1. "PIDMAREN1,Precision Input DMA Request Enable 1" "0: Not triggered,1: Triggered" bitfld.long 0x4 0. "PIDMAREN0,Precision Input DMA Request Enable 0" "0: Not triggered,1: Triggered" line.long 0x8 "DMAR1,DMA Request Enable For Standard Inputs" bitfld.long 0x8 23. "SIDMAREN23,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" bitfld.long 0x8 22. "SIDMAREN22,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" newline bitfld.long 0x8 21. "SIDMAREN21,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" bitfld.long 0x8 20. "SIDMAREN20,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" newline bitfld.long 0x8 19. "SIDMAREN19,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" bitfld.long 0x8 18. "SIDMAREN18,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" newline bitfld.long 0x8 17. "SIDMAREN17,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" bitfld.long 0x8 16. "SIDMAREN16,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" newline bitfld.long 0x8 15. "SIDMAREN15,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" bitfld.long 0x8 14. "SIDMAREN14,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" newline bitfld.long 0x8 13. "SIDMAREN13,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" bitfld.long 0x8 12. "SIDMAREN12,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" newline bitfld.long 0x8 11. "SIDMAREN11,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" bitfld.long 0x8 10. "SIDMAREN10,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" newline bitfld.long 0x8 9. "SIDMAREN9,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" bitfld.long 0x8 8. "SIDMAREN8,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" newline bitfld.long 0x8 7. "SIDMAREN7,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" bitfld.long 0x8 6. "SIDMAREN6,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" newline bitfld.long 0x8 5. "SIDMAREN5,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" bitfld.long 0x8 4. "SIDMAREN4,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" newline bitfld.long 0x8 3. "SIDMAREN3,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" bitfld.long 0x8 2. "SIDMAREN2,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" newline bitfld.long 0x8 1. "SIDMAREN1,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" bitfld.long 0x8 0. "SIDMAREN0,Standard Input DMA Request Enable n" "0: DMA request is not triggered,1: DMA is request triggered" repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x60)++0x3 line.long 0x0 "THRHLR[$1],Analog Watchdog Threshold Values" hexmask.long.word 0x0 16.--30. 1. "THRH,High Threshold Value" hexmask.long.word 0x0 0.--14. 1. "THRL,Low Threshold Value" repeat.end group.long 0x80++0xB line.long 0x0 "PSCR,Presampling Control" bitfld.long 0x0 3. "PREVAL1,Presampling Voltage Select For Standard Inputs" "0: VREFL,1: VREFH" bitfld.long 0x0 1. "PREVAL0,Presampling Voltage Select For Precision Inputs" "0: VREFL,1: VREFH" newline bitfld.long 0x0 0. "PRECONV,Convert Presampled Value" "0: No conversion after presampling,1: Presampling is followed by conversion" line.long 0x4 "PSR0,Presampling Enable For Precision Inputs" bitfld.long 0x4 7. "PRES7,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x4 6. "PRES6,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x4 5. "PRES5,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x4 4. "PRES4,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x4 3. "PRES3,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x4 2. "PRES2,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x4 1. "PRES1,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x4 0. "PRES0,Presampling Enable n" "0: Disable,1: Enable" line.long 0x8 "PSR1,Presampling Enable For Standard Inputs" bitfld.long 0x8 23. "PRES23,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x8 22. "PRES22,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x8 21. "PRES21,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x8 20. "PRES20,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x8 19. "PRES19,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x8 18. "PRES18,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x8 17. "PRES17,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x8 16. "PRES16,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x8 15. "PRES15,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x8 14. "PRES14,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x8 13. "PRES13,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x8 12. "PRES12,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x8 11. "PRES11,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x8 10. "PRES10,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x8 9. "PRES9,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x8 8. "PRES8,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x8 7. "PRES7,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x8 6. "PRES6,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x8 5. "PRES5,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x8 4. "PRES4,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x8 3. "PRES3,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x8 2. "PRES2,Presampling Enable n" "0: Disable,1: Enable" newline bitfld.long 0x8 1. "PRES1,Presampling Enable n" "0: Disable,1: Enable" bitfld.long 0x8 0. "PRES0,Presampling Enable n" "0: Disable,1: Enable" group.long 0x94++0x7 line.long 0x0 "CTR0,Conversion Timing For Precision Inputs" hexmask.long.byte 0x0 0.--7. 1. "INPSAMP,Input Sample Cycles" line.long 0x4 "CTR1,Conversion Timing For Standard Inputs" hexmask.long.byte 0x4 1.--7. 1. "INPSAMP,Specifies the sample duration in terms of conversion clock cycles" bitfld.long 0x4 0. "TSENSOR_SEL,Temperature Sensor Voltage Select" "0: Selects temperature sensor source 0,1: Selects temperature sensor source 1" group.long 0xA4++0x7 line.long 0x0 "NCMR0,Normal Conversion Enable For Precision Inputs" bitfld.long 0x0 7. "CH7,Precision Input To Be Converted" "0: Input is not selected,1: Input is selected" bitfld.long 0x0 6. "CH6,Precision Input To Be Converted" "0: Input is not selected,1: Input is selected" newline bitfld.long 0x0 5. "CH5,Precision Input To Be Converted" "0: Input is not selected,1: Input is selected" bitfld.long 0x0 4. "CH4,Precision Input To Be Converted" "0: Input is not selected,1: Input is selected" newline bitfld.long 0x0 3. "CH3,Precision Input To Be Converted" "0: Input is not selected,1: Input is selected" bitfld.long 0x0 2. "CH2,Precision Input To Be Converted" "0: Input is not selected,1: Input is selected" newline bitfld.long 0x0 1. "CH1,Precision Input To Be Converted" "0: Input is not selected,1: Input is selected" bitfld.long 0x0 0. "CH0,Precision Input To Be Converted" "0: Input is not selected,1: Input is selected" line.long 0x4 "NCMR1,Normal Conversion Enable For Standard Inputs" bitfld.long 0x4 23. "CH55,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 22. "CH54,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 21. "CH53,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 20. "CH52,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 19. "CH51,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 18. "CH50,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 17. "CH49,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 16. "CH48,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 15. "CH47,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 14. "CH46,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 13. "CH45,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 12. "CH44,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 11. "CH43,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 10. "CH42,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 9. "CH41,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 8. "CH40,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 7. "CH39,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 6. "CH38,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 5. "CH37,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 4. "CH36,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 3. "CH35,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 2. "CH34,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 1. "CH33,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 0. "CH32,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" group.long 0xB4++0x7 line.long 0x0 "JCMR0,Injected Conversion Enable For Precision Inputs" bitfld.long 0x0 7. "CH7,Precision Input To Be Converted" "0: Input 7 is not selected,1: Input 7 is selected" bitfld.long 0x0 6. "CH6,Precision Input To Be Converted" "0: Input 6 is not selected,1: Input 6 is selected" newline bitfld.long 0x0 5. "CH5,Precision Input To Be Converted" "0: Input 5 is not selected,1: Input 5 is selected" bitfld.long 0x0 4. "CH4,Precision Input To Be Converted" "0: Input 4 is not selected,1: Input 4 is selected" newline bitfld.long 0x0 3. "CH3,Precision Input To Be Converted" "0: Input 3 is not selected,1: Input 3 is selected" bitfld.long 0x0 2. "CH2,Precision Input To Be Converted" "0: Input 2 is not selected,1: Input 2 is selected" newline bitfld.long 0x0 1. "CH1,Precision Input To Be Converted" "0: Input 1 is not selected,1: Input 1 is selected" bitfld.long 0x0 0. "CH0,Precision Input To Be Converted" "0: Input 0 is not selected,1: Input 0 is selected" line.long 0x4 "JCMR1,Injected Conversion Enable For Standard Inputs" bitfld.long 0x4 23. "CH55,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 22. "CH54,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 21. "CH53,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 20. "CH52,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 19. "CH51,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 18. "CH50,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 17. "CH49,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 16. "CH48,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 15. "CH47,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 14. "CH46,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 13. "CH45,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 12. "CH44,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 11. "CH43,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 10. "CH42,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 9. "CH41,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 8. "CH40,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 7. "CH39,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 6. "CH38,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 5. "CH37,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 4. "CH36,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 3. "CH35,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 2. "CH34,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" newline bitfld.long 0x4 1. "CH33,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" bitfld.long 0x4 0. "CH32,Standard Input To Be Converted" "0: Input n is not selected,1: Input n is selected" group.long 0xC8++0x3 line.long 0x0 "PDEDR,Power Down Exit Delay" hexmask.long.byte 0x0 0.--7. 1. "PDED,Delay" rgroup.long 0x100++0x1F line.long 0x0 "PCDR0,Precision Input n Conversion Data" bitfld.long 0x0 19. "VALID,Conversion Data Available" "0: No unread conversion data,1: Unread conversion data is available" bitfld.long 0x0 18. "OVERW,Overwrite Status Flag" "0: No unread data is overwritten,1: Unread data is overwritten" newline bitfld.long 0x0 16.--17. "RESULT,Conversion Data Type" "0: Normal trigger,1: Injected trigger,2: BCTU trigger,?" hexmask.long.word 0x0 0.--15. 1. "CDATA,Conversion Data" line.long 0x4 "PCDR1,Precision Input n Conversion Data" bitfld.long 0x4 19. "VALID,Conversion Data Available" "0: No unread conversion data,1: Unread conversion data is available" bitfld.long 0x4 18. "OVERW,Overwrite Status Flag" "0: No unread data is overwritten,1: Unread data is overwritten" newline bitfld.long 0x4 16.--17. "RESULT,Conversion Data Type" "0: Normal trigger,1: Injected trigger,2: BCTU trigger,?" hexmask.long.word 0x4 0.--15. 1. "CDATA,Conversion Data" line.long 0x8 "PCDR2,Precision Input n Conversion Data" bitfld.long 0x8 19. "VALID,Conversion Data Available" "0: No unread conversion data,1: Unread conversion data is available" bitfld.long 0x8 18. "OVERW,Overwrite Status Flag" "0: No unread data is overwritten,1: Unread data is overwritten" newline bitfld.long 0x8 16.--17. "RESULT,Conversion Data Type" "0: Normal trigger,1: Injected trigger,2: BCTU trigger,?" hexmask.long.word 0x8 0.--15. 1. "CDATA,Conversion Data" line.long 0xC "PCDR3,Precision Input n Conversion Data" bitfld.long 0xC 19. "VALID,Conversion Data Available" "0: No unread conversion data,1: Unread conversion data is available" bitfld.long 0xC 18. "OVERW,Overwrite Status Flag" "0: No unread data is overwritten,1: Unread data is overwritten" newline bitfld.long 0xC 16.--17. "RESULT,Conversion Data Type" "0: Normal trigger,1: Injected trigger,2: BCTU trigger,?" hexmask.long.word 0xC 0.--15. 1. "CDATA,Conversion Data" line.long 0x10 "PCDR4,Precision Input n Conversion Data" bitfld.long 0x10 19. "VALID,Conversion Data Available" "0: No unread conversion data,1: Unread conversion data is available" bitfld.long 0x10 18. "OVERW,Overwrite Status Flag" "0: No unread data is overwritten,1: Unread data is overwritten" newline bitfld.long 0x10 16.--17. "RESULT,Conversion Data Type" "0: Normal trigger,1: Injected trigger,2: BCTU trigger,?" hexmask.long.word 0x10 0.--15. 1. "CDATA,Conversion Data" line.long 0x14 "PCDR5,Precision Input n Conversion Data" bitfld.long 0x14 19. "VALID,Conversion Data Available" "0: No unread conversion data,1: Unread conversion data is available" bitfld.long 0x14 18. "OVERW,Overwrite Status Flag" "0: No unread data is overwritten,1: Unread data is overwritten" newline bitfld.long 0x14 16.--17. "RESULT,Conversion Data Type" "0: Normal trigger,1: Injected trigger,2: BCTU trigger,?" hexmask.long.word 0x14 0.--15. 1. "CDATA,Conversion Data" line.long 0x18 "PCDR6,Precision Input n Conversion Data" bitfld.long 0x18 19. "VALID,Conversion Data Available" "0: No unread conversion data,1: Unread conversion data is available" bitfld.long 0x18 18. "OVERW,Overwrite Status Flag" "0: No unread data is overwritten,1: Unread data is overwritten" newline bitfld.long 0x18 16.--17. "RESULT,Conversion Data Type" "0: Normal trigger,1: Injected trigger,2: BCTU trigger,?" hexmask.long.word 0x18 0.--15. 1. "CDATA,Conversion Data" line.long 0x1C "PCDR7,Precision Input n Conversion Data" bitfld.long 0x1C 19. "VALID,Conversion Data Available" "0: No unread conversion data,1: Unread conversion data is available" bitfld.long 0x1C 18. "OVERW,Overwrite Status Flag" "0: No unread data is overwritten,1: Unread data is overwritten" newline bitfld.long 0x1C 16.--17. "RESULT,Conversion Data Type" "0: Normal trigger,1: Injected trigger,2: BCTU trigger,?" hexmask.long.word 0x1C 0.--15. 1. "CDATA,Conversion Data" repeat 24. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x180)++0x3 line.long 0x0 "ICDR[$1],Standard Input n Conversion Data" bitfld.long 0x0 19. "VALID,Conversion Data Available" "0: No unread conversion data,1: Unread conversion data is available" bitfld.long 0x0 18. "OVERW,Overwrite Status Flag" "0: No unread data is overwritten,1: Unread data is overwritten" newline bitfld.long 0x0 16.--17. "RESULT,Conversion Data Type" "0: Normal trigger,1: Injected trigger,2: BCTU trigger,?" hexmask.long.word 0x0 0.--15. 1. "CDATA,Conversion Data" repeat.end group.long 0x2B0++0x3 line.long 0x0 "CWSELRPI0,Channel Analog Watchdog Select For Precision Inputs" bitfld.long 0x0 28.--29. "WSEL_SI0_7,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x0 24.--25. "WSEL_SI0_6,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x0 20.--21. "WSEL_SI0_5,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x0 16.--17. "WSEL_SI0_4,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x0 12.--13. "WSEL_SI0_3,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x0 8.--9. "WSEL_SI0_2,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x0 4.--5. "WSEL_SI0_1,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x0 0.--1. "WSEL_SI0_0,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" rgroup.long 0x2B4++0x3 line.long 0x0 "CWSELRPI1,Channel Analog Watchdog Select For Precision Inputs" group.long 0x2C0++0xB line.long 0x0 "CWSELRSI0,Channel Analog Watchdog Select For Standard Inputs" bitfld.long 0x0 28.--29. "WSEL_SI7_0,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x0 24.--25. "WSEL_SI6_0,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x0 20.--21. "WSEL_SI5_0,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x0 16.--17. "WSEL_SI4_0,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x0 12.--13. "WSEL_SI3_0,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x0 8.--9. "WSEL_SI2_0,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x0 4.--5. "WSEL_SI1_0,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x0 0.--1. "WSEL_SI0_0,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" line.long 0x4 "CWSELRSI1,Channel Analog Watchdog Select For Standard Inputs" bitfld.long 0x4 28.--29. "WSEL_SI7_1,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x4 24.--25. "WSEL_SI6_1,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x4 20.--21. "WSEL_SI5_1,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x4 16.--17. "WSEL_SI4_1,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x4 12.--13. "WSEL_SI3_1,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x4 8.--9. "WSEL_SI2_1,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x4 4.--5. "WSEL_SI1_1,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x4 0.--1. "WSEL_SI0_1,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" line.long 0x8 "CWSELRSI2,Channel Analog Watchdog Select For Standard Inputs" bitfld.long 0x8 28.--29. "WSEL_SI7_2,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x8 24.--25. "WSEL_SI6_2,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x8 20.--21. "WSEL_SI5_2,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x8 16.--17. "WSEL_SI4_2,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x8 12.--13. "WSEL_SI3_2,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x8 8.--9. "WSEL_SI2_2,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" newline bitfld.long 0x8 4.--5. "WSEL_SI1_2,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" bitfld.long 0x8 0.--1. "WSEL_SI0_2,Analog Watchdog Selection" "0: Analog watchdog THRHLR0,1: Analog watchdog THRHLR1,2: Analog watchdog THRHLR2,3: Analog watchdog THRHLR3" group.long 0x2E0++0x7 line.long 0x0 "CWENR0,Channel Watchdog Enable For Precision Inputs" bitfld.long 0x0 7. "CWEN7,Channel Analog Watchdog Enable 7" "0: Disable,1: Enable" bitfld.long 0x0 6. "CWEN6,Channel Analog Watchdog Enable 6" "0: Disable,1: Enable" newline bitfld.long 0x0 5. "CWEN5,Channel Analog Watchdog Enable 5" "0: Disable,1: Enable" bitfld.long 0x0 4. "CWEN4,Channel Analog Watchdog Enable 4" "0: Disable,1: Enable" newline bitfld.long 0x0 3. "CWEN3,Channel Analog Watchdog Enable 3" "0: Disable,1: Enable" bitfld.long 0x0 2. "CWEN2,Channel Analog Watchdog Enable 2" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "CWEN1,Channel Analog Watchdog Enable 1" "0: Disable,1: Enable" bitfld.long 0x0 0. "CWEN0,Channel Analog Watchdog Enable 0" "0: Disable,1: Enable" line.long 0x4 "CWENR1,Channel Watchdog Enable For Standard Inputs" bitfld.long 0x4 23. "CWEN55,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" bitfld.long 0x4 22. "CWEN54,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" newline bitfld.long 0x4 21. "CWEN53,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" bitfld.long 0x4 20. "CWEN52,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" newline bitfld.long 0x4 19. "CWEN51,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" bitfld.long 0x4 18. "CWEN50,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" newline bitfld.long 0x4 17. "CWEN49,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" bitfld.long 0x4 16. "CWEN48,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" newline bitfld.long 0x4 15. "CWEN47,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" bitfld.long 0x4 14. "CWEN46,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" newline bitfld.long 0x4 13. "CWEN45,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" bitfld.long 0x4 12. "CWEN44,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" newline bitfld.long 0x4 11. "CWEN43,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" bitfld.long 0x4 10. "CWEN42,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" newline bitfld.long 0x4 9. "CWEN41,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" bitfld.long 0x4 8. "CWEN40,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" newline bitfld.long 0x4 7. "CWEN39,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" bitfld.long 0x4 6. "CWEN38,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" newline bitfld.long 0x4 5. "CWEN37,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" bitfld.long 0x4 4. "CWEN36,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" newline bitfld.long 0x4 3. "CWEN35,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" bitfld.long 0x4 2. "CWEN34,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" newline bitfld.long 0x4 1. "CWEN33,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" bitfld.long 0x4 0. "CWEN32,Channel Analog Watchdog Enable For Standard Inputs" "0: Disable,1: Enable" group.long 0x2F0++0x7 line.long 0x0 "AWORR0,Analog Watchdog Out Of Range For Precision Inputs" eventfld.long 0x0 7. "AWOR_CH7,Analog Watchdog Out Of Range For Precision Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x0 6. "AWOR_CH6,Analog Watchdog Out Of Range For Precision Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x0 5. "AWOR_CH5,Analog Watchdog Out Of Range For Precision Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x0 4. "AWOR_CH4,Analog Watchdog Out Of Range For Precision Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x0 3. "AWOR_CH3,Analog Watchdog Out Of Range For Precision Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x0 2. "AWOR_CH2,Analog Watchdog Out Of Range For Precision Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x0 1. "AWOR_CH1,Analog Watchdog Out Of Range For Precision Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x0 0. "AWOR_CH0,Analog Watchdog Out Of Range For Precision Inputs" "0: Conversion is within limits,1: Conversion is not within limits" line.long 0x4 "AWORR1,Analog Watchdog Out Of Range For Standard Inputs" eventfld.long 0x4 23. "AWOR_CH23,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x4 22. "AWOR_CH22,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x4 21. "AWOR_CH21,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x4 20. "AWOR_CH20,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x4 19. "AWOR_CH19,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x4 18. "AWOR_CH18,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x4 17. "AWOR_CH17,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x4 16. "AWOR_CH16,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x4 15. "AWOR_CH15,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x4 14. "AWOR_CH14,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x4 13. "AWOR_CH13,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x4 12. "AWOR_CH12,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x4 11. "AWOR_CH11,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x4 10. "AWOR_CH10,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x4 9. "AWOR_CH9,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x4 8. "AWOR_CH8,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x4 7. "AWOR_CH7,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x4 6. "AWOR_CH6,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x4 5. "AWOR_CH5,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x4 4. "AWOR_CH4,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x4 3. "AWOR_CH3,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x4 2. "AWOR_CH2,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" newline eventfld.long 0x4 1. "AWOR_CH1,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" eventfld.long 0x4 0. "AWOR_CH0,Analog Watchdog Out Of Range For Standard Inputs" "0: Conversion is within limits,1: Conversion is not within limits" group.long 0x340++0x13 line.long 0x0 "STCR1,Self-Test Configuration 1" hexmask.long.byte 0x0 24.--31. 1. "INPSAMP_C,Input Sampling Time Algorithm C" hexmask.long.byte 0x0 8.--15. 1. "INPSAMP_S,Input Sampling Time Algorithm S" line.long 0x4 "STCR2,Self-Test Configuration 2" bitfld.long 0x4 27. "MSKWDSERR,Mask Interrupt Self-Test Watchdog Sequence Error" "0: No interrupt is generated,1: Interrupt is generated" eventfld.long 0x4 26. "SERR,Self-Test Error Injection" "0: Error can be injected,1: Error is being injected" newline bitfld.long 0x4 25. "MSKWDTERR,Mask Interrupt Self-Test Watchdog Timer Error" "0: No interrupt is generated,1: Interrupt is generated" bitfld.long 0x4 23. "MSKST_EOC,Mask Interrupt Self-Test End Of Conversion" "0: No interrupt is generated,1: Interrupt is generated" newline bitfld.long 0x4 18. "MSKWDG_EOA_C,Mask Error Interrupt End Of Algorithm C" "0: No interrupt is generated,1: Interrupt is generated" bitfld.long 0x4 16. "MSKWDG_EOA_S,Mask Error Interrupt End Of Algorithm S" "0: No interrupt is generated,1: Interrupt is generated" newline bitfld.long 0x4 15. "MSKERR_C,Mask Error Interrupt Algorithm C" "0: No interrupt is generated,1: Interrupt is generated" bitfld.long 0x4 13. "MSKERR_S2,Mask Error Interrupt Algorithm S2" "0: No interrupt is generated,1: Interrupt is generated" newline bitfld.long 0x4 12. "MSKERR_S1,Mask Error Interrupt Algorithm S1" "0: No interrupt is generated,1: Interrupt is generated" bitfld.long 0x4 11. "MSKERR_S0,Mask Error Interrupt Algorithm S0" "0: No interrupt is generated,1: Interrupt is generated" newline bitfld.long 0x4 7. "EN,Self-Test Enable" "0: Disable,1: Enable" bitfld.long 0x4 4. "FMA_WDSERR,Fault Mapping Self-Test Watchdog Sequence Error" "0: Noncritical fault line,1: Critical fault line" newline bitfld.long 0x4 3. "FMA_WDTERR,Fault Mapping Self-Test Watchdog Timer Error" "0: Noncritical fault line,1: Critical fault line" bitfld.long 0x4 2. "FMA_C,Fault Mapping Algorithm C" "0: Noncritical fault line,1: Critical fault line" newline bitfld.long 0x4 0. "FMA_S,Fault Mapping Algorithm S" "0: Noncritical fault line,1: Critical fault line" line.long 0x8 "STCR3,Self-Test Configuration 3" bitfld.long 0x8 8.--9. "ALG,Algorithm Selection" "0,1,2,3" hexmask.long.byte 0x8 0.--4. 1. "MSTEP,Algorithm Step" line.long 0xC "STBRR,Self-Test Baud Rate" bitfld.long 0xC 16.--18. "WDT,Self-Test Watchdog Timer" "0: 8192 conversion clock cycles (~0.1 ms at 80 MHz),1: 39 936 conversion clock cycles (~0.5 ms at 80 MHz),2: 79 872 conversion clock cycles (~1 ms at 80 MHz),3: 159 744 conversion clock cycles (~2 ms at 80 MHz),4: 400 384 conversion clock cycles (~5 ms at 80 MHz),5: 799 744 conversion clock cycles (~10 ms at 80 MHz),6: 1 599 488 conversion clock cycles (~20 ms at 80..,7: 3 999 744 conversion clock cycles (~50 ms at 80.." hexmask.long.byte 0xC 0.--7. 1. "BR,Baud Rate" line.long 0x10 "STSR1,Self-Test Status 1" eventfld.long 0x10 27. "WDSERR,Self-Test Watchdog Sequence Error" "0: Algorithm executed in correct sequence,1: Algorithm did not execute in correct sequence" eventfld.long 0x10 25. "WDTERR,Self-Test Watchdog Timer Error" "0: Algorithm finished within the safe time period..,1: Algorithm did not finish within safe time period." newline eventfld.long 0x10 24. "OVERWR,Self-Test Error Status Overwrite" "0: No self-test error status flag overwritten,1: Self-test error status flag overwritten" eventfld.long 0x10 23. "ST_EOC,Self-Test End Of Conversion" "0: Not complete,1: Complete" newline eventfld.long 0x10 18. "WDG_EOA_C,Self-Test Watchdog End Of Algorithm C" "0: Not complete,1: Complete" eventfld.long 0x10 16. "WDG_EOA_S,Self-Test Watchdog End Of Algorithm S" "0: Not complete,1: Complete" newline eventfld.long 0x10 15. "ERR_C,Error Algorithm C" "0: No error,1: Error" eventfld.long 0x10 13. "ERR_S2,Error Algorithm S Step 2" "0: No error,1: Error" newline eventfld.long 0x10 12. "ERR_S1,Error Algorithm S Step 1" "0: No error,1: Error" eventfld.long 0x10 11. "ERR_S0,Error Algorithm S Step 0" "0: No error,1: Error" newline hexmask.long.byte 0x10 5.--9. 1. "STEP_C,Step Of Algorithm C" rgroup.long 0x354++0xB line.long 0x0 "STSR2,Self-Test Status 2" hexmask.long.word 0x0 0.--14. 1. "DATA0,Conversion Data ERR_S1" line.long 0x4 "STSR3,Self-Test Status 3" hexmask.long.word 0x4 16.--30. 1. "DATA1,Conversion Data ERR_S2" hexmask.long.word 0x4 0.--14. 1. "DATA0,Conversion Data ERR_S0" line.long 0x8 "STSR4,Self-Test Status 4" hexmask.long.word 0x8 16.--30. 1. "DATA1,Conversion Data ERR_C" rgroup.long 0x370++0x3 line.long 0x0 "STDR1,Self-Test Conversion Data 1" bitfld.long 0x0 19. "VALID,Valid Conversion Data" "0: No unread conversion data,1: Unread conversion data is available" bitfld.long 0x0 18. "OWERWR,Conversion Data Overwrite Status" "0: Current conversion data not overwritten,1: Current conversion data was overwritten" newline hexmask.long.word 0x0 0.--14. 1. "TCDATA,Test Channel Conversion Data" group.long 0x380++0x3 line.long 0x0 "STAW0R,Self-Test Analog Watchdog S0" bitfld.long 0x0 31. "AWDE,Self-Test Watchdog Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "WDTE,Self-Test Watchdog Timer Enable" "0: Disable,1: Enable" newline hexmask.long.word 0x0 16.--29. 1. "THRH,Higher Threshold Value" hexmask.long.word 0x0 0.--14. 1. "THRL,Lower Threshold Value" group.long 0x388++0x7 line.long 0x0 "STAW1R,Self-Test Analog Watchdog S1" bitfld.long 0x0 31. "AWDE,Self-Test Watchdog Enable" "0: Disable,1: Enable" hexmask.long.word 0x0 0.--14. 1. "THRL,Lower Threshold Value" line.long 0x4 "STAW2R,Self-Test Analog Watchdog S2" bitfld.long 0x4 31. "AWDE,Self-Test Watchdog Enable" "0: Disable,1: Enable" hexmask.long.word 0x4 0.--14. 1. "THRL,Lower Threshold Value" group.long 0x394++0xF line.long 0x0 "STAW4R,Self-Test Analog Watchdog C0" bitfld.long 0x0 31. "AWDE,Self-Test Watchdog Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "WDTE,Self-Test Watchdog Timer Enable" "0: Disable,1: Enable" newline hexmask.long.word 0x0 16.--29. 1. "THRH,Higher Threshold Value" hexmask.long.word 0x0 0.--14. 1. "THRL,Lower Threshold Value" line.long 0x4 "STAW5R,Self-Test Analog Watchdog C" hexmask.long.word 0x4 16.--30. 1. "THRH,Higher Threshold Value" hexmask.long.word 0x4 0.--14. 1. "THRL,Lower Threshold Value" line.long 0x8 "AMSIO,Analog Miscellaneous In/Out register" bitfld.long 0x8 17.--18. "HSEN,High-Speed Enable" "0,1,2,3" bitfld.long 0x8 16. "CMPCTRL0,Compare Control 0" "0,1" line.long 0xC "CALBISTREG,Control And Calibration Status" bitfld.long 0xC 29.--31. "RESN,Conversion Resolution" "0: 14-bit resolution,1: 12-bit resolution,2: 10-bit resolution,3: 8-bit resolution,?,?,?,?" bitfld.long 0xC 27.--28. "TSAMP,Sample Period In Calibration" "0: 22 conversion clock cycles,1: 8 conversion clock cycles,2: 16 conversion clock cycles,3: 32 conversion clock cycles" newline rbitfld.long 0xC 15. "C_T_BUSY,Calibration Busy" "0: Calibration can be started,1: Calibration is in progress" bitfld.long 0xC 14. "CALSTFUL,Calibration And Self-Test Full Range Comparison" "0: Lowest 11 bits are compared.,1: All 15 bits are compared." newline bitfld.long 0xC 5.--6. "NR_SMPL,Calibration Averaging Number" "0: 4 samples,1: 8 samples,2: 16 samples,3: 32 samples" bitfld.long 0xC 4. "AVG_EN,Calibration Averaging Enable" "0: Disable,1: Enable" newline eventfld.long 0xC 3. "TEST_FAIL,Calibration Status" "0: Calibration finished successfully or has not..,1: Calibration did not finish successfully" bitfld.long 0xC 0. "TEST_EN,Calibration Enable" "0: Wait to start a calibration,1: Start calibration" group.long 0x3A8++0x3 line.long 0x0 "OFSGNUSR,Offset And Gain User" hexmask.long.word 0x0 16.--25. 1. "GAIN_USER,Gain User" hexmask.long.byte 0x0 0.--7. 1. "OFFSET_USER,Offset User" group.long 0x3B4++0x3 line.long 0x0 "CAL2,Calibration Value 2" bitfld.long 0x0 15. "ENX,Enable X" "0: Disable,1: Enable" tree.end tree.end tree "AES_ACCEL (AES Accelerator)" base ad:0x403D0000 group.long 0x0++0xB line.long 0x0 "LEN0,LEN" hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,TLEN" line.long 0x4 "AILEN0,AAD/IV length" hexmask.long.byte 0x4 24.--30. 1. "IVLEN,IV length" hexmask.long.tbyte 0x4 0.--18. 1. "AAD,Additional Authenticated Data" line.long 0x8 "CRYPT0,CRYPT" hexmask.long.byte 0x8 16.--22. 1. "KSLOT,Key Slot" bitfld.long 0x8 12.--13. "CO,Cryptographic Operation" "0,1,2,3" newline hexmask.long.byte 0x8 8.--11. 1. "CMODE,Cryptographic Mode" hexmask.long.byte 0x8 0.--6. 1. "MASK,MASK" rgroup.long 0xC++0x3 line.long 0x0 "OWNSTAT0,OWN_Status" bitfld.long 0x0 7. "PRIV,Privilege" "0: Non-Privileged.,1: Privileged." bitfld.long 0x0 6. "NS,Non-Secure" "0: Secure.,1: Non-Secure." newline hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID" group.long 0x10++0x3 line.long 0x0 "TLVAL0,Timer Load Value" hexmask.long.word 0x0 0.--15. 1. "TSV,Timer Start Value" rgroup.long 0x14++0x3 line.long 0x0 "CVAL0,Current Timer Value" hexmask.long.word 0x0 0.--15. 1. "TVL,Current Timer Value" group.long 0x18++0xF line.long 0x0 "TCTRL0,Timer Control" bitfld.long 0x0 2. "FRZ,Freeze" "0: Timers continue to run in Debug mode.,1: Timers are stopped in Debug mode." bitfld.long 0x0 1. "TIE,Timer Interrupt Enable" "0: Interrupt requests from the ACCEL timers are..,1: Interrupt is requested whenever TIF is set." newline bitfld.long 0x0 0. "TEN,Timer Enable Bit" "0: ACCEL timer is disabled.,1: ACCEL timer is enabled." line.long 0x4 "TFLG0,Timer Flag" eventfld.long 0x4 0. "TIF,Timer Interrupt Flag" "0: Time-out has not yet occurred.,1: Time-out has occurred." line.long 0x8 "FEEDINTMAP0,FEEDINTMAP" bitfld.long 0x8 3. "FIEN24,FIENn" "0,1" bitfld.long 0x8 2. "FIEN16,FIENn" "0,1" newline bitfld.long 0x8 1. "FIEN8,FIENn" "0,1" bitfld.long 0x8 0. "FIEN0,FIENn" "0,1" line.long 0xC "RESULTINTMAP0,RESULTINTMAP" bitfld.long 0xC 2. "RIEN16,RIENn" "0,1" bitfld.long 0xC 1. "RIEN8,RIENn" "0,1" newline bitfld.long 0xC 0. "RIEN0,RIENn" "0,1" group.long 0x10000++0xB line.long 0x0 "LEN1,LEN" hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,TLEN" line.long 0x4 "AILEN1,AAD/IV length" hexmask.long.byte 0x4 24.--30. 1. "IVLEN,IV length" hexmask.long.tbyte 0x4 0.--18. 1. "AAD,Additional Authenticated Data" line.long 0x8 "CRYPT1,CRYPT" hexmask.long.byte 0x8 16.--22. 1. "KSLOT,Key Slot" bitfld.long 0x8 12.--13. "CO,Cryptographic Operation" "0,1,2,3" newline hexmask.long.byte 0x8 8.--11. 1. "CMODE,Cryptographic Mode" hexmask.long.byte 0x8 0.--6. 1. "MASK,MASK" rgroup.long 0x1000C++0x3 line.long 0x0 "OWNSTAT1,OWN_Status" bitfld.long 0x0 7. "PRIV,Privilege" "0: Non-Privileged.,1: Privileged." bitfld.long 0x0 6. "NS,Non-Secure" "0: Secure.,1: Non-Secure." newline hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID" group.long 0x10010++0x3 line.long 0x0 "TLVAL1,Timer Load Value" hexmask.long.word 0x0 0.--15. 1. "TSV,Timer Start Value" rgroup.long 0x10014++0x3 line.long 0x0 "CVAL1,Current Timer Value" hexmask.long.word 0x0 0.--15. 1. "TVL,Current Timer Value" group.long 0x10018++0xF line.long 0x0 "TCTRL1,Timer Control" bitfld.long 0x0 2. "FRZ,Freeze" "0: Timers continue to run in Debug mode.,1: Timers are stopped in Debug mode." bitfld.long 0x0 1. "TIE,Timer Interrupt Enable" "0: Interrupt requests from the ACCEL timers are..,1: Interrupt is requested whenever TIF is set." newline bitfld.long 0x0 0. "TEN,Timer Enable Bit" "0: ACCEL timer is disabled.,1: ACCEL timer is enabled." line.long 0x4 "TFLG1,Timer Flag" eventfld.long 0x4 0. "TIF,Timer Interrupt Flag" "0: Time-out has not yet occurred.,1: Time-out has occurred." line.long 0x8 "FEEDINTMAP1,FEEDINTMAP" bitfld.long 0x8 3. "FIEN25,FIENn" "0,1" bitfld.long 0x8 2. "FIEN17,FIENn" "0,1" newline bitfld.long 0x8 1. "FIEN9,FIENn" "0,1" bitfld.long 0x8 0. "FIEN1,FIENn" "0,1" line.long 0xC "RESULTINTMAP1,RESULTINTMAP" bitfld.long 0xC 2. "RIEN17,RIENn" "0,1" bitfld.long 0xC 1. "RIEN9,RIENn" "0,1" newline bitfld.long 0xC 0. "RIEN1,RIENn" "0,1" group.long 0x20000++0xB line.long 0x0 "LEN2,LEN" hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,TLEN" line.long 0x4 "AILEN2,AAD/IV length" hexmask.long.byte 0x4 24.--30. 1. "IVLEN,IV length" hexmask.long.tbyte 0x4 0.--18. 1. "AAD,Additional Authenticated Data" line.long 0x8 "CRYPT2,CRYPT" hexmask.long.byte 0x8 16.--22. 1. "KSLOT,Key Slot" bitfld.long 0x8 12.--13. "CO,Cryptographic Operation" "0,1,2,3" newline hexmask.long.byte 0x8 8.--11. 1. "CMODE,Cryptographic Mode" hexmask.long.byte 0x8 0.--6. 1. "MASK,MASK" rgroup.long 0x2000C++0x3 line.long 0x0 "OWNSTAT2,OWN_Status" bitfld.long 0x0 7. "PRIV,Privilege" "0: Non-Privileged.,1: Privileged." bitfld.long 0x0 6. "NS,Non-Secure" "0: Secure.,1: Non-Secure." newline hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID" group.long 0x20010++0x3 line.long 0x0 "TLVAL2,Timer Load Value" hexmask.long.word 0x0 0.--15. 1. "TSV,Timer Start Value" rgroup.long 0x20014++0x3 line.long 0x0 "CVAL2,Current Timer Value" hexmask.long.word 0x0 0.--15. 1. "TVL,Current Timer Value" group.long 0x20018++0xF line.long 0x0 "TCTRL2,Timer Control" bitfld.long 0x0 2. "FRZ,Freeze" "0: Timers continue to run in Debug mode.,1: Timers are stopped in Debug mode." bitfld.long 0x0 1. "TIE,Timer Interrupt Enable" "0: Interrupt requests from the ACCEL timers are..,1: Interrupt is requested whenever TIF is set." newline bitfld.long 0x0 0. "TEN,Timer Enable Bit" "0: ACCEL timer is disabled.,1: ACCEL timer is enabled." line.long 0x4 "TFLG2,Timer Flag" eventfld.long 0x4 0. "TIF,Timer Interrupt Flag" "0: Time-out has not yet occurred.,1: Time-out has occurred." line.long 0x8 "FEEDINTMAP2,FEEDINTMAP" bitfld.long 0x8 3. "FIEN26,FIENn" "0,1" bitfld.long 0x8 2. "FIEN18,FIENn" "0,1" newline bitfld.long 0x8 1. "FIEN10,FIENn" "0,1" bitfld.long 0x8 0. "FIEN2,FIENn" "0,1" line.long 0xC "RESULTINTMAP2,RESULTINTMAP" bitfld.long 0xC 2. "RIEN18,RIENn" "0,1" bitfld.long 0xC 1. "RIEN10,RIENn" "0,1" newline bitfld.long 0xC 0. "RIEN2,RIENn" "0,1" group.long 0x150000++0xB line.long 0x0 "LEN3,LEN" hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,TLEN" line.long 0x4 "AILEN3,AAD/IV length" hexmask.long.byte 0x4 24.--30. 1. "IVLEN,IV length" hexmask.long.tbyte 0x4 0.--18. 1. "AAD,Additional Authenticated Data" line.long 0x8 "CRYPT3,CRYPT" hexmask.long.byte 0x8 16.--22. 1. "KSLOT,Key Slot" bitfld.long 0x8 12.--13. "CO,Cryptographic Operation" "0,1,2,3" newline hexmask.long.byte 0x8 8.--11. 1. "CMODE,Cryptographic Mode" hexmask.long.byte 0x8 0.--6. 1. "MASK,MASK" rgroup.long 0x15000C++0x3 line.long 0x0 "OWNSTAT3,OWN_Status" bitfld.long 0x0 7. "PRIV,Privilege" "0: Non-Privileged.,1: Privileged." bitfld.long 0x0 6. "NS,Non-Secure" "0: Secure.,1: Non-Secure." newline hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID" group.long 0x150010++0x3 line.long 0x0 "TLVAL3,Timer Load Value" hexmask.long.word 0x0 0.--15. 1. "TSV,Timer Start Value" rgroup.long 0x150014++0x3 line.long 0x0 "CVAL3,Current Timer Value" hexmask.long.word 0x0 0.--15. 1. "TVL,Current Timer Value" group.long 0x150018++0xF line.long 0x0 "TCTRL3,Timer Control" bitfld.long 0x0 2. "FRZ,Freeze" "0: Timers continue to run in Debug mode.,1: Timers are stopped in Debug mode." bitfld.long 0x0 1. "TIE,Timer Interrupt Enable" "0: Interrupt requests from the ACCEL timers are..,1: Interrupt is requested whenever TIF is set." newline bitfld.long 0x0 0. "TEN,Timer Enable Bit" "0: ACCEL timer is disabled.,1: ACCEL timer is enabled." line.long 0x4 "TFLG3,Timer Flag" eventfld.long 0x4 0. "TIF,Timer Interrupt Flag" "0: Time-out has not yet occurred.,1: Time-out has occurred." line.long 0x8 "FEEDINTMAP3,FEEDINTMAP" bitfld.long 0x8 3. "FIEN27,FIENn" "0,1" bitfld.long 0x8 2. "FIEN19,FIENn" "0,1" newline bitfld.long 0x8 1. "FIEN11,FIENn" "0,1" bitfld.long 0x8 0. "FIEN3,FIENn" "0,1" line.long 0xC "RESULTINTMAP3,RESULTINTMAP" bitfld.long 0xC 2. "RIEN19,RIENn" "0,1" bitfld.long 0xC 1. "RIEN11,RIENn" "0,1" newline bitfld.long 0xC 0. "RIEN3,RIENn" "0,1" group.long 0x160000++0xB line.long 0x0 "LEN4,LEN" hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,TLEN" line.long 0x4 "AILEN4,AAD/IV length" hexmask.long.byte 0x4 24.--30. 1. "IVLEN,IV length" hexmask.long.tbyte 0x4 0.--18. 1. "AAD,Additional Authenticated Data" line.long 0x8 "CRYPT4,CRYPT" hexmask.long.byte 0x8 16.--22. 1. "KSLOT,Key Slot" bitfld.long 0x8 12.--13. "CO,Cryptographic Operation" "0,1,2,3" newline hexmask.long.byte 0x8 8.--11. 1. "CMODE,Cryptographic Mode" hexmask.long.byte 0x8 0.--6. 1. "MASK,MASK" rgroup.long 0x16000C++0x3 line.long 0x0 "OWNSTAT4,OWN_Status" bitfld.long 0x0 7. "PRIV,Privilege" "0: Non-Privileged.,1: Privileged." bitfld.long 0x0 6. "NS,Non-Secure" "0: Secure.,1: Non-Secure." newline hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID" group.long 0x160010++0x3 line.long 0x0 "TLVAL4,Timer Load Value" hexmask.long.word 0x0 0.--15. 1. "TSV,Timer Start Value" rgroup.long 0x160014++0x3 line.long 0x0 "CVAL4,Current Timer Value" hexmask.long.word 0x0 0.--15. 1. "TVL,Current Timer Value" group.long 0x160018++0xF line.long 0x0 "TCTRL4,Timer Control" bitfld.long 0x0 2. "FRZ,Freeze" "0: Timers continue to run in Debug mode.,1: Timers are stopped in Debug mode." bitfld.long 0x0 1. "TIE,Timer Interrupt Enable" "0: Interrupt requests from the ACCEL timers are..,1: Interrupt is requested whenever TIF is set." newline bitfld.long 0x0 0. "TEN,Timer Enable Bit" "0: ACCEL timer is disabled.,1: ACCEL timer is enabled." line.long 0x4 "TFLG4,Timer Flag" eventfld.long 0x4 0. "TIF,Timer Interrupt Flag" "0: Time-out has not yet occurred.,1: Time-out has occurred." line.long 0x8 "FEEDINTMAP4,FEEDINTMAP" bitfld.long 0x8 3. "FIEN28,FIENn" "0,1" bitfld.long 0x8 2. "FIEN20,FIENn" "0,1" newline bitfld.long 0x8 1. "FIEN12,FIENn" "0,1" bitfld.long 0x8 0. "FIEN4,FIENn" "0,1" line.long 0xC "RESULTINTMAP4,RESULTINTMAP" bitfld.long 0xC 2. "RIEN20,RIENn" "0,1" bitfld.long 0xC 1. "RIEN12,RIENn" "0,1" newline bitfld.long 0xC 0. "RIEN4,RIENn" "0,1" group.long 0x170000++0xB line.long 0x0 "LEN5,LEN" hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,TLEN" line.long 0x4 "AILEN5,AAD/IV length" hexmask.long.byte 0x4 24.--30. 1. "IVLEN,IV length" hexmask.long.tbyte 0x4 0.--18. 1. "AAD,Additional Authenticated Data" line.long 0x8 "CRYPT5,CRYPT" hexmask.long.byte 0x8 16.--22. 1. "KSLOT,Key Slot" bitfld.long 0x8 12.--13. "CO,Cryptographic Operation" "0,1,2,3" newline hexmask.long.byte 0x8 8.--11. 1. "CMODE,Cryptographic Mode" hexmask.long.byte 0x8 0.--6. 1. "MASK,MASK" rgroup.long 0x17000C++0x3 line.long 0x0 "OWNSTAT5,OWN_Status" bitfld.long 0x0 7. "PRIV,Privilege" "0: Non-Privileged.,1: Privileged." bitfld.long 0x0 6. "NS,Non-Secure" "0: Secure.,1: Non-Secure." newline hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID" group.long 0x170010++0x3 line.long 0x0 "TLVAL5,Timer Load Value" hexmask.long.word 0x0 0.--15. 1. "TSV,Timer Start Value" rgroup.long 0x170014++0x3 line.long 0x0 "CVAL5,Current Timer Value" hexmask.long.word 0x0 0.--15. 1. "TVL,Current Timer Value" group.long 0x170018++0xF line.long 0x0 "TCTRL5,Timer Control" bitfld.long 0x0 2. "FRZ,Freeze" "0: Timers continue to run in Debug mode.,1: Timers are stopped in Debug mode." bitfld.long 0x0 1. "TIE,Timer Interrupt Enable" "0: Interrupt requests from the ACCEL timers are..,1: Interrupt is requested whenever TIF is set." newline bitfld.long 0x0 0. "TEN,Timer Enable Bit" "0: ACCEL timer is disabled.,1: ACCEL timer is enabled." line.long 0x4 "TFLG5,Timer Flag" eventfld.long 0x4 0. "TIF,Timer Interrupt Flag" "0: Time-out has not yet occurred.,1: Time-out has occurred." line.long 0x8 "FEEDINTMAP5,FEEDINTMAP" bitfld.long 0x8 3. "FIEN29,FIENn" "0,1" bitfld.long 0x8 2. "FIEN21,FIENn" "0,1" newline bitfld.long 0x8 1. "FIEN13,FIENn" "0,1" bitfld.long 0x8 0. "FIEN5,FIENn" "0,1" line.long 0xC "RESULTINTMAP5,RESULTINTMAP" bitfld.long 0xC 2. "RIEN21,RIENn" "0,1" bitfld.long 0xC 1. "RIEN13,RIENn" "0,1" newline bitfld.long 0xC 0. "RIEN5,RIENn" "0,1" group.long 0x180000++0xB line.long 0x0 "LEN6,LEN" hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,TLEN" line.long 0x4 "AILEN6,AAD/IV length" hexmask.long.byte 0x4 24.--30. 1. "IVLEN,IV length" hexmask.long.tbyte 0x4 0.--18. 1. "AAD,Additional Authenticated Data" line.long 0x8 "CRYPT6,CRYPT" hexmask.long.byte 0x8 16.--22. 1. "KSLOT,Key Slot" bitfld.long 0x8 12.--13. "CO,Cryptographic Operation" "0,1,2,3" newline hexmask.long.byte 0x8 8.--11. 1. "CMODE,Cryptographic Mode" hexmask.long.byte 0x8 0.--6. 1. "MASK,MASK" rgroup.long 0x18000C++0x3 line.long 0x0 "OWNSTAT6,OWN_Status" bitfld.long 0x0 7. "PRIV,Privilege" "0: Non-Privileged.,1: Privileged." bitfld.long 0x0 6. "NS,Non-Secure" "0: Secure.,1: Non-Secure." newline hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID" group.long 0x180010++0x3 line.long 0x0 "TLVAL6,Timer Load Value" hexmask.long.word 0x0 0.--15. 1. "TSV,Timer Start Value" rgroup.long 0x180014++0x3 line.long 0x0 "CVAL6,Current Timer Value" hexmask.long.word 0x0 0.--15. 1. "TVL,Current Timer Value" group.long 0x180018++0xF line.long 0x0 "TCTRL6,Timer Control" bitfld.long 0x0 2. "FRZ,Freeze" "0: Timers continue to run in Debug mode.,1: Timers are stopped in Debug mode." bitfld.long 0x0 1. "TIE,Timer Interrupt Enable" "0: Interrupt requests from the ACCEL timers are..,1: Interrupt is requested whenever TIF is set." newline bitfld.long 0x0 0. "TEN,Timer Enable Bit" "0: ACCEL timer is disabled.,1: ACCEL timer is enabled." line.long 0x4 "TFLG6,Timer Flag" eventfld.long 0x4 0. "TIF,Timer Interrupt Flag" "0: Time-out has not yet occurred.,1: Time-out has occurred." line.long 0x8 "FEEDINTMAP6,FEEDINTMAP" bitfld.long 0x8 3. "FIEN30,FIENn" "0,1" bitfld.long 0x8 2. "FIEN22,FIENn" "0,1" newline bitfld.long 0x8 1. "FIEN14,FIENn" "0,1" bitfld.long 0x8 0. "FIEN6,FIENn" "0,1" line.long 0xC "RESULTINTMAP6,RESULTINTMAP" bitfld.long 0xC 2. "RIEN22,RIENn" "0,1" bitfld.long 0xC 1. "RIEN14,RIENn" "0,1" newline bitfld.long 0xC 0. "RIEN6,RIENn" "0,1" group.long 0x190000++0xB line.long 0x0 "LEN7,LEN" hexmask.long.tbyte 0x0 0.--18. 1. "TLEN,TLEN" line.long 0x4 "AILEN7,AAD/IV length" hexmask.long.byte 0x4 24.--30. 1. "IVLEN,IV length" hexmask.long.tbyte 0x4 0.--18. 1. "AAD,Additional Authenticated Data" line.long 0x8 "CRYPT7,CRYPT" hexmask.long.byte 0x8 16.--22. 1. "KSLOT,Key Slot" bitfld.long 0x8 12.--13. "CO,Cryptographic Operation" "0,1,2,3" newline hexmask.long.byte 0x8 8.--11. 1. "CMODE,Cryptographic Mode" hexmask.long.byte 0x8 0.--6. 1. "MASK,MASK" rgroup.long 0x19000C++0x3 line.long 0x0 "OWNSTAT7,OWN_Status" bitfld.long 0x0 7. "PRIV,Privilege" "0: Non-Privileged.,1: Privileged." bitfld.long 0x0 6. "NS,Non-Secure" "0: Secure.,1: Non-Secure." newline hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID" group.long 0x190010++0x3 line.long 0x0 "TLVAL7,Timer Load Value" hexmask.long.word 0x0 0.--15. 1. "TSV,Timer Start Value" rgroup.long 0x190014++0x3 line.long 0x0 "CVAL7,Current Timer Value" hexmask.long.word 0x0 0.--15. 1. "TVL,Current Timer Value" group.long 0x190018++0xF line.long 0x0 "TCTRL7,Timer Control" bitfld.long 0x0 2. "FRZ,Freeze" "0: Timers continue to run in Debug mode.,1: Timers are stopped in Debug mode." bitfld.long 0x0 1. "TIE,Timer Interrupt Enable" "0: Interrupt requests from the ACCEL timers are..,1: Interrupt is requested whenever TIF is set." newline bitfld.long 0x0 0. "TEN,Timer Enable Bit" "0: ACCEL timer is disabled.,1: ACCEL timer is enabled." line.long 0x4 "TFLG7,Timer Flag" eventfld.long 0x4 0. "TIF,Timer Interrupt Flag" "0: Time-out has not yet occurred.,1: Time-out has occurred." line.long 0x8 "FEEDINTMAP7,FEEDINTMAP" bitfld.long 0x8 3. "FIEN31,FIENn" "0,1" bitfld.long 0x8 2. "FIEN23,FIENn" "0,1" newline bitfld.long 0x8 1. "FIEN15,FIENn" "0,1" bitfld.long 0x8 0. "FIEN7,FIENn" "0,1" line.long 0xC "RESULTINTMAP7,RESULTINTMAP" bitfld.long 0xC 2. "RIEN23,RIENn" "0,1" bitfld.long 0xC 1. "RIEN15,RIENn" "0,1" newline bitfld.long 0xC 0. "RIEN7,RIENn" "0,1" tree.end tree "AXBS (Crossbar Switch)" base ad:0x0 tree "AXBS_FEED" group.long 0x0++0x3 line.long 0x0 "PRS0,Priority Slave Registers" bitfld.long 0x0 0.--2. "M0,Master 0 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or the lowest priority.." group.long 0x10++0x3 line.long 0x0 "CRS0,Control Register" bitfld.long 0x0 31. "RO,Read Only" "0: The slave port's registers are writeable.,1: The slave port's registers are read-only and.." bitfld.long 0x0 30. "HLP,Halt Low Priority" "0: The low-power mode request has the highest..,1: The low-power mode request has the lowest.." newline bitfld.long 0x0 8.--9. "ARB,Arbitration Mode" "0: Fixed priority,1: Round-robin(RR) or rotating priority,?,?" bitfld.long 0x0 4.--5. "PCTL,Parking Control" "0: When no master makes a request the arbiter parks..,1: When no master makes a request the arbiter parks..,2: When no master makes a request the slave port is..,?" newline bitfld.long 0x0 0.--2. "PARK,Park" "0: Park on master port M0.,1: Park on master port M1.,2: Park on master port M2.,3: Park on master port M3.,4: Park on master port M4.,5: Park on master port M5.,6: Park on master port M6.,7: Park on master port M7." group.long 0x100++0x3 line.long 0x0 "PRS1,Priority Slave Registers" bitfld.long 0x0 0.--2. "M0,Master 0 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or the lowest priority.." group.long 0x110++0x3 line.long 0x0 "CRS1,Control Register" bitfld.long 0x0 31. "RO,Read Only" "0: The slave port's registers are writeable.,1: The slave port's registers are read-only and.." bitfld.long 0x0 30. "HLP,Halt Low Priority" "0: The low-power mode request has the highest..,1: The low-power mode request has the lowest.." newline bitfld.long 0x0 8.--9. "ARB,Arbitration Mode" "0: Fixed priority,1: Round-robin(RR) or rotating priority,?,?" bitfld.long 0x0 4.--5. "PCTL,Parking Control" "0: When no master makes a request the arbiter parks..,1: When no master makes a request the arbiter parks..,2: When no master makes a request the slave port is..,?" newline bitfld.long 0x0 0.--2. "PARK,Park" "0: Park on master port M0.,1: Park on master port M1.,2: Park on master port M2.,3: Park on master port M3.,4: Park on master port M4.,5: Park on master port M5.,6: Park on master port M6.,7: Park on master port M7." group.long 0x200++0x3 line.long 0x0 "PRS2,Priority Slave Registers" bitfld.long 0x0 0.--2. "M0,Master 0 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or the lowest priority.." group.long 0x210++0x3 line.long 0x0 "CRS2,Control Register" bitfld.long 0x0 31. "RO,Read Only" "0: The slave port's registers are writeable.,1: The slave port's registers are read-only and.." bitfld.long 0x0 30. "HLP,Halt Low Priority" "0: The low-power mode request has the highest..,1: The low-power mode request has the lowest.." newline bitfld.long 0x0 8.--9. "ARB,Arbitration Mode" "0: Fixed priority,1: Round-robin(RR) or rotating priority,?,?" bitfld.long 0x0 4.--5. "PCTL,Parking Control" "0: When no master makes a request the arbiter parks..,1: When no master makes a request the arbiter parks..,2: When no master makes a request the slave port is..,?" newline bitfld.long 0x0 0.--2. "PARK,Park" "0: Park on master port M0.,1: Park on master port M1.,2: Park on master port M2.,3: Park on master port M3.,4: Park on master port M4.,5: Park on master port M5.,6: Park on master port M6.,7: Park on master port M7." group.long 0x300++0x3 line.long 0x0 "PRS3,Priority Slave Registers" bitfld.long 0x0 0.--2. "M0,Master 0 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or the lowest priority.." group.long 0x310++0x3 line.long 0x0 "CRS3,Control Register" bitfld.long 0x0 31. "RO,Read Only" "0: The slave port's registers are writeable.,1: The slave port's registers are read-only and.." bitfld.long 0x0 30. "HLP,Halt Low Priority" "0: The low-power mode request has the highest..,1: The low-power mode request has the lowest.." newline bitfld.long 0x0 8.--9. "ARB,Arbitration Mode" "0: Fixed priority,1: Round-robin(RR) or rotating priority,?,?" bitfld.long 0x0 4.--5. "PCTL,Parking Control" "0: When no master makes a request the arbiter parks..,1: When no master makes a request the arbiter parks..,2: When no master makes a request the slave port is..,?" newline bitfld.long 0x0 0.--2. "PARK,Park" "0: Park on master port M0.,1: Park on master port M1.,2: Park on master port M2.,3: Park on master port M3.,4: Park on master port M4.,5: Park on master port M5.,6: Park on master port M6.,7: Park on master port M7." group.long 0x400++0x3 line.long 0x0 "PRS4,Priority Slave Registers" bitfld.long 0x0 0.--2. "M0,Master 0 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or the lowest priority.." group.long 0x410++0x3 line.long 0x0 "CRS4,Control Register" bitfld.long 0x0 31. "RO,Read Only" "0: The slave port's registers are writeable.,1: The slave port's registers are read-only and.." bitfld.long 0x0 30. "HLP,Halt Low Priority" "0: The low-power mode request has the highest..,1: The low-power mode request has the lowest.." newline bitfld.long 0x0 8.--9. "ARB,Arbitration Mode" "0: Fixed priority,1: Round-robin(RR) or rotating priority,?,?" bitfld.long 0x0 4.--5. "PCTL,Parking Control" "0: When no master makes a request the arbiter parks..,1: When no master makes a request the arbiter parks..,2: When no master makes a request the slave port is..,?" newline bitfld.long 0x0 0.--2. "PARK,Park" "0: Park on master port M0.,1: Park on master port M1.,2: Park on master port M2.,3: Park on master port M3.,4: Park on master port M4.,5: Park on master port M5.,6: Park on master port M6.,7: Park on master port M7." group.long 0x500++0x3 line.long 0x0 "PRS5,Priority Slave Registers" bitfld.long 0x0 0.--2. "M0,Master 0 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or the lowest priority.." group.long 0x510++0x3 line.long 0x0 "CRS5,Control Register" bitfld.long 0x0 31. "RO,Read Only" "0: The slave port's registers are writeable.,1: The slave port's registers are read-only and.." bitfld.long 0x0 30. "HLP,Halt Low Priority" "0: The low-power mode request has the highest..,1: The low-power mode request has the lowest.." newline bitfld.long 0x0 8.--9. "ARB,Arbitration Mode" "0: Fixed priority,1: Round-robin(RR) or rotating priority,?,?" bitfld.long 0x0 4.--5. "PCTL,Parking Control" "0: When no master makes a request the arbiter parks..,1: When no master makes a request the arbiter parks..,2: When no master makes a request the slave port is..,?" newline bitfld.long 0x0 0.--2. "PARK,Park" "0: Park on master port M0.,1: Park on master port M1.,2: Park on master port M2.,3: Park on master port M3.,4: Park on master port M4.,5: Park on master port M5.,6: Park on master port M6.,7: Park on master port M7." group.long 0x600++0x3 line.long 0x0 "PRS6,Priority Slave Registers" bitfld.long 0x0 0.--2. "M0,Master 0 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or the lowest priority.." group.long 0x610++0x3 line.long 0x0 "CRS6,Control Register" bitfld.long 0x0 31. "RO,Read Only" "0: The slave port's registers are writeable.,1: The slave port's registers are read-only and.." bitfld.long 0x0 30. "HLP,Halt Low Priority" "0: The low-power mode request has the highest..,1: The low-power mode request has the lowest.." newline bitfld.long 0x0 8.--9. "ARB,Arbitration Mode" "0: Fixed priority,1: Round-robin(RR) or rotating priority,?,?" bitfld.long 0x0 4.--5. "PCTL,Parking Control" "0: When no master makes a request the arbiter parks..,1: When no master makes a request the arbiter parks..,2: When no master makes a request the slave port is..,?" newline bitfld.long 0x0 0.--2. "PARK,Park" "0: Park on master port M0.,1: Park on master port M1.,2: Park on master port M2.,3: Park on master port M3.,4: Park on master port M4.,5: Park on master port M5.,6: Park on master port M6.,7: Park on master port M7." group.long 0x700++0x3 line.long 0x0 "PRS7,Priority Slave Registers" bitfld.long 0x0 0.--2. "M0,Master 0 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or the lowest priority.." group.long 0x710++0x3 line.long 0x0 "CRS7,Control Register" bitfld.long 0x0 31. "RO,Read Only" "0: The slave port's registers are writeable.,1: The slave port's registers are read-only and.." bitfld.long 0x0 30. "HLP,Halt Low Priority" "0: The low-power mode request has the highest..,1: The low-power mode request has the lowest.." newline bitfld.long 0x0 8.--9. "ARB,Arbitration Mode" "0: Fixed priority,1: Round-robin(RR) or rotating priority,?,?" bitfld.long 0x0 4.--5. "PCTL,Parking Control" "0: When no master makes a request the arbiter parks..,1: When no master makes a request the arbiter parks..,2: When no master makes a request the slave port is..,?" newline bitfld.long 0x0 0.--2. "PARK,Park" "0: Park on master port M0.,1: Park on master port M1.,2: Park on master port M2.,3: Park on master port M3.,4: Park on master port M4.,5: Park on master port M5.,6: Park on master port M6.,7: Park on master port M7." tree.end tree "AXBS_RESULT" group.long 0x0++0x3 line.long 0x0 "PRS0,Priority Slave Registers" bitfld.long 0x0 4.--6. "M1,Master 1 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." bitfld.long 0x0 0.--2. "M0,Master 0 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or the lowest priority.." group.long 0x10++0x3 line.long 0x0 "CRS0,Control Register" bitfld.long 0x0 31. "RO,Read Only" "0: The slave port's registers are writeable.,1: The slave port's registers are read-only and.." bitfld.long 0x0 30. "HLP,Halt Low Priority" "0: The low-power mode request has the highest..,1: The low-power mode request has the lowest.." newline bitfld.long 0x0 8.--9. "ARB,Arbitration Mode" "0: Fixed priority,1: Round-robin(RR) or rotating priority,?,?" bitfld.long 0x0 4.--5. "PCTL,Parking Control" "0: When no master makes a request the arbiter parks..,1: When no master makes a request the arbiter parks..,2: When no master makes a request the slave port is..,?" newline bitfld.long 0x0 0.--2. "PARK,Park" "0: Park on master port M0.,1: Park on master port M1.,2: Park on master port M2.,3: Park on master port M3.,4: Park on master port M4.,5: Park on master port M5.,6: Park on master port M6.,7: Park on master port M7." group.long 0x100++0x3 line.long 0x0 "PRS1,Priority Slave Registers" bitfld.long 0x0 4.--6. "M1,Master 1 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." bitfld.long 0x0 0.--2. "M0,Master 0 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or the lowest priority.." group.long 0x110++0x3 line.long 0x0 "CRS1,Control Register" bitfld.long 0x0 31. "RO,Read Only" "0: The slave port's registers are writeable.,1: The slave port's registers are read-only and.." bitfld.long 0x0 30. "HLP,Halt Low Priority" "0: The low-power mode request has the highest..,1: The low-power mode request has the lowest.." newline bitfld.long 0x0 8.--9. "ARB,Arbitration Mode" "0: Fixed priority,1: Round-robin(RR) or rotating priority,?,?" bitfld.long 0x0 4.--5. "PCTL,Parking Control" "0: When no master makes a request the arbiter parks..,1: When no master makes a request the arbiter parks..,2: When no master makes a request the slave port is..,?" newline bitfld.long 0x0 0.--2. "PARK,Park" "0: Park on master port M0.,1: Park on master port M1.,2: Park on master port M2.,3: Park on master port M3.,4: Park on master port M4.,5: Park on master port M5.,6: Park on master port M6.,7: Park on master port M7." group.long 0x200++0x3 line.long 0x0 "PRS2,Priority Slave Registers" bitfld.long 0x0 4.--6. "M1,Master 1 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." bitfld.long 0x0 0.--2. "M0,Master 0 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or the lowest priority.." group.long 0x210++0x3 line.long 0x0 "CRS2,Control Register" bitfld.long 0x0 31. "RO,Read Only" "0: The slave port's registers are writeable.,1: The slave port's registers are read-only and.." bitfld.long 0x0 30. "HLP,Halt Low Priority" "0: The low-power mode request has the highest..,1: The low-power mode request has the lowest.." newline bitfld.long 0x0 8.--9. "ARB,Arbitration Mode" "0: Fixed priority,1: Round-robin(RR) or rotating priority,?,?" bitfld.long 0x0 4.--5. "PCTL,Parking Control" "0: When no master makes a request the arbiter parks..,1: When no master makes a request the arbiter parks..,2: When no master makes a request the slave port is..,?" newline bitfld.long 0x0 0.--2. "PARK,Park" "0: Park on master port M0.,1: Park on master port M1.,2: Park on master port M2.,3: Park on master port M3.,4: Park on master port M4.,5: Park on master port M5.,6: Park on master port M6.,7: Park on master port M7." group.long 0x300++0x3 line.long 0x0 "PRS3,Priority Slave Registers" bitfld.long 0x0 4.--6. "M1,Master 1 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." bitfld.long 0x0 0.--2. "M0,Master 0 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or the lowest priority.." group.long 0x310++0x3 line.long 0x0 "CRS3,Control Register" bitfld.long 0x0 31. "RO,Read Only" "0: The slave port's registers are writeable.,1: The slave port's registers are read-only and.." bitfld.long 0x0 30. "HLP,Halt Low Priority" "0: The low-power mode request has the highest..,1: The low-power mode request has the lowest.." newline bitfld.long 0x0 8.--9. "ARB,Arbitration Mode" "0: Fixed priority,1: Round-robin(RR) or rotating priority,?,?" bitfld.long 0x0 4.--5. "PCTL,Parking Control" "0: When no master makes a request the arbiter parks..,1: When no master makes a request the arbiter parks..,2: When no master makes a request the slave port is..,?" newline bitfld.long 0x0 0.--2. "PARK,Park" "0: Park on master port M0.,1: Park on master port M1.,2: Park on master port M2.,3: Park on master port M3.,4: Park on master port M4.,5: Park on master port M5.,6: Park on master port M6.,7: Park on master port M7." group.long 0x400++0x3 line.long 0x0 "PRS4,Priority Slave Registers" bitfld.long 0x0 4.--6. "M1,Master 1 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." bitfld.long 0x0 0.--2. "M0,Master 0 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or the lowest priority.." group.long 0x410++0x3 line.long 0x0 "CRS4,Control Register" bitfld.long 0x0 31. "RO,Read Only" "0: The slave port's registers are writeable.,1: The slave port's registers are read-only and.." bitfld.long 0x0 30. "HLP,Halt Low Priority" "0: The low-power mode request has the highest..,1: The low-power mode request has the lowest.." newline bitfld.long 0x0 8.--9. "ARB,Arbitration Mode" "0: Fixed priority,1: Round-robin(RR) or rotating priority,?,?" bitfld.long 0x0 4.--5. "PCTL,Parking Control" "0: When no master makes a request the arbiter parks..,1: When no master makes a request the arbiter parks..,2: When no master makes a request the slave port is..,?" newline bitfld.long 0x0 0.--2. "PARK,Park" "0: Park on master port M0.,1: Park on master port M1.,2: Park on master port M2.,3: Park on master port M3.,4: Park on master port M4.,5: Park on master port M5.,6: Park on master port M6.,7: Park on master port M7." group.long 0x500++0x3 line.long 0x0 "PRS5,Priority Slave Registers" bitfld.long 0x0 4.--6. "M1,Master 1 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." bitfld.long 0x0 0.--2. "M0,Master 0 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or the lowest priority.." group.long 0x510++0x3 line.long 0x0 "CRS5,Control Register" bitfld.long 0x0 31. "RO,Read Only" "0: The slave port's registers are writeable.,1: The slave port's registers are read-only and.." bitfld.long 0x0 30. "HLP,Halt Low Priority" "0: The low-power mode request has the highest..,1: The low-power mode request has the lowest.." newline bitfld.long 0x0 8.--9. "ARB,Arbitration Mode" "0: Fixed priority,1: Round-robin(RR) or rotating priority,?,?" bitfld.long 0x0 4.--5. "PCTL,Parking Control" "0: When no master makes a request the arbiter parks..,1: When no master makes a request the arbiter parks..,2: When no master makes a request the slave port is..,?" newline bitfld.long 0x0 0.--2. "PARK,Park" "0: Park on master port M0.,1: Park on master port M1.,2: Park on master port M2.,3: Park on master port M3.,4: Park on master port M4.,5: Park on master port M5.,6: Park on master port M6.,7: Park on master port M7." group.long 0x600++0x3 line.long 0x0 "PRS6,Priority Slave Registers" bitfld.long 0x0 4.--6. "M1,Master 1 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." bitfld.long 0x0 0.--2. "M0,Master 0 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or the lowest priority.." group.long 0x610++0x3 line.long 0x0 "CRS6,Control Register" bitfld.long 0x0 31. "RO,Read Only" "0: The slave port's registers are writeable.,1: The slave port's registers are read-only and.." bitfld.long 0x0 30. "HLP,Halt Low Priority" "0: The low-power mode request has the highest..,1: The low-power mode request has the lowest.." newline bitfld.long 0x0 8.--9. "ARB,Arbitration Mode" "0: Fixed priority,1: Round-robin(RR) or rotating priority,?,?" bitfld.long 0x0 4.--5. "PCTL,Parking Control" "0: When no master makes a request the arbiter parks..,1: When no master makes a request the arbiter parks..,2: When no master makes a request the slave port is..,?" newline bitfld.long 0x0 0.--2. "PARK,Park" "0: Park on master port M0.,1: Park on master port M1.,2: Park on master port M2.,3: Park on master port M3.,4: Park on master port M4.,5: Park on master port M5.,6: Park on master port M6.,7: Park on master port M7." group.long 0x700++0x3 line.long 0x0 "PRS7,Priority Slave Registers" bitfld.long 0x0 4.--6. "M1,Master 1 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." bitfld.long 0x0 0.--2. "M0,Master 0 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or the lowest priority.." group.long 0x710++0x3 line.long 0x0 "CRS7,Control Register" bitfld.long 0x0 31. "RO,Read Only" "0: The slave port's registers are writeable.,1: The slave port's registers are read-only and.." bitfld.long 0x0 30. "HLP,Halt Low Priority" "0: The low-power mode request has the highest..,1: The low-power mode request has the lowest.." newline bitfld.long 0x0 8.--9. "ARB,Arbitration Mode" "0: Fixed priority,1: Round-robin(RR) or rotating priority,?,?" bitfld.long 0x0 4.--5. "PCTL,Parking Control" "0: When no master makes a request the arbiter parks..,1: When no master makes a request the arbiter parks..,2: When no master makes a request the slave port is..,?" newline bitfld.long 0x0 0.--2. "PARK,Park" "0: Park on master port M0.,1: Park on master port M1.,2: Park on master port M2.,3: Park on master port M3.,4: Park on master port M4.,5: Park on master port M5.,6: Park on master port M6.,7: Park on master port M7." tree.end tree.end tree "AXBS_LITE (Crossbar Switch Lite)" base ad:0x40200000 group.long 0x0++0x3 line.long 0x0 "PRS0,Priority Slave Registers" bitfld.long 0x0 28.--30. "M7,Master 7 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." bitfld.long 0x0 24.--26. "M6,Master 6 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8the or lowest priority.." newline bitfld.long 0x0 20.--22. "M5,Master 5 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." bitfld.long 0x0 16.--18. "M4,Master 4 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." newline bitfld.long 0x0 12.--14. "M3,Master 3 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8the or lowest priority.." bitfld.long 0x0 8.--10. "M2,Master 2 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8the or lowest priority.." newline bitfld.long 0x0 4.--6. "M1,Master 1 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." bitfld.long 0x0 0.--2. "M0,Master 0 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or the lowest priority.." group.long 0x10++0x3 line.long 0x0 "CRS0,Control Register" bitfld.long 0x0 31. "RO,Read Only" "0: The CRSn and PRSn registers are writeable,1: The CRSn and PRSn registers are read-only and.." bitfld.long 0x0 30. "HLP,Halt Low Priority" "0: The low-power mode request has the highest..,1: The low-power mode request has the lowest.." newline bitfld.long 0x0 23. "HPE7,High Priority Elevation 7" "0: Master high-priority elevation for master 7. is..,1: Master high-priority elevation for master 7. is.." bitfld.long 0x0 22. "HPE6,High Priority Elevation 6" "0: Master high-priority elevation for master 6. is..,1: Master high-priority elevation for master 6. is.." newline bitfld.long 0x0 21. "HPE5,High Priority Elevation 5" "0: Master high-priority elevation for master 5. is..,1: Master high-priority elevation for master 5. is.." bitfld.long 0x0 20. "HPE4,High Priority Elevation 4" "0: Master high-priority elevation for master 4. is..,1: Master high-priority elevation for master 4. is.." newline bitfld.long 0x0 19. "HPE3,High Priority Elevation 3" "0: Master high-priority elevation for master 3. is..,1: Master high-priority elevation for master 3. is.." bitfld.long 0x0 18. "HPE2,High Priority Elevation 2" "0: Master high-priority elevation for master 2. is..,1: Master high-priority elevation for master 2. is.." newline bitfld.long 0x0 17. "HPE1,High Priority Elevation 1" "0: Master high-priority elevation for master 1. is..,1: Master high-priority elevation for master 1. is.." bitfld.long 0x0 16. "HPE0,High Priority Elevation 0" "0: Master high-priority elevation for master 0. is..,1: Master high-priority elevation for master 0. is.." newline bitfld.long 0x0 8.--9. "ARB,Arbitration Mode" "0: Fixed priority,1: Round-robin (rotating) priority,?,?" bitfld.long 0x0 4.--5. "PCTL,Parking Control" "0: When no master makes a request the arbiter parks..,1: When no master makes a request the arbiter parks..,2: Low-power park. When no master makes a request..,?" newline bitfld.long 0x0 0.--2. "PARK,Park" "0: Park on master port M0,1: Park on master port M1,2: Park on master port M2,3: Park on master port M3,4: Park on master port M4,5: Park on master port M5,6: Park on master port M6,7: Park on master port M7" group.long 0x100++0x3 line.long 0x0 "PRS1,Priority Slave Registers" bitfld.long 0x0 28.--30. "M7,Master 7 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." bitfld.long 0x0 24.--26. "M6,Master 6 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8the or lowest priority.." newline bitfld.long 0x0 20.--22. "M5,Master 5 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." bitfld.long 0x0 16.--18. "M4,Master 4 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." newline bitfld.long 0x0 12.--14. "M3,Master 3 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8the or lowest priority.." bitfld.long 0x0 8.--10. "M2,Master 2 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8the or lowest priority.." newline bitfld.long 0x0 4.--6. "M1,Master 1 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." bitfld.long 0x0 0.--2. "M0,Master 0 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or the lowest priority.." group.long 0x110++0x3 line.long 0x0 "CRS1,Control Register" bitfld.long 0x0 31. "RO,Read Only" "0: The CRSn and PRSn registers are writeable,1: The CRSn and PRSn registers are read-only and.." bitfld.long 0x0 30. "HLP,Halt Low Priority" "0: The low-power mode request has the highest..,1: The low-power mode request has the lowest.." newline bitfld.long 0x0 23. "HPE7,High Priority Elevation 7" "0: Master high-priority elevation for master 7. is..,1: Master high-priority elevation for master 7. is.." bitfld.long 0x0 22. "HPE6,High Priority Elevation 6" "0: Master high-priority elevation for master 6. is..,1: Master high-priority elevation for master 6. is.." newline bitfld.long 0x0 21. "HPE5,High Priority Elevation 5" "0: Master high-priority elevation for master 5. is..,1: Master high-priority elevation for master 5. is.." bitfld.long 0x0 20. "HPE4,High Priority Elevation 4" "0: Master high-priority elevation for master 4. is..,1: Master high-priority elevation for master 4. is.." newline bitfld.long 0x0 19. "HPE3,High Priority Elevation 3" "0: Master high-priority elevation for master 3. is..,1: Master high-priority elevation for master 3. is.." bitfld.long 0x0 18. "HPE2,High Priority Elevation 2" "0: Master high-priority elevation for master 2. is..,1: Master high-priority elevation for master 2. is.." newline bitfld.long 0x0 17. "HPE1,High Priority Elevation 1" "0: Master high-priority elevation for master 1. is..,1: Master high-priority elevation for master 1. is.." bitfld.long 0x0 16. "HPE0,High Priority Elevation 0" "0: Master high-priority elevation for master 0. is..,1: Master high-priority elevation for master 0. is.." newline bitfld.long 0x0 8.--9. "ARB,Arbitration Mode" "0: Fixed priority,1: Round-robin (rotating) priority,?,?" bitfld.long 0x0 4.--5. "PCTL,Parking Control" "0: When no master makes a request the arbiter parks..,1: When no master makes a request the arbiter parks..,2: Low-power park. When no master makes a request..,?" newline bitfld.long 0x0 0.--2. "PARK,Park" "0: Park on master port M0,1: Park on master port M1,2: Park on master port M2,3: Park on master port M3,4: Park on master port M4,5: Park on master port M5,6: Park on master port M6,7: Park on master port M7" group.long 0x200++0x3 line.long 0x0 "PRS2,Priority Slave Registers" bitfld.long 0x0 28.--30. "M7,Master 7 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." bitfld.long 0x0 24.--26. "M6,Master 6 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8the or lowest priority.." newline bitfld.long 0x0 20.--22. "M5,Master 5 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." bitfld.long 0x0 16.--18. "M4,Master 4 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." newline bitfld.long 0x0 12.--14. "M3,Master 3 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8the or lowest priority.." bitfld.long 0x0 8.--10. "M2,Master 2 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8the or lowest priority.." newline bitfld.long 0x0 4.--6. "M1,Master 1 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." bitfld.long 0x0 0.--2. "M0,Master 0 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or the lowest priority.." group.long 0x210++0x3 line.long 0x0 "CRS2,Control Register" bitfld.long 0x0 31. "RO,Read Only" "0: The CRSn and PRSn registers are writeable,1: The CRSn and PRSn registers are read-only and.." bitfld.long 0x0 30. "HLP,Halt Low Priority" "0: The low-power mode request has the highest..,1: The low-power mode request has the lowest.." newline bitfld.long 0x0 23. "HPE7,High Priority Elevation 7" "0: Master high-priority elevation for master 7. is..,1: Master high-priority elevation for master 7. is.." bitfld.long 0x0 22. "HPE6,High Priority Elevation 6" "0: Master high-priority elevation for master 6. is..,1: Master high-priority elevation for master 6. is.." newline bitfld.long 0x0 21. "HPE5,High Priority Elevation 5" "0: Master high-priority elevation for master 5. is..,1: Master high-priority elevation for master 5. is.." bitfld.long 0x0 20. "HPE4,High Priority Elevation 4" "0: Master high-priority elevation for master 4. is..,1: Master high-priority elevation for master 4. is.." newline bitfld.long 0x0 19. "HPE3,High Priority Elevation 3" "0: Master high-priority elevation for master 3. is..,1: Master high-priority elevation for master 3. is.." bitfld.long 0x0 18. "HPE2,High Priority Elevation 2" "0: Master high-priority elevation for master 2. is..,1: Master high-priority elevation for master 2. is.." newline bitfld.long 0x0 17. "HPE1,High Priority Elevation 1" "0: Master high-priority elevation for master 1. is..,1: Master high-priority elevation for master 1. is.." bitfld.long 0x0 16. "HPE0,High Priority Elevation 0" "0: Master high-priority elevation for master 0. is..,1: Master high-priority elevation for master 0. is.." newline bitfld.long 0x0 8.--9. "ARB,Arbitration Mode" "0: Fixed priority,1: Round-robin (rotating) priority,?,?" bitfld.long 0x0 4.--5. "PCTL,Parking Control" "0: When no master makes a request the arbiter parks..,1: When no master makes a request the arbiter parks..,2: Low-power park. When no master makes a request..,?" newline bitfld.long 0x0 0.--2. "PARK,Park" "0: Park on master port M0,1: Park on master port M1,2: Park on master port M2,3: Park on master port M3,4: Park on master port M4,5: Park on master port M5,6: Park on master port M6,7: Park on master port M7" group.long 0x300++0x3 line.long 0x0 "PRS3,Priority Slave Registers" bitfld.long 0x0 28.--30. "M7,Master 7 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." bitfld.long 0x0 24.--26. "M6,Master 6 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8the or lowest priority.." newline bitfld.long 0x0 20.--22. "M5,Master 5 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." bitfld.long 0x0 16.--18. "M4,Master 4 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." newline bitfld.long 0x0 12.--14. "M3,Master 3 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8the or lowest priority.." bitfld.long 0x0 8.--10. "M2,Master 2 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8the or lowest priority.." newline bitfld.long 0x0 4.--6. "M1,Master 1 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." bitfld.long 0x0 0.--2. "M0,Master 0 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or the lowest priority.." group.long 0x310++0x3 line.long 0x0 "CRS3,Control Register" bitfld.long 0x0 31. "RO,Read Only" "0: The CRSn and PRSn registers are writeable,1: The CRSn and PRSn registers are read-only and.." bitfld.long 0x0 30. "HLP,Halt Low Priority" "0: The low-power mode request has the highest..,1: The low-power mode request has the lowest.." newline bitfld.long 0x0 23. "HPE7,High Priority Elevation 7" "0: Master high-priority elevation for master 7. is..,1: Master high-priority elevation for master 7. is.." bitfld.long 0x0 22. "HPE6,High Priority Elevation 6" "0: Master high-priority elevation for master 6. is..,1: Master high-priority elevation for master 6. is.." newline bitfld.long 0x0 21. "HPE5,High Priority Elevation 5" "0: Master high-priority elevation for master 5. is..,1: Master high-priority elevation for master 5. is.." bitfld.long 0x0 20. "HPE4,High Priority Elevation 4" "0: Master high-priority elevation for master 4. is..,1: Master high-priority elevation for master 4. is.." newline bitfld.long 0x0 19. "HPE3,High Priority Elevation 3" "0: Master high-priority elevation for master 3. is..,1: Master high-priority elevation for master 3. is.." bitfld.long 0x0 18. "HPE2,High Priority Elevation 2" "0: Master high-priority elevation for master 2. is..,1: Master high-priority elevation for master 2. is.." newline bitfld.long 0x0 17. "HPE1,High Priority Elevation 1" "0: Master high-priority elevation for master 1. is..,1: Master high-priority elevation for master 1. is.." bitfld.long 0x0 16. "HPE0,High Priority Elevation 0" "0: Master high-priority elevation for master 0. is..,1: Master high-priority elevation for master 0. is.." newline bitfld.long 0x0 8.--9. "ARB,Arbitration Mode" "0: Fixed priority,1: Round-robin (rotating) priority,?,?" bitfld.long 0x0 4.--5. "PCTL,Parking Control" "0: When no master makes a request the arbiter parks..,1: When no master makes a request the arbiter parks..,2: Low-power park. When no master makes a request..,?" newline bitfld.long 0x0 0.--2. "PARK,Park" "0: Park on master port M0,1: Park on master port M1,2: Park on master port M2,3: Park on master port M3,4: Park on master port M4,5: Park on master port M5,6: Park on master port M6,7: Park on master port M7" group.long 0x400++0x3 line.long 0x0 "PRS4,Priority Slave Registers" bitfld.long 0x0 28.--30. "M7,Master 7 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." bitfld.long 0x0 24.--26. "M6,Master 6 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8the or lowest priority.." newline bitfld.long 0x0 20.--22. "M5,Master 5 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." bitfld.long 0x0 16.--18. "M4,Master 4 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." newline bitfld.long 0x0 12.--14. "M3,Master 3 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8the or lowest priority.." bitfld.long 0x0 8.--10. "M2,Master 2 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8the or lowest priority.." newline bitfld.long 0x0 4.--6. "M1,Master 1 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." bitfld.long 0x0 0.--2. "M0,Master 0 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or the lowest priority.." group.long 0x410++0x3 line.long 0x0 "CRS4,Control Register" bitfld.long 0x0 31. "RO,Read Only" "0: The CRSn and PRSn registers are writeable,1: The CRSn and PRSn registers are read-only and.." bitfld.long 0x0 30. "HLP,Halt Low Priority" "0: The low-power mode request has the highest..,1: The low-power mode request has the lowest.." newline bitfld.long 0x0 23. "HPE7,High Priority Elevation 7" "0: Master high-priority elevation for master 7. is..,1: Master high-priority elevation for master 7. is.." bitfld.long 0x0 22. "HPE6,High Priority Elevation 6" "0: Master high-priority elevation for master 6. is..,1: Master high-priority elevation for master 6. is.." newline bitfld.long 0x0 21. "HPE5,High Priority Elevation 5" "0: Master high-priority elevation for master 5. is..,1: Master high-priority elevation for master 5. is.." bitfld.long 0x0 20. "HPE4,High Priority Elevation 4" "0: Master high-priority elevation for master 4. is..,1: Master high-priority elevation for master 4. is.." newline bitfld.long 0x0 19. "HPE3,High Priority Elevation 3" "0: Master high-priority elevation for master 3. is..,1: Master high-priority elevation for master 3. is.." bitfld.long 0x0 18. "HPE2,High Priority Elevation 2" "0: Master high-priority elevation for master 2. is..,1: Master high-priority elevation for master 2. is.." newline bitfld.long 0x0 17. "HPE1,High Priority Elevation 1" "0: Master high-priority elevation for master 1. is..,1: Master high-priority elevation for master 1. is.." bitfld.long 0x0 16. "HPE0,High Priority Elevation 0" "0: Master high-priority elevation for master 0. is..,1: Master high-priority elevation for master 0. is.." newline bitfld.long 0x0 8.--9. "ARB,Arbitration Mode" "0: Fixed priority,1: Round-robin (rotating) priority,?,?" bitfld.long 0x0 4.--5. "PCTL,Parking Control" "0: When no master makes a request the arbiter parks..,1: When no master makes a request the arbiter parks..,2: Low-power park. When no master makes a request..,?" newline bitfld.long 0x0 0.--2. "PARK,Park" "0: Park on master port M0,1: Park on master port M1,2: Park on master port M2,3: Park on master port M3,4: Park on master port M4,5: Park on master port M5,6: Park on master port M6,7: Park on master port M7" group.long 0x500++0x3 line.long 0x0 "PRS5,Priority Slave Registers" bitfld.long 0x0 28.--30. "M7,Master 7 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." bitfld.long 0x0 24.--26. "M6,Master 6 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8the or lowest priority.." newline bitfld.long 0x0 20.--22. "M5,Master 5 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." bitfld.long 0x0 16.--18. "M4,Master 4 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." newline bitfld.long 0x0 12.--14. "M3,Master 3 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8the or lowest priority.." bitfld.long 0x0 8.--10. "M2,Master 2 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8the or lowest priority.." newline bitfld.long 0x0 4.--6. "M1,Master 1 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." bitfld.long 0x0 0.--2. "M0,Master 0 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or the lowest priority.." group.long 0x510++0x3 line.long 0x0 "CRS5,Control Register" bitfld.long 0x0 31. "RO,Read Only" "0: The CRSn and PRSn registers are writeable,1: The CRSn and PRSn registers are read-only and.." bitfld.long 0x0 30. "HLP,Halt Low Priority" "0: The low-power mode request has the highest..,1: The low-power mode request has the lowest.." newline bitfld.long 0x0 23. "HPE7,High Priority Elevation 7" "0: Master high-priority elevation for master 7. is..,1: Master high-priority elevation for master 7. is.." bitfld.long 0x0 22. "HPE6,High Priority Elevation 6" "0: Master high-priority elevation for master 6. is..,1: Master high-priority elevation for master 6. is.." newline bitfld.long 0x0 21. "HPE5,High Priority Elevation 5" "0: Master high-priority elevation for master 5. is..,1: Master high-priority elevation for master 5. is.." bitfld.long 0x0 20. "HPE4,High Priority Elevation 4" "0: Master high-priority elevation for master 4. is..,1: Master high-priority elevation for master 4. is.." newline bitfld.long 0x0 19. "HPE3,High Priority Elevation 3" "0: Master high-priority elevation for master 3. is..,1: Master high-priority elevation for master 3. is.." bitfld.long 0x0 18. "HPE2,High Priority Elevation 2" "0: Master high-priority elevation for master 2. is..,1: Master high-priority elevation for master 2. is.." newline bitfld.long 0x0 17. "HPE1,High Priority Elevation 1" "0: Master high-priority elevation for master 1. is..,1: Master high-priority elevation for master 1. is.." bitfld.long 0x0 16. "HPE0,High Priority Elevation 0" "0: Master high-priority elevation for master 0. is..,1: Master high-priority elevation for master 0. is.." newline bitfld.long 0x0 8.--9. "ARB,Arbitration Mode" "0: Fixed priority,1: Round-robin (rotating) priority,?,?" bitfld.long 0x0 4.--5. "PCTL,Parking Control" "0: When no master makes a request the arbiter parks..,1: When no master makes a request the arbiter parks..,2: Low-power park. When no master makes a request..,?" newline bitfld.long 0x0 0.--2. "PARK,Park" "0: Park on master port M0,1: Park on master port M1,2: Park on master port M2,3: Park on master port M3,4: Park on master port M4,5: Park on master port M5,6: Park on master port M6,7: Park on master port M7" group.long 0x600++0x3 line.long 0x0 "PRS6,Priority Slave Registers" bitfld.long 0x0 28.--30. "M7,Master 7 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." bitfld.long 0x0 24.--26. "M6,Master 6 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8the or lowest priority.." newline bitfld.long 0x0 20.--22. "M5,Master 5 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." bitfld.long 0x0 16.--18. "M4,Master 4 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." newline bitfld.long 0x0 12.--14. "M3,Master 3 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8the or lowest priority.." bitfld.long 0x0 8.--10. "M2,Master 2 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8the or lowest priority.." newline bitfld.long 0x0 4.--6. "M1,Master 1 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." bitfld.long 0x0 0.--2. "M0,Master 0 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or the lowest priority.." group.long 0x610++0x3 line.long 0x0 "CRS6,Control Register" bitfld.long 0x0 31. "RO,Read Only" "0: The CRSn and PRSn registers are writeable,1: The CRSn and PRSn registers are read-only and.." bitfld.long 0x0 30. "HLP,Halt Low Priority" "0: The low-power mode request has the highest..,1: The low-power mode request has the lowest.." newline bitfld.long 0x0 23. "HPE7,High Priority Elevation 7" "0: Master high-priority elevation for master 7. is..,1: Master high-priority elevation for master 7. is.." bitfld.long 0x0 22. "HPE6,High Priority Elevation 6" "0: Master high-priority elevation for master 6. is..,1: Master high-priority elevation for master 6. is.." newline bitfld.long 0x0 21. "HPE5,High Priority Elevation 5" "0: Master high-priority elevation for master 5. is..,1: Master high-priority elevation for master 5. is.." bitfld.long 0x0 20. "HPE4,High Priority Elevation 4" "0: Master high-priority elevation for master 4. is..,1: Master high-priority elevation for master 4. is.." newline bitfld.long 0x0 19. "HPE3,High Priority Elevation 3" "0: Master high-priority elevation for master 3. is..,1: Master high-priority elevation for master 3. is.." bitfld.long 0x0 18. "HPE2,High Priority Elevation 2" "0: Master high-priority elevation for master 2. is..,1: Master high-priority elevation for master 2. is.." newline bitfld.long 0x0 17. "HPE1,High Priority Elevation 1" "0: Master high-priority elevation for master 1. is..,1: Master high-priority elevation for master 1. is.." bitfld.long 0x0 16. "HPE0,High Priority Elevation 0" "0: Master high-priority elevation for master 0. is..,1: Master high-priority elevation for master 0. is.." newline bitfld.long 0x0 8.--9. "ARB,Arbitration Mode" "0: Fixed priority,1: Round-robin (rotating) priority,?,?" bitfld.long 0x0 4.--5. "PCTL,Parking Control" "0: When no master makes a request the arbiter parks..,1: When no master makes a request the arbiter parks..,2: Low-power park. When no master makes a request..,?" newline bitfld.long 0x0 0.--2. "PARK,Park" "0: Park on master port M0,1: Park on master port M1,2: Park on master port M2,3: Park on master port M3,4: Park on master port M4,5: Park on master port M5,6: Park on master port M6,7: Park on master port M7" group.long 0x700++0x3 line.long 0x0 "PRS7,Priority Slave Registers" bitfld.long 0x0 28.--30. "M7,Master 7 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." bitfld.long 0x0 24.--26. "M6,Master 6 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8the or lowest priority.." newline bitfld.long 0x0 20.--22. "M5,Master 5 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." bitfld.long 0x0 16.--18. "M4,Master 4 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." newline bitfld.long 0x0 12.--14. "M3,Master 3 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8the or lowest priority.." bitfld.long 0x0 8.--10. "M2,Master 2 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8the or lowest priority.." newline bitfld.long 0x0 4.--6. "M1,Master 1 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or lowest priority when.." bitfld.long 0x0 0.--2. "M0,Master 0 Priority" "0: This master has level 1 or highest priority when..,1: This master has level 2 priority when accessing..,2: This master has level 3 priority when accessing..,3: This master has level 4 priority when accessing..,4: This master has level 5 priority when accessing..,5: This master has level 6 priority when accessing..,6: This master has level 7 priority when accessing..,7: This master has level 8 or the lowest priority.." group.long 0x710++0x3 line.long 0x0 "CRS7,Control Register" bitfld.long 0x0 31. "RO,Read Only" "0: The CRSn and PRSn registers are writeable,1: The CRSn and PRSn registers are read-only and.." bitfld.long 0x0 30. "HLP,Halt Low Priority" "0: The low-power mode request has the highest..,1: The low-power mode request has the lowest.." newline bitfld.long 0x0 23. "HPE7,High Priority Elevation 7" "0: Master high-priority elevation for master 7. is..,1: Master high-priority elevation for master 7. is.." bitfld.long 0x0 22. "HPE6,High Priority Elevation 6" "0: Master high-priority elevation for master 6. is..,1: Master high-priority elevation for master 6. is.." newline bitfld.long 0x0 21. "HPE5,High Priority Elevation 5" "0: Master high-priority elevation for master 5. is..,1: Master high-priority elevation for master 5. is.." bitfld.long 0x0 20. "HPE4,High Priority Elevation 4" "0: Master high-priority elevation for master 4. is..,1: Master high-priority elevation for master 4. is.." newline bitfld.long 0x0 19. "HPE3,High Priority Elevation 3" "0: Master high-priority elevation for master 3. is..,1: Master high-priority elevation for master 3. is.." bitfld.long 0x0 18. "HPE2,High Priority Elevation 2" "0: Master high-priority elevation for master 2. is..,1: Master high-priority elevation for master 2. is.." newline bitfld.long 0x0 17. "HPE1,High Priority Elevation 1" "0: Master high-priority elevation for master 1. is..,1: Master high-priority elevation for master 1. is.." bitfld.long 0x0 16. "HPE0,High Priority Elevation 0" "0: Master high-priority elevation for master 0. is..,1: Master high-priority elevation for master 0. is.." newline bitfld.long 0x0 8.--9. "ARB,Arbitration Mode" "0: Fixed priority,1: Round-robin (rotating) priority,?,?" bitfld.long 0x0 4.--5. "PCTL,Parking Control" "0: When no master makes a request the arbiter parks..,1: When no master makes a request the arbiter parks..,2: Low-power park. When no master makes a request..,?" newline bitfld.long 0x0 0.--2. "PARK,Park" "0: Park on master port M0,1: Park on master port M1,2: Park on master port M2,3: Park on master port M3,4: Park on master port M4,5: Park on master port M5,6: Park on master port M6,7: Park on master port M7" tree.end tree "BCTU (Body Cross-triggering Unit)" base ad:0x40084000 group.long 0x0++0x3 line.long 0x0 "MCR,Module Configuration" bitfld.long 0x0 31. "Software_Reset,Software Reset" "0: Deasserts,1: Asserts" bitfld.long 0x0 30. "MDIS,Module Disable" "0: Enable (normal operation),1: Disable (low-power operation)" newline bitfld.long 0x0 29. "FRZ,Debug Freeze" "0: Disables,1: Enables" bitfld.long 0x0 26. "GTRGEN,Global Trigger Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 18. "DMA2,Enable ADC2DR DMA" "0: Disable,1: Enable" bitfld.long 0x0 17. "DMA1,Enable ADC1DR DMA" "0: Disable,1: Enable" newline bitfld.long 0x0 16. "DMA0,Enable ADC0DR DMA" "0: Disable,1: Enable" bitfld.long 0x0 7. "TRGEN,Trigger Interrupt Request Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 5. "LIST_IEN,CL Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x0 2. "IEN2,Interrupt Enable For ADC2DR" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "IEN1,Interrupt Enable For ADC1DR" "0: Disable,1: Enable" bitfld.long 0x0 0. "IEN0,Interrupt Enable For ADC0DR" "0: Disable,1: Enable" group.long 0x8++0x3 line.long 0x0 "MSR,Module Status" bitfld.long 0x0 31. "TRGF_CLR,TRGF Clear" "0: No action,1: Changes to 0" bitfld.long 0x0 26. "LIST2_Last_CLR,CL 2 Last Clear" "0: No action,1: Changes to 0" newline bitfld.long 0x0 25. "LIST1_Last_CLR,CL 1 Last Clear" "0: No action,1: Changes to 0" bitfld.long 0x0 24. "LIST0_Last_CLR,CL 0 Last Clear" "0: No action,1: Changes to 0" newline bitfld.long 0x0 22. "DATAOVR2_CLR,DATAOVR2 Clear" "0: No action,1: Changes to 0" bitfld.long 0x0 21. "DATAOVR1_CLR,DATAOVR1 Clear" "0: No action,1: Changes to 0" newline bitfld.long 0x0 20. "DATAOVR0_CLR,DATAOVR0 Clear" "0: No action,1: Changes to 0" bitfld.long 0x0 18. "NDATA2_CLR,New Data Clear" "0: No action,1: Changes to 0" newline bitfld.long 0x0 17. "NDATA1_CLR,New Data Clear" "0: No action,1: Changes to 0" bitfld.long 0x0 16. "NDATA0_CLR,New Data Clear" "0: No action,1: Changes to 0" newline rbitfld.long 0x0 15. "TRGF,Trigger Flag" "0: No ADC triggered,1: An ADC was triggered" rbitfld.long 0x0 10. "LIST2_Last,CL 2 Last Conversion" "0: Last conversion not complete,1: Last conversion complete" newline rbitfld.long 0x0 9. "LIST1_Last,CL 1 Last Conversion" "0: Last conversion not complete,1: Last conversion complete" rbitfld.long 0x0 8. "LIST0_Last,CL 0 Last Conversion" "0: Last conversion not complete,1: Last conversion complete" newline rbitfld.long 0x0 6. "DATAOVR2,Data Overrun 2" "0: Data not overwritten,1: Data overwritten" rbitfld.long 0x0 5. "DATAOVR1,Data Overrun 1" "0: Data not overwritten,1: Data overwritten" newline rbitfld.long 0x0 4. "DATAOVR0,Data Overrun 0" "0: Data not overwritten,1: Data overwritten" rbitfld.long 0x0 2. "NDATA2,New Data 2" "0: Not available,1: Available" newline rbitfld.long 0x0 1. "NDATA1,New Data 1" "0: Not available,1: Available" rbitfld.long 0x0 0. "NDATA0,New Data 0" "0: Not available,1: Available" repeat 72. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x18)++0x3 line.long 0x0 "TRGCFG_[$1],Trigger Configuration" bitfld.long 0x0 31. "LOOP,Loop" "0: Disable,1: Enable" bitfld.long 0x0 28.--30. "DATA_DEST,Data Destination" "0: ADC-specific data registers,1: FIFO1,2: FIFO2,?,?,?,?,?" newline bitfld.long 0x0 15. "TRIGEN,Trigger Enable" "0: Disable,1: Enable" eventfld.long 0x0 14. "TRG_FLAG,Trigger Flag" "0: No action,1: Changes to 0" newline bitfld.long 0x0 13. "TRS,Trigger Resolution" "0: Single conversion,1: CL conversions" bitfld.long 0x0 10. "ADC_SEL2,ADC Select 2" "0: Deselects,1: Selects" newline bitfld.long 0x0 9. "ADC_SEL1,ADC Select 1" "0: Deselects,1: Selects" bitfld.long 0x0 8. "ADC_SEL0,ADC Select 0" "0: Deselects,1: Selects" newline hexmask.long.byte 0x0 0.--6. 1. "CHANNEL_VALUE_OR_LADDR,Channel or CL Address" repeat.end group.long 0x228++0xF line.long 0x0 "WRPROT,Write Protection" hexmask.long.byte 0x0 0.--3. 1. "PROTEC_CODE,Protection Code" line.long 0x4 "SFTRGR1,Software Trigger 1" bitfld.long 0x4 31. "SFTRG31,Software Trigger 31" "0: No effect,1: Trigger conversion" bitfld.long 0x4 30. "SFTRG30,Software Trigger 30" "0: No effect,1: Trigger conversion" newline bitfld.long 0x4 29. "SFTRG29,Software Trigger 29" "0: No effect,1: Trigger conversion" bitfld.long 0x4 28. "SFTRG28,Software Trigger 28" "0: No effect,1: Trigger conversion" newline bitfld.long 0x4 27. "SFTRG27,Software Trigger 27" "0: No effect,1: Trigger conversion" bitfld.long 0x4 26. "SFTRG26,Software Trigger 26" "0: No effect,1: Trigger conversion" newline bitfld.long 0x4 25. "SFTRG25,Software Trigger 25" "0: No effect,1: Trigger conversion" bitfld.long 0x4 24. "SFTRG24,Software Trigger 24" "0: No effect,1: Trigger conversion" newline bitfld.long 0x4 23. "SFTRG23,Software Trigger 23" "0: No effect,1: Trigger conversion" bitfld.long 0x4 22. "SFTRG22,Software Trigger 22" "0: No effect,1: Trigger conversion" newline bitfld.long 0x4 21. "SFTRG21,Software Trigger 21" "0: No effect,1: Trigger conversion" bitfld.long 0x4 20. "SFTRG20,Software Trigger 20" "0: No effect,1: Trigger conversion" newline bitfld.long 0x4 19. "SFTRG19,Software Trigger 19" "0: No effect,1: Trigger conversion" bitfld.long 0x4 18. "SFTRG18,Software Trigger 18" "0: No effect,1: Trigger conversion" newline bitfld.long 0x4 17. "SFTRG17,Software Trigger 17" "0: No effect,1: Trigger conversion" bitfld.long 0x4 16. "SFTRG16,Software Trigger 16" "0: No effect,1: Trigger conversion" newline bitfld.long 0x4 15. "SFTRG15,Software Trigger 15" "0: No effect,1: Trigger conversion" bitfld.long 0x4 14. "SFTRG14,Software Trigger 14" "0: No effect,1: Trigger conversion" newline bitfld.long 0x4 13. "SFTRG13,Software Trigger 13" "0: No effect,1: Trigger conversion" bitfld.long 0x4 12. "SFTRG12,Software Trigger 12" "0: No effect,1: Trigger conversion" newline bitfld.long 0x4 11. "SFTRG11,Software Trigger 11" "0: No effect,1: Trigger conversion" bitfld.long 0x4 10. "SFTRG10,Software Trigger 10" "0: No effect,1: Trigger conversion" newline bitfld.long 0x4 9. "SFTRG9,Software Trigger 9" "0: No effect,1: Trigger conversion" bitfld.long 0x4 8. "SFTRG8,Software Trigger 8" "0: No effect,1: Trigger conversion" newline bitfld.long 0x4 7. "SFTRG7,Software Trigger 7" "0: No effect,1: Trigger conversion" bitfld.long 0x4 6. "SFTRG6,Software Trigger 6" "0: No effect,1: Trigger conversion" newline bitfld.long 0x4 5. "SFTRG5,Software Trigger 5" "0: No effect,1: Trigger conversion" bitfld.long 0x4 4. "SFTRG4,Software Trigger 4" "0: No effect,1: Trigger conversion" newline bitfld.long 0x4 3. "SFTRG3,Software Trigger 3" "0: No effect,1: Trigger conversion" bitfld.long 0x4 2. "SFTRG2,Software Trigger 2" "0: No effect,1: Trigger conversion" newline bitfld.long 0x4 1. "SFTRG1,Software Trigger 1" "0: No effect,1: Trigger conversion" bitfld.long 0x4 0. "SFTRG0,Software Trigger 0" "0: No effect,1: Trigger conversion" line.long 0x8 "SFTRGR2,Software Trigger 2" bitfld.long 0x8 31. "SFTRG63,Software Trigger 63" "0: No effect,1: Trigger conversion" bitfld.long 0x8 30. "SFTRG62,Software Trigger 62" "0: No effect,1: Trigger conversion" newline bitfld.long 0x8 29. "SFTRG61,Software Trigger 61" "0: No effect,1: Trigger conversion" bitfld.long 0x8 28. "SFTRG60,Software Trigger 60" "0: No effect,1: Trigger conversion" newline bitfld.long 0x8 27. "SFTRG59,Software Trigger 59" "0: No effect,1: Trigger conversion" bitfld.long 0x8 26. "SFTRG58,Software Trigger 58" "0: No effect,1: Trigger conversion" newline bitfld.long 0x8 25. "SFTRG57,Software Trigger 57" "0: No effect,1: Trigger conversion" bitfld.long 0x8 24. "SFTRG56,Software Trigger 56" "0: No effect,1: Trigger conversion" newline bitfld.long 0x8 23. "SFTRG55,Software Trigger 55" "0: No effect,1: Trigger conversion" bitfld.long 0x8 22. "SFTRG54,Software Trigger 54" "0: No effect,1: Trigger conversion" newline bitfld.long 0x8 21. "SFTRG53,Software Trigger 53" "0: No effect,1: Trigger conversion" bitfld.long 0x8 20. "SFTRG52,Software Trigger 52" "0: No effect,1: Trigger conversion" newline bitfld.long 0x8 19. "SFTRG51,Software Trigger 51" "0: No effect,1: Trigger conversion" bitfld.long 0x8 18. "SFTRG50,Software Trigger 50" "0: No effect,1: Trigger conversion" newline bitfld.long 0x8 17. "SFTRG49,Software Trigger 49" "0: No effect,1: Trigger conversion" bitfld.long 0x8 16. "SFTRG48,Software Trigger 48" "0: No effect,1: Trigger conversion" newline bitfld.long 0x8 15. "SFTRG47,Software Trigger 47" "0: No effect,1: Trigger conversion" bitfld.long 0x8 14. "SFTRG46,Software Trigger 46" "0: No effect,1: Trigger conversion" newline bitfld.long 0x8 13. "SFTRG45,Software Trigger 45" "0: No effect,1: Trigger conversion" bitfld.long 0x8 12. "SFTRG44,Software Trigger 44" "0: No effect,1: Trigger conversion" newline bitfld.long 0x8 11. "SFTRG43,Software Trigger 43" "0: No effect,1: Trigger conversion" bitfld.long 0x8 10. "SFTRG42,Software Trigger 42" "0: No effect,1: Trigger conversion" newline bitfld.long 0x8 9. "SFTRG41,Software Trigger 41" "0: No effect,1: Trigger conversion" bitfld.long 0x8 8. "SFTRG40,Software Trigger 40" "0: No effect,1: Trigger conversion" newline bitfld.long 0x8 7. "SFTRG39,Software Trigger 39" "0: No effect,1: Trigger conversion" bitfld.long 0x8 6. "SFTRG38,Software Trigger 38" "0: No effect,1: Trigger conversion" newline bitfld.long 0x8 5. "SFTRG37,Software Trigger 37" "0: No effect,1: Trigger conversion" bitfld.long 0x8 4. "SFTRG36,Software Trigger 36" "0: No effect,1: Trigger conversion" newline bitfld.long 0x8 3. "SFTRG35,Software Trigger 35" "0: No effect,1: Trigger conversion" bitfld.long 0x8 2. "SFTRG34,Software Trigger 34" "0: No effect,1: Trigger conversion" newline bitfld.long 0x8 1. "SFTRG33,Software Trigger 33" "0: No effect,1: Trigger conversion" bitfld.long 0x8 0. "SFTRG32,Software Trigger 32" "0: No effect,1: Trigger conversion" line.long 0xC "SFTRGR3,Software Trigger 3" bitfld.long 0xC 7. "SFTRG71,Software Trigger 71" "0: No effect,1: Trigger conversion" bitfld.long 0xC 6. "SFTRG70,Software Trigger 70" "0: No effect,1: Trigger conversion" newline bitfld.long 0xC 5. "SFTRG69,Software Trigger 69" "0: No effect,1: Trigger conversion" bitfld.long 0xC 4. "SFTRG68,Software Trigger 68" "0: No effect,1: Trigger conversion" newline bitfld.long 0xC 3. "SFTRG67,Software Trigger 67" "0: No effect,1: Trigger conversion" bitfld.long 0xC 2. "SFTRG66,Software Trigger 66" "0: No effect,1: Trigger conversion" newline bitfld.long 0xC 1. "SFTRG65,Software Trigger 65" "0: No effect,1: Trigger conversion" bitfld.long 0xC 0. "SFTRG64,Software Trigger 64" "0: No effect,1: Trigger conversion" repeat 3. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x23C)++0x3 line.long 0x0 "ADCDR[$1],ADCn Result Data" hexmask.long.byte 0x0 25.--31. 1. "TRG_SRC,Trigger Source" hexmask.long.byte 0x0 18.--24. 1. "CH,Channel" newline bitfld.long 0x0 17. "LIST,List" "0: Single conversion,1: CL" bitfld.long 0x0 16. "LAST,Last" "0: Not the last conversion of a CL or not a CL..,1: Last conversion of a CL" newline hexmask.long.word 0x0 0.--14. 1. "ADC_DATA,ADC Data" repeat.end rgroup.long 0x24C++0x3 line.long 0x0 "LISTSTAR,CL Size Status" hexmask.long.byte 0x0 0.--7. 1. "LISTSZ,CL Size" repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x250)++0x3 line.long 0x0 "LISTCHR_[$1],CL Channel Address" bitfld.long 0x0 31. "LAST_y,Last Channel" "0: Not last,1: Last channel in CL" bitfld.long 0x0 30. "NEXT_CH_WAIT_ON_TRIG_y,Next Channel Wait For Trigger" "0: CL executes continuously,1: CL stops executing" newline hexmask.long.byte 0x0 16.--22. 1. "ADC_CH_y,ADC Channel Selection" bitfld.long 0x0 15. "LAST_y_plus_1,Last Channel Plus 1" "0: Not next-to-last,1: Next-to-last channel in CL" newline bitfld.long 0x0 14. "NEXT_CH_WAIT_ON_TRIG_y_plus_1,Next Channel Wait For Trigger Plus 1" "0: CL executes continuously,1: CL stops executing" hexmask.long.byte 0x0 0.--6. 1. "ADC_CHL_y_plus_1,ADC Channel Selection Plus 1" repeat.end rgroup.long 0x450++0x7 line.long 0x0 "FIFO1DR,FIFO Result Data" hexmask.long.byte 0x0 25.--31. 1. "TRG_SRC,Trigger Source" hexmask.long.byte 0x0 18.--24. 1. "CH,Channel" newline bitfld.long 0x0 16.--17. "ADC_NUM,ADC Number" "0: ADC 0,1: ADC 1,2: ADC 2,3: ADC 3" hexmask.long.word 0x0 0.--14. 1. "ADC_DATA,ADC Data" line.long 0x4 "FIFO2DR,FIFO Result Data" hexmask.long.byte 0x4 25.--31. 1. "TRG_SRC,Trigger Source" hexmask.long.byte 0x4 18.--24. 1. "CH,Channel" newline bitfld.long 0x4 16.--17. "ADC_NUM,ADC Number" "0: ADC 0,1: ADC 1,2: ADC 2,3: ADC 3" hexmask.long.word 0x4 0.--14. 1. "ADC_DATA,ADC Data" group.long 0x460++0xB line.long 0x0 "FIFOCR,FIFO Control" bitfld.long 0x0 25. "DMA_EN_FIFO2,FIFO2 DMA Enable" "0: Disable,1: Enable" bitfld.long 0x0 24. "DMA_EN_FIFO1,FIFO1 DMA Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 17. "IEN_FIFO2,FIFO2 Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x0 16. "IEN_FIFO1,FIFO1 Interrupt Enable" "0: Disable,1: Enable" line.long 0x4 "FIFOWM,FIFO Watermark Configuration" bitfld.long 0x4 8.--10. "WM_FIFO2,FIFO2 Watermark Level" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--3. 1. "WM_FIFO1,FIFO1 Watermark Level" line.long 0x8 "FIFOERR,FIFO Error/Status" eventfld.long 0x8 27. "UNDR_ERR_FIFO2,Underrun Error Flag" "0: No underrun,1: Underrun" eventfld.long 0x8 26. "OVR_ERR_FIFO2,Overrun Error Flag" "0: No overrun,1: Overrun" newline eventfld.long 0x8 25. "UNDR_ERR_FIFO1,Underrun Error Flag" "0: No underrun,1: Underrun" eventfld.long 0x8 24. "OVR_ERR_FIFO1,Overrun Error Flag" "0: No overrun,1: Overrun" newline eventfld.long 0x8 17. "WM_INT_FIFO2,FIFO Watermark Interrupt Status" "0: Does not exceed watermark,1: Exceeds watermark" eventfld.long 0x8 16. "WM_INT_FIFO1,FIFO Watermark Interrupt Status" "0: Does not exceed watermark,1: Exceeds watermark" rgroup.long 0x46C++0x7 line.long 0x0 "FIFOSR,FIFO Status" bitfld.long 0x0 1. "FULL_FIFO2,FIFO Full" "0: Not full,1: Full" bitfld.long 0x0 0. "FULL_FIFO1,FIFO Full" "0: Not full,1: Full" line.long 0x4 "FIFOCNTR,FIFO Counter" hexmask.long.byte 0x4 8.--11. 1. "CNTR_FIFO2,FIFO2 Counter" hexmask.long.byte 0x4 0.--4. 1. "CNTR_FIFO1,FIFO1 Counter" tree.end tree "CMU_FC (Clock Monitoring Unit - Frequency Check)" base ad:0x0 tree "CMU_0" base ad:0x402BC000 group.long 0x0++0x17 line.long 0x0 "GCR,Global Configuration Register" bitfld.long 0x0 0. "FCE,Frequency Check Enable" "0: Stops frequency checking,1: Starts frequency checking" line.long 0x4 "RCCR,Reference Count Configuration Register" hexmask.long.word 0x4 0.--15. 1. "REF_CNT,Reference clock count" line.long 0x8 "HTCR,High Threshold Configuration Register" hexmask.long.tbyte 0x8 0.--23. 1. "HFREF,High frequency reference threshold" line.long 0xC "LTCR,Low Threshold Configuration Register" hexmask.long.tbyte 0xC 0.--23. 1. "LFREF,Low Frequency Reference Threshold" line.long 0x10 "SR,Status Register" rbitfld.long 0x10 4. "RS,Run Status" "0: Frequency check stopped,1: Frequency check running" eventfld.long 0x10 1. "FHH,Frequency higher than high frequency reference threshold event status" "0: No FHH event,1: FHH event occurred" newline eventfld.long 0x10 0. "FLL,Frequency lower than low frequency reference threshold event status" "0: No FLL event,1: FLL event occurred" line.long 0x14 "IER,Interrupt Enable Register" bitfld.long 0x14 3. "FHHAIE,Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FHH event interrupt disabled,1: Asynchronous FHH event interrupt enabled" bitfld.long 0x14 2. "FLLAIE,Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FLL event interrupt disabled,1: Asynchronous FLL event interrupt enabled" newline bitfld.long 0x14 1. "FHHIE,Frequency Higher than High Frequency Reference Threshold Synchronous Interrupt Enable" "0: Synchronous FHH event interrupt disabled,1: Synchronous FHH event interrupt enabled" bitfld.long 0x14 0. "FLLIE,Frequency Lower than Low Frequency Reference Threshold Synchronous Interrupt Enable" "0: Synchronous FLL event interrupt disabled,1: Synchronous FLL event interrupt enabled" tree.end tree "CMU_3" base ad:0x402BC060 group.long 0x0++0x17 line.long 0x0 "GCR,Global Configuration Register" bitfld.long 0x0 0. "FCE,Frequency Check Enable" "0: Stops frequency checking,1: Starts frequency checking" line.long 0x4 "RCCR,Reference Count Configuration Register" hexmask.long.word 0x4 0.--15. 1. "REF_CNT,Reference clock count" line.long 0x8 "HTCR,High Threshold Configuration Register" hexmask.long.tbyte 0x8 0.--23. 1. "HFREF,High frequency reference threshold" line.long 0xC "LTCR,Low Threshold Configuration Register" hexmask.long.tbyte 0xC 0.--23. 1. "LFREF,Low Frequency Reference Threshold" line.long 0x10 "SR,Status Register" rbitfld.long 0x10 4. "RS,Run Status" "0: Frequency check stopped,1: Frequency check running" eventfld.long 0x10 1. "FHH,Frequency higher than high frequency reference threshold event status" "0: No FHH event,1: FHH event occurred" newline eventfld.long 0x10 0. "FLL,Frequency lower than low frequency reference threshold event status" "0: No FLL event,1: FLL event occurred" line.long 0x14 "IER,Interrupt Enable Register" bitfld.long 0x14 3. "FHHAIE,Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FHH event interrupt disabled,1: Asynchronous FHH event interrupt enabled" bitfld.long 0x14 2. "FLLAIE,Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FLL event interrupt disabled,1: Asynchronous FLL event interrupt enabled" newline bitfld.long 0x14 1. "FHHIE,Frequency Higher than High Frequency Reference Threshold Synchronous Interrupt Enable" "0: Synchronous FHH event interrupt disabled,1: Synchronous FHH event interrupt enabled" bitfld.long 0x14 0. "FLLIE,Frequency Lower than Low Frequency Reference Threshold Synchronous Interrupt Enable" "0: Synchronous FLL event interrupt disabled,1: Synchronous FLL event interrupt enabled" tree.end tree "CMU_4" base ad:0x402BC080 group.long 0x0++0x17 line.long 0x0 "GCR,Global Configuration Register" bitfld.long 0x0 0. "FCE,Frequency Check Enable" "0: Stops frequency checking,1: Starts frequency checking" line.long 0x4 "RCCR,Reference Count Configuration Register" hexmask.long.word 0x4 0.--15. 1. "REF_CNT,Reference clock count" line.long 0x8 "HTCR,High Threshold Configuration Register" hexmask.long.tbyte 0x8 0.--23. 1. "HFREF,High frequency reference threshold" line.long 0xC "LTCR,Low Threshold Configuration Register" hexmask.long.tbyte 0xC 0.--23. 1. "LFREF,Low Frequency Reference Threshold" line.long 0x10 "SR,Status Register" rbitfld.long 0x10 4. "RS,Run Status" "0: Frequency check stopped,1: Frequency check running" eventfld.long 0x10 1. "FHH,Frequency higher than high frequency reference threshold event status" "0: No FHH event,1: FHH event occurred" newline eventfld.long 0x10 0. "FLL,Frequency lower than low frequency reference threshold event status" "0: No FLL event,1: FLL event occurred" line.long 0x14 "IER,Interrupt Enable Register" bitfld.long 0x14 3. "FHHAIE,Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FHH event interrupt disabled,1: Asynchronous FHH event interrupt enabled" bitfld.long 0x14 2. "FLLAIE,Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FLL event interrupt disabled,1: Asynchronous FLL event interrupt enabled" newline bitfld.long 0x14 1. "FHHIE,Frequency Higher than High Frequency Reference Threshold Synchronous Interrupt Enable" "0: Synchronous FHH event interrupt disabled,1: Synchronous FHH event interrupt enabled" bitfld.long 0x14 0. "FLLIE,Frequency Lower than Low Frequency Reference Threshold Synchronous Interrupt Enable" "0: Synchronous FLL event interrupt disabled,1: Synchronous FLL event interrupt enabled" tree.end tree "CMU_5" base ad:0x402BC0A0 group.long 0x0++0x17 line.long 0x0 "GCR,Global Configuration Register" bitfld.long 0x0 0. "FCE,Frequency Check Enable" "0: Stops frequency checking,1: Starts frequency checking" line.long 0x4 "RCCR,Reference Count Configuration Register" hexmask.long.word 0x4 0.--15. 1. "REF_CNT,Reference clock count" line.long 0x8 "HTCR,High Threshold Configuration Register" hexmask.long.tbyte 0x8 0.--23. 1. "HFREF,High frequency reference threshold" line.long 0xC "LTCR,Low Threshold Configuration Register" hexmask.long.tbyte 0xC 0.--23. 1. "LFREF,Low Frequency Reference Threshold" line.long 0x10 "SR,Status Register" rbitfld.long 0x10 4. "RS,Run Status" "0: Frequency check stopped,1: Frequency check running" eventfld.long 0x10 1. "FHH,Frequency higher than high frequency reference threshold event status" "0: No FHH event,1: FHH event occurred" newline eventfld.long 0x10 0. "FLL,Frequency lower than low frequency reference threshold event status" "0: No FLL event,1: FLL event occurred" line.long 0x14 "IER,Interrupt Enable Register" bitfld.long 0x14 3. "FHHAIE,Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FHH event interrupt disabled,1: Asynchronous FHH event interrupt enabled" bitfld.long 0x14 2. "FLLAIE,Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FLL event interrupt disabled,1: Asynchronous FLL event interrupt enabled" newline bitfld.long 0x14 1. "FHHIE,Frequency Higher than High Frequency Reference Threshold Synchronous Interrupt Enable" "0: Synchronous FHH event interrupt disabled,1: Synchronous FHH event interrupt enabled" bitfld.long 0x14 0. "FLLIE,Frequency Lower than Low Frequency Reference Threshold Synchronous Interrupt Enable" "0: Synchronous FLL event interrupt disabled,1: Synchronous FLL event interrupt enabled" tree.end tree "CMU_6" base ad:0x402BC0C0 group.long 0x0++0x17 line.long 0x0 "GCR,Global Configuration Register" bitfld.long 0x0 0. "FCE,Frequency Check Enable" "0: Stops frequency checking,1: Starts frequency checking" line.long 0x4 "RCCR,Reference Count Configuration Register" hexmask.long.word 0x4 0.--15. 1. "REF_CNT,Reference clock count" line.long 0x8 "HTCR,High Threshold Configuration Register" hexmask.long.tbyte 0x8 0.--23. 1. "HFREF,High frequency reference threshold" line.long 0xC "LTCR,Low Threshold Configuration Register" hexmask.long.tbyte 0xC 0.--23. 1. "LFREF,Low Frequency Reference Threshold" line.long 0x10 "SR,Status Register" rbitfld.long 0x10 4. "RS,Run Status" "0: Frequency check stopped,1: Frequency check running" eventfld.long 0x10 1. "FHH,Frequency higher than high frequency reference threshold event status" "0: No FHH event,1: FHH event occurred" newline eventfld.long 0x10 0. "FLL,Frequency lower than low frequency reference threshold event status" "0: No FLL event,1: FLL event occurred" line.long 0x14 "IER,Interrupt Enable Register" bitfld.long 0x14 3. "FHHAIE,Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FHH event interrupt disabled,1: Asynchronous FHH event interrupt enabled" bitfld.long 0x14 2. "FLLAIE,Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FLL event interrupt disabled,1: Asynchronous FLL event interrupt enabled" newline bitfld.long 0x14 1. "FHHIE,Frequency Higher than High Frequency Reference Threshold Synchronous Interrupt Enable" "0: Synchronous FHH event interrupt disabled,1: Synchronous FHH event interrupt enabled" bitfld.long 0x14 0. "FLLIE,Frequency Lower than Low Frequency Reference Threshold Synchronous Interrupt Enable" "0: Synchronous FLL event interrupt disabled,1: Synchronous FLL event interrupt enabled" tree.end tree.end tree "CMU_FM (Clock Monitoring Unit - Frequency Meter)" base ad:0x0 tree "CMU_1" base ad:0x402BC020 group.long 0x0++0xF line.long 0x0 "GCR,Global Configuration Register" bitfld.long 0x0 0. "FME,Frequency Meter Enable" "0: Stops frequency metering,1: Starts frequency metering" line.long 0x4 "RCCR,Reference Count Configuration Register" hexmask.long.word 0x4 0.--15. 1. "REF_CNT,Reference Clock Count" line.long 0x8 "SR,Status Register" hexmask.long.tbyte 0x8 8.--31. 1. "MET_CNT,Meter Clock Count" rbitfld.long 0x8 4. "RS,Run Status" "0: Frequency meter stopped,1: Frequency meter running" eventfld.long 0x8 1. "FMTO,Frequency Meter Time Out" "0,1" eventfld.long 0x8 0. "FMC,Frequency Meter Operation Complete" "0,1" line.long 0xC "IER,Interrupt Enable Register" bitfld.long 0xC 0. "FMCIE,Frequency Meter Complete Interrupt Enable" "0: Frequency Meter complete interrupt is disabled,1: Frequency Meter complete interrupt is enabled" tree.end tree "CMU_2" base ad:0x402BC040 group.long 0x0++0xF line.long 0x0 "GCR,Global Configuration Register" bitfld.long 0x0 0. "FME,Frequency Meter Enable" "0: Stops frequency metering,1: Starts frequency metering" line.long 0x4 "RCCR,Reference Count Configuration Register" hexmask.long.word 0x4 0.--15. 1. "REF_CNT,Reference Clock Count" line.long 0x8 "SR,Status Register" hexmask.long.tbyte 0x8 8.--31. 1. "MET_CNT,Meter Clock Count" rbitfld.long 0x8 4. "RS,Run Status" "0: Frequency meter stopped,1: Frequency meter running" eventfld.long 0x8 1. "FMTO,Frequency Meter Time Out" "0,1" eventfld.long 0x8 0. "FMC,Frequency Meter Operation Complete" "0,1" line.long 0xC "IER,Interrupt Enable Register" bitfld.long 0xC 0. "FMCIE,Frequency Meter Complete Interrupt Enable" "0: Frequency Meter complete interrupt is disabled,1: Frequency Meter complete interrupt is enabled" tree.end tree.end tree "CONFIGURATION_GPR (Configuration General-Purpose Registers)" base ad:0x4039C000 rgroup.long 0x1C++0x3 line.long 0x0 "CONFIG_REG0,General Purpose Configuration 0" bitfld.long 0x0 6. "EDB,Hardware Debugger Attached" "0: Debugger not connected,1: Debugger connected" rgroup.long 0x34++0x13 line.long 0x0 "CONFIG_REG6,General Purpose Configuration 6" bitfld.long 0x0 31. "HL,Hard Lock" "0: You can write to this register,1: Register is locked for any write" bitfld.long 0x0 5. "SAI_SDID_PCTL,SAI0 and SAI1 clock gating" "0: Clock is off (gated),1: Clock is on" newline bitfld.long 0x0 4. "FLEXIO_CLOCK_GATE,FlexIO Clock Gating" "0: Clock is off (gated),1: Clock is on" bitfld.long 0x0 2. "MAC_CLOCK_GATE,Ethernet Clock Gating" "0: Clock is off (gated),1: Clock is on" newline bitfld.long 0x0 0. "QUADSPI_SDID_PCTL,QuadSPI Clock Gating" "0: Clock is off (gated),1: Clock is on" line.long 0x4 "CONFIG_RAMPR,Configuration RAM Protected Region" bitfld.long 0x4 31. "HARD_LOCK,Hard Lock" "0: Write access is allowed,1: Write access is not allowed until next.." bitfld.long 0x4 30. "SOFT_LOCK,Soft Lock" "0: Write access is allowed,1: Write access is not allowed" newline hexmask.long.word 0x4 5.--20. 1. "SECURE_SIZE,Secure Size" line.long 0x8 "CONFIG_CFPRL,Configuration Code Flash Memory Active Block" bitfld.long 0x8 31. "HARD_LOCK,Hard Lock" "0: Write access is allowed,1: Write access is not allowed until next.." bitfld.long 0x8 30. "SOFT_LOCK,Soft Lock" "0: Write access is allowed,1: Write access is not allowed" newline hexmask.long.byte 0x8 13.--20. 1. "SECURE_SIZE,Secure Size" line.long 0xC "CONFIG_CFPRH,Configuration Code Flash Memory Passive Block" bitfld.long 0xC 31. "HARD_LOCK,Hard Lock" "0: Write access is allowed,1: Write access is not allowed until next.." bitfld.long 0xC 30. "SOFT_LOCK,Soft Lock" "0: Write access is allowed,1: Write access is not allowed" newline hexmask.long.byte 0xC 13.--20. 1. "SECURE_SIZE,Secure Size" line.long 0x10 "CONFIG_DFPR,Configuration Data Flash Memory Protected Region" bitfld.long 0x10 31. "HARD_LOCK,Hard Lock" "0: Write access is allowed,1: Write access is not allowed until next.." bitfld.long 0x10 30. "SOFT_LOCK,Soft Lock" "0: Write access is allowed,1: Write access is not allowed" newline hexmask.long.byte 0x10 13.--20. 1. "SECURE_SIZE,Secure Size" rgroup.long 0x50++0x13 line.long 0x0 "CONFIG_PE_LOCK,Configuration Program and Erase Lock" bitfld.long 0x0 18. "PE_LOCK_UTEST,Program/Erase Lock for UTEST" "0: UTEST lock request is clear,1: UTEST lock requested" bitfld.long 0x0 16. "PE_LOCK_BLOCK_4,Program/Erase Lock for Block 4" "0: Block 4 lock request is clear,1: Block 4 lock requested" newline bitfld.long 0x0 15. "PE_LOCK_BLOCK_3,Program/Erase Lock for Block 3" "0: Block 3 lock request is clear,1: Block 3 lock requested" bitfld.long 0x0 14. "PE_LOCK_BLOCK_2,Program/Erase Lock for Block 2" "0: Block 2 lock request is clear,1: Block 2 lock requested" newline bitfld.long 0x0 13. "PE_LOCK_BLOCK_1,Program/Erase Lock for Block 1" "0: Block 1 lock request is clear,1: Block 1 lock requested" bitfld.long 0x0 12. "PE_LOCK_BLOCK_0,Program/Erase Lock for Block 0" "0: Block 0 lock request is clear,1: Block 0 lock requested" line.long 0x4 "CONFIG_RAMPR_ALT,Configuration RAM Protected Region Alternate" hexmask.long 0x4 0.--31. 1. "INVERT_VALUE_RAMPR,Invert Value RAMPR" line.long 0x8 "CONFIG_CFPRL_ALT,Configuration Code Flash Memory Active Block Alternate" hexmask.long 0x8 0.--31. 1. "INVERT_VALUE_CFPRAB,Invert Value CFPRAB" line.long 0xC "CONFIG_CFPRH_ALT,Configuration Code Flash Memory Passive Block Alternate" hexmask.long 0xC 0.--31. 1. "INVERT_VALUE_CFPRP,Invert Value CFPRP" line.long 0x10 "CONFIG_DFPR_ALT,Configuration Data Flash Memory Protected Region Alternate" hexmask.long 0x10 0.--31. 1. "INVERT_VALUE_DFPR,Invert Value CFPRP" group.long 0x64++0x3 line.long 0x0 "CONFIG_REG_GPR,Configuration REG_GPR" rbitfld.long 0x0 29.--31. "APP_CORE_ACC,FIRC Divider" "?,?,?,?,?,5: Application core can write this field..,?,?" bitfld.long 0x0 0.--1. "FIRC_DIV_SEL,FIRC Divider" "0: Divided by 2,1: Divided by 2,2: Divided by 16,3: Undivided" tree.end tree "CRC (Cyclic Redundancy Check)" base ad:0x40380000 group.long 0x0++0xB line.long 0x0 "DATA,CRC Data" hexmask.long.byte 0x0 24.--31. 1. "HU,CRC High Upper Byte" hexmask.long.byte 0x0 16.--23. 1. "HL,CRC High Lower Byte" newline hexmask.long.byte 0x0 8.--15. 1. "LU,CRC Low Upper Byte" hexmask.long.byte 0x0 0.--7. 1. "LL,CRC Low Lower Byte" line.long 0x4 "GPOLY,CRC Polynomial" hexmask.long.word 0x4 16.--31. 1. "HIGH,High Polynomial Half-Word" hexmask.long.word 0x4 0.--15. 1. "LOW,Low Polynomial Half-Word" line.long 0x8 "CTRL,CRC Control" bitfld.long 0x8 30.--31. "TOT,Transpose Type for Writes" "0: No transposition,1: Bits in bytes are transposed; bytes are not..,2: Both bits in bytes and bytes are transposed,3: Only bytes are transposed; no bits in a byte are.." bitfld.long 0x8 28.--29. "TOTR,Transpose Type for Read" "0: No transposition,1: Bits in bytes are transposed; bytes are not..,2: Both bits in bytes and bytes are transposed,3: Only bytes are transposed; no bits in a byte are.." newline bitfld.long 0x8 26. "FXOR,Complement Read of CRC Data Register" "0: No XOR on reading,1: Inverts or complements the read value of the CRC.." bitfld.long 0x8 25. "WAS,Write as Seed" "0: Data values,1: Seed values" newline bitfld.long 0x8 24. "TCRC,TCRC" "0: 16-bit,1: 32-bit" tree.end tree "DCM (Device Configuration Module)" base ad:0x402AC000 rgroup.long 0x0++0x7 line.long 0x0 "DCMSTAT,DCM Status" bitfld.long 0x0 10. "DCMDBGPS,Debug Password Scanning Status" "0: Completed with errors,1: Completed successfully" bitfld.long 0x0 9. "DCMOTAS,DCM OTA Scanning Status (valid only when the value of the DCMDONE field is 1)" "0: Completed with errors,1: Completed successfully" newline bitfld.long 0x0 8. "DCMUTS,DCM Utest DCF Scanning Status (valid only if DCMDONE bit is set)" "0: DCM Utest DCF completed with errors.,1: DCM Utest DCF completed successfully." bitfld.long 0x0 4. "DCMLCST,LC Scanning Status" "0: Completed with errors,1: Completed successfully" newline bitfld.long 0x0 1. "DCMERR,DCM completion with error status (valid only if DCMDONE bit is set)" "0: DCM completed with success.,1: DCM completed with error." bitfld.long 0x0 0. "DCMDONE,DCM Scanning Status" "0: Running,1: Completed" line.long 0x4 "DCMLCC,LC and LC Control" bitfld.long 0x4 4.--6. "DCMRLC,Real LC" "0: FA,1: Pre-FA,2: OEM_PROD,?,?,?,?,7: IN_FIELD" bitfld.long 0x4 0.--2. "DCMCLC,Current LC" "0: FA,1: Pre-FA,2: OEM_PROD,?,?,?,?,7: IN_FIELD" group.long 0x8++0x3 line.long 0x0 "DCMLCS,LC Scan Status" eventfld.long 0x0 29. "DCMLCFE5,Pre-FA Flash Memory Error Check" "0: Successful,1: Failed" eventfld.long 0x0 28. "DCMLCE5,Pre-FA ECC Errors" "0: No errors,1: Marking error" newline eventfld.long 0x0 25.--27. "DCMLCC5,Pre-FA Marking Status" "0: Not scanned yet,1: Marked as active,2: Marked as inactive,3: Region is erased/virgin,?,5: Marked as inactive by an unknown pattern,6: Scanning timed out,?" eventfld.long 0x0 24. "DCMLCSS5,Pre-FA Scan Status" "0: Successful,1: Errors exist" newline eventfld.long 0x0 23. "DCMLCFE4,IN_FIELD Flash Memory Error Check" "0: Successful,1: Failed" eventfld.long 0x0 22. "DCMLCE4,IN_FIELD ECC Errors" "0: No errors,1: Errors exist" newline eventfld.long 0x0 19.--21. "DCMLCC4,IN_FIELD Marking Status" "0: Not scanned yet,1: Marked as active,2: Marked as inactive,3: Region is erased/virgin,?,5: Marked as inactive by an unknown pattern,6: Scanning timed out,?" eventfld.long 0x0 18. "DCMLCSS4,IN_FIELD Scan Status" "0: No errors,1: Errors exist" newline eventfld.long 0x0 17. "DCMLCFE3,OEM_PROD Flash Memory Error Check" "0: Successful,1: Failed" eventfld.long 0x0 16. "DCMLCE3,OEM_PROD ECC Errors" "0: No errors,1: Errors exist" newline eventfld.long 0x0 13.--15. "DCMLCC3,OEM_PROD Marking" "0: Not scanned yet,1: Marked as active,2: Marked as inactive,3: Region is erased/virgin,?,5: Marked as inactive by an unknown pattern,6: Scanning timed out,?" eventfld.long 0x0 12. "DCMLCSS3,OEM_PROD Scan Status" "0: No errors,1: Errors exist" group.long 0x1C++0x3 line.long 0x0 "DCMMISC,DCM Miscellaneous" eventfld.long 0x0 28. "DCMCERS,DCF Client Errors" "0: No errors on any of the DCF clients,1: Atleast one safety DCF client has an error" eventfld.long 0x0 11. "DCMDBGE,DCM ECC error on DBG sections" "0: No error on DBG section,1: DBG section error" newline eventfld.long 0x0 10. "DCMDBGT,DBG Section Error" "0: No error,1: Error exists" rgroup.long 0x20++0x3 line.long 0x0 "DCMDEB,Debug Status and Configuration" bitfld.long 0x0 16. "APPDBG_STAT_SOC,Application Debug Status" "0: Disabled,1: Enabled" bitfld.long 0x0 1. "DCM_APPDBG_STAT,DCM Authentication Engine Status" "0: Disabled,1: Enabled" rgroup.long 0x2C++0x3 line.long 0x0 "DCMEC,DCF Error Count" hexmask.long.word 0x0 0.--15. 1. "DCMECT,Error Count" repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "DCMSRR$1,DCF Scan Report" eventfld.long 0x0 29. "DCMDCFT1,Scanning Timeout On Flash Memory" "0: Does not exist,1: Exists" eventfld.long 0x0 28. "DCMESD1,Chip Side Error" "0: No errors,1: Errors exist" newline eventfld.long 0x0 27. "DCMESF1,Flash Memory Error" "0: No errors,1: Errors exist" eventfld.long 0x0 24.--26. "DCMDCFF1,DCF Record Location" "?,?,2: Utest region,?,?,5: Others: Reserved,?,?" newline hexmask.long.tbyte 0x0 0.--20. 1. "DCMDCFE1,Flash Memory Address" repeat.end group.long 0x80++0x3 line.long 0x0 "DCMLCS_2,LC Scan Status 2" eventfld.long 0x0 5. "DCMLCFE6,Flash Memory Error Check" "0: Successful,1: Failed" eventfld.long 0x0 4. "DCMLCE6,FA ECC Errors" "0: No errors,1: Errors exist" newline eventfld.long 0x0 1.--3. "DCMLCC6,FA Marking" "0: Not scanned yet,1: Marked as active,2: Marked as inactive,3: Region is erased/virgin,?,5: Marked as inactive by an unknown pattern,6: Scanning timed out,?" eventfld.long 0x0 0. "DCMLCSS6,FA Scan Status" "0: No errors,1: Errors exist" tree.end tree "DCM_GPR (DCM General-Purpose Registers)" base ad:0x402AC000 group.long 0x200++0x3 line.long 0x0 "DCMROD1,Read-Only GPR On Destructive Reset 1" eventfld.long 0x0 0. "PCU_ISO_STATUS,PCU Input Isolation Status On Previous Standby Entry" "0: No,1: Yes" group.long 0x208++0x1B line.long 0x0 "DCMROD3,Read-Only GPR On Destructive Reset 3" eventfld.long 0x0 31. "CM7_1_ICDATA_ECC_ERR,Cortex-M7_1 I-cache Multi-Bit ECC Error" "0: No,1: Yes" newline eventfld.long 0x0 30. "CM7_0_ICDATA_ECC_ERR,Cortex-M7_0 I-cache Data ECC Error" "0: No,1: Yes" newline eventfld.long 0x0 29. "CM7_1_DCTAG_ECC_ERR,Cortex-M7_1 D-cache Tag ECC Error" "0: No,1: Yes" newline eventfld.long 0x0 28. "CM7_0_DCTAG_ECC_ERR,Cortex-M7_0 D-cache Tag ECC Error" "0: No,1: Yes" newline eventfld.long 0x0 27. "CM7_1_DCDATA_ECC_ERR,Cortex-M7_1 D-cache Data Memory ECC Error" "0: No,1: Yes" newline eventfld.long 0x0 26. "CM7_0_DCDATA_ECC_ERR,Cortex-M7_0 D-cache Data Memory ECC Error" "0: No,1: Yes" newline eventfld.long 0x0 25. "PRAM0_ECC_ERR,Multi-Bit ECC Error From PRAM0" "0: No,1: Yes" newline eventfld.long 0x0 24. "PRAM1_ECC_ERR,Multi-Bit ECC Error From PRAM1" "0: No,1: Yes" newline eventfld.long 0x0 23. "PRAM2_ECC_ERR,Multi bit ECC error from SRAM2. Read this bit to identify the reason for a fault in case of FCCU NCF 2." "0: No multi-bit ECC error.,1: Multi-bit ECC error." newline eventfld.long 0x0 22. "LC_ERR,Error In Life Cycle Scanning" "0: No error while lifecycle scanning.,1: Error while lifecycle scanning" newline eventfld.long 0x0 21. "PF3_DATA_ECC_ERR,Program Flash Memory 3 Data ECC Uncorrectable Error" "0: No,1: Yes" newline eventfld.long 0x0 20. "PF3_CODE_ECC_ERR,Flash Memory 3 Code ECC Uncorrectable Error" "0: No,1: Yes" newline eventfld.long 0x0 19. "PERIPH_AXBS_ALARM,Peripheral AXBS_Lite Safety Alarm Status" "0: No,1: Yes" newline eventfld.long 0x0 18. "MAC_GSKT_ALARM,MAC IAHB Gasket Alarm Status" "0: No,1: Yes" newline eventfld.long 0x0 17. "TCM_AXBS_ALARM,TCM AHB Splitter Safety Alarm Status" "0: No,1: Yes" newline eventfld.long 0x0 16. "DATA_EDC_ERR,Data EDC Error" "0: No,1: Yes" newline eventfld.long 0x0 15. "ADDR_EDC_ERR,Address EDC Error Status" "0: No,1: Yes" newline eventfld.long 0x0 14. "AIPS2_GSKT_ALARM,AIPS2 IAHB Gasket Alarm Status. Read this bit to identify the reason for a fault in case of FCCU NCF 1." "0: No alarm indicated by AIPS2 IAHB gasket.,1: Alarm indicated by AIPS2 IAHB gasket." newline eventfld.long 0x0 13. "AIPS1_GSKT_ALARM,AIPS1 IAHB Gasket Alarm Status. Read this bit to identify the reason for a fault in case of FCCU NCF 1." "0: No alarm indicated by AIPS1 IAHB gasket.,1: Alarm indicated by AIPS1 IAHB gasket." newline eventfld.long 0x0 12. "QSPI_GSKT_ALARM,QuadSPI IAHB Gasket Alarm Status" "0: No,1: Yes" newline eventfld.long 0x0 11. "HSE_GSKT_ALARM,HSE IAHB Gasket Alarm Status" "0: No,1: Yes" newline eventfld.long 0x0 9. "DMA_AXBS_ALARM,eDMA AXBS_Lite Safety Alarm Status" "0: No,1: Yes" newline eventfld.long 0x0 8. "SYS_AXBS_ALARM,System AXBS Safety Alarm Status" "0: No,1: Yes" newline eventfld.long 0x0 7. "DMA_PERIPH_GSKT_ALARM,eDMA Peripheral Gasket Alarm Status" "0: No,1: Yes" newline eventfld.long 0x0 6. "DMA_SYS_GSKT_ALARM,eDMA System Gasket Alarm Status" "0: No,1: Yes" newline eventfld.long 0x0 5. "TCM_GSKT_ALARM,TCM IAHB Gasket Monitor Alarm Status" "0: No,1: Yes" newline eventfld.long 0x0 4. "CM7_RCCU2_ALARM,Cortex-M7 Core Redundant Lockstep Error Status" "0: No,1: Yes" newline eventfld.long 0x0 3. "CM7_RCCU1_ALARM,Cortex-M7 Core Lockstep Error Status" "0: No,1: Yes" newline eventfld.long 0x0 2. "HSE_LOCKUP,HSE_B Core Lockup Status" "0: No,1: Yes" newline eventfld.long 0x0 1. "CM7_1_LOCKUP,Cortex-M7_1 Core Lockup Status" "0: No,1: Yes" newline eventfld.long 0x0 0. "CM7_0_LOCKUP,Cortex-M7_0 Core Lockup Status" "0: No,1: Yes" line.long 0x4 "DCMROD4,Read-Only GPR On Destructive Reset 4" eventfld.long 0x4 31. "CM7_2_LOCKUP,CM7_2 Core Lockup Status" "0: CM7_2 core not in lockup state.,1: CM7_2 core in lockup state." newline eventfld.long 0x4 30. "TEST_ACTIVATION_1_ERR,Accidental Partial Test Activation 1 Error" "0: No,1: Yes" newline eventfld.long 0x4 29. "TEST_ACTIVATION_0_ERR,Accidental Partial Test Activation 0 Error" "0: No,1: Yes" newline eventfld.long 0x4 27. "VDD2P5_GNG_ERR,Go/No-go Indicator For VDD_HV_FLA" "0: Yes,1: No" newline eventfld.long 0x4 26. "VDD1P1_GNG_ERR,Go/No-go Indicator For VDD1PD1" "0: Yes,1: No" newline eventfld.long 0x4 25. "FLASH_ECC_ERR,ECC Error From Flash Controller" "0: No ECC error from flash controller.,1: ECC error from flash controller." newline eventfld.long 0x4 23. "PRAM2_FCCU_ALARM,Status of PRAM2 safety alarm" "0: No safety alarm indicated by PRAM2.,1: Safety alarm indicated by PRAM2." newline eventfld.long 0x4 22. "FLASH_SCAN_ERR,Flash Memory Scan Error Status" "0: No,1: Yes" newline eventfld.long 0x4 21. "FLASH_RST_ERR,Flash Reset Error Status" "0: No,1: Yes" newline eventfld.long 0x4 20. "FLASH_REF_ERR,Flash Memory Reference Error Status" "0: No,1: Yes" newline eventfld.long 0x4 19. "FLASH_ADDR_ENC_ERR,Flash Memory Address Encode Error Status" "0: No,1: Yes" newline eventfld.long 0x4 18. "FLASH_EDC_ERR,Flash Memory EDC Error Status" "0: No,1: Yes" newline eventfld.long 0x4 17. "PF2_DATA_ECC_ERR,Program Flash Memory 2 Data ECC Error Status" "0: No,1: Yes" newline eventfld.long 0x4 16. "PF2_CODE_ECC_ERR,Program Flash Memory 2 Code ECC Error Status" "0: No,1: Yes" newline eventfld.long 0x4 15. "PF1_DATA_ECC_ERR,Program Flash Memory 1 Data ECC Error Status" "0: No,1: Yes" newline eventfld.long 0x4 14. "PF1_CODE_ECC_ERR,Program Flash Memory 1 Code ECC Error Status" "0: No,1: Yes" newline eventfld.long 0x4 13. "PF0_DATA_ECC_ERR,Program Flash Memory 0 Data ECC Error Status" "0: No,1: Yes" newline eventfld.long 0x4 12. "PF0_CODE_ECC_ERR,Program Flash Memory 0 Code ECC Error Status" "0: No,1: Yes" newline eventfld.long 0x4 11. "HSE_RAM_ECC_ERR,HSE_B RAM Uncorrectable ECC Status" "0: No,1: Yes" newline eventfld.long 0x4 10. "PRAM1_FCCU_ALARM,PRAM1 FCCU Alarm Status" "0: No,1: Yes" newline eventfld.long 0x4 9. "PRAM0_FCCU_ALARM,PRAM0 FCCU Alarm Status" "0: No,1: Yes" newline eventfld.long 0x4 8. "DMA_TCD_RAM_ECC_ERR,eDMA TCD RAM ECC Error" "0: No,1: Yes" newline eventfld.long 0x4 7. "CM7_1_DTCM1_ECC_ERR,Cortex-M7_1 DTCM 1 ECC Error" "0: No,1: Yes" newline eventfld.long 0x4 6. "CM7_1_DTCM0_ECC_ERR,Cortex-M7_1 DTCM 0 ECC Error" "0: No,1: Yes" newline eventfld.long 0x4 5. "CM7_1_ITCM_ECC_ERR,Cortex-M7_1 ITCM ECC Error" "0: No,1: Yes" newline eventfld.long 0x4 4. "CM7_0_DTCM1_ECC_ERR,Cortex-M7_0 DTCM 1 ECC Error" "0: No,1: Yes" newline eventfld.long 0x4 3. "CM7_0_DTCM0_ECC_ERR,Cortex-M7_0 DTCM 0 ECC Error" "0: No,1: Yes" newline eventfld.long 0x4 2. "CM7_0_ITCM_ECC_ERR,Cortex-M7_0 ITCM ECC Error" "0: No,1: Yes" newline eventfld.long 0x4 1. "CM7_1_ICTAG_ECC_ERR,Cortex-M7_1 I-cache Tag ECC Error" "0: No,1: Yes" newline eventfld.long 0x4 0. "CM7_0_ICTAG_ECC_ERR,Cortex-M7_0 I-cache Tag ECC Error" "0: No,1: Yes" line.long 0x8 "DCMROD5,Read-Only GPR On Destructive Reset 5" eventfld.long 0x8 31. "CM7_2_DTCM1_ECC_ERR,Cortex-M7_2 DTCM 1 ECC Error" "0: No,1: Yes" newline eventfld.long 0x8 30. "CM7_2_DTCM0_ECC_ERR,Cortex-M7_2 DTCM 0 ECC Error" "0: No,1: Yes" newline eventfld.long 0x8 29. "CM7_2_ITCM_ECC_ERR,Cortex-M7_2 ITCM ECC Error" "0: No,1: Yes" newline eventfld.long 0x8 28. "CM7_2_ICTAG_ECC_ERR,Cortex-M7_2 I-cache Tag ECC Error" "0: No,1: Yes" newline eventfld.long 0x8 27. "CM7_2_ICDATA_ECC_ERR,Cortex-M7_2 I-cache Data ECC Error" "0: No,1: Yes" newline eventfld.long 0x8 26. "CM7_2_DCTAG_ECC_ERR,Cortex-M7_2 D-cache Tag ECC Error" "0: No,1: Yes" newline eventfld.long 0x8 25. "CM7_2_DCDATA_ECC_ERR,Cortex-M7_2 D-cache Data ECC Error" "0: No,1: Yes" newline eventfld.long 0x8 24. "CM7_2_AHBM_RDATA_EDC_ERR,Cortex-M7_2 AHBM Read Data EDC Error" "0: No,1: Yes" newline eventfld.long 0x8 23. "CM7_2_AHBP_RDATA_EDC_ERR,Cortex-M7_2 AHBP Read Data EDC Error" "0: No,1: Yes" newline eventfld.long 0x8 22. "HSE_RDATA_EDC_ERR,HSE_B Read Data EDC Error" "0: No,1: Yes" newline eventfld.long 0x8 21. "CM7_0_AHBM_RDATA_EDC_ERR,Cortex-M7_0 AHBM Read Data EDC Error" "0: No,1: Yes" newline eventfld.long 0x8 20. "CM7_0_AHBP_RDATA_EDC_ERR,Cortex-M7_0 AHBP Read Data EDC Error" "0: No,1: Yes" newline eventfld.long 0x8 19. "CM7_1_AHBM_RDATA_EDC_ERR,Cortex-M7_1 AHBM Read Data EDC Error" "0: No,1: Yes" newline eventfld.long 0x8 18. "CM7_1_AHBP_RDATA_EDC_ERR,Cortex-M7_1 AHBP Read Data EDC Error" "0: No,1: Yes" newline eventfld.long 0x8 17. "DMA_RDATA_EDC_ERR,eDMA Read Data EDC Error" "0: No,1: Yes" newline eventfld.long 0x8 15. "MAC_RDATA_EDC_ERR,MAC Read Data EDC Error" "0: No,1: Yes" newline eventfld.long 0x8 13. "DEBUG_ACTIVATION_ERR,Debug Activation Error" "0: No,1: Yes" newline eventfld.long 0x8 12. "MCT_BUS_ERR,MCT Bus Error" "0: No transfer error indicated from MCT.,1: Transfer error indicated from MCT." newline eventfld.long 0x8 11. "STCU_BIST_USER_CF,STCU2 BIST User Critical Fault (CF)" "0: No,1: Yes" newline eventfld.long 0x8 10. "MBIST_ACTIVATION_ERR,MBIST Activation Error" "0: No,1: Yes" newline eventfld.long 0x8 9. "STCU_NCF,STCU2 NCF Result Error" "0: No,1: Yes" newline eventfld.long 0x8 8. "SW_NCF_3,Software NCF3 Status" "0: No,1: Yes" newline eventfld.long 0x8 7. "SW_NCF_2,Software NCF2 Status" "0: No,1: Yes" newline eventfld.long 0x8 6. "SW_NCF_1,Software NCF1 Status" "0: No,1: Yes" newline eventfld.long 0x8 5. "SW_NCF_0,Software NCF 0 Status" "0: No,1: Yes" newline eventfld.long 0x8 4. "INTM_3_ERR,INTM_3 Error" "0: No,1: Yes" newline eventfld.long 0x8 3. "INTM_2_ERR,INTM_2 Error" "0: No,1: Yes" newline eventfld.long 0x8 2. "INTM_1_ERR,INTM_1 Error" "0: No,1: Yes" newline eventfld.long 0x8 1. "INTM_0_ERR,INTM_0 Error" "0: No,1: Yes" line.long 0xC "DCMROD6,Read-Only GPR On Destructive Reset 6" eventfld.long 0xC 30. "TCM_PRAM_AXBS_ALARM,Status of TCM_PRAM AXBS_Lite safety alarm. Read this bit to identify the reason of fault in case of FCCU NCF 1." "0: No safety alarm indicated by TCM_PRAM AXBS_Lite.,1: Safety alarm indicated by TCM_PRAM AXBS_Lite." newline eventfld.long 0xC 26. "AIPS0_GSKT_ALARM,AIPS0 IAHB Gasket Alarm Status. Read this bit to identify the reason of fault in case of FCCU NCF 1." "0: No alarm indicated by AIPS0 IAHB gasket.,1: Alarm indicated by AIPS0 IAHB gasket." newline eventfld.long 0xC 3. "QSPI_FLASHA_ECC_ERR,Uncorrectable ECC error status from flashA interface of QuadSPI. Read this bit to identify the reason of fault in case of FCCU NCF 2." "0: Uncorrectable ECC error from flashA disabled/not..,1: Uncorrectable ECC error detected from flashA." line.long 0x10 "DCMROD7,Read-Only GPR On Destructive Reset 7" eventfld.long 0x10 30. "CM7_2_AHBS_ALARM,CM7_2 AHBS interface IAHB Gasket monitor alarm status. Read this bit to identify the reason of fault in case of FCCU NCF 1." "0: No alarm reported from CM7_0 AHBS interface IAHB..,1: Monitor alarm reported from CM7_0 AHBS interface.." newline eventfld.long 0x10 29. "CM7_1_AHBS_ALARM,CM7_1 AHBS interface IAHB Gasket monitor alarm status. Read this bit to identify the reason of fault in case of FCCU NCF 1." "0: No alarm reported from CM7_0 AHBS interface IAHB..,1: Monitor alarm reported from CM7_0 AHBS interface.." newline eventfld.long 0x10 28. "CM7_0_AHBS_ALARM,CM7_0 AHBS interface IAHB Gasket monitor alarm status. Read this bit to identify the reason of fault in case of FCCU NCF 1." "0: No alarm reported from CM7_0 AHBS interface IAHB..,1: Monitor alarm reported from CM7_0 AHBS interface.." newline eventfld.long 0x10 12. "VDD2P5_GNG2_ERR,Go/Nogo indicator status for VDD_HV_FLA (triple bond) going to FXOSC and PLL. Read this bit to identify the reason of fault in case of FCCU NCF4." "0: Go indication referring to the supply being clean.,1: No go indication referring to the supply being.." newline eventfld.long 0x10 11. "VDD1P1_GNG2_ERR,Go/Nogo indicator status for VDD_HV_FLA (triple bond) going to FXOSC and PLL. Read this bit to identify the reason of fault in case of FCCU NCF4." "0: Go indication referring to the supply being clean.,1: No go indication referring to the supply being.." newline eventfld.long 0x10 5. "CM7_2_AHBP_ALARM,Cortex-M7_2 AHBP Alarm Status" "0: No,1: Yes" newline eventfld.long 0x10 4. "CM7_1_AHBP_ALARM,Cortex-M7_1 AHBP Alarm Status" "0: No,1: Yes" newline eventfld.long 0x10 3. "CM7_0_AHBP_ALARM,Cortex-M7_0 AHBP Alarm Status" "0: No,1: Yes" newline eventfld.long 0x10 2. "CM7_2_AHBM_ALARM,Cortex-M7_2 AHBM Alarm Status" "0: No,1: Yes" newline eventfld.long 0x10 1. "CM7_1_AHBM_ALARM,Cortex-M7_1 AHBM Alarm Status" "0: No,1: Yes" newline eventfld.long 0x10 0. "CM7_0_AHBM_ALARM,Cortex-M7_0 AHBM Alarm Status" "0: No,1: Yes" line.long 0x14 "DCMROD8,Read-Only GPR On Destructive Reset Register" eventfld.long 0x14 29. "CM7_3_DTCM1_ECC_ERR,Status of Uncorrectable ECC error from CM7_3 Data TCM memory block 1" "0: Uncorrectable ECC error detection not enabled at..,1: Uncorrectable ECC error detection enabled at FCCU" newline eventfld.long 0x14 28. "CM7_3_DTCM0_ECC_ERR,Status of Uncorrectable ECC error from CM7_3 Data TCM memory block 0" "0: Uncorrectable ECC error detection not enabled at..,1: Uncorrectable ECC error detection enabled at FCCU" newline eventfld.long 0x14 27. "CM7_3_ITCM_ECC_ERR,Status of Uncorrectable ECC error from CM7_3 Instruction TCM memory" "0: No uncorrectable ECC error detected,1: Uncorrectable ECC error detected" newline eventfld.long 0x14 26. "CM7_3_ICTAG_ECC_ERR,Status of Multi bit ECC error from CM7_3 ICache tag memory" "0: No multi-bit ECC error reported,1: Multi-bit ECC error reported" newline eventfld.long 0x14 25. "CM7_3_ICDATA_ECC_ERR,Status of Multi bit ECC error from CM7_3 ICache data memory" "0: No multi-bit ECC error reported,1: Multi-bit ECC error reported" newline eventfld.long 0x14 24. "CM7_3_DCTAG_ECC_ERR,Status of Multi bit ECC error from CM7_3 DCache tag memory" "0: No multi-bit ECC error reported,1: Multi-bit ECC error reported" newline eventfld.long 0x14 23. "CM7_3_DCDATA_ECC_ERR,Status of Multi bit ECC error from CM7_3 DCache data memory" "0: No multi-bit ECC error reported,1: Multi-bit ECC error reported" newline eventfld.long 0x14 22. "CM7_3_AHBP_ALARM,Status of CM7_3 AHBP interface IAHB Gasket monitor alarm" "0: No alarm reported,1: Monitor alarm reported" newline eventfld.long 0x14 21. "CM7_3_AHBM_ALARM,Status of CM7_3 AHBM interface IAHB Gasket monitor alarm" "0: No alarm reported,1: Monitor alarm reported" newline eventfld.long 0x14 19. "AES_ACCEL_GSKT_ALARM,AES ACCEL IAHB Gasket monitor alarm status" "0: No alarm reported,1: Monitor alarm reported" newline eventfld.long 0x14 18. "AES_ACCEL_AXBS_ALARM,AES_ACCEL AXBS_Lite safety alarm status" "0: No safety alarm indicated,1: Safety alarm indicated" newline eventfld.long 0x14 17. "ACE_FEED_RDATA_EDC_ERR,Status of Integrity error on ACE ACCEL FEED DMA master port read data for safety" "0: No integrity error reported,1: Integrity error reported" newline eventfld.long 0x14 16. "ACE_RESULT_RDATA_EDC_ERR,Status of Integrity error on ACE ACCEL RESULT DMA master port read data for safety" "0: No integrity error reported,1: Integrity error reported" newline eventfld.long 0x14 14. "CM7_3_AHBS_ALARM,CM7_3 AHBS interface IAHB Gasket monitor alarm status" "0: No alarm reported,1: Monitor alarm reported" newline eventfld.long 0x14 13. "HSE_AES_ACCEL_AXBS_ALARM,HSE_AES_ACCEL AXBS_Lite safety alarm status" "0: No safety alarm indicated,1: Safety alarm indicated" newline eventfld.long 0x14 12. "CM7_3_AHBM_RDATA_EDC_ERR,Status of Integrity error on CM7_3 main read data for safety" "0: No integrity error reported,1: Integrity error reported" newline eventfld.long 0x14 11. "CM7_3_AHBP_RDATA_EDC_ERR,Status of Integrity error on CM7_3 peripheral read data for safety" "0: No integrity error reported,1: Integrity error reported" newline eventfld.long 0x14 10. "MAC2_RDATA_EDC_ERR,Status of Integrity(EDC) error on MAC2 read data for safety" "0: No integrity error reported,1: Integrity error reported" newline eventfld.long 0x14 9. "MAC2_GSKT_ALARM,MAC2 IAHB gasket alarm status. Read this bit to identify the reason of fault in case of FCCU NCF 1." "0: No alarm indicated,1: Alarm indicated" newline eventfld.long 0x14 7. "PERIPH_AXBS_S3_GSKT_ALARM,Peripheral AXBS bridge S3 IAHB gasket alarm status" "0: No alarm reported,1: Monitor alarm reported" newline eventfld.long 0x14 6. "CM7_2_RCCU2_ALARM,Cortex M7 cores (CM7_2 and CM7_2_checker core) redundant lockstep error status" "0: No Error reported.,1: Error reported" newline eventfld.long 0x14 5. "CM7_2_RCCU1_ALARM,Cortex M7 cores (CM7_2 and CM7_2_checker core) lockstep error status" "0: No Error reported.,1: Error reported" newline eventfld.long 0x14 4. "CM7_3_LOCKUP,CM7_3 core lockup status. Read this bit to identify the reason of fault in case of FCCU NCF 0." "0: Not in lockup state,1: In lockup state" line.long 0x18 "DCMROD9,Read-Only GPR On Destructive Reset 9" eventfld.long 0x18 6. "AES_RESULT_DID_SAFETY_ERR,AES RESULT DMA DID error status" "0: AES RESULT DMA DID error not reported.,1: AES RESULT DMA DID error reported." newline eventfld.long 0x18 5. "AES_FEED_DID_SAFETY_ERR,AES FEED DMA DID Error Status" "0: AES FEED DMA DID error not reported.,1: AES FEED DMA DID error reported." newline eventfld.long 0x18 3. "AES_RESULT_DMA_TCD_ADDR_ECC_ERR,AES ACCEL RESULT DMA_TCD Address ECC Error Status" "0: No address error reported in AES ACCEL RESULT..,1: Address error reported in AES ACCEL RESULT.." newline eventfld.long 0x18 2. "AES_RESULT_DMA_TCD_ECC_ERR,AES ACCEL RESULT DMA_TCD memory uncorrectable ECC error status. Read this bit to identify the reason of fault in case of FCCU NCF 2." "0: No uncorrectable error reported,1: Uncorrectable error reported" newline eventfld.long 0x18 1. "AES_FEED_DMA_TCD_ADDR_ECC_ERR,AES ACCEL FEED DMA TCD Address ECC Error Status" "0: No address error reported in AES ACCEL FEED..,1: Address error reported in AES ACCEL FEED DMA_TCD.." newline eventfld.long 0x18 0. "AES_FEED_DMA_TCD_ECC_ERR,AES ACCEL FEED DMA_TCD memory uncorrectable ECC error status. Read this bit to identify the reason of fault in case of FCCU NCF 2." "0: No uncorrectable error reported,1: Uncorrectable error reported" group.long 0x300++0x43 line.long 0x0 "DCMROF1,Read-Only GPR On Functional Reset 1" hexmask.long.byte 0x0 26.--29. 1. "AES_RESULT_DID_ERR_DID,Indicates DID[3:0] value when the AES result DID error was reported." newline eventfld.long 0x0 25. "AES_RESULT_DID_ERR_NS,Indicates whether the non-secure attribute was set or not when the AES result DID error was reported" "0: Not set,1: Set" newline eventfld.long 0x0 24. "AES_RESULT_DID_ERR_PRIV,Indicates whether the privilege attribute was set or not when the AES result DID error was reported" "0: Not set,1: Set" newline hexmask.long.byte 0x0 18.--21. 1. "AES_FEED_DID_ERR_DID,Indicates DID[3:0] value when the AES feed DID error was reported." newline eventfld.long 0x0 17. "AES_FEED_DID_ERR_NS,Indicates whether the non-secure attribute was set or not when the AES feed DID error was reported." "0: Not set,1: Set" newline eventfld.long 0x0 16. "AES_FEED_DID_ERR_PRIV,Indicates whether the privilege attribute was set or not when the AES feed DID error was reported." "0: Not set,1: Set" newline eventfld.long 0x0 5. "MAC1_MDC_CHID_2,MAC eDMA Channel ID2 Status" "0: No,1: Yes" newline eventfld.long 0x0 4. "MAC1_MDC_CHID_1,MAC eDMA Channel ID1 Status" "0: No,1: Yes" newline eventfld.long 0x0 3. "MAC1_MDC_CHID_0,MAC eDMA Channel ID0 Status" "0: No,1: Yes" newline eventfld.long 0x0 2. "MAC_MDC_CHID_2,MAC eDMA Channel ID2 Status" "0: No,1: Yes" newline eventfld.long 0x0 1. "MAC_MDC_CHID_1,MAC eDMA Channel ID1 Status" "0: No,1: Yes" newline eventfld.long 0x0 0. "MAC_MDC_CHID_0,MAC eDMA Channel ID0 Status" "0: No,1: Yes" line.long 0x4 "DCMROF2,Read-Only GPR On Functional Reset 2" hexmask.long 0x4 0.--31. 1. "DCF_SDID0,DCF Client SDID 0 Configuration" line.long 0x8 "DCMROF3,Read-Only GPR On Functional Reset 3" hexmask.long 0x8 0.--31. 1. "DCF_SDID1,DCF Client SDID 1 Configuration" line.long 0xC "DCMROF4,Read-Only GPR On Functional Reset 4" hexmask.long 0xC 0.--31. 1. "DCF_SDID2,DCF Client SDID 2 Configuration" line.long 0x10 "DCMROF5,Read-Only GPR On Functional Reset 5" hexmask.long 0x10 0.--31. 1. "DCF_SDID3,DCF Client SDID 3 Configuration" line.long 0x14 "DCMROF6,Read-Only GPR On Functional Reset 6" hexmask.long 0x14 0.--31. 1. "DCF_SDID4,DCF Client SDID 4 Configuration" line.long 0x18 "DCMROF7,Read-Only GPR On Functional Reset 7" hexmask.long 0x18 0.--31. 1. "DCF_SDID5,DCF Client SDID 5 Configuration" line.long 0x1C "DCMROF8,Read-Only GPR On Functional Reset 8" hexmask.long 0x1C 0.--31. 1. "DCF_SDID6,DCF Client SDID 6 Configuration" line.long 0x20 "DCMROF9,Read-Only GPR On Functional Reset 9" hexmask.long 0x20 0.--31. 1. "DCF_SDID7,DCF Client SDID 7 Configuration" line.long 0x24 "DCMROF10,Read-Only GPR On Functional Reset 10" hexmask.long 0x24 0.--31. 1. "DCF_SDID8,DCF Client SDID 8 Configuration" line.long 0x28 "DCMROF11,Read-Only GPR On Functional Reset 11" hexmask.long 0x28 0.--31. 1. "DCF_SDID9,DCF Client SDID 9 Configuration" line.long 0x2C "DCMROF12,Read-Only GPR On Functional Reset 12" hexmask.long 0x2C 0.--31. 1. "DCF_SDID10,DCF Client SDID 10 Configuration" line.long 0x30 "DCMROF13,Read-Only GPR On Functional Reset 13" hexmask.long 0x30 0.--31. 1. "DCF_SDID11,DCF Client SDID 11 Configuration" line.long 0x34 "DCMROF14,Read-Only GPR On Functional Reset 14" hexmask.long 0x34 0.--31. 1. "DCF_SDID12,DCF Client SDID 12 Configuration" line.long 0x38 "DCMROF15,Read-Only GPR On Functional Reset 15" hexmask.long 0x38 0.--31. 1. "DCF_SDID13,DCF Client SDID 13 Configuration" line.long 0x3C "DCMROF16,Read-Only GPR On Functional Reset 16" hexmask.long 0x3C 0.--31. 1. "DCF_SDID14,DCF Client SDID 14 Configuration" line.long 0x40 "DCMROF17,Read-Only GPR On Functional Reset 17" hexmask.long 0x40 0.--31. 1. "DCF_SDID15,DCF Client SDID 15 Configuration" rgroup.long 0x348++0xB line.long 0x0 "DCMROF19,Read-Only GPR On Functional Reset 19" bitfld.long 0x0 31. "FCCU_EOUT_DEDICATED,FCCU EOUT Status" "0: General purpose supporting all functions,1: Dedicated EOUT pins" newline bitfld.long 0x0 30. "DCM_DONE,Flash Memory Scanning Status" "0: Incomplete,1: Complete" newline bitfld.long 0x0 29. "LOCKSTEP_EN,Lockstep Enable" "0: Decoupled operation of Cortex-M7_0 and Cortex-M7_1,1: Lockstep operation of Cortex-M7_0 and Cortex-M7_1" line.long 0x4 "DCMROF20,Read-Only GPR On Functional Reset 20" hexmask.long.word 0x4 18.--31. 1. "DCF_DEST_RST_ESC,DCF Destructive Reset Escalation" newline bitfld.long 0x4 6. "AIPS_IAHB_BYP,Status of AIPS1/2 IAHB gasket as configured in DCF record UTEST_MISC[AIPS_IAHB_BYP]." "0: Register wall enabled.,1: Register wall bypassed." newline bitfld.long 0x4 5. "QSPI_IAHB_BYP,QuadSPI IAHB Bypass Status" "0: Register wall enabled,1: Register wall bypassed" newline bitfld.long 0x4 3. "DMA_AXBS_IAHB_BYP,Status of DMA AXBS IAHB gasket as configured in DCF record UTEST_MISC[DMA_AXBS_IAHB_BYP]." "0: Register wall enabled.,1: Register wall bypassed." newline bitfld.long 0x4 0. "POR_WDG_EN,POR Watchdog (POR_WDG) Status" "0: Disabled,1: Enabled" line.long 0x8 "DCMROF21,Read-Only GPR On Functional Reset 21" bitfld.long 0x8 19.--20. "HSE_CLK_MODE_OPTION,HSE_B Clock Mode Option" "0: Option A,1: Options C D E E2 and F,2: Option B,3: Option B" newline hexmask.long.tbyte 0x8 0.--17. 1. "DCF_DEST_RST_ESC,DCF Destructive Reset Escalation" group.long 0x400++0x3 line.long 0x0 "DCMRWP1,Read Write GPR On POR 1" bitfld.long 0x0 23. "SBAF_REC_DIS_DRST,Disable Recovery Mode On Destructive Reset" "0,1" newline bitfld.long 0x0 22. "SBAF_REC_DIS_FRST,Disable Recovery Mode On Functional Reset" "0,1" newline hexmask.long.byte 0x0 16.--20. 1. "SYS_REC_COUNTER,System Recovery Counter" newline hexmask.long.byte 0x0 11.--14. 1. "DEST_RESET_COUNT,Destructive Reset Counts" newline bitfld.long 0x0 9.--10. "POR_WDOG_TRIM,POR_WDG Trim" "0: POR_WDG timeout = 06.25 ms,1: POR_WDG timeout = 12.50 ms,2: POR_WDG timeout = 25.00 ms,3: POR_WDG timeout = 50.00 ms" newline bitfld.long 0x0 8. "STANBDY_PWDOG_DIS,Standby POR_WDG Disable" "0: Enables,1: Disables" newline bitfld.long 0x0 3. "CLKOUT_STANDBY,Clockout Standby Expose Over Functional And Destructive Reset" "0: No,1: Yes" group.long 0x408++0x3 line.long 0x0 "DCMRWP3,Read Write GPR On POR 3" bitfld.long 0x0 9. "DEST_RST9_AS_IPI,Destructive Reset 9" "0: Destructive reset,1: PLL LOL interrupt" group.long 0x504++0x1F line.long 0x0 "DCMRWD2,Read Write GPR On Destructive Reset 2" bitfld.long 0x0 7. "EOUT_STAT_DUR_STEST,Controls the EOUT state during self-test" "0: High impedance,1: Fault state" line.long 0x4 "DCMRWD3,Read Write GPR On Destructive Reset 3" bitfld.long 0x4 30. "CM7_0_ICDATA_ECC_ERR_EN,Cortex-M7_0 I-cache ECC Error Enable" "0: No,1: Yes" newline bitfld.long 0x4 28. "CM7_0_DCTAG_ECC_ERR_EN,Cortex-M7_0 D-cache Tag ECC Error Enable" "0: No,1: Yes" newline bitfld.long 0x4 26. "CM7_0_DCDATA_ECC_ERR_EN,Cortex-M7_0 D-cache Data ECC Error Enable" "0: No,1: Yes" newline bitfld.long 0x4 25. "PRAM0_ECC_ERR_EN,PRAM0 ECC Error Enable" "0: No,1: Yes" newline bitfld.long 0x4 24. "PRAM1_ECC_ERR_EN,PRAM1 ECC Error Enable" "0: No,1: Yes" newline bitfld.long 0x4 23. "PRAM2_ECC_ERR_EN,Enable bit for enabling the fault monitoring at FCCU NCF 2 for the fault: Multi bit ECC error from SRAM1" "0: No multi-bit ECC error.,1: Multi-bit ECC error." newline bitfld.long 0x4 22. "LC_ERR_EN,Life Cycle Scanning Error Enable" "0: No,1: Yes" newline bitfld.long 0x4 21. "PF3_DATA_ECC_ERR_EN,Program Flash Memory 3 Data ECC Error Enable" "0: No,1: Yes" newline bitfld.long 0x4 20. "PF3_CODE_ECC_ERR_EN,Program Flash Memory 3 Code ECC Error Enable" "0: No,1: Yes" newline bitfld.long 0x4 19. "PERIPH_AXBS_ALARM_EN,Peripheral AXBS Alarm Enable" "0: No,1: Yes" newline bitfld.long 0x4 18. "MAC_GSKT_ALARM_EN,MAC Gasket Alarm Enable" "0: No,1: Yes" newline bitfld.long 0x4 17. "TCM_AXBS_ALARM_EN,TCM AXBS Alarm Enable" "0: No,1: Yes" newline bitfld.long 0x4 16. "DATA_EDC_ERR_EN,Data EDC Error Enable" "0: No,1: Yes" newline bitfld.long 0x4 15. "ADDR_EDC_ERR_EN,Address EDC Error Enable" "0: No,1: Yes" newline bitfld.long 0x4 14. "AIPS2_GSKT_ALARM_EN,Enable bit for enabling the fault monitoring at FCCU NCF 1 for the fault: AIPS2 IAHB gasket alarm." "0: No alarm indicated by AIPS2 IAHB gasket.,1: Alarm indicated by AIPS2 IAHB gasket." newline bitfld.long 0x4 13. "AIPS1_GSKT_ALARM_EN,Enable bit for enabling the fault monitoring at FCCU NCF 1 for the fault: AIPS1 IAHB gasket alarm." "0: No alarm indicated by AIPS1 IAHB gasket.,1: Alarm indicated by AIPS1 IAHB gasket." newline bitfld.long 0x4 12. "QSPI_GSKT_ALARM_EN,QuadSPI Gasket Alarm Enable" "0: No,1: Yes" newline bitfld.long 0x4 11. "HSE_GSKT_ALARM_EN,HSE_B Gasket Alarm Enable" "0: No,1: Yes" newline bitfld.long 0x4 9. "DMA_AXBS_ALARM_EN,DMA AXBS Alarm Enable" "0: No,1: Yes" newline bitfld.long 0x4 8. "SYS_AXBS_ALARM_EN,System AXBS Alarm Enable" "0: No,1: Yes" newline bitfld.long 0x4 7. "DMA_PERIPH_GSKT_ALARM_EN,TCM Gasket Alarm Enable" "0: No,1: Yes" newline bitfld.long 0x4 6. "DMA_SYS_GSKT_ALARM_EN,DMA System Gasket Alarm Enable" "0: No,1: Yes" newline bitfld.long 0x4 5. "TCM_GSKT_ALARM_EN,TCM Gasket Alarm Enable" "0: No,1: Yes" newline bitfld.long 0x4 4. "CM7_RCCU2_ALARM_EN,Cortex-M7 RCCU2 Alarm Enable" "0: No,1: Yes" newline bitfld.long 0x4 3. "CM7_RCCU1_ALARM_EN,Cortex-M7 RCCU1 Alarm Enable" "0: No,1: Yes" newline bitfld.long 0x4 0. "CM7_0_LOCKUP_EN,Cortex-M7 Lockup Enable" "0: No,1: Yes" line.long 0x8 "DCMRWD4,Read Write GPR On Destructive Reset 4" bitfld.long 0x8 31. "CM7_2_LOCKUP_EN,Enable bit for enabling the fault monitoring at FCCU NCF 0 for the fault: CM7_2 core lockup." "0: CM7_2 core not in lockup state.,1: CM7_2 core in lockup state." newline bitfld.long 0x8 30. "TEST_ACTIVATION_1_ERR_EN,Test Activation 1 Error Enable" "0: No,1: Yes" newline bitfld.long 0x8 29. "TEST_ACTIVATION_0_ERR_EN,Test Activation 0 Error Enable" "0: No,1: Yes" newline bitfld.long 0x8 27. "VDD2P5_GNG_ERR_EN,VDD2P5 Go/No-go Error Enable" "0: Clean,1: Unclean" newline bitfld.long 0x8 26. "VDD1P1_GNG_ERR_EN,VDD1PD1 Go/No-go Error Enable" "0: Clean,1: Unclean" newline bitfld.long 0x8 24. "FLASH_ACCESS_ERR_EN,Flash Memory Access Error Enable" "0: No,1: Yes" newline bitfld.long 0x8 23. "PRAM2_FCCU_ALARM_EN,Enable bit for enabling the fault monitoring at FCCU NCF 2 for the fault: PRAM2 safety alarm" "0: No safety alarm indicated by PRAM2.,1: Safety alarm indicated by PRAM2." newline bitfld.long 0x8 22. "FLASH_SCAN_ERR_EN,Flash Memory Scanning Error Enable" "0: No,1: Yes" newline bitfld.long 0x8 21. "FLASH_RST_ERR_EN,Flash Memory Reset Error Enable" "0: No,1: Yes" newline bitfld.long 0x8 20. "FLASH_REF_ERR_EN,Flash Memory Reference Error Encode" "0: No,1: Yes" newline bitfld.long 0x8 19. "FLASH_ADDR_ENC_ERR_EN,Flash Memory Address Encode Error Enable" "0: No,1: Yes" newline bitfld.long 0x8 18. "FLASH_EDC_ERR_EN,Flash Memory EDC Error Enable" "0: No,1: Yes" newline bitfld.long 0x8 15. "PF1_DATA_ECC_ERR_EN,PF1 Data ECC Error Enable" "0: No,1: Yes" newline bitfld.long 0x8 14. "PF1_CODE_ECC_ERR_EN,PF1 Code ECC Error Enable" "0: No,1: Yes" newline bitfld.long 0x8 13. "PF0_DATA_ECC_ERR_EN,PF0 Data ECC Error Enable" "0: No,1: Yes" newline bitfld.long 0x8 12. "PF0_CODE_ECC_ERR_EN,PF0 Code ECC Error Enable" "0: No,1: Yes" newline bitfld.long 0x8 10. "PRAM1_FCCU_ALARM_EN,PRAM1 FCCU Alarm Enable" "0: No,1: Yes" newline bitfld.long 0x8 9. "PRAM0_FCCU_ALARM_EN,PRAM0 FCCU Alarm Enable" "0: No,1: Yes" newline bitfld.long 0x8 8. "DMA_TCD_RAM_ECC_ERR_EN,eDMA TCD RAM ECC Error Enable" "0: No,1: Yes" newline bitfld.long 0x8 7. "CM7_1_DTCM1_ECC_ERR_EN,Cortex-M7_1 DTCM 1 ECC Error Enable" "0: No,1: Yes" newline bitfld.long 0x8 6. "CM7_1_DTCM0_ECC_ERR_EN,Cortex-M7_1 DTCM 0 ECC Error Enable" "0: No,1: Yes" newline bitfld.long 0x8 5. "CM7_1_ITCM_ECC_ERR_EN,Cortex-M7_1 ITCM ECC Error Enable" "0: No,1: Yes" newline bitfld.long 0x8 4. "CM7_0_DTCM1_ECC_ERR_EN,Cortex-M7_0 DTCM 1 ECC Error Enable" "0: No,1: Yes" newline bitfld.long 0x8 3. "CM7_0_DTCM0_ECC_ERR_EN,Cortex-M7_0 DTCM 0 ECC Error Enable" "0: No,1: Yes" newline bitfld.long 0x8 2. "CM7_0_ITCM_ECC_ERR_EN,Cortex-M7 ITCM ECC Error Enable" "0: No,1: Yes" newline bitfld.long 0x8 0. "CM7_0_ICTAG_ECC_ERR_EN,Cortex-M7_0 I-cache Tag ECC Error Enable" "0: No,1: Yes" line.long 0xC "DCMRWD5,Read Write GPR On Destructive Reset 5" bitfld.long 0xC 31. "CM7_2_DTCM1_ECC_ERR_EN,Cortex-M7_2 DTCM 1 ECC Error Enable" "0: No,1: Yes" newline bitfld.long 0xC 30. "CM7_2_DTCM0_ECC_ERR_EN,Cortex-M7_2 DTCM 0 ECC Error Enable" "0: No,1: Yes" newline bitfld.long 0xC 29. "CM7_2_ITCM_ECC_ERR_EN,Cortex-M7_2 ITCM ECC Error Enable" "0: No,1: Yes" newline bitfld.long 0xC 28. "CM7_2_ICTAG_ECC_ERR_EN,Cortex-M7_2 I-cache Tag ECC Error Enable" "0: No,1: Yes" newline bitfld.long 0xC 27. "CM7_2_ICDATA_ECC_ERR_EN,Cortex-M7_2 I-cache Data ECC Error Enable" "0: No,1: Yes" newline bitfld.long 0xC 26. "CM7_2_DCTAG_ECC_ERR_EN,Cortex-M7_2 D-cache Tag ECC Error Enable" "0: No,1: Yes" newline bitfld.long 0xC 25. "CM7_2_DCDATA_ECC_ERR_EN,Cortex-M7_2 D-cache Data ECC Error Enable" "0: No,1: Yes" newline bitfld.long 0xC 24. "CM7_2_AHBM_RDATA_EDC_ERR_EN,Cortex-M7_2 AHBM Read Data EDC Error Enable" "0: No,1: Yes" newline bitfld.long 0xC 23. "CM7_2_AHBP_RDATA_EDC_ERR_EN,Cortex-M7_2 AHBP Read Data EDC Error Enable" "0: No,1: Yes" newline bitfld.long 0xC 21. "CM7_0_AHBM_RDATA_EDC_ERR_EN,Cortex-M7_0 AHBM Read Data EDC Error Enable" "0: No,1: Yes" newline bitfld.long 0xC 20. "CM7_0_AHBP_RDATA_EDC_ERR_EN,Cortex-M7_0 AHBP Read Data EDC Error Enable" "0: No,1: Yes" newline bitfld.long 0xC 17. "DMA_RDATA_EDC_ERR_EN,eDMA Read Data EDC Error Enable" "0: No,1: Yes" newline bitfld.long 0xC 15. "MAC_RDATA_EDC_ERR_EN,MAC Read Data EDC Error Enable" "0: No,1: Yes" newline bitfld.long 0xC 13. "DEBUG_ACTIVATION_ERR_EN,Debug Activation Error Enable" "0: No,1: Yes" newline bitfld.long 0xC 12. "MCT_BUS_ERR_EN,MCT Bus Error Enable" "0: No transfer error indicated from MCT.,1: Transfer error indicated from MCT." newline bitfld.long 0xC 11. "STCU_BIST_USER_CF_EN,STCU2 BIST User CF Enable" "0: No,1: Yes" newline bitfld.long 0xC 10. "MBIST_ACTIVATION_ERR_EN,MBIST Activation Error Enable" "0: No,1: Yes" newline bitfld.long 0xC 9. "STCU_NCF_EN,STCU2 NCF Enable" "0: Disables,1: Enables" newline bitfld.long 0xC 8. "SW_NCF_3_EN,Software NCF 3 Enable" "0: Disables,1: Enables" newline bitfld.long 0xC 7. "SW_NCF_2_EN,Software NCF 2 Enable" "0: Disables,1: Enables" newline bitfld.long 0xC 6. "SW_NCF_1_EN,Software NCF 1 Enable" "0: Disables,1: Enables" newline bitfld.long 0xC 5. "SW_NCF_0_EN,Software NCF 0 Enable" "0: Disables,1: Enables" newline bitfld.long 0xC 4. "INTM_3_ERR_EN,INTM 3 Error Enable" "0: No,1: Yes" newline bitfld.long 0xC 3. "INTM_2_ERR_EN,INTM 2 Error Enable" "0: No,1: Yes" newline bitfld.long 0xC 2. "INTM_1_ERR_EN,INTM 1 Error Enable" "0: No,1: Yes" newline bitfld.long 0xC 1. "INTM_0_ERR_EN,INTM 0 Error Enable" "0: No,1: Yes" line.long 0x10 "DCMRWD6,Read Write GPR On Destructive Reset 6" bitfld.long 0x10 31. "SAI1_DBG_DIS_CM7_0,SAI1 debug disable bit for CM7_0. Set this bit 1 to disable the debug of IP." "0: SAI1 enters debug mode when CM7_0 enters debug..,1: SAI1 remains functional and is not impacted when.." newline bitfld.long 0x10 30. "SAI0_DBG_DIS_CM7_0,SAI0 debug disable bit for CM7_0. Set this bit 1 to disable the debug of IP." "0: SAI0 enters debug mode when CM7_0 enters debug..,1: SAI0 remains functional and is not impacted when.." newline bitfld.long 0x10 29. "FLEXCAN5_DBG_DIS_CM7_0,FlexCAN_5 Debug Disable Cortex-M7_0" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x10 28. "FLEXCAN4_DBG_DIS_CM7_0,FlexCAN_4 Debug Disable Cortex-M7_0" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x10 27. "FLEXCAN3_DBG_DIS_CM7_0,FlexCAN_3 Debug Disable Cortex-M7_0" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x10 26. "FLEXCAN2_DBG_DIS_CM7_0,FlexCAN_2 Debug Disable Cortex-M7_0" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x10 25. "FLEXCAN1_DBG_DIS_CM7_0,FlexCAN_1 Debug Disable Cortex-M7_0" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x10 24. "FLEXCAN0_DBG_DIS_CM7_0,FlexCAN_0 Debug Disable Cortex-M7_0" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x10 23. "FLEXIO_DBG_DIS_CM7_0,FlexIO Debug Disable Cortex-M7_0" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x10 22. "LPI2C1_DBG_DIS_CM7_0,LPI2C_1 Debug Disable Cortex-M7_0" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x10 21. "LPI2C0_DBG_DIS_CM7_0,LPI2C_0 Debug Disable Cortex-M7_0" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x10 20. "LPSPI5_DBG_DIS_CM7_0,LPSPI_5 Debug Disable Cortex-M7_0" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x10 19. "LPSPI4_DBG_DIS_CM7_0,LPSPI_4 Debug Disable Cortex-M7_0" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x10 18. "LPSPI3_DBG_DIS_CM7_0,LPSPI_3 Debug Disable Cortex-M7_0" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x10 17. "LPSPI2_DBG_DIS_CM7_0,LPSPI_2 Debug Disable Cortex-M7_0" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x10 16. "LPSPI1_DBG_DIS_CM7_0,LPSPI_1 Debug Disable Cortex-M7_0" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x10 15. "LPSPI0_DBG_DIS_CM7_0,LPSPI_0 Debug Disable Cortex-M7_0" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x10 14. "PIT2_DBG_DIS_CM7_0,PIT_2 Debug Disable Cortex-M7_0" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x10 13. "PIT1_DBG_DIS_CM7_0,PIT_1 Debug Disable Cortex-M7_0" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x10 12. "PIT0_DBG_DIS_CM7_0,PIT_0 Debug Disable Cortex-M7_0" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x10 11. "STM1_DBG_DIS_CM7_0,STM_1 Debug Disable Cortex-M7_0" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x10 10. "STM0_DBG_DIS_CM7_0,STM_0 Debug Disable Cortex-M7_0" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x10 8. "SWT0_DBG_DIS_CM7_0,SWT_0 Debug Disable Cortex-M7_0" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x10 7. "RTC_DBG_DIS_CM7_0,RTC Debug Disable Cortex-M7_0" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x10 6. "EMIOS2_DBG_DIS_CM7_0,EMIOS2 debug disable bit for CM7_0. Set this bit 1 to disable the debug of IP." "0: eMIOS2 enters debug mode when CM7_0 enters debug..,1: eMIOS2 remains functional and is not impacted.." newline bitfld.long 0x10 5. "EMIOS1_DBG_DIS_CM7_0,EMIOS1 debug disable bit for CM7_0. Set this bit 1 to disable the debug of IP." "0: eMIOS1 enters debug mode when CM7_0 enters debug..,1: eMIOS1 remains functional and is not impacted.." newline bitfld.long 0x10 4. "EMIOS0_DBG_DIS_CM7_0,eMIOS_0 Debug Disable Cortex-M7_0" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x10 3. "LCU1_DBG_DIS_CM7_0,LCU_1 Debug Disable Cortex-M7_0" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x10 2. "LCU0_DBG_DIS_CM7_0,LCU_0 Debug Disable Cortex-M7_0" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x10 1. "FCCU_DBG_DIS_CM7_0,FCCU Debug Disable Cortex-M7_0" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x10 0. "EDMA_DBG_DIS_CM7_0,eDMA Debug Disable Cortex-M7_0" "0: Enters Debug mode,1: Remains functional and unimpacted" line.long 0x14 "DCMRWD7,Read Write GPR On Destructive Reset 7" bitfld.long 0x14 25. "FLEXCAN9_DBG_DIS_CM7_0,FLEXCAN9 Debug Disable Cortex-M7_0" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x14 23. "PIT3_DBG_DIS_CM7_0,PIT3 Debug Disable Cortex-M7_0" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x14 22. "STM3_DBG_DIS_CM7_0,STM3 Debug Disable Cortex-M7_0" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x14 21. "SWT3_DBG_DIS_CM7_0,SWT3 Debug Disable Cortex-M7_0" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x14 4. "SWT2_DBG_DIS_CM7_0,SWT_2 Debug Disable Cortex-M7_0" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x14 3. "STM2_DBG_DIS_CM7_0,STM_2 Debug Disable Cortex-M7_0" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x14 2. "FLEXCAN7_DBG_DIS_CM7_0,FLEXCAN7 debug disable bit for CM7_0. Set this bit 1 to disable the debug of module." "0: FLEXCAN7 enters debug mode when CM7_0 enters..,1: FLEXCAN7 remains functional and is not impacted.." newline bitfld.long 0x14 1. "FLEXCAN6_DBG_DIS_CM7_0,FLEXCAN6 debug disable bit for CM7_0. Set this bit 1 to disable the debug of module." "0: FLEXCAN6 enters debug mode when CM7_0 enters..,1: FLEXCAN6 remains functional and is not impacted.." line.long 0x18 "DCMRWD8,Read Write GPR On Destructive Reset 8" bitfld.long 0x18 31. "SAI1_DBG_DIS_CM7_1,SAI1 debug disable bit for CM7_1. Set this bit 1 to disable the debug of IP." "0: SAI1 enters debug mode when CM7_1 enters debug..,1: SAI1 remains functional and is not impacted when.." newline bitfld.long 0x18 30. "SAI0_DBG_DIS_CM7_1,SAI0 debug disable bit for CM7_1. Set this bit 1 to disable the debug of IP." "0: SAI0 enters debug mode when CM7_1 enters debug..,1: SAI0 remains functional and is not impacted when.." newline bitfld.long 0x18 29. "FLEXCAN5_DBG_DIS_CM7_1,FlexCAN_5 Debug Disable Cortex-M7_1" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x18 28. "FLEXCAN4_DBG_DIS_CM7_1,FlexCAN_4 Debug Disable Cortex-M7_1" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x18 27. "FLEXCAN3_DBG_DIS_CM7_1,FlexCAN_3 Debug Disable Cortex-M7_1" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x18 26. "FLEXCAN2_DBG_DIS_CM7_1,FlexCAN_2 Debug Disable Cortex-M7_1" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x18 25. "FLEXCAN1_DBG_DIS_CM7_1,FlexCAN_1 Debug Disable Cortex-M7_1" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x18 24. "FLEXCAN0_DBG_DIS_CM7_1,FlexCAN_0 Debug Disable Cortex-M7_1" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x18 23. "FLEXIO_DBG_DIS_CM7_1,FlexIO Debug Disable Cortex-M7_1" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x18 22. "LPI2C1_DBG_DIS_CM7_1,LPI2C_1 Debug Disable Cortex-M7_1" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x18 21. "LPI2C0_DBG_DIS_CM7_1,LPI2C_0 Debug Disable Cortex-M7_1" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x18 20. "LPSPI5_DBG_DIS_CM7_1,LPSPI_5 Debug Disable Cortex-M7_1" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x18 19. "LPSPI4_DBG_DIS_CM7_1,LPSPI_4 Debug Disable Cortex-M7_1" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x18 18. "LPSPI3_DBG_DIS_CM7_1,LPSPI_3 Debug Disable Cortex-M7_1" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x18 17. "LPSPI2_DBG_DIS_CM7_1,LPSPI_2 Debug Disable Cortex-M7_1" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x18 16. "LPSPI1_DBG_DIS_CM7_1,LPSPI_1 Debug Disable Cortex-M7_1" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x18 15. "LPSPI0_DBG_DIS_CM7_1,LPSPI_0 Debug Disable Cortex-M7_1" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x18 14. "PIT2_DBG_DIS_CM7_1,PIT_2 Debug Disable Cortex-M7_1" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x18 13. "PIT1_DBG_DIS_CM7_1,PIT_1 Debug Disable Cortex-M7_1" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x18 12. "PIT0_DBG_DIS_CM7_1,PIT_0 Debug Disable Cortex-M7_1" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x18 11. "STM1_DBG_DIS_CM7_1,STM_1 Debug Disable Cortex-M7_1" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x18 10. "STM0_DBG_DIS_CM7_1,STM_0 Debug Disable Cortex-M7_1" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x18 9. "SWT1_DBG_DIS_CM7_1,SWT_1 Debug Disable Cortex-M7_1" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x18 8. "SWT0_DBG_DIS_CM7_1,SWT_0 Debug Disable Cortex-M7_1" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x18 7. "RTC_DBG_DIS_CM7_1,RTC Debug Disable Cortex-M7_1" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x18 6. "EMIOS2_DBG_DIS_CM7_1,EMIOS2 debug disable bit for CM7_1. Set this bit 1 to disable the debug of IP." "0: EMIOS2 enters debug mode when CM7_1 enters debug..,1: EMIOS2 remains functional and is not impacted.." newline bitfld.long 0x18 5. "EMIOS1_DBG_DIS_CM7_1,EMIOS1 debug disable bit for CM7_1. Set this bit 1 to disable the debug of IP." "0: EMIOS1 enters debug mode when CM7_1 enters debug..,1: EMIOS1 remains functional and is not impacted.." newline bitfld.long 0x18 4. "EMIOS0_DBG_DIS_CM7_1,eMIOS_0 Debug Disable Cortex-M7_1" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x18 3. "LCU1_DBG_DIS_CM7_1,LCU_1 Debug Disable Cortex-M7_1" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x18 2. "LCU0_DBG_DIS_CM7_1,LCU_0 Debug Disable Cortex-M7_1" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x18 1. "FCCU_DBG_DIS_CM7_1,FCCU Debug Disable Cortex-M7_1" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x18 0. "EDMA_DBG_DIS_CM7_1,eDMA Debug Disable Cortex-M7_1" "0: Enters Debug mode,1: Remains functional and unimpacted" line.long 0x1C "DCMRWD9,Read Write GPR On Destructive Reset 9" bitfld.long 0x1C 25. "FLEXCAN9_DBG_DIS_CM7_1,FLEXCAN9 Debug Disable Cortex-M7_1" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x1C 23. "PIT3_DBG_DIS_CM7_1,PIT3 Debug Disable Cortex-M7_1" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x1C 22. "STM3_DBG_DIS_CM7_1,STM3 Debug Disable Cortex-M7_1" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x1C 21. "SWT3_DBG_DIS_CM7_1,SWT3 Debug Disable Cortex-M7_1" "0: Enters Debug mode,1: Remains functional and unimpacted" group.long 0x52C++0x17 line.long 0x0 "DCMRWD12,Read Write GPR On Destructive Reset 12" bitfld.long 0x0 31. "SAI1_DBG_DIS_CM7_2,SAI1 debug disable bit for CM7_2. Set this bit 1 to disable the debug of module." "0: SAI1 enters debug mode when CM7_2 enters debug..,1: SAI1 remains functional and is not impacted when.." newline bitfld.long 0x0 30. "SAI0_DBG_DIS_CM7_2,SAI0 debug disable bit for CM7_2. Set this bit 1 to disable the debug of module." "0: SAI0 enters debug mode when CM7_2 enters debug..,1: SAI0 remains functional and is not impacted when.." newline bitfld.long 0x0 29. "FLEXCAN5_DBG_DIS_CM7_2,FlexCAN5 Debug Disable For Cortex M7_2" "0: Enables Debug mode,1: Disables Debug mode" newline bitfld.long 0x0 28. "FLEXCAN4_DBG_DIS_CM7_2,FlexCAN4 Debug Disable For Cortex M7_2" "0: Enables Debug mode,1: Disables Debug mode" newline bitfld.long 0x0 27. "FLEXCAN3_DBG_DIS_CM7_2,FlexCAN3 Debug Disable For Cortex M7_2" "0: Enables Debug mode,1: Disables Debug mode" newline bitfld.long 0x0 26. "FLEXCAN2_DBG_DIS_CM7_2,FlexCAN2 Debug Disable For Cortex M7_2" "0: Enables Debug mode,1: Disables Debug mode" newline bitfld.long 0x0 25. "FLEXCAN1_DBG_DIS_CM7_2,FlexCAN1 Debug Disable For Cortex M7_2" "0: Enables Debug mode,1: Disables Debug mode" newline bitfld.long 0x0 24. "FLEXCAN0_DBG_DIS_CM7_2,FlexCAN0 Debug Disable For Cortex M7_2" "0: Enables Debug mode,1: Disables Debug mode" newline bitfld.long 0x0 23. "FLEXIO_DBG_DIS_CM7_2,FlexIO Debug Disable For Cortex M7_2" "0: Enables Debug mode,1: Disables Debug mode" newline bitfld.long 0x0 22. "LPI2C1_DBG_DIS_CM7_2,LPI2C1 Debug Disable For Cortex M7_2" "0: Enables Debug mode,1: Disables Debug mode" newline bitfld.long 0x0 21. "LPI2C0_DBG_DIS_CM7_2,LPI2C0 Debug Disable For Cortex M7_2" "0: Enables Debug mode,1: Disables Debug mode" newline bitfld.long 0x0 20. "LPSPI5_DBG_DIS_CM7_2,LPSPI5 Debug Disable For Cortex M7_2" "0: Enables Debug mode,1: Disables Debug mode" newline bitfld.long 0x0 19. "LPSPI4_DBG_DIS_CM7_2,LPSPI4 Debug Disable For Cortex M7_2" "0: Enables Debug mode,1: Disables Debug mode" newline bitfld.long 0x0 18. "LPSPI3_DBG_DIS_CM7_2,LPSPI3 Debug Disable For Cortex M7_2" "0: Enables Debug mode,1: Disables Debug mode" newline bitfld.long 0x0 17. "LPSPI2_DBG_DIS_CM7_2,LPSPI2 Debug Disable For Cortex M7_2" "0: Enables Debug mode,1: Disables Debug mode" newline bitfld.long 0x0 16. "LPSPI1_DBG_DIS_CM7_2,LPSPI1 Debug Disable For Cortex M7_2" "0: Enables Debug mode,1: Disables Debug mode" newline bitfld.long 0x0 15. "LPSPI0_DBG_DIS_CM7_2,LPSPI0 Debug Disable For Cortex M7_2" "0: Enables Debug mode,1: Disables Debug mode" newline bitfld.long 0x0 14. "PIT2_DBG_DIS_CM7_2,PIT2 Debug Disable For Cortex M7_2" "0: Enables Debug mode,1: Disables Debug mode" newline bitfld.long 0x0 13. "PIT1_DBG_DIS_CM7_2,PIT1 Debug Disable For Cortex M7_2" "0: Enables Debug mode,1: Disables Debug mode" newline bitfld.long 0x0 12. "PIT0_DBG_DIS_CM7_2,PIT0 Debug Disable For Cortex M7_2" "0: Enables Debug mode,1: Disables Debug mode" newline bitfld.long 0x0 11. "STM1_DBG_DIS_CM7_2,STM1 Debug Disable For Cortex M7_2" "0: Enables Debug mode,1: Disables Debug mode" newline bitfld.long 0x0 10. "STM0_DBG_DIS_CM7_2,STM0 Debug Disable For Cortex M7_2" "0: Enables Debug mode,1: Disables Debug mode" newline bitfld.long 0x0 8. "SWT0_DBG_DIS_CM7_2,SWT0 Debug Disable For Cortex M7_2" "0: Enables Debug mode,1: Disables Debug mode" newline bitfld.long 0x0 7. "RTC_DBG_DIS_CM7_2,RTC Debug Disable For Cortex M7_2" "0: Enables Debug mode,1: Disables Debug mode" newline bitfld.long 0x0 6. "eMIOS2_DBG_DIS_CM7_2,eMIOS2 debug disable bit for CM7_2. Set this bit 1 to disable the debug of module." "0: eMIOS2 enters debug mode when CM7_2 enters debug..,1: eMIOS2 remains functional and is not impacted.." newline bitfld.long 0x0 5. "eMIOS1_DBG_DIS_CM7_2,eMIOS1 debug disable bit for CM7_2. Set this bit 1 to disable the debug of module." "0: eMIOS1 enters debug mode when CM7_2 enters debug..,1: eMIOS1 remains functional and is not impacted.." newline bitfld.long 0x0 4. "eMIOS0_DBG_DIS_CM7_2,eMIOS0 Debug Disable For Cortex M7_2" "0: Enables Debug mode,1: Disables Debug mode" newline bitfld.long 0x0 3. "LCU1_DBG_DIS_CM7_2,LCU1 Debug Disable For Cortex M7_2" "0: Enables Debug mode,1: Disables Debug mode" newline bitfld.long 0x0 2. "LCU0_DBG_DIS_CM7_2,LCU0 Debug Disable For Cortex M7_2" "0: Enables Debug mode,1: Disables Debug mode" newline bitfld.long 0x0 1. "FCCU_DBG_DIS_CM7_2,FCCU Debug Disable For Cortex M7_2" "0: Enables Debug mode,1: Disables Debug mode" newline bitfld.long 0x0 0. "EDMA_DBG_DIS_CM7_2,eDMA Debug Disable For Cortex M7_2" "0: Enables Debug mode,1: Disables Debug mode" line.long 0x4 "DCMRWD13,Read Write GPR On Destructive Reset 13" bitfld.long 0x4 25. "FLEXCAN9_DBG_DIS_CM7_2,FLEXCAN9 Debug Disable Cortex-M7_2" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x4 23. "PIT3_DBG_DIS_CM7_2,PIT3 Debug Disable Cortex-M7_2" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x4 22. "STM3_DBG_DIS_CM7_2,STM3 Debug Disable Cortex-M7_2" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x4 21. "SWT3_DBG_DIS_CM7_2,SWT3 Debug Disable Cortex-M7_2" "0: Enters Debug mode,1: Remains functional and unimpacted" newline bitfld.long 0x4 4. "SWT2_DBG_DIS_CM7_2,SWT2 Debug Disable For Cortex-M7_2" "0: Enables Debug mode,1: Disables Debug mode" newline bitfld.long 0x4 3. "STM2_DBG_DIS_CM7_2,STM2 Debug Disable For Cortex-M7_2" "0: Enables Debug mode,1: Disables Debug mode" newline bitfld.long 0x4 2. "FLEXCAN7_DBG_DIS_CM7_2,FLEXCAN7 debug disable bit for CM7_2. Set this bit 1 to disable the debug of module." "0: FLEXCAN7 enters debug mode when CM7_2 enters..,1: FLEXCAN7 remains functional and is not impacted.." newline bitfld.long 0x4 1. "FLEXCAN6_DBG_DIS_CM7_2,FlexCAN6 Debug Disable For Cortex-M7_2" "0: Enables Debug mode,1: Disables Debug mode" line.long 0x8 "DCMRWD14,Read Write GPR On Destructive Reset 14" bitfld.long 0x8 30. "TCM_PRAM_AXBS_ALARM_EN,TCM_PRAM AXBS Alarm Enable" "0: No,1: Yes" newline bitfld.long 0x8 26. "AIPS0_GSKT_ALARM_EN,AIPS0 Gasket Alarm Enable" "0: No,1: Yes" newline bitfld.long 0x8 3. "QSPI_FLASHA_ECC_ERR_EN,QSPI FLASHA ECC Error Enable" "0: No,1: Yes" line.long 0xC "DCMRWD15,Read Write GPR On Destructive Reset 15" bitfld.long 0xC 30. "CM7_2_AHBS_ALARM_EN,Cortex-M7_2 AHBS Alarm Enable" "0: No,1: Yes" newline bitfld.long 0xC 28. "CM7_0_AHBS_ALARM_EN,Cortex-M7_0 AHBS Alarm Enable" "0: No,1: Yes" newline bitfld.long 0xC 12. "VDD2P5_GNG2_ERR_EN,VDD2P5 Go Nogo Error Enable" "0: Go indication referring to the supply being clean.,1: No go indication referring to the supply being.." newline bitfld.long 0xC 11. "VDD1P1_GNG2_ERR_EN,VDD1P1 Go Nogo Error Enable" "0: Go indication referring to the supply being clean.,1: No go indication referring to the supply being.." newline bitfld.long 0xC 5. "CM7_2_AHBP_ALARM_EN,Cortex-M7_2 AHBP Alarm Enable" "0: No,1: Yes" newline bitfld.long 0xC 4. "CM7_1_AHBP_ALARM_EN,Cortex-M7_1 AHBP Alarm Enable" "0: No,1: Yes" newline bitfld.long 0xC 3. "CM7_0_AHBP_ALARM_EN,Cortex-M7_0 AHBP Alarm Enable" "0: No,1: Yes" newline bitfld.long 0xC 2. "CM7_2_AHBM_ALARM_EN,Cortex-M7_2 AHBM Alarm Enable" "0: No,1: Yes" newline bitfld.long 0xC 1. "CM7_1_AHBM_ALARM_EN,Cortex-M7_1 AHBM Alarm Enable" "0: No,1: Yes" newline bitfld.long 0xC 0. "CM7_0_AHBM_ALARM_EN,Cortex-M7_0 AHBM Alarm Enable" "0: No,1: Yes" line.long 0x10 "DCMRWD16,Read Write GPR On Destructive Reset 16" bitfld.long 0x10 29. "CM7_3_DTCM1_ECC_ERR_EN,Enables bit for enabling the fault monitoring at FCCU NCF 2 for the fault: Uncorrectable ECC error from CM7_3 Data TCM memory block 1" "0: Uncorrectable ECC error detection at FCCU not..,1: Uncorrectable ECC error detection enabled at FCCU." newline bitfld.long 0x10 28. "CM7_3_DTCM0_ECC_ERR_EN,Enables bit for enabling the fault monitoring at FCCU NCF 2 for the fault: Uncorrectable ECC error from CM7_3 Data TCM memory block 0" "0: Uncorrectable ECC error detection at FCCU not..,1: Uncorrectable ECC error detection enabled at FCCU." newline bitfld.long 0x10 27. "CM7_3_ITCM_ECC_ERR_EN,Enables bit for enabling the fault monitoring at FCCU NCF 2 for the fault: Uncorrectable ECC error from CM7_3 Instruction TCM memory" "0: Uncorrectable ECC error detection at FCCU not..,1: Uncorrectable ECC error detection enabled at FCCU." newline bitfld.long 0x10 26. "CM7_3_ICTAG_ECC_ERR_EN,Enables bit for enabling the fault monitoring at FCCU NCF 2 for the fault: Multi bit ECC error from CM7_3 ICache tag memory" "0: No multi-bit ECC error.,1: Multi-bit ECC error." newline bitfld.long 0x10 25. "CM7_3_ICDATA_ECC_ERR_EN,Enables bit for enabling the fault monitoring at FCCU NCF 2 for the fault: Multi bit ECC error from CM7_3 ICache data memory" "0: No multi-bit ECC error.,1: Multi-bit ECC error." newline bitfld.long 0x10 24. "CM7_3_DCTAG_ECC_ERR_EN,Enables bit for enabling the fault monitoring at FCCU NCF 2 for the fault: Multi bit ECC error from CM7_3 DCache tag memory" "0: No multi-bit ECC error.,1: Multi-bit ECC error." newline bitfld.long 0x10 23. "CM7_3_DCDATA_ECC_ERR_EN,Enables bit for enabling the fault monitoring at FCCU NCF 2 for the fault: Multi bit ECC error from CM7_3 DCache data memory" "0: No multi-bit ECC error.,1: Multi-bit ECC error." newline bitfld.long 0x10 22. "CM7_3_AHBP_ALARM_EN,Enables bit for enabling the fault monitoring at FCCU NCF 1 for the fault: CM7_3 AHBP interface IAHB Gasket monitor alarm" "0: No alarm reported from CM7_3 AHBP interface IAHB..,1: Monitor alarm reported from CM7_3 AHBP interface.." newline bitfld.long 0x10 21. "CM7_3_AHBM_ALARM_EN,Enables bit for enabling the fault monitoring at FCCU NCF 1 for the fault: CM7_3 AHBM interface IAHB Gasket monitor alarm" "0: No alarm reported from CM7_3 AHBP interface IAHB..,1: Monitor alarm reported from CM7_3 AHBP interface.." newline bitfld.long 0x10 19. "AES_ACCEL_GSKT_ALARM_EN,Enables bit for enabling the fault monitoring at FCCU NCF 1 for the fault: AES ACCEL IAHB Gasket monitor alarm" "0: No alarm reported from AES ACCEL IAHB gasket.,1: Monitor alarm reported from AES ACCEL IAHB gasket." newline bitfld.long 0x10 18. "AES_ACCEL_AXBS_ALARM_EN,Enables bit for enabling the fault monitoring at FCCU NCF 1 for the fault: AES_ACCEL AXBS_Lite safety alarm" "0: No safety alarm indicated by AES_ACCEL AXBS_Lite.,1: Safety alarm indicated by AES_ACCEL AXBS_Lite." newline bitfld.long 0x10 17. "ACE_FEED_RDATA_EDC_ERR_EN,Enables bit for enabling the fault monitoring at FCCU NCF 1 for the fault: Integrity error on ACE ACCEL FEED DMA master port read data for safety" "0: No integrity error reported on ACE ACCEL FEED..,1: Integrity error reported on ACE ACCEL FEED DMA.." newline bitfld.long 0x10 16. "ACE_RESULT_RDATA_EDC_ERR_EN,Enables bit for enabling the fault monitoring at FCCU NCF 1 for the fault: Integrity error on ACE ACCEL RESULT DMA master port read data for safety" "0: No integrity error reported on ACE ACCEL RESULT..,1: Integrity error reported on ACE ACCEL RESULT DMA.." newline bitfld.long 0x10 14. "CM7_3_AHBS_ALARM_EN,Enables bit for enabling the fault monitoring at FCCU NCF 1 for the fault: CM7_3 AHBS interface IAHB Gasket monitor alarm" "0: No alarm reported from CM7_3 AHBS interface IAHB..,1: Monitor alarm reported from CM7_3 AHBS interface.." newline bitfld.long 0x10 13. "HSE_AES_ACCEL_AXBS_ALARM_EN,Enables bit for enabling the fault monitoring at FCCU NCF 1 for the fault: HSE_AES_ACCEL AXBS_Lite safety alarm" "0: No safety alarm indicated by HSE_AES_ACCEL..,1: Safety alarm indicated by HSE_AES_ACCEL AXBS_Lite." newline bitfld.long 0x10 12. "CM7_3_AHBM_RDATA_EDC_ERR_EN,Enables bit for enabling the fault monitoring at FCCU NCF 1 for the fault: Integrity error on CM7_3 main read data for safety" "0: No integrity error reported on CM7_3 main read..,1: Integrity error reported on CM7_3 main read data." newline bitfld.long 0x10 11. "CM7_3_AHBP_RDATA_EDC_ERR_EN,Enables bit for enabling the fault monitoring at FCCU NCF 1 for the fault: Integrity error on CM7_3 peripheral read data for safety" "0: No integrity error reported on CM7_3 peripheral..,1: Integrity error reported on CM7_3 peripheral.." newline bitfld.long 0x10 10. "MAC2_RDATA_EDC_ERR_EN,Enables bit for enabling the fault monitoring at FCCU NCF 1 for the fault: Integrity(EDC) error on MAC2 read data for safety" "0: No integrity error reported on MAC2 read data.,1: Integrity error reported on MAC2 read data." newline bitfld.long 0x10 9. "MAC2_GSKT_ALARM_EN,Enables bit for enabling the fault monitoring at FCCU NCF 1 for the fault: MAC2 IAHB gasket alarm." "0: No alarm indicated by MAC2 IAHB gasket.,1: Alarm indicated by MAC2 IAHB gasket." newline bitfld.long 0x10 7. "PERIPH_AXBS_S3_GSKT_ALARM_EN,Enables bit for enabling the fault monitoring at FCCU NCF 1 for the fault: Peripheral AXBS bridge S3 IAHB gasket alarm" "0: No alarm indicated by Peripheral AXBS bridge S3..,1: Alarm indicated by Peripheral AXBS bridge S3.." newline bitfld.long 0x10 6. "CM7_2_RCCU2_ALARM_EN,Enables bit for enabling the fault monitoring at FCCU NCF 0 for the fault: Cortex M7 cores (CM7_2 and CM7_2_checker core) redundant lockstep error" "0: No lockstep alarm reported by redundant RCCU.,1: Lockstep alarm reported by redundant RCCU." newline bitfld.long 0x10 5. "CM7_2_RCCU1_ALARM_EN,Enables bit for enabling the fault monitoring at FCCU NCF 0 for the fault: Cortex M7 cores (CM7_2 and CM7_2_checker core) lockstep error" "0: No lockstep alarm reported by RCCU.,1: Lockstep alarm reported by RCCU." newline bitfld.long 0x10 4. "CM7_3_LOCKUP_EN,Enables bit for enabling the fault monitoring at FCCU NCF 0 for the fault: CM7_3 core lockup." "0: CM7_3 core not in lockup state.,1: CM7_3 core in lockup state." line.long 0x14 "DCMRWD17,Read Write GPR On Destructive Reset 17" bitfld.long 0x14 6. "AES_RESULT_DID_SAFETY_ERR_EN,Enables bit for enabling the fault monitoring at FCCU NCF 2 for the fault: AES RESULT DMA DID error" "0: AES RESULT DMA DID error not enabled.,1: AES RESULT DMA DID error enabled." newline bitfld.long 0x14 5. "AES_FEED_DID_SAFETY_ERR_EN,Enables bit for enabling the fault monitoring at FCCU NCF 2 for the fault: AES FEED DMA DID error." "0: AES FEED DMA DID error not enabled.,1: AES FEED DMA DID error enabled." newline bitfld.long 0x14 4. "AES_KP_CRC_SAFETY_ERR_EN,Enables bit for enabling the fault monitoring at FCCU NCF 2 for the fault: AES Key Property CRC Safety Error" "0: AES key-property CRC safety error not enabled.,1: AES key-property CRC safety error enabled." newline bitfld.long 0x14 3. "AES_RESULT_DMA_TCD_ADDR_ECC_ERR_EN,Enables bit for enabling the fault monitoring at FCCU NCF 2 for the fault: AES ACCEL RESULT DMA_TCD address ECC error" "0: No address error reported in AES ACCEL RESULT..,1: Address error reported in AES ACCEL RESULT.." newline bitfld.long 0x14 2. "AES_RESULT_DMA_TCD_ECC_ERR_EN,Enables bit for enabling the fault monitoring at FCCU NCF 2 for the fault: AES ACCEL RESULT DMA_TCD memory uncorrectable ECC error" "0: No uncorrectable error reported in AES ACCEL..,1: Uncorrectable error reported in AES ACCEL RESULT.." newline bitfld.long 0x14 1. "AES_FEED_DMA_TCD_ADDR_ECC_ERR_EN,Enables bit for enabling the fault monitoring at FCCU NCF 2 for the fault: AES ACCEL FEED DMA_TCD address ECC error" "0: No address error reported in AES ACCEL FEED..,1: Address error reported in AES ACCEL FEED DMA_TCD.." newline bitfld.long 0x14 0. "AES_FEED_DMA_TCD_ECC_ERR_EN,Enables bit for enabling the fault monitoring at FCCU NCF 2 for the fault: AES ACCEL FEED DMA_TCD memory uncorrectable ECC error" "0: No uncorrectable error reported in AES ACCEL..,1: Uncorrectable error reported in AES ACCEL FEED.." group.long 0x548++0x7 line.long 0x0 "DCMRWD19,Read Write GPR On Destructive Reset 19" bitfld.long 0x0 31. "SAI1_DBG_DIS_CM7_3,Specifies whether SAI1 enters Debug mode or remains functional and unimpacted when the Cortex-M7_3 core enters Debug mode" "0: SAI1 enters debug mode when CM7_3 enters debug..,1: SAI1 remains functional and is not impacted when.." newline bitfld.long 0x0 30. "SAI0_DBG_DIS_CM7_3,Specifies whether SAI0 enters Debug mode or remains functional and unimpacted when the Cortex-M7_3 core enters Debug mode" "0: SAI0 enters debug mode when CM7_3 enters debug..,1: SAI0 remains functional and is not impacted when.." newline bitfld.long 0x0 29. "FLEXCAN5_DBG_DIS_CM7_3,FlexCAN5 Debug Disable For Cortex-M7_3" "0: FlexCAN5 enters debug mode when CM7_3 enters..,1: FlexCAN5 remains functional and is not impacted.." newline bitfld.long 0x0 28. "FLEXCAN4_DBG_DIS_CM7_3,FlexCAN4 Debug Disable For Cortex-M7_3" "0: FlexCAN4 enters debug mode when CM7_3 enters..,1: FlexCAN4 remains functional and is not impacted.." newline bitfld.long 0x0 27. "FLEXCAN3_DBG_DIS_CM7_3,FlexCAN3 Debug Disable For Cortex-M7_3" "0: FlexCAN3 enters debug mode when CM7_3 enters..,1: FlexCAN3 remains functional and is not impacted.." newline bitfld.long 0x0 26. "FLEXCAN2_DBG_DIS_CM7_3,FlexCAN2 Debug Disable For Cortex-M7_3" "0: FlexCAN2 enters debug mode when CM7_3 enters..,1: FlexCAN2 remains functional and is not impacted.." newline bitfld.long 0x0 25. "FLEXCAN1_DBG_DIS_CM7_3,FlexCAN1 Debug Disable For Cortex-M7_3" "0: FlexCAN1 enters debug mode when CM7_3 enters..,1: FlexCAN1 remains functional and is not impacted.." newline bitfld.long 0x0 24. "FLEXCAN0_DBG_DIS_CM7_3,FlexCAN0 Debug Disable For Cortex-M7_3" "0: FlexCAN0 enters debug mode when CM7_3 enters..,1: FlexCAN0 remains functional and is not impacted.." newline bitfld.long 0x0 23. "FLEXIO_DBG_DIS_CM7_3,FlexIO Debug Disable For Cortex-M7_3" "0: FlexIO enters debug mode when CM7_3 enters debug..,1: FlexIO remains functional and is not impacted.." newline bitfld.long 0x0 22. "LPI2C1_DBG_DIS_CM7_3,LPI2C1 Debug Disable For Cortex-M7_3" "0: LPI2C1 enters debug mode when CM7_3 enters debug..,1: LPI2C1 remains functional and is not impacted.." newline bitfld.long 0x0 21. "LPI2C0_DBG_DIS_CM7_3,LPI2C0 Debug Disable For Cortex-M7_3" "0: LPI2C0 enters debug mode when CM7_3 enters debug..,1: LPI2C0 remains functional and is not impacted.." newline bitfld.long 0x0 20. "LPSPI5_DBG_DIS_CM7_3,LPSPI5 Debug Disable For Cortex-M7_3" "0: LPSPI5 enters debug mode when CM7_3 enters debug..,1: LPSPI5 remains functional and is not impacted.." newline bitfld.long 0x0 19. "LPSPI4_DBG_DIS_CM7_3,LPSPI4 Debug Disable For Cortex-M7_3" "0: LPSPI4 enters debug mode when CM7_3 enters debug..,1: LPSPI4 remains functional and is not impacted.." newline bitfld.long 0x0 18. "LPSPI3_DBG_DIS_CM7_3,LPSPI3 Debug Disable For Cortex-M7_3" "0: LPSPI3 enters debug mode when CM7_3 enters debug..,1: LPSPI3 remains functional and is not impacted.." newline bitfld.long 0x0 17. "LPSPI2_DBG_DIS_CM7_3,LPSPI2 Debug Disable For Cortex-M7_3" "0: LPSPI2 enters debug mode when CM7_3 enters debug..,1: LPSPI2 remains functional and is not impacted.." newline bitfld.long 0x0 16. "LPSPI1_DBG_DIS_CM7_3,LPSPI1 Debug Disable For Cortex-M7_3" "0: LPSPI1 enters debug mode when CM7_3 enters debug..,1: LPSPI1 remains functional and is not impacted.." newline bitfld.long 0x0 15. "LPSPI0_DBG_DIS_CM7_3,LPSPI0 Debug Disable For Cortex-M7_3" "0: LPSPI0 enters debug mode when CM7_3 enters debug..,1: LPSPI0 remains functional and is not impacted.." newline bitfld.long 0x0 14. "PIT2_DBG_DIS_CM7_3,PIT2 Debug Disable For Cortex-M7_3" "0: PIT2 enters debug mode when CM7_3 enters debug..,1: PIT2 remains functional and is not impacted when.." newline bitfld.long 0x0 13. "PIT1_DBG_DIS_CM7_3,PIT1 Debug Disable For Cortex-M7_3" "0: PIT1 enters debug mode when CM7_3 enters debug..,1: PIT1 remains functional and is not impacted when.." newline bitfld.long 0x0 12. "PIT0_DBG_DIS_CM7_3,PIT0 Debug Disable For Cortex-M7_3" "0: PIT0 enters debug mode when CM7_3 enters debug..,1: PIT0 remains functional and is not impacted when.." newline bitfld.long 0x0 11. "STM1_DBG_DIS_CM7_3,STM1 Debug Disable For Cortex-M7_3" "0: STM1 enters debug mode when CM7_3 enters debug..,1: STM1 remains functional and is not impacted when.." newline bitfld.long 0x0 10. "STM0_DBG_DIS_CM7_3,STM0 Debug Disable For Cortex-M7_3" "0: STM0 enters debug mode when CM7_3 enters debug..,1: STM0 remains functional and is not impacted when.." newline bitfld.long 0x0 9. "SWT1_DBG_DIS_CM7_3,SWT1 Debug Disable For Cortex-M7_3" "0: SWT1 enters debug mode when CM7_3 enters debug..,1: SWT1 remains functional and is not impacted when.." newline bitfld.long 0x0 8. "SWT0_DBG_DIS_CM7_3,SWT0 Debug Disable For Cortex-M7_3" "0: SWT0 enters debug mode when CM7_3 enters debug..,1: SWT0 remains functional and is not impacted when.." newline bitfld.long 0x0 7. "RTC_DBG_DIS_CM7_3,RTC Debug Disable For Cortex-M7_3" "0: RTC enters debug mode when CM7_3 enters debug..,1: RTC remains functional and is not impacted when.." newline bitfld.long 0x0 6. "eMIOS2_DBG_DIS_CM7_3,Specifies whether eMIOS2 enters Debug mode or remains functional and unimpacted when the Cortex-M7_3 core enters Debug mode" "0: eMIOS2 enters debug mode when CM7_3 enters debug..,1: eMIOS2 remains functional and is not impacted.." newline bitfld.long 0x0 5. "eMIOS1_DBG_DIS_CM7_3,Specifies whether eMIOS1 enters Debug mode or remains functional and unimpacted when the Cortex-M7_3 core enters Debug mode" "0: eMIOS1 enters debug mode when CM7_3 enters debug..,1: eMIOS1 remains functional and is not impacted.." newline bitfld.long 0x0 4. "eMIOS0_DBG_DIS_CM7_3,eMIOS0 Debug Disable For Cortex-M7_3" "0: eMIOS0 enters debug mode when CM7_3 enters debug..,1: eMIOS0 remains functional and is not impacted.." newline bitfld.long 0x0 3. "LCU1_DBG_DIS_CM7_3,LCU1 Debug Disable For Cortex-M7_3" "0: LCU1 enters debug mode when CM7_3 enters debug..,1: LCU1 remains functional and is not impacted when.." newline bitfld.long 0x0 2. "LCU0_DBG_DIS_CM7_3,LCU0 Debug Disable For Cortex-M7_3" "0: LCU0 enters debug mode when CM7_3 enters debug..,1: LCU0 remains functional and is not impacted when.." newline bitfld.long 0x0 1. "FCCU_DBG_DIS_CM7_3,FCCU Debug Disable For Cortex-M7_3" "0: FCCU enters debug mode when CM7_3 enters debug..,1: FCCU remains functional and is not impacted when.." newline bitfld.long 0x0 0. "EDMA_DBG_DIS_CM7_3,EDMA Debug Disable For Cortex-M7_3" "0: EDMA enters debug mode when CM7_3 enters debug..,1: EDMA remains functional and is not impacted when.." line.long 0x4 "DCMRWD20,Read Write GPR On Destructive Reset 20" bitfld.long 0x4 25. "FLEXCAN9_DBG_DIS_CM7_3,FLEXCAN9 Debug Disable Cortex-M7_3" "0: FLEXCAN9 enters debug mode when CM7_3 enters..,1: FLEXCAN9 remains functional and is not impacted.." newline bitfld.long 0x4 23. "PIT3_DBG_DIS_CM7_3,PIT3 Debug Disable Cortex-M7_3" "0: PIT3 enters debug mode when CM7_3 enters debug..,1: PIT3 remains functional and is not impacted when.." newline bitfld.long 0x4 22. "STM3_DBG_DIS_CM7_3,STM3 Debug Disable Cortex-M7_3" "0: STM3 enters debug mode when CM7_3 enters debug..,1: STM3 remains functional and is not impacted when.." newline bitfld.long 0x4 21. "SWT3_DBG_DIS_CM7_3,SWT3 Debug Disable Cortex-M7_3" "0: SWT3 enters debug mode when CM7_3 enters debug..,1: SWT3 remains functional and is not impacted when.." newline bitfld.long 0x4 4. "SWT2_DBG_DIS_CM7_3,SWT2 Debug Disable For Cortex-M7_3" "0: SWT2 enters debug mode when CM7_3 enters debug..,1: SWT2 remains functional and is not impacted when.." newline bitfld.long 0x4 3. "STM2_DBG_DIS_CM7_3,STM2 Debug Disable For Cortex-M7_3" "0: STM2 enters debug mode when CM7_3 enters debug..,1: STM2 remains functional and is not impacted when.." newline bitfld.long 0x4 2. "FLEXCAN7_DBG_DIS_CM7_3,Specifies whether FLEXCAN7 enters Debug mode or remains functional and unimpacted when the Cortex-M7_3 core enters Debug mode" "0: FLEXCAN7 enters debug mode when CM7_3 enters..,1: FLEXCAN7 remains functional and is not impacted.." newline bitfld.long 0x4 1. "FLEXCAN6_DBG_DIS_CM7_3,FlexCAN6 Debug Disable For Cortex-M7_3" "0: FlexCAN6 enters debug mode when CM7_3 enters..,1: FlexCAN6 remains functional and is not impacted.." group.long 0x600++0x13 line.long 0x0 "DCMRWF1,Read Write GPR On Functional Reset 1" bitfld.long 0x0 31. "MAC_TX_RMII_CLK_LPBCK_EN,MAC_TX_RMII_CLK Loopback Enable" "0: Disables,1: Enables" newline bitfld.long 0x0 27. "VDD_1_5_VLT_DVDR_EN,VDD1P5 Voltage Divider Enable" "0: Disables,1: Enables" newline bitfld.long 0x0 26. "VDD_HV_B_VLT_DVDR_EN,VDD_HV_B Voltage Divider Enable" "0: Disables,1: Enables" newline bitfld.long 0x0 25. "VDD_HV_A_VLT_DVDR_EN,VDD_HV_A Voltage Divider Enable" "0: Disables,1: Enables" newline bitfld.long 0x0 24. "VSS_LV_ANMUX_EN,VSS_LV Monitoring Enable" "0: Disables,1: Enables" newline bitfld.long 0x0 21.--23. "SUPPLY_MON_SEL,Supply Monitoring Select" "0: VDD_HV_A_DIV,1: VDD_HV_B_DIV,2: VDD_1.5_DIV,3: VDD_2.5_OSC,4: VDD1.1_PD1_HOT_POINT,5: VDD1.1_PD1_COLD_POINT,6: VDD1.1_PLL,7: VDD1.1_PD0" newline bitfld.long 0x0 20. "SUPPLY_MON_EN,Supply Monitoring Enable" "0: Disables,1: Enables" newline bitfld.long 0x0 19. "MAC_SB_END_CTRL,MAC Sideband Data Endianness Control" "0: The MAC sideband data is transferred in..,1: The MAC sideband data is transferred in.." newline bitfld.long 0x0 18. "PMIC_PGOOD_HNDSHK_BYP,Enables or bypass the PMIC_PGOOD handshake with the external power management device (PMIC) while standby exit." "0: Enables the PMIC_PGOOD handshake with the..,1: Bypasses the PMIC_PGOOD handshake with the.." newline bitfld.long 0x0 16. "STANDBY_IO_CONFIG,Standby I/O Configuration" "0: Must be written as 0 before IO configurations..,1: Must be written as 1 after IO configurations are.." newline bitfld.long 0x0 15. "VDD_HV_B_IO_CTRL_LATCH,VDD_HV_B I/O Control Latch" "0: VDD_HV_B domain pins function as normal.,1: The IO controls of VDD_HV_B domain pins are.." newline bitfld.long 0x0 6.--7. "MAC_CONF_SEL,Selects between MII and RMII mode of ethernet." "0: MII mode,1: RGMII mode,2: RMII mode,?" newline bitfld.long 0x0 5. "FCCU_SW_NCF3,FCCU Software NCF 3" "0: Not generated,1: Generated" newline bitfld.long 0x0 4. "FCCU_SW_NCF2,FCCU Software NCF 2" "0: Not generated,1: Generated" newline bitfld.long 0x0 3. "FCCU_SW_NCF1,FCCU Software NCF 1" "0: Not generated,1: Generated" newline bitfld.long 0x0 2. "FCCU_SW_NCF0,FCCU Software NCF 0" "0: Not generated,1: Generated" newline bitfld.long 0x0 1. "CAN_TIMESTAMP_EN,FlexCAN Timestamp Enable" "0: Disables,1: Enables" newline bitfld.long 0x0 0. "CAN_TIMESTAMP_SEL,FlexCAN Timestamp Select" "0: EMAC,1: STM0" line.long 0x4 "DCMRWF2,Read Write GPR On Functional Reset 2" bitfld.long 0x4 31. "WKPU8_SRC_SELECT,WKPU[8] Source Select" "0: GPIO[34],1: GPIO[231]" newline bitfld.long 0x4 30. "WKPU45_SRC_SELECT,WKPU[45] Source Select" "0: GPIO[89],1: GPIO[217]" newline bitfld.long 0x4 29. "WKPU27_SRC_SELECT,WKPU[27] Source Select" "0: GPIO[130],1: GPIO[233]" newline bitfld.long 0x4 28. "WKPU18_SRC_SELECT,WKPU[18] Source Select" "0: GPIO[75],1: GPIO[235]" newline bitfld.long 0x4 27. "WKPU15_SRC_SELECT,Controls the source of WKPU[15]." "0: GPIO[6] is used as source of WKPU[15].,1: GPIO[227] is used as source of WKPU[15]." newline bitfld.long 0x4 26. "WKPU14_SRC_SELECT,Controls the source of WKPU[14]." "0: GPIO[49] is used as source of WKPU[14].,1: GPIO[229] is used as source of WKPU[14]." newline bitfld.long 0x4 25. "WKPU0_SRC_SELECT,Controls the source of WKPU[0]." "0: GPIO[2] is used as source of WKPU[0].,1: GPIO[225] is used as source of WKPU[0]." newline bitfld.long 0x4 24. "PLL1_LOL_RST_EN,PLL1 LOL Reset Enable" "0: PLL1 LOL event results in an interrupt,1: PLL1 LOL event results in a reset" newline bitfld.long 0x4 21. "PGOOD_POLARITY,PGOOD Polarity" "0: Active-high signal,1: Active-low signal" newline bitfld.long 0x4 17. "VIRT_WRAP_IPSYNC_BYPASS,VIRT_WRAPPER IPSYNC Bypass" "0: Enables,1: Bypasses" newline bitfld.long 0x4 16. "HSE_GSKT_BYPASS,HSE_B Gasket Bypass" "0: Not bypassed,1: Bypassed" newline bitfld.long 0x4 13.--15. "SUPPLY2_MON_SEL,Supply 2 Monitoring Select" "0: VDD2P5_PLL2,1: VDD1P1_PLL2,?,?,?,?,?,?" newline bitfld.long 0x4 12. "SUPPLY2_MON_EN,Supply 2 Monitoring Enable" "0: Disables,1: Enables" newline bitfld.long 0x4 11. "SAI_MCLK2_SEL,SAI MCLK2 Select" "0: FXOSC is the SAI_MCLK2 clock source.,1: PLL_AUX_PHI1 is the SAI_MCLK2 clock source." newline bitfld.long 0x4 8. "PMOS_CTRL_GPIO_DATA,PMOS Control GPIO Data" "0: Data is 0,1: Data is 1" newline bitfld.long 0x4 6. "SIRC_TRIM_BYP_STDBY_EXT,SIRC Trim Bypass Standby Exit" "0: Not bypassed,?" newline bitfld.long 0x4 5. "PMC_TRIM_RGM_DCF_BYP_STDBY_EXT,PMC Trim MC_RGM DCF Bypass Standby Exit" "0: Not bypassed,1: Bypassed" newline bitfld.long 0x4 4. "FIRC_TRIM_BYP_STDBY_EXT,FIRC Trim Bypass Standby Exit" "0: Not bypassed,1: Bypassed" newline bitfld.long 0x4 3. "DCM_SCAN_BYP_STDBY_EXT,DCM Scan Bypass Standby Exit" "0: Not bypassed,1: Bypassed" newline bitfld.long 0x4 2. "MAC2_LOOBPACK_CLK_SEL,Selects MAC2_LOOPBACK_CLK source." "?,1: MAC_CLK_TX is selected." newline bitfld.long 0x4 1. "MAC2_TX_RMII_CLK_LPBCK_EN,Enables the MAC2_TX_RMII_CLK loopback." "0: Disabled,1: Enabled" line.long 0x8 "DCMRWF3,Read Write GPR On Functional Reset 3" bitfld.long 0x8 15. "MAC_TX_CLK_MUX_BYPASS,Bypasses the MAC_TX_CLK mux MC_CGM_MUX8 and the TX_CLK arrives without MC_CGM_MUX8 to the MAC in case of external clock source." "0: The MAC_TX_CLK is derived from MC_CGM_MUX8.,1: The MAC_TX_CLK arrives directly from the.." newline bitfld.long 0x8 13.--14. "MAC_RX_CLK_MUX_BYPASS,Bypasses the MAC_RX_CLK mux MC_CGM_MUX7 and the RX_CLK arrives without MC_CGM_MUX7 to the MAC in case of external clock source." "0: The MAC_RX_CLK is derived from MC_CGM_MUX7.,1: The MAC_RX_CLK arrives directly from the RX_CLK..,2: The MAC_RX_CLK arrives directly from the..,?" line.long 0xC "DCMRWF4,Read Write GPR On Functional Reset 4" bitfld.long 0xC 31. "MAC2_TX_CLK_MUX_BYPASS,MAC2 TX Clock Mux Bypass" "0: The MAC2_TX_CLK is derived from MC_CGM_MUX16.,1: The MAC2_TX_CLK arrives directly from the.." newline bitfld.long 0xC 29.--30. "MAC2_RX_CLK_MUX_BYPASS,MAC2 RX Clock Mux Bypass" "0: The MAC2_RX_CLK is derived from MC_CGM_MUX15.,1: The MAC2_RX_CLK arrives directly from the MAC..,2: The MAC2_RX_CLK arrives directly from the MAC2..,?" newline bitfld.long 0xC 27. "MAC2_RMII_CLK_MUX_BYPASS,MAC2 RMII Clock Mux Bypass" "0: The MAC2_RMII_CLK is derived from MC_CGM_MUX16.,1: The MAC2_RMII_CLK arrives directly from the.." newline bitfld.long 0xC 26. "MAC_RMII_CLK_MUX_BYPASS,MAC RMII Clock Mux Bypass" "0: The MAC_RMII_CLK is derived from MC_CGM_MUX8.,1: The MAC_RMII_CLK arrives directly from the.." newline bitfld.long 0xC 24.--25. "MAC2_CONF_SEL,MAC Configuration Selection" "0: MII mode,1: RGMII mode,2: RMII mode,?" newline bitfld.long 0xC 23. "MAC_SB_END_CTRL,MAC Sideband Data Endianness Control" "0: Data is transferred in little-endian mode.,1: Data is transferred in big-endian mode." newline bitfld.long 0xC 20. "CM7_3_CPUWAIT,Cortex-M7_3 CPU Wait" "0: Disables CPUWAIT,1: Enables CPUWAIT" newline bitfld.long 0xC 19. "CM7_2_CPUWAIT,Cortex-M7_2 CPU Wait" "0: Disables CPUWAIT,1: Enables CPUWAIT" newline bitfld.long 0xC 18. "CM7_1_CPUWAIT,Cortex-M7_1 CPU Wait" "0: Disables CPUWAIT,1: Enables CPUWAIT" newline bitfld.long 0xC 17. "CM7_0_CPUWAIT,Cortex-M7_0 CPU Wait" "0: Disables CPUWAIT,1: Enables CPUWAIT" newline bitfld.long 0xC 16. "GLITCH_FIL_TRG_IN3_BYP,Glitch Filter TRGMUX Input 3 Bypass" "0: Enables,1: Bypasses" newline bitfld.long 0xC 15. "GLITCH_FIL_TRG_IN2_BYP,Glitch Filter TRGMUX Input 2 Bypass" "0: Enables,1: Bypasses" newline bitfld.long 0xC 14. "GLITCH_FIL_TRG_IN1_BYP,Glitch Filter TRGMUX Input 1 Bypass" "0: Enables,1: Bypasses" newline bitfld.long 0xC 13. "GLITCH_FIL_TRG_IN0_BYP,Glitch Filter TRGMUX Input 0 Bypass" "0: Enables,1: Bypasses" newline bitfld.long 0xC 10. "MUX_MODE_EN_ADC2_S9,Mux Mode Enable ADC2 Standard Channel 9" "0: GPIO_132,1: GPIO_46" newline bitfld.long 0xC 9. "MUX_MODE_EN_ADC2_S8,Mux Mode Enable ADC2 Standard Channel 8" "0: GPIO_133,1: GPIO_45" newline bitfld.long 0xC 6. "MUX_MODE_EN_ADC1_S23,Mux Mode Enable ADC_1 Standard Channel 23" "0: GPIO_125,1: GPIO_146" newline bitfld.long 0xC 5. "MUX_MODE_EN_ADC1_S22,Mux Mode Enable ADC_1 Standard Channel 22" "0: GPIO_124,1: GPIO_145" newline bitfld.long 0xC 4. "MUX_MODE_EN_ADC1_S15,Mux Mode Enable ADC_1 Standard Channel 15" "0: GPIO_4,1: GPIO_33" newline bitfld.long 0xC 3. "MUX_MODE_EN_ADC1_S14,Mux Mode Enable ADC_1 Standard Channel 14" "0: GPIO_69,1: GPIO_32" newline bitfld.long 0xC 2. "MUX_MODE_EN_ADC0_S9,Mux Mode Enable ADC_0 Standard Channel 9" "0: GPIO_1,1: GPIO_46" newline bitfld.long 0xC 1. "MUX_MODE_EN_ADC0_S8,Mux Mode Enable ADC_0 Standard Channel 8" "0: GPIO_0,1: GPIO_45" line.long 0x10 "DCMRWF5,Read Write GPR On Functional Reset 5" hexmask.long 0x10 1.--31. 1. "BOOT_ADDRESS,Boot Address" newline bitfld.long 0x10 0. "BOOT_MODE,Boot Mode" "0: Normal,1: Fast Standby" group.long 0x700++0xF line.long 0x0 "DCMROPP1,Read-Only GPR On PMCPOR Reset 1" eventfld.long 0x0 31. "POR_WDG_STAT31,POR_WDG Status 31" "0: Not detected,1: Detected" newline eventfld.long 0x0 30. "POR_WDG_STAT30,POR_WDG Status 30" "0: Not acknowledged,1: Acknowledged" newline eventfld.long 0x0 29. "POR_WDG_STAT29,POR_WDG Status 29" "0: Active,1: Inactive" newline eventfld.long 0x0 20. "POR_WDG_STAT20,POR_WDG Status 20" "0: Inactive,1: Active" newline eventfld.long 0x0 17. "POR_WDG_STAT17,POR_WDG Status 17" "0: Inactive,1: Active" newline eventfld.long 0x0 14. "POR_WDG_STAT14,POR_WDG Status 14" "0: Inactive,1: Active" newline eventfld.long 0x0 11. "POR_WDG_STAT11,POR_WDG Status 11" "0: Inactive,1: Active" newline eventfld.long 0x0 10. "POR_WDG_STAT10,POR_WDG Status 10" "0: Inactive,1: Active" newline eventfld.long 0x0 6. "POR_WDG_STAT6,POR_WDG Status 6" "0: Inactive,1: Active" newline eventfld.long 0x0 5. "POR_WDG_STAT5,POR_WDG Status 5" "0: Inactive,1: Active" newline eventfld.long 0x0 4. "POR_WDG_STAT4,POR_WDG Status 4" "0: Inactive,1: Active" newline eventfld.long 0x0 3. "POR_WDG_STAT3,POR_WDG Status 3" "0: Inactive,1: Active" newline eventfld.long 0x0 2. "POR_WDG_STAT2,POR_WDG Status 2" "0: Inactive,1: Active" newline eventfld.long 0x0 1. "POR_WDG_STAT1,POR_WDG Status 1" "0: Inactive,1: Active" newline eventfld.long 0x0 0. "POR_WDG_STAT0,POR_WDG Status 0" "0: Inactive,1: Active" line.long 0x4 "DCMROPP2,Read-Only GPR On PMCPOR Reset 2" eventfld.long 0x4 30. "POR_WDG_STAT62,POR_WDG Status 62" "0: 0,1: 1" newline eventfld.long 0x4 29. "POR_WDG_STAT61,POR_WDG Status 61" "0: 0,1: 1" newline eventfld.long 0x4 20. "POR_WDG_STAT52,POR_WDG Status 52" "0: 0,1: 1" newline eventfld.long 0x4 16. "POR_WDG_STAT48,POR_WDG Status 48" "0: 0,1: 1" newline eventfld.long 0x4 12. "POR_WDG_STAT44,POR_WDG Status 44" "0: 0,1: 1" newline eventfld.long 0x4 9. "POR_WDG_STAT41,POR_WDG Status 41" "0: 0,1: 1" newline eventfld.long 0x4 8. "POR_WDG_STAT40,POR_WDG Status 40" "0: 0,1: 1" newline eventfld.long 0x4 7. "POR_WDG_STAT39,POR_WDG Status 39" "0: 0,1: 1" newline eventfld.long 0x4 6. "POR_WDG_STAT38,POR_WDG Status 38" "0: 0,1: 1" newline eventfld.long 0x4 4. "POR_WDG_STAT36,POR_WDG Status 36" "0: 0,1: 1" newline eventfld.long 0x4 3. "POR_WDG_STAT35,POR_WDG Status 35" "0: 0,1: 1" newline eventfld.long 0x4 0. "POR_WDG_STAT32,POR_WDG Status 32" "0: 0,1: 1" line.long 0x8 "DCMROPP3,Read-Only GPR On PMCPOR Reset 3" eventfld.long 0x8 30. "POR_WDG_STAT94,POR_WDG Status 94" "0: 0,1: 1" newline eventfld.long 0x8 29. "POR_WDG_STAT93,POR_WDG Status 93" "0: 0,1: 1" newline eventfld.long 0x8 18. "POR_WDG_STAT82,POR_WDG Status 82" "0: 0,1: 1" newline eventfld.long 0x8 17. "POR_WDG_STAT81,POR_WDG Status 81" "0: 0,1: 1" newline eventfld.long 0x8 16. "POR_WDG_STAT80,POR_WDG Status 80" "0: 0,1: 1" newline eventfld.long 0x8 15. "POR_WDG_STAT79,POR_WDG Status 79" "0: 0,1: 1" newline eventfld.long 0x8 14. "POR_WDG_STAT78,POR_WDG Status 78" "0: 0,1: 1" newline eventfld.long 0x8 12. "POR_WDG_STAT76,POR_WDG Status 76" "0: 0,1: 1" newline eventfld.long 0x8 10. "POR_WDG_STAT74,POR_WDG Status 74" "0: 0,1: 1" newline eventfld.long 0x8 9. "POR_WDG_STAT73,POR_WDG Status 73" "0: 0,1: 1" newline eventfld.long 0x8 8. "POR_WDG_STAT72,POR_WDG Status 72" "0: 0,1: 1" newline eventfld.long 0x8 6. "POR_WDG_STAT70,POR_WDG Status 70" "0: 0,1: 1" newline eventfld.long 0x8 4. "POR_WDG_STAT68,POR_WDG Status 68" "0: 0,1: 1" newline eventfld.long 0x8 3. "POR_WDG_STAT67,POR_WDG Status 67" "0: 0,1: 1" newline eventfld.long 0x8 0. "POR_WDG_STAT64,POR_WDG Status 64" "0: 0,1: 1" line.long 0xC "DCMROPP4,Read-Only GPR On PMCPOR Reset 4" eventfld.long 0xC 0. "POR_WDG_STAT96,POR_WDG Status 96" "0: Inactive,1: Active" tree.end tree "DMA (Direct Memory Access)" base ad:0x0 tree "DMA_MP" base ad:0x4020C000 group.long 0x0++0x3 line.long 0x0 "CSR,Management Page Control" rbitfld.long 0x0 31. "ACTIVE,DMA Active Status" "0: eDMA is idle,1: eDMA is executing a channel" hexmask.long.byte 0x0 24.--28. 1. "ACTIVE_ID,Active Channel ID" newline bitfld.long 0x0 9. "CX,Cancel Transfer" "0: Normal operation,1: Cancel the remaining data transfer" bitfld.long 0x0 8. "ECX,Cancel Transfer With Error" "0: Normal operation,1: Cancel the remaining data transfer" newline bitfld.long 0x0 7. "GMRC,Global Master ID Replication Control" "0: Master ID replication disabled for all channels,1: Master ID replication available and controlled.." bitfld.long 0x0 6. "GCLC,Global Channel Linking Control" "0: Channel linking disabled for all channels,1: Channel linking available and controlled by each.." newline bitfld.long 0x0 5. "HALT,Halt DMA Operations" "0: Normal operation,1: Stall the start of any new channels" bitfld.long 0x0 4. "HAE,Halt After Error" "0: Normal operation,1: Any error causes the HALT field to be set to 1" newline bitfld.long 0x0 2. "ERCA,Enable Round Robin Channel Arbitration" "0: Round-robin channel arbitration disabled,1: Round-robin channel arbitration enabled" bitfld.long 0x0 1. "EDBG,Enable Debug" "0: Debug mode disabled,1: Debug mode is enabled." rgroup.long 0x4++0xB line.long 0x0 "ES,Management Page Error Status" bitfld.long 0x0 31. "VLD,Valid" "0: No ERR fields are set to 1,1: At least one ERR field is set to 1 indicating a.." hexmask.long.byte 0x0 24.--28. 1. "ERRCHN,Error Channel Number or Canceled Channel Number" newline bitfld.long 0x0 9. "UCE,Uncorrectable TCD Error During Channel Execution" "0: No uncorrectable ECC error,1: Last recorded error was an uncorrectable TCD RAM.." bitfld.long 0x0 8. "ECX,Transfer Canceled" "0: No canceled transfers,1: Last recorded entry was a canceled transfer by.." newline bitfld.long 0x0 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." bitfld.long 0x0 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." newline bitfld.long 0x0 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." bitfld.long 0x0 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." newline bitfld.long 0x0 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: The last recorded error was NBYTES equal to zero.." bitfld.long 0x0 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." newline bitfld.long 0x0 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was a bus error on a source.." bitfld.long 0x0 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was a bus error on a.." line.long 0x4 "INT,Management Page Interrupt Request Status" hexmask.long 0x4 0.--31. 1. "INT,Interrupt Request Status" line.long 0x8 "HRS,Management Page Hardware Request Status" hexmask.long 0x8 0.--31. 1. "HRS,Hardware Request Status" repeat 32. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x100)++0x3 line.long 0x0 "CH_GRPRI[$1],Channel Arbitration Group" hexmask.long.byte 0x0 0.--4. 1. "GRPRI,Arbitration Group For Channel n" repeat.end tree.end tree "DMA_TCD" base ad:0x40210000 group.long 0x0++0x13 line.long 0x0 "CH0_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH0_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH0_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH0_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--3. 1. "MID,Master ID" line.long 0x10 "CH0_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x20++0x3 line.long 0x0 "TCD0_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x24++0x3 line.word 0x0 "TCD0_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD0_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x28++0x3 line.long 0x0 "TCD0_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x28++0xB line.long 0x0 "TCD0_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD0_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD0_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x34++0x3 line.word 0x0 "TCD0_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD0_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x36++0x1 line.word 0x0 "TCD0_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x38++0x3 line.long 0x0 "TCD0_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x3C++0x3 line.word 0x0 "TCD0_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD0_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x3E++0x1 line.word 0x0 "TCD0_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x4000++0x13 line.long 0x0 "CH1_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH1_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH1_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH1_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--3. 1. "MID,Master ID" line.long 0x10 "CH1_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x4020++0x3 line.long 0x0 "TCD1_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x4024++0x3 line.word 0x0 "TCD1_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD1_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x4028++0x3 line.long 0x0 "TCD1_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x4028++0xB line.long 0x0 "TCD1_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD1_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD1_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x4034++0x3 line.word 0x0 "TCD1_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD1_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x4036++0x1 line.word 0x0 "TCD1_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x4038++0x3 line.long 0x0 "TCD1_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x403C++0x3 line.word 0x0 "TCD1_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD1_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x403E++0x1 line.word 0x0 "TCD1_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x8000++0x13 line.long 0x0 "CH2_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH2_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH2_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH2_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--3. 1. "MID,Master ID" line.long 0x10 "CH2_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x8020++0x3 line.long 0x0 "TCD2_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x8024++0x3 line.word 0x0 "TCD2_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD2_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x8028++0x3 line.long 0x0 "TCD2_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x8028++0xB line.long 0x0 "TCD2_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD2_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD2_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x8034++0x3 line.word 0x0 "TCD2_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD2_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x8036++0x1 line.word 0x0 "TCD2_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x8038++0x3 line.long 0x0 "TCD2_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x803C++0x3 line.word 0x0 "TCD2_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD2_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x803E++0x1 line.word 0x0 "TCD2_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0xC000++0x13 line.long 0x0 "CH3_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH3_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH3_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH3_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--3. 1. "MID,Master ID" line.long 0x10 "CH3_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0xC020++0x3 line.long 0x0 "TCD3_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0xC024++0x3 line.word 0x0 "TCD3_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD3_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0xC028++0x3 line.long 0x0 "TCD3_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0xC028++0xB line.long 0x0 "TCD3_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD3_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD3_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0xC034++0x3 line.word 0x0 "TCD3_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD3_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0xC036++0x1 line.word 0x0 "TCD3_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0xC038++0x3 line.long 0x0 "TCD3_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0xC03C++0x3 line.word 0x0 "TCD3_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD3_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0xC03E++0x1 line.word 0x0 "TCD3_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x10000++0x13 line.long 0x0 "CH4_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH4_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH4_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH4_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--3. 1. "MID,Master ID" line.long 0x10 "CH4_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x10020++0x3 line.long 0x0 "TCD4_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x10024++0x3 line.word 0x0 "TCD4_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD4_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x10028++0x3 line.long 0x0 "TCD4_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x10028++0xB line.long 0x0 "TCD4_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD4_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD4_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x10034++0x3 line.word 0x0 "TCD4_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD4_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x10036++0x1 line.word 0x0 "TCD4_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x10038++0x3 line.long 0x0 "TCD4_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1003C++0x3 line.word 0x0 "TCD4_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD4_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1003E++0x1 line.word 0x0 "TCD4_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x14000++0x13 line.long 0x0 "CH5_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH5_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH5_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH5_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--3. 1. "MID,Master ID" line.long 0x10 "CH5_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x14020++0x3 line.long 0x0 "TCD5_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x14024++0x3 line.word 0x0 "TCD5_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD5_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x14028++0x3 line.long 0x0 "TCD5_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x14028++0xB line.long 0x0 "TCD5_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD5_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD5_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x14034++0x3 line.word 0x0 "TCD5_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD5_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x14036++0x1 line.word 0x0 "TCD5_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x14038++0x3 line.long 0x0 "TCD5_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1403C++0x3 line.word 0x0 "TCD5_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD5_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1403E++0x1 line.word 0x0 "TCD5_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x18000++0x13 line.long 0x0 "CH6_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH6_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH6_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH6_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--3. 1. "MID,Master ID" line.long 0x10 "CH6_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x18020++0x3 line.long 0x0 "TCD6_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x18024++0x3 line.word 0x0 "TCD6_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD6_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x18028++0x3 line.long 0x0 "TCD6_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x18028++0xB line.long 0x0 "TCD6_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD6_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD6_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x18034++0x3 line.word 0x0 "TCD6_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD6_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x18036++0x1 line.word 0x0 "TCD6_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x18038++0x3 line.long 0x0 "TCD6_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1803C++0x3 line.word 0x0 "TCD6_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD6_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1803E++0x1 line.word 0x0 "TCD6_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x1C000++0x13 line.long 0x0 "CH7_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH7_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH7_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH7_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--3. 1. "MID,Master ID" line.long 0x10 "CH7_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x1C020++0x3 line.long 0x0 "TCD7_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x1C024++0x3 line.word 0x0 "TCD7_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD7_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x1C028++0x3 line.long 0x0 "TCD7_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x1C028++0xB line.long 0x0 "TCD7_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD7_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD7_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x1C034++0x3 line.word 0x0 "TCD7_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD7_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x1C036++0x1 line.word 0x0 "TCD7_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x1C038++0x3 line.long 0x0 "TCD7_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1C03C++0x3 line.word 0x0 "TCD7_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD7_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1C03E++0x1 line.word 0x0 "TCD7_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x20000++0x13 line.long 0x0 "CH8_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH8_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH8_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH8_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--3. 1. "MID,Master ID" line.long 0x10 "CH8_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x20020++0x3 line.long 0x0 "TCD8_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x20024++0x3 line.word 0x0 "TCD8_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD8_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x20028++0x3 line.long 0x0 "TCD8_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x20028++0xB line.long 0x0 "TCD8_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD8_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD8_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x20034++0x3 line.word 0x0 "TCD8_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD8_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x20036++0x1 line.word 0x0 "TCD8_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x20038++0x3 line.long 0x0 "TCD8_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x2003C++0x3 line.word 0x0 "TCD8_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD8_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x2003E++0x1 line.word 0x0 "TCD8_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x24000++0x13 line.long 0x0 "CH9_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH9_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH9_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH9_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--3. 1. "MID,Master ID" line.long 0x10 "CH9_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x24020++0x3 line.long 0x0 "TCD9_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x24024++0x3 line.word 0x0 "TCD9_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD9_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x24028++0x3 line.long 0x0 "TCD9_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x24028++0xB line.long 0x0 "TCD9_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD9_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD9_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x24034++0x3 line.word 0x0 "TCD9_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD9_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x24036++0x1 line.word 0x0 "TCD9_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x24038++0x3 line.long 0x0 "TCD9_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x2403C++0x3 line.word 0x0 "TCD9_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD9_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x2403E++0x1 line.word 0x0 "TCD9_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x28000++0x13 line.long 0x0 "CH10_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH10_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH10_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH10_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--3. 1. "MID,Master ID" line.long 0x10 "CH10_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x28020++0x3 line.long 0x0 "TCD10_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x28024++0x3 line.word 0x0 "TCD10_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD10_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x28028++0x3 line.long 0x0 "TCD10_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x28028++0xB line.long 0x0 "TCD10_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD10_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD10_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x28034++0x3 line.word 0x0 "TCD10_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD10_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x28036++0x1 line.word 0x0 "TCD10_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x28038++0x3 line.long 0x0 "TCD10_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x2803C++0x3 line.word 0x0 "TCD10_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD10_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x2803E++0x1 line.word 0x0 "TCD10_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x2C000++0x13 line.long 0x0 "CH11_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH11_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH11_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH11_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--3. 1. "MID,Master ID" line.long 0x10 "CH11_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x2C020++0x3 line.long 0x0 "TCD11_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x2C024++0x3 line.word 0x0 "TCD11_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD11_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x2C028++0x3 line.long 0x0 "TCD11_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x2C028++0xB line.long 0x0 "TCD11_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD11_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD11_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x2C034++0x3 line.word 0x0 "TCD11_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD11_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x2C036++0x1 line.word 0x0 "TCD11_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x2C038++0x3 line.long 0x0 "TCD11_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x2C03C++0x3 line.word 0x0 "TCD11_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD11_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x2C03E++0x1 line.word 0x0 "TCD11_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x200000++0x13 line.long 0x0 "CH12_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH12_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH12_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH12_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--3. 1. "MID,Master ID" line.long 0x10 "CH12_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x200020++0x3 line.long 0x0 "TCD12_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x200024++0x3 line.word 0x0 "TCD12_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD12_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x200028++0x3 line.long 0x0 "TCD12_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x200028++0xB line.long 0x0 "TCD12_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD12_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD12_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x200034++0x3 line.word 0x0 "TCD12_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD12_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x200036++0x1 line.word 0x0 "TCD12_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x200038++0x3 line.long 0x0 "TCD12_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x20003C++0x3 line.word 0x0 "TCD12_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD12_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x20003E++0x1 line.word 0x0 "TCD12_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x204000++0x13 line.long 0x0 "CH13_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH13_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH13_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH13_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--3. 1. "MID,Master ID" line.long 0x10 "CH13_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x204020++0x3 line.long 0x0 "TCD13_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x204024++0x3 line.word 0x0 "TCD13_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD13_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x204028++0x3 line.long 0x0 "TCD13_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x204028++0xB line.long 0x0 "TCD13_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD13_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD13_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x204034++0x3 line.word 0x0 "TCD13_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD13_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x204036++0x1 line.word 0x0 "TCD13_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x204038++0x3 line.long 0x0 "TCD13_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x20403C++0x3 line.word 0x0 "TCD13_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD13_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x20403E++0x1 line.word 0x0 "TCD13_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x208000++0x13 line.long 0x0 "CH14_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH14_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH14_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH14_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--3. 1. "MID,Master ID" line.long 0x10 "CH14_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x208020++0x3 line.long 0x0 "TCD14_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x208024++0x3 line.word 0x0 "TCD14_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD14_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x208028++0x3 line.long 0x0 "TCD14_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x208028++0xB line.long 0x0 "TCD14_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD14_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD14_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x208034++0x3 line.word 0x0 "TCD14_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD14_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x208036++0x1 line.word 0x0 "TCD14_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x208038++0x3 line.long 0x0 "TCD14_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x20803C++0x3 line.word 0x0 "TCD14_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD14_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x20803E++0x1 line.word 0x0 "TCD14_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x20C000++0x13 line.long 0x0 "CH15_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH15_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH15_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH15_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--3. 1. "MID,Master ID" line.long 0x10 "CH15_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x20C020++0x3 line.long 0x0 "TCD15_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x20C024++0x3 line.word 0x0 "TCD15_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD15_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x20C028++0x3 line.long 0x0 "TCD15_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x20C028++0xB line.long 0x0 "TCD15_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD15_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD15_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x20C034++0x3 line.word 0x0 "TCD15_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD15_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x20C036++0x1 line.word 0x0 "TCD15_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x20C038++0x3 line.long 0x0 "TCD15_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x20C03C++0x3 line.word 0x0 "TCD15_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD15_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x20C03E++0x1 line.word 0x0 "TCD15_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x210000++0x13 line.long 0x0 "CH16_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH16_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH16_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH16_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--3. 1. "MID,Master ID" line.long 0x10 "CH16_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x210020++0x3 line.long 0x0 "TCD16_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x210024++0x3 line.word 0x0 "TCD16_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD16_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x210028++0x3 line.long 0x0 "TCD16_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x210028++0xB line.long 0x0 "TCD16_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD16_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD16_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x210034++0x3 line.word 0x0 "TCD16_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD16_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x210036++0x1 line.word 0x0 "TCD16_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x210038++0x3 line.long 0x0 "TCD16_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x21003C++0x3 line.word 0x0 "TCD16_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD16_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x21003E++0x1 line.word 0x0 "TCD16_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x214000++0x13 line.long 0x0 "CH17_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH17_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH17_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH17_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--3. 1. "MID,Master ID" line.long 0x10 "CH17_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x214020++0x3 line.long 0x0 "TCD17_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x214024++0x3 line.word 0x0 "TCD17_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD17_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x214028++0x3 line.long 0x0 "TCD17_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x214028++0xB line.long 0x0 "TCD17_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD17_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD17_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x214034++0x3 line.word 0x0 "TCD17_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD17_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x214036++0x1 line.word 0x0 "TCD17_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x214038++0x3 line.long 0x0 "TCD17_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x21403C++0x3 line.word 0x0 "TCD17_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD17_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x21403E++0x1 line.word 0x0 "TCD17_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x218000++0x13 line.long 0x0 "CH18_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH18_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH18_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH18_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--3. 1. "MID,Master ID" line.long 0x10 "CH18_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x218020++0x3 line.long 0x0 "TCD18_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x218024++0x3 line.word 0x0 "TCD18_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD18_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x218028++0x3 line.long 0x0 "TCD18_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x218028++0xB line.long 0x0 "TCD18_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD18_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD18_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x218034++0x3 line.word 0x0 "TCD18_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD18_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x218036++0x1 line.word 0x0 "TCD18_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x218038++0x3 line.long 0x0 "TCD18_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x21803C++0x3 line.word 0x0 "TCD18_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD18_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x21803E++0x1 line.word 0x0 "TCD18_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x21C000++0x13 line.long 0x0 "CH19_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH19_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH19_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH19_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--3. 1. "MID,Master ID" line.long 0x10 "CH19_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x21C020++0x3 line.long 0x0 "TCD19_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x21C024++0x3 line.word 0x0 "TCD19_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD19_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x21C028++0x3 line.long 0x0 "TCD19_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x21C028++0xB line.long 0x0 "TCD19_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD19_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD19_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x21C034++0x3 line.word 0x0 "TCD19_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD19_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x21C036++0x1 line.word 0x0 "TCD19_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x21C038++0x3 line.long 0x0 "TCD19_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x21C03C++0x3 line.word 0x0 "TCD19_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD19_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x21C03E++0x1 line.word 0x0 "TCD19_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x220000++0x13 line.long 0x0 "CH20_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH20_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH20_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH20_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--3. 1. "MID,Master ID" line.long 0x10 "CH20_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x220020++0x3 line.long 0x0 "TCD20_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x220024++0x3 line.word 0x0 "TCD20_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD20_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x220028++0x3 line.long 0x0 "TCD20_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x220028++0xB line.long 0x0 "TCD20_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD20_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD20_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x220034++0x3 line.word 0x0 "TCD20_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD20_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x220036++0x1 line.word 0x0 "TCD20_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x220038++0x3 line.long 0x0 "TCD20_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x22003C++0x3 line.word 0x0 "TCD20_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD20_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x22003E++0x1 line.word 0x0 "TCD20_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x224000++0x13 line.long 0x0 "CH21_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH21_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH21_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH21_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--3. 1. "MID,Master ID" line.long 0x10 "CH21_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x224020++0x3 line.long 0x0 "TCD21_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x224024++0x3 line.word 0x0 "TCD21_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD21_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x224028++0x3 line.long 0x0 "TCD21_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x224028++0xB line.long 0x0 "TCD21_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD21_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD21_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x224034++0x3 line.word 0x0 "TCD21_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD21_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x224036++0x1 line.word 0x0 "TCD21_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x224038++0x3 line.long 0x0 "TCD21_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x22403C++0x3 line.word 0x0 "TCD21_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD21_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x22403E++0x1 line.word 0x0 "TCD21_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x228000++0x13 line.long 0x0 "CH22_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH22_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH22_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH22_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--3. 1. "MID,Master ID" line.long 0x10 "CH22_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x228020++0x3 line.long 0x0 "TCD22_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x228024++0x3 line.word 0x0 "TCD22_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD22_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x228028++0x3 line.long 0x0 "TCD22_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x228028++0xB line.long 0x0 "TCD22_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD22_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD22_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x228034++0x3 line.word 0x0 "TCD22_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD22_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x228036++0x1 line.word 0x0 "TCD22_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x228038++0x3 line.long 0x0 "TCD22_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x22803C++0x3 line.word 0x0 "TCD22_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD22_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x22803E++0x1 line.word 0x0 "TCD22_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x22C000++0x13 line.long 0x0 "CH23_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH23_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH23_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH23_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--3. 1. "MID,Master ID" line.long 0x10 "CH23_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x22C020++0x3 line.long 0x0 "TCD23_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x22C024++0x3 line.word 0x0 "TCD23_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD23_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x22C028++0x3 line.long 0x0 "TCD23_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x22C028++0xB line.long 0x0 "TCD23_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD23_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD23_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x22C034++0x3 line.word 0x0 "TCD23_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD23_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x22C036++0x1 line.word 0x0 "TCD23_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x22C038++0x3 line.long 0x0 "TCD23_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x22C03C++0x3 line.word 0x0 "TCD23_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD23_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x22C03E++0x1 line.word 0x0 "TCD23_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x230000++0x13 line.long 0x0 "CH24_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH24_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH24_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH24_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--3. 1. "MID,Master ID" line.long 0x10 "CH24_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x230020++0x3 line.long 0x0 "TCD24_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x230024++0x3 line.word 0x0 "TCD24_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD24_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x230028++0x3 line.long 0x0 "TCD24_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x230028++0xB line.long 0x0 "TCD24_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD24_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD24_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x230034++0x3 line.word 0x0 "TCD24_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD24_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x230036++0x1 line.word 0x0 "TCD24_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x230038++0x3 line.long 0x0 "TCD24_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x23003C++0x3 line.word 0x0 "TCD24_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD24_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x23003E++0x1 line.word 0x0 "TCD24_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x234000++0x13 line.long 0x0 "CH25_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH25_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH25_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH25_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--3. 1. "MID,Master ID" line.long 0x10 "CH25_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x234020++0x3 line.long 0x0 "TCD25_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x234024++0x3 line.word 0x0 "TCD25_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD25_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x234028++0x3 line.long 0x0 "TCD25_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x234028++0xB line.long 0x0 "TCD25_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD25_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD25_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x234034++0x3 line.word 0x0 "TCD25_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD25_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x234036++0x1 line.word 0x0 "TCD25_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x234038++0x3 line.long 0x0 "TCD25_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x23403C++0x3 line.word 0x0 "TCD25_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD25_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x23403E++0x1 line.word 0x0 "TCD25_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x238000++0x13 line.long 0x0 "CH26_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH26_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH26_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH26_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--3. 1. "MID,Master ID" line.long 0x10 "CH26_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x238020++0x3 line.long 0x0 "TCD26_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x238024++0x3 line.word 0x0 "TCD26_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD26_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x238028++0x3 line.long 0x0 "TCD26_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x238028++0xB line.long 0x0 "TCD26_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD26_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD26_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x238034++0x3 line.word 0x0 "TCD26_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD26_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x238036++0x1 line.word 0x0 "TCD26_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x238038++0x3 line.long 0x0 "TCD26_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x23803C++0x3 line.word 0x0 "TCD26_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD26_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x23803E++0x1 line.word 0x0 "TCD26_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x23C000++0x13 line.long 0x0 "CH27_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH27_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH27_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH27_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--3. 1. "MID,Master ID" line.long 0x10 "CH27_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x23C020++0x3 line.long 0x0 "TCD27_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x23C024++0x3 line.word 0x0 "TCD27_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD27_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x23C028++0x3 line.long 0x0 "TCD27_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x23C028++0xB line.long 0x0 "TCD27_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD27_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD27_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x23C034++0x3 line.word 0x0 "TCD27_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD27_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x23C036++0x1 line.word 0x0 "TCD27_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x23C038++0x3 line.long 0x0 "TCD27_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x23C03C++0x3 line.word 0x0 "TCD27_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD27_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x23C03E++0x1 line.word 0x0 "TCD27_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x240000++0x13 line.long 0x0 "CH28_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH28_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH28_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH28_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--3. 1. "MID,Master ID" line.long 0x10 "CH28_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x240020++0x3 line.long 0x0 "TCD28_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x240024++0x3 line.word 0x0 "TCD28_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD28_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x240028++0x3 line.long 0x0 "TCD28_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x240028++0xB line.long 0x0 "TCD28_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD28_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD28_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x240034++0x3 line.word 0x0 "TCD28_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD28_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x240036++0x1 line.word 0x0 "TCD28_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x240038++0x3 line.long 0x0 "TCD28_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x24003C++0x3 line.word 0x0 "TCD28_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD28_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x24003E++0x1 line.word 0x0 "TCD28_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x244000++0x13 line.long 0x0 "CH29_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH29_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH29_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH29_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--3. 1. "MID,Master ID" line.long 0x10 "CH29_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x244020++0x3 line.long 0x0 "TCD29_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x244024++0x3 line.word 0x0 "TCD29_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD29_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x244028++0x3 line.long 0x0 "TCD29_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x244028++0xB line.long 0x0 "TCD29_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD29_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD29_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x244034++0x3 line.word 0x0 "TCD29_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD29_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x244036++0x1 line.word 0x0 "TCD29_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x244038++0x3 line.long 0x0 "TCD29_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x24403C++0x3 line.word 0x0 "TCD29_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD29_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x24403E++0x1 line.word 0x0 "TCD29_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x248000++0x13 line.long 0x0 "CH30_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH30_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH30_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH30_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--3. 1. "MID,Master ID" line.long 0x10 "CH30_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x248020++0x3 line.long 0x0 "TCD30_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x248024++0x3 line.word 0x0 "TCD30_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD30_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x248028++0x3 line.long 0x0 "TCD30_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x248028++0xB line.long 0x0 "TCD30_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD30_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD30_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x248034++0x3 line.word 0x0 "TCD30_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD30_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x248036++0x1 line.word 0x0 "TCD30_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x248038++0x3 line.long 0x0 "TCD30_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x24803C++0x3 line.word 0x0 "TCD30_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD30_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x24803E++0x1 line.word 0x0 "TCD30_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x24C000++0x13 line.long 0x0 "CH31_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH31_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH31_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH31_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--3. 1. "MID,Master ID" line.long 0x10 "CH31_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x24C020++0x3 line.long 0x0 "TCD31_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x24C024++0x3 line.word 0x0 "TCD31_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD31_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x24C028++0x3 line.long 0x0 "TCD31_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x24C028++0xB line.long 0x0 "TCD31_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD31_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD31_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x24C034++0x3 line.word 0x0 "TCD31_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD31_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x24C036++0x1 line.word 0x0 "TCD31_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x24C038++0x3 line.long 0x0 "TCD31_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x24C03C++0x3 line.word 0x0 "TCD31_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation (HPE)..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD31_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x24C03E++0x1 line.word 0x0 "TCD31_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" tree.end base ad:0x0 tree "DMAMUX" tree "DMAMUX_0" base ad:0x40280000 group.byte 0x0++0xF line.byte 0x0 "CHCFG3,Channel Configuration" bitfld.byte 0x0 7. "ENBL,DMA Channel Enable" "0: Disable,1: Enable" bitfld.byte 0x0 6. "TRIG,DMA Channel Trigger Enable" "0: Disable,1: Enable" hexmask.byte 0x0 0.--5. 1. "SOURCE,DMA Channel Source (Slot)" line.byte 0x1 "CHCFG2,Channel Configuration" bitfld.byte 0x1 7. "ENBL,DMA Channel Enable" "0: Disable,1: Enable" bitfld.byte 0x1 6. "TRIG,DMA Channel Trigger Enable" "0: Disable,1: Enable" hexmask.byte 0x1 0.--5. 1. "SOURCE,DMA Channel Source (Slot)" line.byte 0x2 "CHCFG1,Channel Configuration" bitfld.byte 0x2 7. "ENBL,DMA Channel Enable" "0: Disable,1: Enable" bitfld.byte 0x2 6. "TRIG,DMA Channel Trigger Enable" "0: Disable,1: Enable" hexmask.byte 0x2 0.--5. 1. "SOURCE,DMA Channel Source (Slot)" line.byte 0x3 "CHCFG0,Channel Configuration" bitfld.byte 0x3 7. "ENBL,DMA Channel Enable" "0: Disable,1: Enable" bitfld.byte 0x3 6. "TRIG,DMA Channel Trigger Enable" "0: Disable,1: Enable" hexmask.byte 0x3 0.--5. 1. "SOURCE,DMA Channel Source (Slot)" line.byte 0x4 "CHCFG7,Channel Configuration" bitfld.byte 0x4 7. "ENBL,DMA Channel Enable" "0: Disable,1: Enable" hexmask.byte 0x4 0.--5. 1. "SOURCE,DMA Channel Source (Slot)" line.byte 0x5 "CHCFG6,Channel Configuration" bitfld.byte 0x5 7. "ENBL,DMA Channel Enable" "0: Disable,1: Enable" hexmask.byte 0x5 0.--5. 1. "SOURCE,DMA Channel Source (Slot)" line.byte 0x6 "CHCFG5,Channel Configuration" bitfld.byte 0x6 7. "ENBL,DMA Channel Enable" "0: Disable,1: Enable" hexmask.byte 0x6 0.--5. 1. "SOURCE,DMA Channel Source (Slot)" line.byte 0x7 "CHCFG4,Channel Configuration" bitfld.byte 0x7 7. "ENBL,DMA Channel Enable" "0: Disable,1: Enable" hexmask.byte 0x7 0.--5. 1. "SOURCE,DMA Channel Source (Slot)" line.byte 0x8 "CHCFG11,Channel Configuration" bitfld.byte 0x8 7. "ENBL,DMA Channel Enable" "0: Disable,1: Enable" hexmask.byte 0x8 0.--5. 1. "SOURCE,DMA Channel Source (Slot)" line.byte 0x9 "CHCFG10,Channel Configuration" bitfld.byte 0x9 7. "ENBL,DMA Channel Enable" "0: Disable,1: Enable" hexmask.byte 0x9 0.--5. 1. "SOURCE,DMA Channel Source (Slot)" line.byte 0xA "CHCFG9,Channel Configuration" bitfld.byte 0xA 7. "ENBL,DMA Channel Enable" "0: Disable,1: Enable" hexmask.byte 0xA 0.--5. 1. "SOURCE,DMA Channel Source (Slot)" line.byte 0xB "CHCFG8,Channel Configuration" bitfld.byte 0xB 7. "ENBL,DMA Channel Enable" "0: Disable,1: Enable" hexmask.byte 0xB 0.--5. 1. "SOURCE,DMA Channel Source (Slot)" line.byte 0xC "CHCFG15,Channel Configuration" bitfld.byte 0xC 7. "ENBL,DMA Channel Enable" "0: Disable,1: Enable" hexmask.byte 0xC 0.--5. 1. "SOURCE,DMA Channel Source (Slot)" line.byte 0xD "CHCFG14,Channel Configuration" bitfld.byte 0xD 7. "ENBL,DMA Channel Enable" "0: Disable,1: Enable" hexmask.byte 0xD 0.--5. 1. "SOURCE,DMA Channel Source (Slot)" line.byte 0xE "CHCFG13,Channel Configuration" bitfld.byte 0xE 7. "ENBL,DMA Channel Enable" "0: Disable,1: Enable" hexmask.byte 0xE 0.--5. 1. "SOURCE,DMA Channel Source (Slot)" line.byte 0xF "CHCFG12,Channel Configuration" bitfld.byte 0xF 7. "ENBL,DMA Channel Enable" "0: Disable,1: Enable" hexmask.byte 0xF 0.--5. 1. "SOURCE,DMA Channel Source (Slot)" tree.end tree "DMAMUX_1" base ad:0x40284000 group.byte 0x0++0xF line.byte 0x0 "CHCFG3,Channel Configuration" bitfld.byte 0x0 7. "ENBL,DMA Channel Enable" "0: Disable,1: Enable" bitfld.byte 0x0 6. "TRIG,DMA Channel Trigger Enable" "0: Disable,1: Enable" hexmask.byte 0x0 0.--5. 1. "SOURCE,DMA Channel Source (Slot)" line.byte 0x1 "CHCFG2,Channel Configuration" bitfld.byte 0x1 7. "ENBL,DMA Channel Enable" "0: Disable,1: Enable" bitfld.byte 0x1 6. "TRIG,DMA Channel Trigger Enable" "0: Disable,1: Enable" hexmask.byte 0x1 0.--5. 1. "SOURCE,DMA Channel Source (Slot)" line.byte 0x2 "CHCFG1,Channel Configuration" bitfld.byte 0x2 7. "ENBL,DMA Channel Enable" "0: Disable,1: Enable" bitfld.byte 0x2 6. "TRIG,DMA Channel Trigger Enable" "0: Disable,1: Enable" hexmask.byte 0x2 0.--5. 1. "SOURCE,DMA Channel Source (Slot)" line.byte 0x3 "CHCFG0,Channel Configuration" bitfld.byte 0x3 7. "ENBL,DMA Channel Enable" "0: Disable,1: Enable" bitfld.byte 0x3 6. "TRIG,DMA Channel Trigger Enable" "0: Disable,1: Enable" hexmask.byte 0x3 0.--5. 1. "SOURCE,DMA Channel Source (Slot)" line.byte 0x4 "CHCFG7,Channel Configuration" bitfld.byte 0x4 7. "ENBL,DMA Channel Enable" "0: Disable,1: Enable" hexmask.byte 0x4 0.--5. 1. "SOURCE,DMA Channel Source (Slot)" line.byte 0x5 "CHCFG6,Channel Configuration" bitfld.byte 0x5 7. "ENBL,DMA Channel Enable" "0: Disable,1: Enable" hexmask.byte 0x5 0.--5. 1. "SOURCE,DMA Channel Source (Slot)" line.byte 0x6 "CHCFG5,Channel Configuration" bitfld.byte 0x6 7. "ENBL,DMA Channel Enable" "0: Disable,1: Enable" hexmask.byte 0x6 0.--5. 1. "SOURCE,DMA Channel Source (Slot)" line.byte 0x7 "CHCFG4,Channel Configuration" bitfld.byte 0x7 7. "ENBL,DMA Channel Enable" "0: Disable,1: Enable" hexmask.byte 0x7 0.--5. 1. "SOURCE,DMA Channel Source (Slot)" line.byte 0x8 "CHCFG11,Channel Configuration" bitfld.byte 0x8 7. "ENBL,DMA Channel Enable" "0: Disable,1: Enable" hexmask.byte 0x8 0.--5. 1. "SOURCE,DMA Channel Source (Slot)" line.byte 0x9 "CHCFG10,Channel Configuration" bitfld.byte 0x9 7. "ENBL,DMA Channel Enable" "0: Disable,1: Enable" hexmask.byte 0x9 0.--5. 1. "SOURCE,DMA Channel Source (Slot)" line.byte 0xA "CHCFG9,Channel Configuration" bitfld.byte 0xA 7. "ENBL,DMA Channel Enable" "0: Disable,1: Enable" hexmask.byte 0xA 0.--5. 1. "SOURCE,DMA Channel Source (Slot)" line.byte 0xB "CHCFG8,Channel Configuration" bitfld.byte 0xB 7. "ENBL,DMA Channel Enable" "0: Disable,1: Enable" hexmask.byte 0xB 0.--5. 1. "SOURCE,DMA Channel Source (Slot)" line.byte 0xC "CHCFG15,Channel Configuration" bitfld.byte 0xC 7. "ENBL,DMA Channel Enable" "0: Disable,1: Enable" hexmask.byte 0xC 0.--5. 1. "SOURCE,DMA Channel Source (Slot)" line.byte 0xD "CHCFG14,Channel Configuration" bitfld.byte 0xD 7. "ENBL,DMA Channel Enable" "0: Disable,1: Enable" hexmask.byte 0xD 0.--5. 1. "SOURCE,DMA Channel Source (Slot)" line.byte 0xE "CHCFG13,Channel Configuration" bitfld.byte 0xE 7. "ENBL,DMA Channel Enable" "0: Disable,1: Enable" hexmask.byte 0xE 0.--5. 1. "SOURCE,DMA Channel Source (Slot)" line.byte 0xF "CHCFG12,Channel Configuration" bitfld.byte 0xF 7. "ENBL,DMA Channel Enable" "0: Disable,1: Enable" hexmask.byte 0xF 0.--5. 1. "SOURCE,DMA Channel Source (Slot)" tree.end tree.end tree "FEED_DMA_MP" base ad:0x403C2000 group.long 0x0++0x3 line.long 0x0 "CSR,Management Page Control" rbitfld.long 0x0 31. "ACTIVE,DMA Active Status" "0: eDMA is idle,1: eDMA is executing a channel" hexmask.long.byte 0x0 24.--28. 1. "ACTIVE_ID,Active Channel ID" newline bitfld.long 0x0 9. "CX,Cancel Transfer" "0: Normal operation,1: Cancel the remaining data transfer" bitfld.long 0x0 8. "ECX,Cancel Transfer With Error" "0: Normal operation,1: Cancel the remaining data transfer" newline bitfld.long 0x0 7. "GMRC,Global Master ID Replication Control" "0: Master ID replication disabled for all channels,1: Master ID replication available and controlled.." bitfld.long 0x0 6. "GCLC,Global Channel Linking Control" "0: Channel linking disabled for all channels,1: Channel linking available and controlled by each.." newline bitfld.long 0x0 5. "HALT,Halt DMA Operations" "0: Normal operation,1: Stall the start of any new channels" bitfld.long 0x0 4. "HAE,Halt After Error" "0: Normal operation,1: Any error causes the HALT field to be set to 1" newline bitfld.long 0x0 2. "ERCA,Enable Round Robin Channel Arbitration" "0: Round-robin channel arbitration disabled,1: Round-robin channel arbitration enabled" bitfld.long 0x0 1. "EDBG,Enable Debug" "0: Debug mode disabled,1: Debug mode is enabled." rgroup.long 0x4++0xB line.long 0x0 "ES,Management Page Error Status" bitfld.long 0x0 31. "VLD,Valid" "0: No ERR fields are set to 1,1: At least one ERR field is set to 1 indicating a.." hexmask.long.byte 0x0 24.--28. 1. "ERRCHN,Error Channel Number or Canceled Channel Number" newline bitfld.long 0x0 9. "UCE,Uncorrectable TCD Error During Channel Execution" "0: No uncorrectable ECC error,1: Last recorded error was an uncorrectable TCD RAM.." bitfld.long 0x0 8. "ECX,Transfer Canceled" "0: No canceled transfers,1: Last recorded entry was a canceled transfer by.." newline bitfld.long 0x0 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." bitfld.long 0x0 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." newline bitfld.long 0x0 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." bitfld.long 0x0 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." newline bitfld.long 0x0 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: The last recorded error was NBYTES equal to zero.." bitfld.long 0x0 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." newline bitfld.long 0x0 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was a bus error on a source.." bitfld.long 0x0 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was a bus error on a.." line.long 0x4 "INT,Management Page Interrupt Request Status" hexmask.long 0x4 0.--31. 1. "INT,Interrupt Request Status" line.long 0x8 "HRS,Management Page Hardware Request Status" hexmask.long 0x8 0.--31. 1. "HRS,Hardware Request Status" repeat 32. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x100)++0x3 line.long 0x0 "CH_GRPRI[$1],Channel Arbitration Group" hexmask.long.byte 0x0 0.--4. 1. "GRPRI,Arbitration Group For Channel n" repeat.end tree.end tree "FEED_DMA_TCD" base ad:0x403D1000 group.long 0x0++0x13 line.long 0x0 "CH0_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH0_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH0_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH0_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH0_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x20++0x3 line.long 0x0 "TCD0_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x24++0x3 line.word 0x0 "TCD0_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD0_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x28++0x3 line.long 0x0 "TCD0_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x28++0xB line.long 0x0 "TCD0_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD0_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD0_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x34++0x3 line.word 0x0 "TCD0_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD0_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x36++0x1 line.word 0x0 "TCD0_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x38++0x3 line.long 0x0 "TCD0_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x3C++0x3 line.word 0x0 "TCD0_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD0_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x3E++0x1 line.word 0x0 "TCD0_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x1000++0x13 line.long 0x0 "CH1_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH1_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH1_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH1_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH1_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x1020++0x3 line.long 0x0 "TCD1_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x1024++0x3 line.word 0x0 "TCD1_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD1_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x1028++0x3 line.long 0x0 "TCD1_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x1028++0xB line.long 0x0 "TCD1_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD1_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD1_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x1034++0x3 line.word 0x0 "TCD1_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD1_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x1036++0x1 line.word 0x0 "TCD1_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x1038++0x3 line.long 0x0 "TCD1_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x103C++0x3 line.word 0x0 "TCD1_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD1_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x103E++0x1 line.word 0x0 "TCD1_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x2000++0x13 line.long 0x0 "CH2_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH2_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH2_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH2_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH2_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x2020++0x3 line.long 0x0 "TCD2_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x2024++0x3 line.word 0x0 "TCD2_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD2_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x2028++0x3 line.long 0x0 "TCD2_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x2028++0xB line.long 0x0 "TCD2_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD2_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD2_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x2034++0x3 line.word 0x0 "TCD2_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD2_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x2036++0x1 line.word 0x0 "TCD2_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x2038++0x3 line.long 0x0 "TCD2_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x203C++0x3 line.word 0x0 "TCD2_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD2_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x203E++0x1 line.word 0x0 "TCD2_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x3000++0x13 line.long 0x0 "CH3_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH3_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH3_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH3_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH3_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x3020++0x3 line.long 0x0 "TCD3_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x3024++0x3 line.word 0x0 "TCD3_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD3_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x3028++0x3 line.long 0x0 "TCD3_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x3028++0xB line.long 0x0 "TCD3_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD3_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD3_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x3034++0x3 line.word 0x0 "TCD3_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD3_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x3036++0x1 line.word 0x0 "TCD3_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x3038++0x3 line.long 0x0 "TCD3_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x303C++0x3 line.word 0x0 "TCD3_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD3_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x303E++0x1 line.word 0x0 "TCD3_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x4000++0x13 line.long 0x0 "CH4_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH4_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH4_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH4_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH4_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x4020++0x3 line.long 0x0 "TCD4_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x4024++0x3 line.word 0x0 "TCD4_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD4_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x4028++0x3 line.long 0x0 "TCD4_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x4028++0xB line.long 0x0 "TCD4_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD4_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD4_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x4034++0x3 line.word 0x0 "TCD4_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD4_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x4036++0x1 line.word 0x0 "TCD4_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x4038++0x3 line.long 0x0 "TCD4_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x403C++0x3 line.word 0x0 "TCD4_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD4_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x403E++0x1 line.word 0x0 "TCD4_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x5000++0x13 line.long 0x0 "CH5_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH5_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH5_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH5_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH5_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x5020++0x3 line.long 0x0 "TCD5_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x5024++0x3 line.word 0x0 "TCD5_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD5_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x5028++0x3 line.long 0x0 "TCD5_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x5028++0xB line.long 0x0 "TCD5_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD5_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD5_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x5034++0x3 line.word 0x0 "TCD5_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD5_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x5036++0x1 line.word 0x0 "TCD5_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x5038++0x3 line.long 0x0 "TCD5_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x503C++0x3 line.word 0x0 "TCD5_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD5_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x503E++0x1 line.word 0x0 "TCD5_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x6000++0x13 line.long 0x0 "CH6_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH6_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH6_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH6_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH6_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x6020++0x3 line.long 0x0 "TCD6_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x6024++0x3 line.word 0x0 "TCD6_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD6_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x6028++0x3 line.long 0x0 "TCD6_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x6028++0xB line.long 0x0 "TCD6_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD6_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD6_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x6034++0x3 line.word 0x0 "TCD6_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD6_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x6036++0x1 line.word 0x0 "TCD6_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x6038++0x3 line.long 0x0 "TCD6_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x603C++0x3 line.word 0x0 "TCD6_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD6_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x603E++0x1 line.word 0x0 "TCD6_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x7000++0x13 line.long 0x0 "CH7_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH7_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH7_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH7_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH7_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x7020++0x3 line.long 0x0 "TCD7_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x7024++0x3 line.word 0x0 "TCD7_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD7_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x7028++0x3 line.long 0x0 "TCD7_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x7028++0xB line.long 0x0 "TCD7_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD7_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD7_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x7034++0x3 line.word 0x0 "TCD7_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD7_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x7036++0x1 line.word 0x0 "TCD7_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x7038++0x3 line.long 0x0 "TCD7_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x703C++0x3 line.word 0x0 "TCD7_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD7_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x703E++0x1 line.word 0x0 "TCD7_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x8000++0x13 line.long 0x0 "CH8_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH8_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH8_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH8_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH8_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x8020++0x3 line.long 0x0 "TCD8_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x8024++0x3 line.word 0x0 "TCD8_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD8_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x8028++0x3 line.long 0x0 "TCD8_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x8028++0xB line.long 0x0 "TCD8_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD8_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD8_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x8034++0x3 line.word 0x0 "TCD8_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD8_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x8036++0x1 line.word 0x0 "TCD8_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x8038++0x3 line.long 0x0 "TCD8_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x803C++0x3 line.word 0x0 "TCD8_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD8_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x803E++0x1 line.word 0x0 "TCD8_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x9000++0x13 line.long 0x0 "CH9_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH9_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH9_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH9_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH9_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x9020++0x3 line.long 0x0 "TCD9_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x9024++0x3 line.word 0x0 "TCD9_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD9_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x9028++0x3 line.long 0x0 "TCD9_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x9028++0xB line.long 0x0 "TCD9_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD9_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD9_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x9034++0x3 line.word 0x0 "TCD9_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD9_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x9036++0x1 line.word 0x0 "TCD9_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x9038++0x3 line.long 0x0 "TCD9_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x903C++0x3 line.word 0x0 "TCD9_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD9_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x903E++0x1 line.word 0x0 "TCD9_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0xA000++0x13 line.long 0x0 "CH10_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH10_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH10_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH10_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH10_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0xA020++0x3 line.long 0x0 "TCD10_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0xA024++0x3 line.word 0x0 "TCD10_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD10_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0xA028++0x3 line.long 0x0 "TCD10_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0xA028++0xB line.long 0x0 "TCD10_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD10_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD10_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0xA034++0x3 line.word 0x0 "TCD10_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD10_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0xA036++0x1 line.word 0x0 "TCD10_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0xA038++0x3 line.long 0x0 "TCD10_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0xA03C++0x3 line.word 0x0 "TCD10_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD10_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0xA03E++0x1 line.word 0x0 "TCD10_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0xB000++0x13 line.long 0x0 "CH11_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH11_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH11_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH11_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH11_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0xB020++0x3 line.long 0x0 "TCD11_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0xB024++0x3 line.word 0x0 "TCD11_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD11_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0xB028++0x3 line.long 0x0 "TCD11_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0xB028++0xB line.long 0x0 "TCD11_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD11_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD11_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0xB034++0x3 line.word 0x0 "TCD11_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD11_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0xB036++0x1 line.word 0x0 "TCD11_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0xB038++0x3 line.long 0x0 "TCD11_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0xB03C++0x3 line.word 0x0 "TCD11_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD11_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0xB03E++0x1 line.word 0x0 "TCD11_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0xC000++0x13 line.long 0x0 "CH12_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH12_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH12_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH12_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH12_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0xC020++0x3 line.long 0x0 "TCD12_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0xC024++0x3 line.word 0x0 "TCD12_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD12_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0xC028++0x3 line.long 0x0 "TCD12_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0xC028++0xB line.long 0x0 "TCD12_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD12_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD12_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0xC034++0x3 line.word 0x0 "TCD12_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD12_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0xC036++0x1 line.word 0x0 "TCD12_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0xC038++0x3 line.long 0x0 "TCD12_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0xC03C++0x3 line.word 0x0 "TCD12_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD12_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0xC03E++0x1 line.word 0x0 "TCD12_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0xD000++0x13 line.long 0x0 "CH13_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH13_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH13_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH13_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH13_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0xD020++0x3 line.long 0x0 "TCD13_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0xD024++0x3 line.word 0x0 "TCD13_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD13_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0xD028++0x3 line.long 0x0 "TCD13_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0xD028++0xB line.long 0x0 "TCD13_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD13_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD13_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0xD034++0x3 line.word 0x0 "TCD13_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD13_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0xD036++0x1 line.word 0x0 "TCD13_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0xD038++0x3 line.long 0x0 "TCD13_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0xD03C++0x3 line.word 0x0 "TCD13_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD13_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0xD03E++0x1 line.word 0x0 "TCD13_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0xE000++0x13 line.long 0x0 "CH14_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH14_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH14_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH14_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH14_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0xE020++0x3 line.long 0x0 "TCD14_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0xE024++0x3 line.word 0x0 "TCD14_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD14_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0xE028++0x3 line.long 0x0 "TCD14_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0xE028++0xB line.long 0x0 "TCD14_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD14_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD14_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0xE034++0x3 line.word 0x0 "TCD14_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD14_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0xE036++0x1 line.word 0x0 "TCD14_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0xE038++0x3 line.long 0x0 "TCD14_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0xE03C++0x3 line.word 0x0 "TCD14_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD14_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0xE03E++0x1 line.word 0x0 "TCD14_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0xF000++0x13 line.long 0x0 "CH15_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH15_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH15_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH15_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH15_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0xF020++0x3 line.long 0x0 "TCD15_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0xF024++0x3 line.word 0x0 "TCD15_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD15_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0xF028++0x3 line.long 0x0 "TCD15_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0xF028++0xB line.long 0x0 "TCD15_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD15_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD15_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0xF034++0x3 line.word 0x0 "TCD15_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD15_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0xF036++0x1 line.word 0x0 "TCD15_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0xF038++0x3 line.long 0x0 "TCD15_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0xF03C++0x3 line.word 0x0 "TCD15_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD15_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0xF03E++0x1 line.word 0x0 "TCD15_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x10000++0x13 line.long 0x0 "CH16_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH16_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH16_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH16_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH16_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x10020++0x3 line.long 0x0 "TCD16_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x10024++0x3 line.word 0x0 "TCD16_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD16_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x10028++0x3 line.long 0x0 "TCD16_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x10028++0xB line.long 0x0 "TCD16_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD16_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD16_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x10034++0x3 line.word 0x0 "TCD16_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD16_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x10036++0x1 line.word 0x0 "TCD16_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x10038++0x3 line.long 0x0 "TCD16_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1003C++0x3 line.word 0x0 "TCD16_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD16_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1003E++0x1 line.word 0x0 "TCD16_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x11000++0x13 line.long 0x0 "CH17_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH17_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH17_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH17_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH17_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x11020++0x3 line.long 0x0 "TCD17_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x11024++0x3 line.word 0x0 "TCD17_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD17_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x11028++0x3 line.long 0x0 "TCD17_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x11028++0xB line.long 0x0 "TCD17_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD17_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD17_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x11034++0x3 line.word 0x0 "TCD17_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD17_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x11036++0x1 line.word 0x0 "TCD17_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x11038++0x3 line.long 0x0 "TCD17_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1103C++0x3 line.word 0x0 "TCD17_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD17_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1103E++0x1 line.word 0x0 "TCD17_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x12000++0x13 line.long 0x0 "CH18_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH18_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH18_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH18_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH18_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x12020++0x3 line.long 0x0 "TCD18_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x12024++0x3 line.word 0x0 "TCD18_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD18_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x12028++0x3 line.long 0x0 "TCD18_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x12028++0xB line.long 0x0 "TCD18_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD18_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD18_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x12034++0x3 line.word 0x0 "TCD18_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD18_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x12036++0x1 line.word 0x0 "TCD18_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x12038++0x3 line.long 0x0 "TCD18_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1203C++0x3 line.word 0x0 "TCD18_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD18_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1203E++0x1 line.word 0x0 "TCD18_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x13000++0x13 line.long 0x0 "CH19_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH19_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH19_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH19_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH19_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x13020++0x3 line.long 0x0 "TCD19_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x13024++0x3 line.word 0x0 "TCD19_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD19_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x13028++0x3 line.long 0x0 "TCD19_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x13028++0xB line.long 0x0 "TCD19_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD19_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD19_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x13034++0x3 line.word 0x0 "TCD19_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD19_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x13036++0x1 line.word 0x0 "TCD19_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x13038++0x3 line.long 0x0 "TCD19_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1303C++0x3 line.word 0x0 "TCD19_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD19_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1303E++0x1 line.word 0x0 "TCD19_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x14000++0x13 line.long 0x0 "CH20_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH20_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH20_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH20_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH20_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x14020++0x3 line.long 0x0 "TCD20_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x14024++0x3 line.word 0x0 "TCD20_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD20_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x14028++0x3 line.long 0x0 "TCD20_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x14028++0xB line.long 0x0 "TCD20_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD20_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD20_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x14034++0x3 line.word 0x0 "TCD20_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD20_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x14036++0x1 line.word 0x0 "TCD20_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x14038++0x3 line.long 0x0 "TCD20_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1403C++0x3 line.word 0x0 "TCD20_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD20_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1403E++0x1 line.word 0x0 "TCD20_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x15000++0x13 line.long 0x0 "CH21_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH21_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH21_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH21_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH21_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x15020++0x3 line.long 0x0 "TCD21_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x15024++0x3 line.word 0x0 "TCD21_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD21_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x15028++0x3 line.long 0x0 "TCD21_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x15028++0xB line.long 0x0 "TCD21_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD21_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD21_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x15034++0x3 line.word 0x0 "TCD21_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD21_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x15036++0x1 line.word 0x0 "TCD21_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x15038++0x3 line.long 0x0 "TCD21_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1503C++0x3 line.word 0x0 "TCD21_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD21_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1503E++0x1 line.word 0x0 "TCD21_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x16000++0x13 line.long 0x0 "CH22_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH22_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH22_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH22_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH22_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x16020++0x3 line.long 0x0 "TCD22_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x16024++0x3 line.word 0x0 "TCD22_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD22_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x16028++0x3 line.long 0x0 "TCD22_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x16028++0xB line.long 0x0 "TCD22_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD22_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD22_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x16034++0x3 line.word 0x0 "TCD22_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD22_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x16036++0x1 line.word 0x0 "TCD22_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x16038++0x3 line.long 0x0 "TCD22_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1603C++0x3 line.word 0x0 "TCD22_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD22_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1603E++0x1 line.word 0x0 "TCD22_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x17000++0x13 line.long 0x0 "CH23_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH23_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH23_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH23_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH23_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x17020++0x3 line.long 0x0 "TCD23_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x17024++0x3 line.word 0x0 "TCD23_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD23_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x17028++0x3 line.long 0x0 "TCD23_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x17028++0xB line.long 0x0 "TCD23_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD23_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD23_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x17034++0x3 line.word 0x0 "TCD23_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD23_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x17036++0x1 line.word 0x0 "TCD23_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x17038++0x3 line.long 0x0 "TCD23_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1703C++0x3 line.word 0x0 "TCD23_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD23_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1703E++0x1 line.word 0x0 "TCD23_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x18000++0x13 line.long 0x0 "CH24_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH24_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH24_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH24_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH24_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x18020++0x3 line.long 0x0 "TCD24_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x18024++0x3 line.word 0x0 "TCD24_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD24_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x18028++0x3 line.long 0x0 "TCD24_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x18028++0xB line.long 0x0 "TCD24_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD24_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD24_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x18034++0x3 line.word 0x0 "TCD24_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD24_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x18036++0x1 line.word 0x0 "TCD24_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x18038++0x3 line.long 0x0 "TCD24_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1803C++0x3 line.word 0x0 "TCD24_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD24_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1803E++0x1 line.word 0x0 "TCD24_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x19000++0x13 line.long 0x0 "CH25_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH25_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH25_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH25_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH25_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x19020++0x3 line.long 0x0 "TCD25_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x19024++0x3 line.word 0x0 "TCD25_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD25_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x19028++0x3 line.long 0x0 "TCD25_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x19028++0xB line.long 0x0 "TCD25_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD25_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD25_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x19034++0x3 line.word 0x0 "TCD25_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD25_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x19036++0x1 line.word 0x0 "TCD25_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x19038++0x3 line.long 0x0 "TCD25_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1903C++0x3 line.word 0x0 "TCD25_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD25_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1903E++0x1 line.word 0x0 "TCD25_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x1A000++0x13 line.long 0x0 "CH26_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH26_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH26_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH26_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH26_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x1A020++0x3 line.long 0x0 "TCD26_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x1A024++0x3 line.word 0x0 "TCD26_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD26_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x1A028++0x3 line.long 0x0 "TCD26_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x1A028++0xB line.long 0x0 "TCD26_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD26_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD26_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x1A034++0x3 line.word 0x0 "TCD26_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD26_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x1A036++0x1 line.word 0x0 "TCD26_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x1A038++0x3 line.long 0x0 "TCD26_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1A03C++0x3 line.word 0x0 "TCD26_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD26_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1A03E++0x1 line.word 0x0 "TCD26_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x1B000++0x13 line.long 0x0 "CH27_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH27_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH27_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH27_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH27_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x1B020++0x3 line.long 0x0 "TCD27_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x1B024++0x3 line.word 0x0 "TCD27_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD27_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x1B028++0x3 line.long 0x0 "TCD27_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x1B028++0xB line.long 0x0 "TCD27_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD27_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD27_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x1B034++0x3 line.word 0x0 "TCD27_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD27_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x1B036++0x1 line.word 0x0 "TCD27_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x1B038++0x3 line.long 0x0 "TCD27_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1B03C++0x3 line.word 0x0 "TCD27_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD27_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1B03E++0x1 line.word 0x0 "TCD27_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x1C000++0x13 line.long 0x0 "CH28_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH28_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH28_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH28_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH28_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x1C020++0x3 line.long 0x0 "TCD28_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x1C024++0x3 line.word 0x0 "TCD28_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD28_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x1C028++0x3 line.long 0x0 "TCD28_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x1C028++0xB line.long 0x0 "TCD28_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD28_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD28_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x1C034++0x3 line.word 0x0 "TCD28_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD28_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x1C036++0x1 line.word 0x0 "TCD28_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x1C038++0x3 line.long 0x0 "TCD28_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1C03C++0x3 line.word 0x0 "TCD28_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD28_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1C03E++0x1 line.word 0x0 "TCD28_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x1D000++0x13 line.long 0x0 "CH29_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH29_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH29_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH29_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH29_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x1D020++0x3 line.long 0x0 "TCD29_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x1D024++0x3 line.word 0x0 "TCD29_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD29_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x1D028++0x3 line.long 0x0 "TCD29_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x1D028++0xB line.long 0x0 "TCD29_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD29_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD29_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x1D034++0x3 line.word 0x0 "TCD29_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD29_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x1D036++0x1 line.word 0x0 "TCD29_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x1D038++0x3 line.long 0x0 "TCD29_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1D03C++0x3 line.word 0x0 "TCD29_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD29_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1D03E++0x1 line.word 0x0 "TCD29_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x1E000++0x13 line.long 0x0 "CH30_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH30_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH30_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH30_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH30_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x1E020++0x3 line.long 0x0 "TCD30_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x1E024++0x3 line.word 0x0 "TCD30_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD30_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x1E028++0x3 line.long 0x0 "TCD30_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x1E028++0xB line.long 0x0 "TCD30_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD30_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD30_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x1E034++0x3 line.word 0x0 "TCD30_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD30_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x1E036++0x1 line.word 0x0 "TCD30_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x1E038++0x3 line.long 0x0 "TCD30_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1E03C++0x3 line.word 0x0 "TCD30_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD30_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1E03E++0x1 line.word 0x0 "TCD30_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x1F000++0x13 line.long 0x0 "CH31_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH31_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH31_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH31_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH31_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x1F020++0x3 line.long 0x0 "TCD31_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x1F024++0x3 line.word 0x0 "TCD31_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD31_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x1F028++0x3 line.long 0x0 "TCD31_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x1F028++0xB line.long 0x0 "TCD31_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD31_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD31_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x1F034++0x3 line.word 0x0 "TCD31_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD31_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x1F036++0x1 line.word 0x0 "TCD31_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x1F038++0x3 line.long 0x0 "TCD31_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1F03C++0x3 line.word 0x0 "TCD31_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD31_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1F03E++0x1 line.word 0x0 "TCD31_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" tree.end tree "RESULT_DMA_MP" base ad:0x403C5000 group.long 0x0++0x3 line.long 0x0 "CSR,Management Page Control" rbitfld.long 0x0 31. "ACTIVE,DMA Active Status" "0: eDMA is idle,1: eDMA is executing a channel" hexmask.long.byte 0x0 24.--28. 1. "ACTIVE_ID,Active Channel ID" newline bitfld.long 0x0 9. "CX,Cancel Transfer" "0: Normal operation,1: Cancel the remaining data transfer" bitfld.long 0x0 8. "ECX,Cancel Transfer With Error" "0: Normal operation,1: Cancel the remaining data transfer" newline bitfld.long 0x0 7. "GMRC,Global Master ID Replication Control" "0: Master ID replication disabled for all channels,1: Master ID replication available and controlled.." bitfld.long 0x0 6. "GCLC,Global Channel Linking Control" "0: Channel linking disabled for all channels,1: Channel linking available and controlled by each.." newline bitfld.long 0x0 5. "HALT,Halt DMA Operations" "0: Normal operation,1: Stall the start of any new channels" bitfld.long 0x0 4. "HAE,Halt After Error" "0: Normal operation,1: Any error causes the HALT field to be set to 1" newline bitfld.long 0x0 2. "ERCA,Enable Round Robin Channel Arbitration" "0: Round-robin channel arbitration disabled,1: Round-robin channel arbitration enabled" bitfld.long 0x0 1. "EDBG,Enable Debug" "0: Debug mode disabled,1: Debug mode is enabled." rgroup.long 0x4++0xB line.long 0x0 "ES,Management Page Error Status" bitfld.long 0x0 31. "VLD,Valid" "0: No ERR fields are set to 1,1: At least one ERR field is set to 1 indicating a.." hexmask.long.byte 0x0 24.--28. 1. "ERRCHN,Error Channel Number or Canceled Channel Number" newline bitfld.long 0x0 9. "UCE,Uncorrectable TCD Error During Channel Execution" "0: No uncorrectable ECC error,1: Last recorded error was an uncorrectable TCD RAM.." bitfld.long 0x0 8. "ECX,Transfer Canceled" "0: No canceled transfers,1: Last recorded entry was a canceled transfer by.." newline bitfld.long 0x0 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." bitfld.long 0x0 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." newline bitfld.long 0x0 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." bitfld.long 0x0 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." newline bitfld.long 0x0 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: The last recorded error was NBYTES equal to zero.." bitfld.long 0x0 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." newline bitfld.long 0x0 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was a bus error on a source.." bitfld.long 0x0 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was a bus error on a.." line.long 0x4 "INT,Management Page Interrupt Request Status" hexmask.long.tbyte 0x4 0.--23. 1. "INT,Interrupt Request Status" line.long 0x8 "HRS,Management Page Hardware Request Status" hexmask.long 0x8 0.--31. 1. "HRS,Hardware Request Status" repeat 24. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x100)++0x3 line.long 0x0 "CH_GRPRI[$1],Channel Arbitration Group" hexmask.long.byte 0x0 0.--4. 1. "GRPRI,Arbitration Group For Channel n" repeat.end tree.end tree "RESULT_DMA_TCD" base ad:0x403D5000 group.long 0x0++0x13 line.long 0x0 "CH0_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH0_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH0_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH0_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH0_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x20++0x3 line.long 0x0 "TCD0_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x24++0x3 line.word 0x0 "TCD0_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD0_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x28++0x3 line.long 0x0 "TCD0_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x28++0xB line.long 0x0 "TCD0_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD0_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD0_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x34++0x3 line.word 0x0 "TCD0_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD0_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x36++0x1 line.word 0x0 "TCD0_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x38++0x3 line.long 0x0 "TCD0_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x3C++0x3 line.word 0x0 "TCD0_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD0_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x3E++0x1 line.word 0x0 "TCD0_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x1000++0x13 line.long 0x0 "CH1_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH1_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH1_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH1_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH1_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x1020++0x3 line.long 0x0 "TCD1_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x1024++0x3 line.word 0x0 "TCD1_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD1_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x1028++0x3 line.long 0x0 "TCD1_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x1028++0xB line.long 0x0 "TCD1_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD1_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD1_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x1034++0x3 line.word 0x0 "TCD1_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD1_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x1036++0x1 line.word 0x0 "TCD1_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x1038++0x3 line.long 0x0 "TCD1_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x103C++0x3 line.word 0x0 "TCD1_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD1_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x103E++0x1 line.word 0x0 "TCD1_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x2000++0x13 line.long 0x0 "CH2_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH2_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH2_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH2_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH2_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x2020++0x3 line.long 0x0 "TCD2_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x2024++0x3 line.word 0x0 "TCD2_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD2_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x2028++0x3 line.long 0x0 "TCD2_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x2028++0xB line.long 0x0 "TCD2_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD2_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD2_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x2034++0x3 line.word 0x0 "TCD2_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD2_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x2036++0x1 line.word 0x0 "TCD2_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x2038++0x3 line.long 0x0 "TCD2_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x203C++0x3 line.word 0x0 "TCD2_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD2_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x203E++0x1 line.word 0x0 "TCD2_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x3000++0x13 line.long 0x0 "CH3_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH3_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH3_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH3_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH3_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x3020++0x3 line.long 0x0 "TCD3_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x3024++0x3 line.word 0x0 "TCD3_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD3_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x3028++0x3 line.long 0x0 "TCD3_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x3028++0xB line.long 0x0 "TCD3_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD3_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD3_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x3034++0x3 line.word 0x0 "TCD3_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD3_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x3036++0x1 line.word 0x0 "TCD3_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x3038++0x3 line.long 0x0 "TCD3_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x303C++0x3 line.word 0x0 "TCD3_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD3_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x303E++0x1 line.word 0x0 "TCD3_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x4000++0x13 line.long 0x0 "CH4_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH4_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH4_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH4_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH4_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x4020++0x3 line.long 0x0 "TCD4_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x4024++0x3 line.word 0x0 "TCD4_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD4_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x4028++0x3 line.long 0x0 "TCD4_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x4028++0xB line.long 0x0 "TCD4_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD4_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD4_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x4034++0x3 line.word 0x0 "TCD4_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD4_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x4036++0x1 line.word 0x0 "TCD4_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x4038++0x3 line.long 0x0 "TCD4_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x403C++0x3 line.word 0x0 "TCD4_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD4_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x403E++0x1 line.word 0x0 "TCD4_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x5000++0x13 line.long 0x0 "CH5_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH5_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH5_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH5_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH5_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x5020++0x3 line.long 0x0 "TCD5_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x5024++0x3 line.word 0x0 "TCD5_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD5_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x5028++0x3 line.long 0x0 "TCD5_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x5028++0xB line.long 0x0 "TCD5_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD5_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD5_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x5034++0x3 line.word 0x0 "TCD5_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD5_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x5036++0x1 line.word 0x0 "TCD5_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x5038++0x3 line.long 0x0 "TCD5_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x503C++0x3 line.word 0x0 "TCD5_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD5_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x503E++0x1 line.word 0x0 "TCD5_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x6000++0x13 line.long 0x0 "CH6_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH6_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH6_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH6_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH6_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x6020++0x3 line.long 0x0 "TCD6_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x6024++0x3 line.word 0x0 "TCD6_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD6_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x6028++0x3 line.long 0x0 "TCD6_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x6028++0xB line.long 0x0 "TCD6_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD6_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD6_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x6034++0x3 line.word 0x0 "TCD6_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD6_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x6036++0x1 line.word 0x0 "TCD6_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x6038++0x3 line.long 0x0 "TCD6_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x603C++0x3 line.word 0x0 "TCD6_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD6_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x603E++0x1 line.word 0x0 "TCD6_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x7000++0x13 line.long 0x0 "CH7_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH7_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH7_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH7_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH7_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x7020++0x3 line.long 0x0 "TCD7_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x7024++0x3 line.word 0x0 "TCD7_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD7_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x7028++0x3 line.long 0x0 "TCD7_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x7028++0xB line.long 0x0 "TCD7_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD7_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD7_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x7034++0x3 line.word 0x0 "TCD7_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD7_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x7036++0x1 line.word 0x0 "TCD7_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x7038++0x3 line.long 0x0 "TCD7_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x703C++0x3 line.word 0x0 "TCD7_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD7_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x703E++0x1 line.word 0x0 "TCD7_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x8000++0x13 line.long 0x0 "CH8_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH8_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH8_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH8_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH8_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x8020++0x3 line.long 0x0 "TCD8_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x8024++0x3 line.word 0x0 "TCD8_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD8_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x8028++0x3 line.long 0x0 "TCD8_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x8028++0xB line.long 0x0 "TCD8_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD8_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD8_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x8034++0x3 line.word 0x0 "TCD8_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD8_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x8036++0x1 line.word 0x0 "TCD8_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x8038++0x3 line.long 0x0 "TCD8_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x803C++0x3 line.word 0x0 "TCD8_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD8_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x803E++0x1 line.word 0x0 "TCD8_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x9000++0x13 line.long 0x0 "CH9_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH9_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH9_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH9_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH9_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x9020++0x3 line.long 0x0 "TCD9_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x9024++0x3 line.word 0x0 "TCD9_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD9_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x9028++0x3 line.long 0x0 "TCD9_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x9028++0xB line.long 0x0 "TCD9_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD9_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD9_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x9034++0x3 line.word 0x0 "TCD9_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD9_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x9036++0x1 line.word 0x0 "TCD9_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x9038++0x3 line.long 0x0 "TCD9_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x903C++0x3 line.word 0x0 "TCD9_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD9_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x903E++0x1 line.word 0x0 "TCD9_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0xA000++0x13 line.long 0x0 "CH10_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH10_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH10_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH10_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH10_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0xA020++0x3 line.long 0x0 "TCD10_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0xA024++0x3 line.word 0x0 "TCD10_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD10_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0xA028++0x3 line.long 0x0 "TCD10_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0xA028++0xB line.long 0x0 "TCD10_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD10_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD10_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0xA034++0x3 line.word 0x0 "TCD10_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD10_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0xA036++0x1 line.word 0x0 "TCD10_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0xA038++0x3 line.long 0x0 "TCD10_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0xA03C++0x3 line.word 0x0 "TCD10_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD10_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0xA03E++0x1 line.word 0x0 "TCD10_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0xB000++0x13 line.long 0x0 "CH11_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH11_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH11_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH11_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH11_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0xB020++0x3 line.long 0x0 "TCD11_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0xB024++0x3 line.word 0x0 "TCD11_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD11_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0xB028++0x3 line.long 0x0 "TCD11_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0xB028++0xB line.long 0x0 "TCD11_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD11_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD11_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0xB034++0x3 line.word 0x0 "TCD11_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD11_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0xB036++0x1 line.word 0x0 "TCD11_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0xB038++0x3 line.long 0x0 "TCD11_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0xB03C++0x3 line.word 0x0 "TCD11_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD11_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0xB03E++0x1 line.word 0x0 "TCD11_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0xC000++0x13 line.long 0x0 "CH12_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH12_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH12_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH12_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH12_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0xC020++0x3 line.long 0x0 "TCD12_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0xC024++0x3 line.word 0x0 "TCD12_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD12_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0xC028++0x3 line.long 0x0 "TCD12_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0xC028++0xB line.long 0x0 "TCD12_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD12_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD12_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0xC034++0x3 line.word 0x0 "TCD12_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD12_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0xC036++0x1 line.word 0x0 "TCD12_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0xC038++0x3 line.long 0x0 "TCD12_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0xC03C++0x3 line.word 0x0 "TCD12_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD12_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0xC03E++0x1 line.word 0x0 "TCD12_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0xD000++0x13 line.long 0x0 "CH13_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH13_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH13_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH13_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH13_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0xD020++0x3 line.long 0x0 "TCD13_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0xD024++0x3 line.word 0x0 "TCD13_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD13_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0xD028++0x3 line.long 0x0 "TCD13_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0xD028++0xB line.long 0x0 "TCD13_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD13_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD13_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0xD034++0x3 line.word 0x0 "TCD13_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD13_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0xD036++0x1 line.word 0x0 "TCD13_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0xD038++0x3 line.long 0x0 "TCD13_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0xD03C++0x3 line.word 0x0 "TCD13_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD13_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0xD03E++0x1 line.word 0x0 "TCD13_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0xE000++0x13 line.long 0x0 "CH14_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH14_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH14_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH14_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH14_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0xE020++0x3 line.long 0x0 "TCD14_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0xE024++0x3 line.word 0x0 "TCD14_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD14_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0xE028++0x3 line.long 0x0 "TCD14_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0xE028++0xB line.long 0x0 "TCD14_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD14_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD14_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0xE034++0x3 line.word 0x0 "TCD14_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD14_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0xE036++0x1 line.word 0x0 "TCD14_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0xE038++0x3 line.long 0x0 "TCD14_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0xE03C++0x3 line.word 0x0 "TCD14_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD14_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0xE03E++0x1 line.word 0x0 "TCD14_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0xF000++0x13 line.long 0x0 "CH15_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH15_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH15_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH15_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH15_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0xF020++0x3 line.long 0x0 "TCD15_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0xF024++0x3 line.word 0x0 "TCD15_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD15_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0xF028++0x3 line.long 0x0 "TCD15_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0xF028++0xB line.long 0x0 "TCD15_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD15_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD15_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0xF034++0x3 line.word 0x0 "TCD15_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD15_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0xF036++0x1 line.word 0x0 "TCD15_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0xF038++0x3 line.long 0x0 "TCD15_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0xF03C++0x3 line.word 0x0 "TCD15_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD15_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0xF03E++0x1 line.word 0x0 "TCD15_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x10000++0x13 line.long 0x0 "CH16_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH16_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH16_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH16_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH16_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x10020++0x3 line.long 0x0 "TCD16_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x10024++0x3 line.word 0x0 "TCD16_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD16_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x10028++0x3 line.long 0x0 "TCD16_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x10028++0xB line.long 0x0 "TCD16_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD16_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD16_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x10034++0x3 line.word 0x0 "TCD16_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD16_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x10036++0x1 line.word 0x0 "TCD16_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x10038++0x3 line.long 0x0 "TCD16_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1003C++0x3 line.word 0x0 "TCD16_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD16_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1003E++0x1 line.word 0x0 "TCD16_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x11000++0x13 line.long 0x0 "CH17_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH17_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH17_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH17_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH17_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x11020++0x3 line.long 0x0 "TCD17_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x11024++0x3 line.word 0x0 "TCD17_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD17_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x11028++0x3 line.long 0x0 "TCD17_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x11028++0xB line.long 0x0 "TCD17_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD17_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD17_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x11034++0x3 line.word 0x0 "TCD17_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD17_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x11036++0x1 line.word 0x0 "TCD17_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x11038++0x3 line.long 0x0 "TCD17_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1103C++0x3 line.word 0x0 "TCD17_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD17_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1103E++0x1 line.word 0x0 "TCD17_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x12000++0x13 line.long 0x0 "CH18_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH18_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH18_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH18_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH18_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x12020++0x3 line.long 0x0 "TCD18_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x12024++0x3 line.word 0x0 "TCD18_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD18_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x12028++0x3 line.long 0x0 "TCD18_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x12028++0xB line.long 0x0 "TCD18_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD18_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD18_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x12034++0x3 line.word 0x0 "TCD18_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD18_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x12036++0x1 line.word 0x0 "TCD18_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x12038++0x3 line.long 0x0 "TCD18_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1203C++0x3 line.word 0x0 "TCD18_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD18_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1203E++0x1 line.word 0x0 "TCD18_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x13000++0x13 line.long 0x0 "CH19_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH19_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH19_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH19_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH19_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x13020++0x3 line.long 0x0 "TCD19_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x13024++0x3 line.word 0x0 "TCD19_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD19_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x13028++0x3 line.long 0x0 "TCD19_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x13028++0xB line.long 0x0 "TCD19_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD19_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD19_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x13034++0x3 line.word 0x0 "TCD19_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD19_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x13036++0x1 line.word 0x0 "TCD19_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x13038++0x3 line.long 0x0 "TCD19_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1303C++0x3 line.word 0x0 "TCD19_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD19_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1303E++0x1 line.word 0x0 "TCD19_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x14000++0x13 line.long 0x0 "CH20_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH20_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH20_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH20_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH20_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x14020++0x3 line.long 0x0 "TCD20_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x14024++0x3 line.word 0x0 "TCD20_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD20_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x14028++0x3 line.long 0x0 "TCD20_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x14028++0xB line.long 0x0 "TCD20_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD20_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD20_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x14034++0x3 line.word 0x0 "TCD20_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD20_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x14036++0x1 line.word 0x0 "TCD20_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x14038++0x3 line.long 0x0 "TCD20_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1403C++0x3 line.word 0x0 "TCD20_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD20_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1403E++0x1 line.word 0x0 "TCD20_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x15000++0x13 line.long 0x0 "CH21_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH21_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH21_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH21_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH21_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x15020++0x3 line.long 0x0 "TCD21_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x15024++0x3 line.word 0x0 "TCD21_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD21_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x15028++0x3 line.long 0x0 "TCD21_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x15028++0xB line.long 0x0 "TCD21_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD21_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD21_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x15034++0x3 line.word 0x0 "TCD21_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD21_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x15036++0x1 line.word 0x0 "TCD21_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x15038++0x3 line.long 0x0 "TCD21_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1503C++0x3 line.word 0x0 "TCD21_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD21_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1503E++0x1 line.word 0x0 "TCD21_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x16000++0x13 line.long 0x0 "CH22_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH22_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH22_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH22_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH22_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x16020++0x3 line.long 0x0 "TCD22_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x16024++0x3 line.word 0x0 "TCD22_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD22_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x16028++0x3 line.long 0x0 "TCD22_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x16028++0xB line.long 0x0 "TCD22_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD22_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD22_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x16034++0x3 line.word 0x0 "TCD22_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD22_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x16036++0x1 line.word 0x0 "TCD22_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x16038++0x3 line.long 0x0 "TCD22_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1603C++0x3 line.word 0x0 "TCD22_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD22_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1603E++0x1 line.word 0x0 "TCD22_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" group.long 0x17000++0x13 line.long 0x0 "CH23_CSR,Channel Control and Status" rbitfld.long 0x0 31. "ACTIVE,Channel Active" "0,1" eventfld.long 0x0 30. "DONE,Channel Done" "0,1" newline bitfld.long 0x0 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled" bitfld.long 0x0 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does not..,1: Assertion of error signal for corresponding.." newline bitfld.long 0x0 1. "EARQ,Enable Asynchronous DMA Request In Stop Mode For Channel" "0: Disable asynchronous DMA request for the channel,1: Enable asynchronous DMA request for the channel" bitfld.long 0x0 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.." line.long 0x4 "CH23_ES,Channel Error Status" eventfld.long 0x4 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred" rbitfld.long 0x4 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.." newline rbitfld.long 0x4 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.." rbitfld.long 0x4 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source read" newline rbitfld.long 0x4 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on destination.." line.long 0x8 "CH23_INT,Channel Interrupt Status" eventfld.long 0x8 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel active" line.long 0xC "CH23_SBR,Channel System Bus" bitfld.long 0xC 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled" newline rbitfld.long 0xC 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers" hexmask.long.byte 0xC 0.--5. 1. "MID,Master ID" line.long 0x10 "CH23_PRI,Channel Priority" bitfld.long 0x10 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a higher-priority..,1: Channel can be temporarily suspended by a.." bitfld.long 0x10 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.." newline bitfld.long 0x10 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7" group.long 0x17020++0x3 line.long 0x0 "TCD23_SADDR,TCD Source Address" hexmask.long 0x0 0.--31. 1. "SADDR,Source Address" group.word 0x17024++0x3 line.word 0x0 "TCD23_SOFF,TCD Signed Source Address Offset" hexmask.word 0x0 0.--15. 1. "SOFF,Source Address Signed Offset" line.word 0x2 "TCD23_ATTR,TCD Transfer Attributes" hexmask.word.byte 0x2 11.--15. 1. "SMOD,Source Address Modulo" bitfld.word 0x2 8.--10. "SSIZE,Source Data Transfer Size" "0: 8-bit,1: 16-bit,2: 32-bit,3: 64-bit,4: 16-byte,5: 32-byte,6: 64-byte,?" newline hexmask.word.byte 0x2 3.--7. 1. "DMOD,Destination Address Modulo" bitfld.word 0x2 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7" group.long 0x17028++0x3 line.long 0x0 "TCD23_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long 0x0 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" group.long 0x17028++0xB line.long 0x0 "TCD23_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets" bitfld.long 0x0 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR" bitfld.long 0x0 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR" newline hexmask.long.tbyte 0x0 10.--29. 1. "MLOFF,Minor Loop Offset" hexmask.long.word 0x0 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request" line.long 0x4 "TCD23_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address" hexmask.long 0x4 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address" line.long 0x8 "TCD23_DADDR,TCD Destination Address" hexmask.long 0x8 0.--31. 1. "DADDR,Destination Address" group.word 0x17034++0x3 line.word 0x0 "TCD23_DOFF,TCD Signed Destination Address Offset" hexmask.word 0x0 0.--15. 1. "DOFF,Destination Address Signed Offset" line.word 0x2 "TCD23_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "CITER,Current Major Iteration Count" group.word 0x17036++0x1 line.word 0x0 "TCD23_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Minor Loop Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "CITER,Current Major Iteration Count" group.long 0x17038++0x3 line.long 0x0 "TCD23_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address" hexmask.long 0x0 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address" group.word 0x1703C++0x3 line.word 0x0 "TCD23_CSR,TCD Control and Status" bitfld.word 0x0 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W" hexmask.word.byte 0x0 8.--12. 1. "MAJORLINKCH,Major Loop Link Channel Number" newline bitfld.word 0x0 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to system..,1: Ability to store destination address to system.." bitfld.word 0x0 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" newline bitfld.word 0x0 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies scatter/gather.." bitfld.word 0x0 3. "DREQ,Disable Request" "0: No operation,1: Clear the ERQ field to 0 upon major loop.." newline bitfld.word 0x0 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled" bitfld.word 0x0 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled" newline bitfld.word 0x0 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.." line.word 0x2 "TCD23_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)" bitfld.word 0x2 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word 0x2 0.--14. 1. "BITER,Starting Major Iteration Count" group.word 0x1703E++0x1 line.word 0x0 "TCD23_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)" bitfld.word 0x0 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled" hexmask.word.byte 0x0 9.--13. 1. "LINKCH,Link Channel Number" newline hexmask.word 0x0 0.--8. 1. "BITER,Starting Major Iteration Count" tree.end tree.end tree "EIM (Error Injection Module)" base ad:0x0 tree "EIM_0" base ad:0x4050C000 group.long 0x0++0x7 line.long 0x0 "EIMCR,Error Injection Module Configuration Register" bitfld.long 0x0 0. "GEIEN,Global Error Injection Enable" "0: Disabled,1: Enabled" line.long 0x4 "EICHEN,Error Injection Channel Enable register" bitfld.long 0x4 31. "EICH0EN,Error Injection Channel 0 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 30. "EICH1EN,Error Injection Channel 1 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 29. "EICH2EN,Error Injection Channel 2 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 28. "EICH3EN,Error Injection Channel 3 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 27. "EICH4EN,Error Injection Channel 4 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 26. "EICH5EN,Error Injection Channel 5 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 25. "EICH6EN,Error Injection Channel 6 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 24. "EICH7EN,Error Injection Channel 7 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 23. "EICH8EN,Error Injection Channel 8 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 22. "EICH9EN,Error Injection Channel 9 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 21. "EICH10EN,Error Injection Channel 10 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 20. "EICH11EN,Error Injection Channel 11 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 19. "EICH12EN,Error Injection Channel 12 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 18. "EICH13EN,Error Injection Channel 13 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 17. "EICH14EN,Error Injection Channel 14 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 16. "EICH15EN,Error Injection Channel 15 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 15. "EICH16EN,Error Injection Channel 16 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." group.long 0x100++0xB line.long 0x0 "EICHD0_WORD0,Error Injection Channel Descriptor 0. Word0" hexmask.long.word 0x0 18.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD0_WORD1,Error Injection Channel Descriptor 0. Word1" hexmask.long.word 0x4 0.--11. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD0_WORD2,Error Injection Channel Descriptor 0. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x140++0x13 line.long 0x0 "EICHD1_WORD0,Error Injection Channel Descriptor 1. Word0" hexmask.long.word 0x0 16.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD1_WORD1,Error Injection Channel Descriptor 1. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD1_WORD2,Error Injection Channel Descriptor 1. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD1_WORD3,Error Injection Channel Descriptor 1. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD1_WORD4,Error Injection Channel Descriptor 1. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" group.long 0x180++0x13 line.long 0x0 "EICHD2_WORD0,Error Injection Channel Descriptor 2. Word0" hexmask.long 0x0 4.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD2_WORD1,Error Injection Channel Descriptor 2. Word1" hexmask.long.byte 0x4 0.--7. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD2_WORD2,Error Injection Channel Descriptor 2. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD2_WORD3,Error Injection Channel Descriptor 2. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD2_WORD4,Error Injection Channel Descriptor 2. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" group.long 0x1C0++0x13 line.long 0x0 "EICHD3_WORD0,Error Injection Channel Descriptor 3. Word0" hexmask.long 0x0 4.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD3_WORD1,Error Injection Channel Descriptor 3. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD3_WORD2,Error Injection Channel Descriptor 3. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD3_WORD3,Error Injection Channel Descriptor 3. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD3_WORD4,Error Injection Channel Descriptor 3. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" group.long 0x200++0x13 line.long 0x0 "EICHD4_WORD0,Error Injection Channel Descriptor 4. Word0" hexmask.long 0x0 4.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD4_WORD1,Error Injection Channel Descriptor 4. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD4_WORD2,Error Injection Channel Descriptor 4. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD4_WORD3,Error Injection Channel Descriptor 4. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD4_WORD4,Error Injection Channel Descriptor 4. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" group.long 0x240++0xB line.long 0x0 "EICHD5_WORD0,Error Injection Channel Descriptor 5. Word0" hexmask.long.word 0x0 18.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD5_WORD1,Error Injection Channel Descriptor 5. Word1" hexmask.long.word 0x4 0.--11. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD5_WORD2,Error Injection Channel Descriptor 5. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x280++0x13 line.long 0x0 "EICHD6_WORD0,Error Injection Channel Descriptor 6. Word0" hexmask.long.word 0x0 16.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD6_WORD1,Error Injection Channel Descriptor 6. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD6_WORD2,Error Injection Channel Descriptor 6. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD6_WORD3,Error Injection Channel Descriptor 6. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD6_WORD4,Error Injection Channel Descriptor 6. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" group.long 0x2C0++0x13 line.long 0x0 "EICHD7_WORD0,Error Injection Channel Descriptor 7. Word0" hexmask.long 0x0 4.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD7_WORD1,Error Injection Channel Descriptor 7. Word1" hexmask.long.byte 0x4 0.--7. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD7_WORD2,Error Injection Channel Descriptor 7. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD7_WORD3,Error Injection Channel Descriptor 7. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD7_WORD4,Error Injection Channel Descriptor 7. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" group.long 0x300++0x13 line.long 0x0 "EICHD8_WORD0,Error Injection Channel Descriptor 8. Word0" hexmask.long 0x0 4.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD8_WORD1,Error Injection Channel Descriptor 8. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD8_WORD2,Error Injection Channel Descriptor 8. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD8_WORD3,Error Injection Channel Descriptor 8. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD8_WORD4,Error Injection Channel Descriptor 8. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" group.long 0x340++0x13 line.long 0x0 "EICHD9_WORD0,Error Injection Channel Descriptor 9. Word0" hexmask.long 0x0 4.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD9_WORD1,Error Injection Channel Descriptor 9. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD9_WORD2,Error Injection Channel Descriptor 9. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD9_WORD3,Error Injection Channel Descriptor 9. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD9_WORD4,Error Injection Channel Descriptor 9. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" group.long 0x380++0xB line.long 0x0 "EICHD10_WORD0,Error Injection Channel Descriptor 10. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD10_WORD1,Error Injection Channel Descriptor 10. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD10_WORD2,Error Injection Channel Descriptor 10. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x3C0++0x7 line.long 0x0 "EICHD11_WORD0,Error Injection Channel Descriptor 11. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD11_WORD1,Error Injection Channel Descriptor 11. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x400++0x7 line.long 0x0 "EICHD12_WORD0,Error Injection Channel Descriptor 12. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD12_WORD1,Error Injection Channel Descriptor 12. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x440++0xB line.long 0x0 "EICHD13_WORD0,Error Injection Channel Descriptor 13. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD13_WORD1,Error Injection Channel Descriptor 13. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD13_WORD2,Error Injection Channel Descriptor 13. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x480++0x7 line.long 0x0 "EICHD14_WORD0,Error Injection Channel Descriptor 14. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD14_WORD1,Error Injection Channel Descriptor 14. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x4C0++0x7 line.long 0x0 "EICHD15_WORD0,Error Injection Channel Descriptor 15. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD15_WORD1,Error Injection Channel Descriptor 15. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x504++0x3 line.long 0x0 "EICHD16_WORD1,Error Injection Channel Descriptor 16. Word1" hexmask.long 0x0 0.--29. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" tree.end tree "EIM_1" base ad:0x40510000 group.long 0x0++0x7 line.long 0x0 "EIMCR,Error Injection Module Configuration Register" bitfld.long 0x0 0. "GEIEN,Global Error Injection Enable" "0: Disabled,1: Enabled" line.long 0x4 "EICHEN,Error Injection Channel Enable register" bitfld.long 0x4 31. "EICH0EN,Error Injection Channel 0 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 30. "EICH1EN,Error Injection Channel 1 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 29. "EICH2EN,Error Injection Channel 2 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 28. "EICH3EN,Error Injection Channel 3 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 27. "EICH4EN,Error Injection Channel 4 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 26. "EICH5EN,Error Injection Channel 5 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 25. "EICH6EN,Error Injection Channel 6 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 24. "EICH7EN,Error Injection Channel 7 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 23. "EICH8EN,Error Injection Channel 8 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 22. "EICH9EN,Error Injection Channel 9 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 21. "EICH10EN,Error Injection Channel 10 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 20. "EICH11EN,Error Injection Channel 11 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 19. "EICH12EN,Error Injection Channel 12 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 18. "EICH13EN,Error Injection Channel 13 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 17. "EICH14EN,Error Injection Channel 14 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 16. "EICH15EN,Error Injection Channel 15 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 15. "EICH16EN,Error Injection Channel 16 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." group.long 0x100++0xB line.long 0x0 "EICHD0_WORD0,Error Injection Channel Descriptor 0. Word0" hexmask.long.word 0x0 18.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD0_WORD1,Error Injection Channel Descriptor 0. Word1" hexmask.long.word 0x4 0.--11. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD0_WORD2,Error Injection Channel Descriptor 0. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x140++0x13 line.long 0x0 "EICHD1_WORD0,Error Injection Channel Descriptor 1. Word0" hexmask.long.word 0x0 16.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD1_WORD1,Error Injection Channel Descriptor 1. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD1_WORD2,Error Injection Channel Descriptor 1. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD1_WORD3,Error Injection Channel Descriptor 1. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD1_WORD4,Error Injection Channel Descriptor 1. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" group.long 0x180++0x13 line.long 0x0 "EICHD2_WORD0,Error Injection Channel Descriptor 2. Word0" hexmask.long 0x0 4.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD2_WORD1,Error Injection Channel Descriptor 2. Word1" hexmask.long.byte 0x4 0.--7. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD2_WORD2,Error Injection Channel Descriptor 2. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD2_WORD3,Error Injection Channel Descriptor 2. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD2_WORD4,Error Injection Channel Descriptor 2. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" group.long 0x1C0++0x13 line.long 0x0 "EICHD3_WORD0,Error Injection Channel Descriptor 3. Word0" hexmask.long 0x0 4.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD3_WORD1,Error Injection Channel Descriptor 3. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD3_WORD2,Error Injection Channel Descriptor 3. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD3_WORD3,Error Injection Channel Descriptor 3. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD3_WORD4,Error Injection Channel Descriptor 3. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" group.long 0x200++0x13 line.long 0x0 "EICHD4_WORD0,Error Injection Channel Descriptor 4. Word0" hexmask.long 0x0 4.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD4_WORD1,Error Injection Channel Descriptor 4. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD4_WORD2,Error Injection Channel Descriptor 4. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD4_WORD3,Error Injection Channel Descriptor 4. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD4_WORD4,Error Injection Channel Descriptor 4. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" group.long 0x240++0xB line.long 0x0 "EICHD5_WORD0,Error Injection Channel Descriptor 5. Word0" hexmask.long.word 0x0 18.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD5_WORD1,Error Injection Channel Descriptor 5. Word1" hexmask.long.word 0x4 0.--11. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD5_WORD2,Error Injection Channel Descriptor 5. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x280++0x13 line.long 0x0 "EICHD6_WORD0,Error Injection Channel Descriptor 6. Word0" hexmask.long.word 0x0 16.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD6_WORD1,Error Injection Channel Descriptor 6. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD6_WORD2,Error Injection Channel Descriptor 6. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD6_WORD3,Error Injection Channel Descriptor 6. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD6_WORD4,Error Injection Channel Descriptor 6. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" group.long 0x2C0++0x13 line.long 0x0 "EICHD7_WORD0,Error Injection Channel Descriptor 7. Word0" hexmask.long 0x0 4.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD7_WORD1,Error Injection Channel Descriptor 7. Word1" hexmask.long.byte 0x4 0.--7. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD7_WORD2,Error Injection Channel Descriptor 7. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD7_WORD3,Error Injection Channel Descriptor 7. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD7_WORD4,Error Injection Channel Descriptor 7. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" group.long 0x300++0x13 line.long 0x0 "EICHD8_WORD0,Error Injection Channel Descriptor 8. Word0" hexmask.long 0x0 4.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD8_WORD1,Error Injection Channel Descriptor 8. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD8_WORD2,Error Injection Channel Descriptor 8. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD8_WORD3,Error Injection Channel Descriptor 8. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD8_WORD4,Error Injection Channel Descriptor 8. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" group.long 0x340++0x13 line.long 0x0 "EICHD9_WORD0,Error Injection Channel Descriptor 9. Word0" hexmask.long 0x0 4.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD9_WORD1,Error Injection Channel Descriptor 9. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD9_WORD2,Error Injection Channel Descriptor 9. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0xC "EICHD9_WORD3,Error Injection Channel Descriptor 9. Word3" hexmask.long 0xC 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0x10 "EICHD9_WORD4,Error Injection Channel Descriptor 9. Word4" hexmask.long 0x10 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" group.long 0x380++0xB line.long 0x0 "EICHD10_WORD0,Error Injection Channel Descriptor 10. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD10_WORD1,Error Injection Channel Descriptor 10. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD10_WORD2,Error Injection Channel Descriptor 10. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x3C0++0x7 line.long 0x0 "EICHD11_WORD0,Error Injection Channel Descriptor 11. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD11_WORD1,Error Injection Channel Descriptor 11. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x400++0x7 line.long 0x0 "EICHD12_WORD0,Error Injection Channel Descriptor 12. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD12_WORD1,Error Injection Channel Descriptor 12. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x440++0xB line.long 0x0 "EICHD13_WORD0,Error Injection Channel Descriptor 13. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD13_WORD1,Error Injection Channel Descriptor 13. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD13_WORD2,Error Injection Channel Descriptor 13. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x480++0x7 line.long 0x0 "EICHD14_WORD0,Error Injection Channel Descriptor 14. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD14_WORD1,Error Injection Channel Descriptor 14. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x4C0++0x7 line.long 0x0 "EICHD15_WORD0,Error Injection Channel Descriptor 15. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD15_WORD1,Error Injection Channel Descriptor 15. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x504++0x3 line.long 0x0 "EICHD16_WORD1,Error Injection Channel Descriptor 16. Word1" hexmask.long 0x0 0.--29. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" tree.end tree "EIM_2" base ad:0x40514000 group.long 0x0++0x7 line.long 0x0 "EIMCR,Error Injection Module Configuration Register" bitfld.long 0x0 0. "GEIEN,Global Error Injection Enable" "0: Disabled,1: Enabled" line.long 0x4 "EICHEN,Error Injection Channel Enable register" bitfld.long 0x4 31. "EICH0EN,Error Injection Channel 0 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 30. "EICH1EN,Error Injection Channel 1 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 29. "EICH2EN,Error Injection Channel 2 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 28. "EICH3EN,Error Injection Channel 3 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 27. "EICH4EN,Error Injection Channel 4 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 26. "EICH5EN,Error Injection Channel 5 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 24. "EICH7EN,Error Injection Channel 7 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 23. "EICH8EN,Error Injection Channel 8 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 22. "EICH9EN,Error Injection Channel 9 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 21. "EICH10EN,Error Injection Channel 10 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 20. "EICH11EN,Error Injection Channel 11 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 19. "EICH12EN,Error Injection Channel 12 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 18. "EICH13EN,Error Injection Channel 13 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 17. "EICH14EN,Error Injection Channel 14 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 16. "EICH15EN,Error Injection Channel 15 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 15. "EICH16EN,Error Injection Channel 16 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 14. "EICH17EN,Error Injection Channel 17 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 13. "EICH18EN,Error Injection Channel 18 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 12. "EICH19EN,Error Injection Channel 19 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 11. "EICH20EN,Error Injection Channel 20 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 10. "EICH21EN,Error Injection Channel 21 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 9. "EICH22EN,Error Injection Channel 22 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 8. "EICH23EN,Error Injection Channel 23 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 7. "EICH24EN,Error Injection Channel 24 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 6. "EICH25EN,Error Injection Channel 25 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 5. "EICH26EN,Error Injection Channel 26 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 4. "EICH27EN,Error Injection Channel 27 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 3. "EICH28EN,Error Injection Channel 28 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 2. "EICH29EN,Error Injection Channel 29 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 1. "EICH30EN,Error Injection Channel 30 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 0. "EICH31EN,Error Injection Channel 31 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." group.long 0x100++0xB line.long 0x0 "EICHD0_WORD0,Error Injection Channel Descriptor 0. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD0_WORD1,Error Injection Channel Descriptor 0. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD0_WORD2,Error Injection Channel Descriptor 0. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x140++0xB line.long 0x0 "EICHD1_WORD0,Error Injection Channel Descriptor 1. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD1_WORD1,Error Injection Channel Descriptor 1. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD1_WORD2,Error Injection Channel Descriptor 1. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x180++0xB line.long 0x0 "EICHD2_WORD0,Error Injection Channel Descriptor 2. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD2_WORD1,Error Injection Channel Descriptor 2. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD2_WORD2,Error Injection Channel Descriptor 2. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x1C0++0xB line.long 0x0 "EICHD3_WORD0,Error Injection Channel Descriptor 3. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD3_WORD1,Error Injection Channel Descriptor 3. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD3_WORD2,Error Injection Channel Descriptor 3. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x204++0x7 line.long 0x0 "EICHD4_WORD1,Error Injection Channel Descriptor 4. Word1" hexmask.long 0x0 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD4_WORD2,Error Injection Channel Descriptor 4. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x244++0x7 line.long 0x0 "EICHD5_WORD1,Error Injection Channel Descriptor 5. Word1" hexmask.long 0x0 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD5_WORD2,Error Injection Channel Descriptor 5. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x2C4++0x7 line.long 0x0 "EICHD7_WORD1,Error Injection Channel Descriptor 7. Word1" hexmask.long 0x0 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD7_WORD2,Error Injection Channel Descriptor 7. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x304++0x7 line.long 0x0 "EICHD8_WORD1,Error Injection Channel Descriptor 8. Word1" hexmask.long 0x0 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD8_WORD2,Error Injection Channel Descriptor 8. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x344++0x7 line.long 0x0 "EICHD9_WORD1,Error Injection Channel Descriptor 9. Word1" hexmask.long 0x0 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD9_WORD2,Error Injection Channel Descriptor 9. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x384++0x7 line.long 0x0 "EICHD10_WORD1,Error Injection Channel Descriptor 10. Word1" hexmask.long 0x0 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD10_WORD2,Error Injection Channel Descriptor 10. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x3C4++0x7 line.long 0x0 "EICHD11_WORD1,Error Injection Channel Descriptor 11. Word1" hexmask.long 0x0 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD11_WORD2,Error Injection Channel Descriptor 11. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x404++0x7 line.long 0x0 "EICHD12_WORD1,Error Injection Channel Descriptor 12. Word1" hexmask.long 0x0 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD12_WORD2,Error Injection Channel Descriptor 12. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x444++0x7 line.long 0x0 "EICHD13_WORD1,Error Injection Channel Descriptor 13. Word1" hexmask.long 0x0 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD13_WORD2,Error Injection Channel Descriptor 13. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x484++0x7 line.long 0x0 "EICHD14_WORD1,Error Injection Channel Descriptor 14. Word1" hexmask.long 0x0 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD14_WORD2,Error Injection Channel Descriptor 14. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x4C4++0x7 line.long 0x0 "EICHD15_WORD1,Error Injection Channel Descriptor 15. Word1" hexmask.long 0x0 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD15_WORD2,Error Injection Channel Descriptor 15. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x504++0x7 line.long 0x0 "EICHD16_WORD1,Error Injection Channel Descriptor 16. Word1" hexmask.long 0x0 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD16_WORD2,Error Injection Channel Descriptor 16. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x544++0x7 line.long 0x0 "EICHD17_WORD1,Error Injection Channel Descriptor 17. Word1" hexmask.long 0x0 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD17_WORD2,Error Injection Channel Descriptor 17. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x584++0x7 line.long 0x0 "EICHD18_WORD1,Error Injection Channel Descriptor 18. Word1" hexmask.long 0x0 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD18_WORD2,Error Injection Channel Descriptor 18. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x5C4++0x7 line.long 0x0 "EICHD19_WORD1,Error Injection Channel Descriptor 19. Word1" hexmask.long 0x0 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD19_WORD2,Error Injection Channel Descriptor 19. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x604++0x7 line.long 0x0 "EICHD20_WORD1,Error Injection Channel Descriptor 20. Word1" hexmask.long 0x0 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD20_WORD2,Error Injection Channel Descriptor 20. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x644++0x7 line.long 0x0 "EICHD21_WORD1,Error Injection Channel Descriptor 21. Word1" hexmask.long 0x0 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD21_WORD2,Error Injection Channel Descriptor 21. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x684++0x17 line.long 0x0 "EICHD22_WORD1,Error Injection Channel Descriptor 22. Word1" hexmask.long 0x0 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD22_WORD2,Error Injection Channel Descriptor 22. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD22_WORD3,Error Injection Channel Descriptor 22. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0xC "EICHD22_WORD4,Error Injection Channel Descriptor 22. Word4" hexmask.long 0xC 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x10 "EICHD22_WORD5,Error Injection Channel Descriptor 22. Word5" hexmask.long 0x10 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x14 "EICHD22_WORD6,Error Injection Channel Descriptor 22. Word6" hexmask.long 0x14 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" group.long 0x6C4++0x17 line.long 0x0 "EICHD23_WORD1,Error Injection Channel Descriptor 23. Word1" hexmask.long 0x0 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD23_WORD2,Error Injection Channel Descriptor 23. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD23_WORD3,Error Injection Channel Descriptor 23. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0xC "EICHD23_WORD4,Error Injection Channel Descriptor 23. Word4" hexmask.long 0xC 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x10 "EICHD23_WORD5,Error Injection Channel Descriptor 23. Word5" hexmask.long 0x10 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x14 "EICHD23_WORD6,Error Injection Channel Descriptor 23. Word6" hexmask.long 0x14 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" group.long 0x704++0x17 line.long 0x0 "EICHD24_WORD1,Error Injection Channel Descriptor 24. Word1" hexmask.long 0x0 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD24_WORD2,Error Injection Channel Descriptor 24. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD24_WORD3,Error Injection Channel Descriptor 24. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0xC "EICHD24_WORD4,Error Injection Channel Descriptor 24. Word4" hexmask.long 0xC 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x10 "EICHD24_WORD5,Error Injection Channel Descriptor 24. Word5" hexmask.long 0x10 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x14 "EICHD24_WORD6,Error Injection Channel Descriptor 24. Word6" hexmask.long 0x14 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" group.long 0x744++0x17 line.long 0x0 "EICHD25_WORD1,Error Injection Channel Descriptor 25. Word1" hexmask.long 0x0 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD25_WORD2,Error Injection Channel Descriptor 25. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" line.long 0x8 "EICHD25_WORD3,Error Injection Channel Descriptor 25. Word3" hexmask.long 0x8 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11" line.long 0xC "EICHD25_WORD4,Error Injection Channel Descriptor 25. Word4" hexmask.long 0xC 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15" line.long 0x10 "EICHD25_WORD5,Error Injection Channel Descriptor 25. Word5" hexmask.long 0x10 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19" line.long 0x14 "EICHD25_WORD6,Error Injection Channel Descriptor 25. Word6" hexmask.long 0x14 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23" group.long 0x784++0x3 line.long 0x0 "EICHD26_WORD1,Error Injection Channel Descriptor 26. Word1" hexmask.long.word 0x0 0.--13. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x7C4++0x3 line.long 0x0 "EICHD27_WORD1,Error Injection Channel Descriptor 27. Word1" hexmask.long.byte 0x0 0.--7. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x804++0x3 line.long 0x0 "EICHD28_WORD1,Error Injection Channel Descriptor 28. Word1" hexmask.long.word 0x0 0.--13. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x844++0x3 line.long 0x0 "EICHD29_WORD1,Error Injection Channel Descriptor 29. Word1" hexmask.long 0x0 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x884++0x3 line.long 0x0 "EICHD30_WORD1,Error Injection Channel Descriptor 30. Word1" hexmask.long.tbyte 0x0 0.--17. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" group.long 0x8C4++0x3 line.long 0x0 "EICHD31_WORD1,Error Injection Channel Descriptor 31. Word1" hexmask.long.word 0x0 0.--15. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" tree.end tree "EIM_3" base ad:0x40518000 group.long 0x0++0x7 line.long 0x0 "EIMCR,Error Injection Module Configuration Register" bitfld.long 0x0 0. "GEIEN,Global Error Injection Enable" "0: Disabled,1: Enabled" line.long 0x4 "EICHEN,Error Injection Channel Enable register" bitfld.long 0x4 31. "EICH0EN,Error Injection Channel 0 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 30. "EICH1EN,Error Injection Channel 1 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 29. "EICH2EN,Error Injection Channel 2 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." bitfld.long 0x4 28. "EICH3EN,Error Injection Channel 3 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." newline bitfld.long 0x4 27. "EICH4EN,Error Injection Channel 4 Enable" "0: Error injection is disabled on Error Injection..,1: Error injection is enabled on Error Injection.." group.long 0x104++0x7 line.long 0x0 "EICHD0_WORD1,Error Injection Channel Descriptor 0. Word1" hexmask.long 0x0 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD0_WORD2,Error Injection Channel Descriptor 0. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x144++0x7 line.long 0x0 "EICHD1_WORD1,Error Injection Channel Descriptor 1. Word1" hexmask.long 0x0 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD1_WORD2,Error Injection Channel Descriptor 1. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x180++0xB line.long 0x0 "EICHD2_WORD0,Error Injection Channel Descriptor 2. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD2_WORD1,Error Injection Channel Descriptor 2. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD2_WORD2,Error Injection Channel Descriptor 2. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x1C0++0xB line.long 0x0 "EICHD3_WORD0,Error Injection Channel Descriptor 3. Word0" hexmask.long.byte 0x0 24.--31. 1. "CHKBIT_MASK,Checkbit Mask" line.long 0x4 "EICHD3_WORD1,Error Injection Channel Descriptor 3. Word1" hexmask.long 0x4 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x8 "EICHD3_WORD2,Error Injection Channel Descriptor 3. Word2" hexmask.long 0x8 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" group.long 0x204++0x7 line.long 0x0 "EICHD4_WORD1,Error Injection Channel Descriptor 4. Word1" hexmask.long 0x0 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3" line.long 0x4 "EICHD4_WORD2,Error Injection Channel Descriptor 4. Word2" hexmask.long 0x4 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7" tree.end tree.end tree "EMIOS (Enhanced Modular IO Subsystem)" base ad:0x0 tree "EMIOS_0" base ad:0x40088000 group.long 0x0++0x3 line.long 0x0 "MCR,Module Configuration" bitfld.long 0x0 30. "MDIS,Module Disable" "0: Enable,1: Disable" bitfld.long 0x0 29. "FRZ,Freeze" "0: Exit Freeze state,1: Enter Freeze state" newline bitfld.long 0x0 28. "GTBE,Global Timebase Enable" "0: Deassert GTBE_OUT,1: Assert GTBE_OUT" bitfld.long 0x0 26. "GPREN,Global Prescaler Enable" "0: Disable,1: Enable" newline hexmask.long.byte 0x0 8.--15. 1. "GPRE,Global Prescaler" rgroup.long 0x4++0x3 line.long 0x0 "GFLAG,Global Flag" bitfld.long 0x0 23. "F23,Mirror of UC 23 FLAG" "0,1" bitfld.long 0x0 22. "F22,Mirror of UC 22 FLAG" "0,1" newline bitfld.long 0x0 21. "F21,Mirror of UC 21 FLAG" "0,1" bitfld.long 0x0 20. "F20,Mirror of UC 20 FLAG" "0,1" newline bitfld.long 0x0 19. "F19,Mirror of UC 19 FLAG" "0,1" bitfld.long 0x0 18. "F18,Mirror of UC 18 FLAG" "0,1" newline bitfld.long 0x0 17. "F17,Mirror of UC 17 FLAG" "0,1" bitfld.long 0x0 16. "F16,Mirror of UC 16 FLAG" "0,1" newline bitfld.long 0x0 15. "F15,Mirror of UC 15 FLAG" "0,1" bitfld.long 0x0 14. "F14,Mirror of UC 14 FLAG" "0,1" newline bitfld.long 0x0 13. "F13,Mirror of UC 13 FLAG" "0,1" bitfld.long 0x0 12. "F12,Mirror of UC 12 FLAG" "0,1" newline bitfld.long 0x0 11. "F11,Mirror of UC 11 FLAG" "0,1" bitfld.long 0x0 10. "F10,Mirror of UC 10 FLAG" "0,1" newline bitfld.long 0x0 9. "F9,Mirror of UC 9 FLAG" "0,1" bitfld.long 0x0 8. "F8,Mirror of UC 8 FLAG" "0,1" newline bitfld.long 0x0 7. "F7,Mirror of UC 7 FLAG" "0,1" bitfld.long 0x0 6. "F6,Mirror of UC 6 FLAG" "0,1" newline bitfld.long 0x0 5. "F5,Mirror of UC 5 FLAG" "0,1" bitfld.long 0x0 4. "F4,Mirror of UC 4 FLAG" "0,1" newline bitfld.long 0x0 3. "F3,Mirror of UC 3 FLAG" "0,1" bitfld.long 0x0 2. "F2,Mirror of UC 2 FLAG" "0,1" newline bitfld.long 0x0 1. "F1,Mirror of UC 1 FLAG" "0,1" bitfld.long 0x0 0. "F0,Mirror of UC 0 FLAG" "0,1" group.long 0x8++0x7 line.long 0x0 "OUDIS,Output Update Disable" bitfld.long 0x0 23. "OU23,Channel 23 Output Update Disable" "0: Enable,1: Disable" bitfld.long 0x0 22. "OU22,Channel 22 Output Update Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 21. "OU21,Channel 21 Output Update Disable" "0: Enable,1: Disable" bitfld.long 0x0 20. "OU20,Channel 20 Output Update Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 19. "OU19,Channel 19 Output Update Disable" "0: Enable,1: Disable" bitfld.long 0x0 18. "OU18,Channel 18 Output Update Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 17. "OU17,Channel 17 Output Update Disable" "0: Enable,1: Disable" bitfld.long 0x0 16. "OU16,Channel 16 Output Update Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 15. "OU15,Channel 15 Output Update Disable" "0: Enable,1: Disable" bitfld.long 0x0 14. "OU14,Channel 14 Output Update Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 13. "OU13,Channel 13 Output Update Disable" "0: Enable,1: Disable" bitfld.long 0x0 12. "OU12,Channel 12 Output Update Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 11. "OU11,Channel 11 Output Update Disable" "0: Enable,1: Disable" bitfld.long 0x0 10. "OU10,Channel 10 Output Update Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 9. "OU9,Channel 9 Output Update Disable" "0: Enable,1: Disable" bitfld.long 0x0 8. "OU8,Channel 8 Output Update Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 7. "OU7,Channel 7 Output Update Disable" "0: Enable,1: Disable" bitfld.long 0x0 6. "OU6,Channel 6 Output Update Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 5. "OU5,Channel 5 Output Update Disable" "0: Enable,1: Disable" bitfld.long 0x0 4. "OU4,Channel 4 Output Update Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 3. "OU3,Channel 3 Output Update Disable" "0: Enable,1: Disable" bitfld.long 0x0 2. "OU2,Channel 2 Output Update Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 1. "OU1,Channel 1 Output Update Disable" "0: Enable,1: Disable" bitfld.long 0x0 0. "OU0,Channel 0 Output Update Disable" "0: Enable,1: Disable" line.long 0x4 "UCDIS,Disable Channel" bitfld.long 0x4 23. "UCDIS23,Disable UC 23" "0: Enable,1: Disable" bitfld.long 0x4 22. "UCDIS22,Disable UC 22" "0: Enable,1: Disable" newline bitfld.long 0x4 21. "UCDIS21,Disable UC 21" "0: Enable,1: Disable" bitfld.long 0x4 20. "UCDIS20,Disable UC 20" "0: Enable,1: Disable" newline bitfld.long 0x4 19. "UCDIS19,Disable UC 19" "0: Enable,1: Disable" bitfld.long 0x4 18. "UCDIS18,Disable UC 18" "0: Enable,1: Disable" newline bitfld.long 0x4 17. "UCDIS17,Disable UC 17" "0: Enable,1: Disable" bitfld.long 0x4 16. "UCDIS16,Disable UC 16" "0: Enable,1: Disable" newline bitfld.long 0x4 15. "UCDIS15,Disable UC 15" "0: Enable,1: Disable" bitfld.long 0x4 14. "UCDIS14,Disable UC 14" "0: Enable,1: Disable" newline bitfld.long 0x4 13. "UCDIS13,Disable UC 13" "0: Enable,1: Disable" bitfld.long 0x4 12. "UCDIS12,Disable UC 12" "0: Enable,1: Disable" newline bitfld.long 0x4 11. "UCDIS11,Disable UC 11" "0: Enable,1: Disable" bitfld.long 0x4 10. "UCDIS10,Disable UC 10" "0: Enable,1: Disable" newline bitfld.long 0x4 9. "UCDIS9,Disable UC 9" "0: Enable,1: Disable" bitfld.long 0x4 8. "UCDIS8,Disable UC 8" "0: Enable,1: Disable" newline bitfld.long 0x4 7. "UCDIS7,Disable UC 7" "0: Enable,1: Disable" bitfld.long 0x4 6. "UCDIS6,Disable UC 6" "0: Enable,1: Disable" newline bitfld.long 0x4 5. "UCDIS5,Disable UC 5" "0: Enable,1: Disable" bitfld.long 0x4 4. "UCDIS4,Disable UC 4" "0: Enable,1: Disable" newline bitfld.long 0x4 3. "UCDIS3,Disable UC 3" "0: Enable,1: Disable" bitfld.long 0x4 2. "UCDIS2,Disable UC 2" "0: Enable,1: Disable" newline bitfld.long 0x4 1. "UCDIS1,Disable UC 1" "0: Enable,1: Disable" bitfld.long 0x4 0. "UCDIS0,Disable UC 0" "0: Enable,1: Disable" group.long 0x20++0x1B line.long 0x0 "A0,UC A 0" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B0,UC B 0" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" line.long 0x8 "CNT0,UC Counter 0" hexmask.long.tbyte 0x8 0.--23. 1. "C,Internal Counter Value" line.long 0xC "C0,UC Control 0" bitfld.long 0xC 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0xC 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0xC 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0xC 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0xC 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0xC 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0xC 19.--22. 1. "IF,Input Filter" bitfld.long 0xC 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0xC 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0xC 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0xC 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0xC 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0xC 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0xC 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0xC 0.--6. 1. "MODE,Mode Selection" line.long 0x10 "S0,UC Status 0" eventfld.long 0x10 31. "OVR,Overrun" "0: No overrun,1: Overrun" eventfld.long 0x10 15. "OVFL,Overflow" "0: No overflow,1: Overflow" newline rbitfld.long 0x10 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" rbitfld.long 0x10 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" newline eventfld.long 0x10 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x14 "ALTA0,Alternate Address 0" hexmask.long.tbyte 0x14 0.--23. 1. "ALTA,Alternate Address" line.long 0x18 "C2_0,UC Control 2 0" hexmask.long.byte 0x18 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0x18 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0x18 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x40++0x1B line.long 0x0 "A1,UC A 1" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B1,UC B 1" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" line.long 0x8 "CNT1,UC Counter 1" hexmask.long.tbyte 0x8 0.--23. 1. "C,Internal Counter Value" line.long 0xC "C1,UC Control 1" bitfld.long 0xC 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0xC 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0xC 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0xC 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0xC 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0xC 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0xC 19.--22. 1. "IF,Input Filter" bitfld.long 0xC 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0xC 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0xC 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0xC 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0xC 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0xC 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0xC 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0xC 0.--6. 1. "MODE,Mode Selection" line.long 0x10 "S1,UC Status 1" eventfld.long 0x10 31. "OVR,Overrun" "0: No overrun,1: Overrun" eventfld.long 0x10 15. "OVFL,Overflow" "0: No overflow,1: Overflow" newline rbitfld.long 0x10 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" rbitfld.long 0x10 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" newline eventfld.long 0x10 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x14 "ALTA1,Alternate Address 1" hexmask.long.tbyte 0x14 0.--23. 1. "ALTA,Alternate Address" line.long 0x18 "C2_1,UC Control 2 1" hexmask.long.byte 0x18 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0x18 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0x18 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x60++0x1B line.long 0x0 "A2,UC A 2" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B2,UC B 2" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" line.long 0x8 "CNT2,UC Counter 2" hexmask.long.tbyte 0x8 0.--23. 1. "C,Internal Counter Value" line.long 0xC "C2,UC Control 2" bitfld.long 0xC 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0xC 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0xC 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0xC 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0xC 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0xC 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0xC 19.--22. 1. "IF,Input Filter" bitfld.long 0xC 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0xC 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0xC 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0xC 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0xC 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0xC 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0xC 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0xC 0.--6. 1. "MODE,Mode Selection" line.long 0x10 "S2,UC Status 2" eventfld.long 0x10 31. "OVR,Overrun" "0: No overrun,1: Overrun" eventfld.long 0x10 15. "OVFL,Overflow" "0: No overflow,1: Overflow" newline rbitfld.long 0x10 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" rbitfld.long 0x10 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" newline eventfld.long 0x10 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x14 "ALTA2,Alternate Address 2" hexmask.long.tbyte 0x14 0.--23. 1. "ALTA,Alternate Address" line.long 0x18 "C2_2,UC Control 2 2" hexmask.long.byte 0x18 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0x18 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0x18 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x80++0x1B line.long 0x0 "A3,UC A 3" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B3,UC B 3" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" line.long 0x8 "CNT3,UC Counter 3" hexmask.long.tbyte 0x8 0.--23. 1. "C,Internal Counter Value" line.long 0xC "C3,UC Control 3" bitfld.long 0xC 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0xC 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0xC 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0xC 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0xC 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0xC 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0xC 19.--22. 1. "IF,Input Filter" bitfld.long 0xC 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0xC 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0xC 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0xC 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0xC 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0xC 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0xC 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0xC 0.--6. 1. "MODE,Mode Selection" line.long 0x10 "S3,UC Status 3" eventfld.long 0x10 31. "OVR,Overrun" "0: No overrun,1: Overrun" eventfld.long 0x10 15. "OVFL,Overflow" "0: No overflow,1: Overflow" newline rbitfld.long 0x10 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" rbitfld.long 0x10 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" newline eventfld.long 0x10 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x14 "ALTA3,Alternate Address 3" hexmask.long.tbyte 0x14 0.--23. 1. "ALTA,Alternate Address" line.long 0x18 "C2_3,UC Control 2 3" hexmask.long.byte 0x18 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0x18 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0x18 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0xA0++0x1B line.long 0x0 "A4,UC A 4" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B4,UC B 4" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" line.long 0x8 "CNT4,UC Counter 4" hexmask.long.tbyte 0x8 0.--23. 1. "C,Internal Counter Value" line.long 0xC "C4,UC Control 4" bitfld.long 0xC 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0xC 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0xC 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0xC 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0xC 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0xC 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0xC 19.--22. 1. "IF,Input Filter" bitfld.long 0xC 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0xC 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0xC 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0xC 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0xC 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0xC 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0xC 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0xC 0.--6. 1. "MODE,Mode Selection" line.long 0x10 "S4,UC Status 4" eventfld.long 0x10 31. "OVR,Overrun" "0: No overrun,1: Overrun" eventfld.long 0x10 15. "OVFL,Overflow" "0: No overflow,1: Overflow" newline rbitfld.long 0x10 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" rbitfld.long 0x10 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" newline eventfld.long 0x10 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x14 "ALTA4,Alternate Address 4" hexmask.long.tbyte 0x14 0.--23. 1. "ALTA,Alternate Address" line.long 0x18 "C2_4,UC Control 2 4" hexmask.long.byte 0x18 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0x18 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0x18 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0xC0++0x1B line.long 0x0 "A5,UC A 5" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B5,UC B 5" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" line.long 0x8 "CNT5,UC Counter 5" hexmask.long.tbyte 0x8 0.--23. 1. "C,Internal Counter Value" line.long 0xC "C5,UC Control 5" bitfld.long 0xC 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0xC 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0xC 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0xC 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0xC 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0xC 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0xC 19.--22. 1. "IF,Input Filter" bitfld.long 0xC 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0xC 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0xC 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0xC 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0xC 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0xC 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0xC 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0xC 0.--6. 1. "MODE,Mode Selection" line.long 0x10 "S5,UC Status 5" eventfld.long 0x10 31. "OVR,Overrun" "0: No overrun,1: Overrun" eventfld.long 0x10 15. "OVFL,Overflow" "0: No overflow,1: Overflow" newline rbitfld.long 0x10 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" rbitfld.long 0x10 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" newline eventfld.long 0x10 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x14 "ALTA5,Alternate Address 5" hexmask.long.tbyte 0x14 0.--23. 1. "ALTA,Alternate Address" line.long 0x18 "C2_5,UC Control 2 5" hexmask.long.byte 0x18 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0x18 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0x18 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0xE0++0x1B line.long 0x0 "A6,UC A 6" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B6,UC B 6" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" line.long 0x8 "CNT6,UC Counter 6" hexmask.long.tbyte 0x8 0.--23. 1. "C,Internal Counter Value" line.long 0xC "C6,UC Control 6" bitfld.long 0xC 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0xC 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0xC 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0xC 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0xC 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0xC 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0xC 19.--22. 1. "IF,Input Filter" bitfld.long 0xC 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0xC 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0xC 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0xC 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0xC 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0xC 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0xC 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0xC 0.--6. 1. "MODE,Mode Selection" line.long 0x10 "S6,UC Status 6" eventfld.long 0x10 31. "OVR,Overrun" "0: No overrun,1: Overrun" eventfld.long 0x10 15. "OVFL,Overflow" "0: No overflow,1: Overflow" newline rbitfld.long 0x10 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" rbitfld.long 0x10 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" newline eventfld.long 0x10 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x14 "ALTA6,Alternate Address 6" hexmask.long.tbyte 0x14 0.--23. 1. "ALTA,Alternate Address" line.long 0x18 "C2_6,UC Control 2 6" hexmask.long.byte 0x18 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0x18 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0x18 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x100++0x1B line.long 0x0 "A7,UC A 7" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B7,UC B 7" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" line.long 0x8 "CNT7,UC Counter 7" hexmask.long.tbyte 0x8 0.--23. 1. "C,Internal Counter Value" line.long 0xC "C7,UC Control 7" bitfld.long 0xC 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0xC 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0xC 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0xC 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0xC 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0xC 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0xC 19.--22. 1. "IF,Input Filter" bitfld.long 0xC 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0xC 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0xC 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0xC 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0xC 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0xC 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0xC 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0xC 0.--6. 1. "MODE,Mode Selection" line.long 0x10 "S7,UC Status 7" eventfld.long 0x10 31. "OVR,Overrun" "0: No overrun,1: Overrun" eventfld.long 0x10 15. "OVFL,Overflow" "0: No overflow,1: Overflow" newline rbitfld.long 0x10 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" rbitfld.long 0x10 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" newline eventfld.long 0x10 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x14 "ALTA7,Alternate Address 7" hexmask.long.tbyte 0x14 0.--23. 1. "ALTA,Alternate Address" line.long 0x18 "C2_7,UC Control 2 7" hexmask.long.byte 0x18 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0x18 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0x18 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x120++0x1B line.long 0x0 "A8,UC A 8" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B8,UC B 8" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" line.long 0x8 "CNT8,UC Counter 8" hexmask.long.tbyte 0x8 0.--23. 1. "C,Internal Counter Value" line.long 0xC "C8,UC Control 8" bitfld.long 0xC 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0xC 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0xC 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0xC 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0xC 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0xC 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0xC 19.--22. 1. "IF,Input Filter" bitfld.long 0xC 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0xC 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0xC 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0xC 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0xC 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0xC 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0xC 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0xC 0.--6. 1. "MODE,Mode Selection" line.long 0x10 "S8,UC Status 8" eventfld.long 0x10 31. "OVR,Overrun" "0: No overrun,1: Overrun" eventfld.long 0x10 15. "OVFL,Overflow" "0: No overflow,1: Overflow" newline rbitfld.long 0x10 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" rbitfld.long 0x10 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" newline eventfld.long 0x10 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x14 "ALTA8,Alternate Address 8" hexmask.long.tbyte 0x14 0.--23. 1. "ALTA,Alternate Address" line.long 0x18 "C2_8,UC Control 2 8" hexmask.long.byte 0x18 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0x18 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0x18 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x140++0x7 line.long 0x0 "A9,UC A 9" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B9,UC B 9" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x14C++0xF line.long 0x0 "C9,UC Control 9" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S9,UC Status 9" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA9,Alternate Address 9" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_9,UC Control 2 9" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x160++0x7 line.long 0x0 "A10,UC A 10" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B10,UC B 10" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x16C++0xF line.long 0x0 "C10,UC Control 10" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S10,UC Status 10" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA10,Alternate Address 10" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_10,UC Control 2 10" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x180++0x7 line.long 0x0 "A11,UC A 11" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B11,UC B 11" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x18C++0xF line.long 0x0 "C11,UC Control 11" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S11,UC Status 11" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA11,Alternate Address 11" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_11,UC Control 2 11" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x1A0++0x7 line.long 0x0 "A12,UC A 12" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B12,UC B 12" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x1AC++0xF line.long 0x0 "C12,UC Control 12" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S12,UC Status 12" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA12,Alternate Address 12" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_12,UC Control 2 12" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x1C0++0x7 line.long 0x0 "A13,UC A 13" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B13,UC B 13" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x1CC++0xF line.long 0x0 "C13,UC Control 13" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S13,UC Status 13" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA13,Alternate Address 13" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_13,UC Control 2 13" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x1E0++0x7 line.long 0x0 "A14,UC A 14" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B14,UC B 14" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x1EC++0xF line.long 0x0 "C14,UC Control 14" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S14,UC Status 14" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA14,Alternate Address 14" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_14,UC Control 2 14" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x200++0x7 line.long 0x0 "A15,UC A 15" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B15,UC B 15" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x20C++0xF line.long 0x0 "C15,UC Control 15" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S15,UC Status 15" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA15,Alternate Address 15" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_15,UC Control 2 15" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x220++0x1B line.long 0x0 "A16,UC A 16" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B16,UC B 16" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" line.long 0x8 "CNT16,UC Counter 16" hexmask.long.tbyte 0x8 0.--23. 1. "C,Internal Counter Value" line.long 0xC "C16,UC Control 16" bitfld.long 0xC 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0xC 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0xC 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0xC 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0xC 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0xC 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0xC 19.--22. 1. "IF,Input Filter" bitfld.long 0xC 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0xC 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0xC 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0xC 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0xC 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0xC 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0xC 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0xC 0.--6. 1. "MODE,Mode Selection" line.long 0x10 "S16,UC Status 16" eventfld.long 0x10 31. "OVR,Overrun" "0: No overrun,1: Overrun" eventfld.long 0x10 15. "OVFL,Overflow" "0: No overflow,1: Overflow" newline rbitfld.long 0x10 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" rbitfld.long 0x10 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" newline eventfld.long 0x10 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x14 "ALTA16,Alternate Address 16" hexmask.long.tbyte 0x14 0.--23. 1. "ALTA,Alternate Address" line.long 0x18 "C2_16,UC Control 2 16" hexmask.long.byte 0x18 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0x18 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0x18 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x240++0x7 line.long 0x0 "A17,UC A 17" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B17,UC B 17" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x24C++0xF line.long 0x0 "C17,UC Control 17" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S17,UC Status 17" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA17,Alternate Address 17" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_17,UC Control 2 17" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x260++0x7 line.long 0x0 "A18,UC A 18" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B18,UC B 18" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x26C++0xF line.long 0x0 "C18,UC Control 18" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S18,UC Status 18" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA18,Alternate Address 18" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_18,UC Control 2 18" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x280++0x7 line.long 0x0 "A19,UC A 19" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B19,UC B 19" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x28C++0xF line.long 0x0 "C19,UC Control 19" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S19,UC Status 19" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA19,Alternate Address 19" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_19,UC Control 2 19" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x2A0++0x7 line.long 0x0 "A20,UC A 20" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B20,UC B 20" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x2AC++0xF line.long 0x0 "C20,UC Control 20" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S20,UC Status 20" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA20,Alternate Address 20" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_20,UC Control 2 20" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x2C0++0x7 line.long 0x0 "A21,UC A 21" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B21,UC B 21" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x2CC++0xF line.long 0x0 "C21,UC Control 21" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S21,UC Status 21" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA21,Alternate Address 21" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_21,UC Control 2 21" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x2E0++0x1B line.long 0x0 "A22,UC A 22" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B22,UC B 22" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" line.long 0x8 "CNT22,UC Counter 22" hexmask.long.tbyte 0x8 0.--23. 1. "C,Internal Counter Value" line.long 0xC "C22,UC Control 22" bitfld.long 0xC 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0xC 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0xC 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0xC 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0xC 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0xC 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0xC 19.--22. 1. "IF,Input Filter" bitfld.long 0xC 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0xC 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0xC 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0xC 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0xC 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0xC 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0xC 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0xC 0.--6. 1. "MODE,Mode Selection" line.long 0x10 "S22,UC Status 22" eventfld.long 0x10 31. "OVR,Overrun" "0: No overrun,1: Overrun" eventfld.long 0x10 15. "OVFL,Overflow" "0: No overflow,1: Overflow" newline rbitfld.long 0x10 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" rbitfld.long 0x10 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" newline eventfld.long 0x10 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x14 "ALTA22,Alternate Address 22" hexmask.long.tbyte 0x14 0.--23. 1. "ALTA,Alternate Address" line.long 0x18 "C2_22,UC Control 2 22" hexmask.long.byte 0x18 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0x18 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0x18 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x300++0x1B line.long 0x0 "A23,UC A 23" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B23,UC B 23" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" line.long 0x8 "CNT23,UC Counter 23" hexmask.long.tbyte 0x8 0.--23. 1. "C,Internal Counter Value" line.long 0xC "C23,UC Control 23" bitfld.long 0xC 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0xC 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0xC 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0xC 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0xC 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0xC 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0xC 19.--22. 1. "IF,Input Filter" bitfld.long 0xC 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0xC 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0xC 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0xC 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0xC 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0xC 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0xC 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0xC 0.--6. 1. "MODE,Mode Selection" line.long 0x10 "S23,UC Status 23" eventfld.long 0x10 31. "OVR,Overrun" "0: No overrun,1: Overrun" eventfld.long 0x10 15. "OVFL,Overflow" "0: No overflow,1: Overflow" newline rbitfld.long 0x10 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" rbitfld.long 0x10 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" newline eventfld.long 0x10 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x14 "ALTA23,Alternate Address 23" hexmask.long.tbyte 0x14 0.--23. 1. "ALTA,Alternate Address" line.long 0x18 "C2_23,UC Control 2 23" hexmask.long.byte 0x18 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0x18 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0x18 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" tree.end tree "EMIOS_1" base ad:0x4008C000 group.long 0x0++0x3 line.long 0x0 "MCR,Module Configuration" bitfld.long 0x0 30. "MDIS,Module Disable" "0: Enable,1: Disable" bitfld.long 0x0 29. "FRZ,Freeze" "0: Exit Freeze state,1: Enter Freeze state" newline bitfld.long 0x0 28. "GTBE,Global Timebase Enable" "0: Deassert GTBE_OUT,1: Assert GTBE_OUT" bitfld.long 0x0 26. "GPREN,Global Prescaler Enable" "0: Disable,1: Enable" newline hexmask.long.byte 0x0 8.--15. 1. "GPRE,Global Prescaler" rgroup.long 0x4++0x3 line.long 0x0 "GFLAG,Global Flag" bitfld.long 0x0 23. "F23,Mirror of UC 23 FLAG" "0,1" bitfld.long 0x0 22. "F22,Mirror of UC 22 FLAG" "0,1" newline bitfld.long 0x0 21. "F21,Mirror of UC 21 FLAG" "0,1" bitfld.long 0x0 20. "F20,Mirror of UC 20 FLAG" "0,1" newline bitfld.long 0x0 19. "F19,Mirror of UC 19 FLAG" "0,1" bitfld.long 0x0 18. "F18,Mirror of UC 18 FLAG" "0,1" newline bitfld.long 0x0 17. "F17,Mirror of UC 17 FLAG" "0,1" bitfld.long 0x0 16. "F16,Mirror of UC 16 FLAG" "0,1" newline bitfld.long 0x0 15. "F15,Mirror of UC 15 FLAG" "0,1" bitfld.long 0x0 14. "F14,Mirror of UC 14 FLAG" "0,1" newline bitfld.long 0x0 13. "F13,Mirror of UC 13 FLAG" "0,1" bitfld.long 0x0 12. "F12,Mirror of UC 12 FLAG" "0,1" newline bitfld.long 0x0 11. "F11,Mirror of UC 11 FLAG" "0,1" bitfld.long 0x0 10. "F10,Mirror of UC 10 FLAG" "0,1" newline bitfld.long 0x0 9. "F9,Mirror of UC 9 FLAG" "0,1" bitfld.long 0x0 8. "F8,Mirror of UC 8 FLAG" "0,1" newline bitfld.long 0x0 7. "F7,Mirror of UC 7 FLAG" "0,1" bitfld.long 0x0 6. "F6,Mirror of UC 6 FLAG" "0,1" newline bitfld.long 0x0 5. "F5,Mirror of UC 5 FLAG" "0,1" bitfld.long 0x0 4. "F4,Mirror of UC 4 FLAG" "0,1" newline bitfld.long 0x0 3. "F3,Mirror of UC 3 FLAG" "0,1" bitfld.long 0x0 2. "F2,Mirror of UC 2 FLAG" "0,1" newline bitfld.long 0x0 1. "F1,Mirror of UC 1 FLAG" "0,1" bitfld.long 0x0 0. "F0,Mirror of UC 0 FLAG" "0,1" group.long 0x8++0x7 line.long 0x0 "OUDIS,Output Update Disable" bitfld.long 0x0 23. "OU23,Channel 23 Output Update Disable" "0: Enable,1: Disable" bitfld.long 0x0 22. "OU22,Channel 22 Output Update Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 21. "OU21,Channel 21 Output Update Disable" "0: Enable,1: Disable" bitfld.long 0x0 20. "OU20,Channel 20 Output Update Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 19. "OU19,Channel 19 Output Update Disable" "0: Enable,1: Disable" bitfld.long 0x0 18. "OU18,Channel 18 Output Update Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 17. "OU17,Channel 17 Output Update Disable" "0: Enable,1: Disable" bitfld.long 0x0 16. "OU16,Channel 16 Output Update Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 15. "OU15,Channel 15 Output Update Disable" "0: Enable,1: Disable" bitfld.long 0x0 14. "OU14,Channel 14 Output Update Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 13. "OU13,Channel 13 Output Update Disable" "0: Enable,1: Disable" bitfld.long 0x0 12. "OU12,Channel 12 Output Update Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 11. "OU11,Channel 11 Output Update Disable" "0: Enable,1: Disable" bitfld.long 0x0 10. "OU10,Channel 10 Output Update Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 9. "OU9,Channel 9 Output Update Disable" "0: Enable,1: Disable" bitfld.long 0x0 8. "OU8,Channel 8 Output Update Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 7. "OU7,Channel 7 Output Update Disable" "0: Enable,1: Disable" bitfld.long 0x0 6. "OU6,Channel 6 Output Update Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 5. "OU5,Channel 5 Output Update Disable" "0: Enable,1: Disable" bitfld.long 0x0 4. "OU4,Channel 4 Output Update Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 3. "OU3,Channel 3 Output Update Disable" "0: Enable,1: Disable" bitfld.long 0x0 2. "OU2,Channel 2 Output Update Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 1. "OU1,Channel 1 Output Update Disable" "0: Enable,1: Disable" bitfld.long 0x0 0. "OU0,Channel 0 Output Update Disable" "0: Enable,1: Disable" line.long 0x4 "UCDIS,Disable Channel" bitfld.long 0x4 23. "UCDIS23,Disable UC 23" "0: Enable,1: Disable" bitfld.long 0x4 22. "UCDIS22,Disable UC 22" "0: Enable,1: Disable" newline bitfld.long 0x4 21. "UCDIS21,Disable UC 21" "0: Enable,1: Disable" bitfld.long 0x4 20. "UCDIS20,Disable UC 20" "0: Enable,1: Disable" newline bitfld.long 0x4 19. "UCDIS19,Disable UC 19" "0: Enable,1: Disable" bitfld.long 0x4 18. "UCDIS18,Disable UC 18" "0: Enable,1: Disable" newline bitfld.long 0x4 17. "UCDIS17,Disable UC 17" "0: Enable,1: Disable" bitfld.long 0x4 16. "UCDIS16,Disable UC 16" "0: Enable,1: Disable" newline bitfld.long 0x4 15. "UCDIS15,Disable UC 15" "0: Enable,1: Disable" bitfld.long 0x4 14. "UCDIS14,Disable UC 14" "0: Enable,1: Disable" newline bitfld.long 0x4 13. "UCDIS13,Disable UC 13" "0: Enable,1: Disable" bitfld.long 0x4 12. "UCDIS12,Disable UC 12" "0: Enable,1: Disable" newline bitfld.long 0x4 11. "UCDIS11,Disable UC 11" "0: Enable,1: Disable" bitfld.long 0x4 10. "UCDIS10,Disable UC 10" "0: Enable,1: Disable" newline bitfld.long 0x4 9. "UCDIS9,Disable UC 9" "0: Enable,1: Disable" bitfld.long 0x4 8. "UCDIS8,Disable UC 8" "0: Enable,1: Disable" newline bitfld.long 0x4 7. "UCDIS7,Disable UC 7" "0: Enable,1: Disable" bitfld.long 0x4 6. "UCDIS6,Disable UC 6" "0: Enable,1: Disable" newline bitfld.long 0x4 5. "UCDIS5,Disable UC 5" "0: Enable,1: Disable" bitfld.long 0x4 4. "UCDIS4,Disable UC 4" "0: Enable,1: Disable" newline bitfld.long 0x4 3. "UCDIS3,Disable UC 3" "0: Enable,1: Disable" bitfld.long 0x4 2. "UCDIS2,Disable UC 2" "0: Enable,1: Disable" newline bitfld.long 0x4 1. "UCDIS1,Disable UC 1" "0: Enable,1: Disable" bitfld.long 0x4 0. "UCDIS0,Disable UC 0" "0: Enable,1: Disable" group.long 0x20++0x1B line.long 0x0 "A0,UC A 0" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B0,UC B 0" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" line.long 0x8 "CNT0,UC Counter 0" hexmask.long.tbyte 0x8 0.--23. 1. "C,Internal Counter Value" line.long 0xC "C0,UC Control 0" bitfld.long 0xC 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0xC 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0xC 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0xC 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0xC 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0xC 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0xC 19.--22. 1. "IF,Input Filter" bitfld.long 0xC 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0xC 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0xC 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0xC 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0xC 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0xC 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0xC 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0xC 0.--6. 1. "MODE,Mode Selection" line.long 0x10 "S0,UC Status 0" eventfld.long 0x10 31. "OVR,Overrun" "0: No overrun,1: Overrun" eventfld.long 0x10 15. "OVFL,Overflow" "0: No overflow,1: Overflow" newline rbitfld.long 0x10 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" rbitfld.long 0x10 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" newline eventfld.long 0x10 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x14 "ALTA0,Alternate Address 0" hexmask.long.tbyte 0x14 0.--23. 1. "ALTA,Alternate Address" line.long 0x18 "C2_0,UC Control 2 0" hexmask.long.byte 0x18 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0x18 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0x18 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x40++0x7 line.long 0x0 "A1,UC A 1" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B1,UC B 1" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x4C++0xF line.long 0x0 "C1,UC Control 1" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S1,UC Status 1" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA1,Alternate Address 1" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_1,UC Control 2 1" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x60++0x7 line.long 0x0 "A2,UC A 2" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B2,UC B 2" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x6C++0xF line.long 0x0 "C2,UC Control 2" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S2,UC Status 2" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA2,Alternate Address 2" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_2,UC Control 2 2" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x80++0x7 line.long 0x0 "A3,UC A 3" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B3,UC B 3" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x8C++0xF line.long 0x0 "C3,UC Control 3" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S3,UC Status 3" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA3,Alternate Address 3" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_3,UC Control 2 3" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0xA0++0x7 line.long 0x0 "A4,UC A 4" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B4,UC B 4" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0xAC++0xF line.long 0x0 "C4,UC Control 4" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S4,UC Status 4" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA4,Alternate Address 4" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_4,UC Control 2 4" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0xC0++0x7 line.long 0x0 "A5,UC A 5" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B5,UC B 5" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0xCC++0xF line.long 0x0 "C5,UC Control 5" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S5,UC Status 5" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA5,Alternate Address 5" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_5,UC Control 2 5" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0xE0++0x7 line.long 0x0 "A6,UC A 6" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B6,UC B 6" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0xEC++0xF line.long 0x0 "C6,UC Control 6" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S6,UC Status 6" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA6,Alternate Address 6" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_6,UC Control 2 6" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x100++0x7 line.long 0x0 "A7,UC A 7" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B7,UC B 7" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x10C++0xF line.long 0x0 "C7,UC Control 7" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S7,UC Status 7" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA7,Alternate Address 7" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_7,UC Control 2 7" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x120++0x1B line.long 0x0 "A8,UC A 8" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B8,UC B 8" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" line.long 0x8 "CNT8,UC Counter 8" hexmask.long.tbyte 0x8 0.--23. 1. "C,Internal Counter Value" line.long 0xC "C8,UC Control 8" bitfld.long 0xC 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0xC 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0xC 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0xC 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0xC 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0xC 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0xC 19.--22. 1. "IF,Input Filter" bitfld.long 0xC 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0xC 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0xC 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0xC 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0xC 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0xC 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0xC 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0xC 0.--6. 1. "MODE,Mode Selection" line.long 0x10 "S8,UC Status 8" eventfld.long 0x10 31. "OVR,Overrun" "0: No overrun,1: Overrun" eventfld.long 0x10 15. "OVFL,Overflow" "0: No overflow,1: Overflow" newline rbitfld.long 0x10 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" rbitfld.long 0x10 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" newline eventfld.long 0x10 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x14 "ALTA8,Alternate Address 8" hexmask.long.tbyte 0x14 0.--23. 1. "ALTA,Alternate Address" line.long 0x18 "C2_8,UC Control 2 8" hexmask.long.byte 0x18 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0x18 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0x18 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x140++0x7 line.long 0x0 "A9,UC A 9" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B9,UC B 9" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x14C++0xF line.long 0x0 "C9,UC Control 9" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S9,UC Status 9" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA9,Alternate Address 9" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_9,UC Control 2 9" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x160++0x7 line.long 0x0 "A10,UC A 10" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B10,UC B 10" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x16C++0xF line.long 0x0 "C10,UC Control 10" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S10,UC Status 10" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA10,Alternate Address 10" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_10,UC Control 2 10" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x180++0x7 line.long 0x0 "A11,UC A 11" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B11,UC B 11" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x18C++0xF line.long 0x0 "C11,UC Control 11" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S11,UC Status 11" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA11,Alternate Address 11" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_11,UC Control 2 11" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x1A0++0x7 line.long 0x0 "A12,UC A 12" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B12,UC B 12" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x1AC++0xF line.long 0x0 "C12,UC Control 12" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S12,UC Status 12" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA12,Alternate Address 12" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_12,UC Control 2 12" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x1C0++0x7 line.long 0x0 "A13,UC A 13" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B13,UC B 13" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x1CC++0xF line.long 0x0 "C13,UC Control 13" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S13,UC Status 13" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA13,Alternate Address 13" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_13,UC Control 2 13" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x1E0++0x7 line.long 0x0 "A14,UC A 14" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B14,UC B 14" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x1EC++0xF line.long 0x0 "C14,UC Control 14" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S14,UC Status 14" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA14,Alternate Address 14" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_14,UC Control 2 14" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x200++0x7 line.long 0x0 "A15,UC A 15" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B15,UC B 15" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x20C++0xF line.long 0x0 "C15,UC Control 15" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S15,UC Status 15" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA15,Alternate Address 15" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_15,UC Control 2 15" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x220++0x1B line.long 0x0 "A16,UC A 16" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B16,UC B 16" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" line.long 0x8 "CNT16,UC Counter 16" hexmask.long.tbyte 0x8 0.--23. 1. "C,Internal Counter Value" line.long 0xC "C16,UC Control 16" bitfld.long 0xC 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0xC 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0xC 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0xC 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0xC 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0xC 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0xC 19.--22. 1. "IF,Input Filter" bitfld.long 0xC 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0xC 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0xC 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0xC 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0xC 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0xC 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0xC 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0xC 0.--6. 1. "MODE,Mode Selection" line.long 0x10 "S16,UC Status 16" eventfld.long 0x10 31. "OVR,Overrun" "0: No overrun,1: Overrun" eventfld.long 0x10 15. "OVFL,Overflow" "0: No overflow,1: Overflow" newline rbitfld.long 0x10 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" rbitfld.long 0x10 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" newline eventfld.long 0x10 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x14 "ALTA16,Alternate Address 16" hexmask.long.tbyte 0x14 0.--23. 1. "ALTA,Alternate Address" line.long 0x18 "C2_16,UC Control 2 16" hexmask.long.byte 0x18 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0x18 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0x18 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x240++0x7 line.long 0x0 "A17,UC A 17" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B17,UC B 17" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x24C++0xF line.long 0x0 "C17,UC Control 17" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S17,UC Status 17" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA17,Alternate Address 17" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_17,UC Control 2 17" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x260++0x7 line.long 0x0 "A18,UC A 18" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B18,UC B 18" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x26C++0xF line.long 0x0 "C18,UC Control 18" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S18,UC Status 18" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA18,Alternate Address 18" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_18,UC Control 2 18" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x280++0x7 line.long 0x0 "A19,UC A 19" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B19,UC B 19" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x28C++0xF line.long 0x0 "C19,UC Control 19" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S19,UC Status 19" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA19,Alternate Address 19" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_19,UC Control 2 19" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x2A0++0x7 line.long 0x0 "A20,UC A 20" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B20,UC B 20" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x2AC++0xF line.long 0x0 "C20,UC Control 20" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S20,UC Status 20" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA20,Alternate Address 20" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_20,UC Control 2 20" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x2C0++0x7 line.long 0x0 "A21,UC A 21" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B21,UC B 21" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x2CC++0xF line.long 0x0 "C21,UC Control 21" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S21,UC Status 21" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA21,Alternate Address 21" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_21,UC Control 2 21" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x2E0++0x1B line.long 0x0 "A22,UC A 22" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B22,UC B 22" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" line.long 0x8 "CNT22,UC Counter 22" hexmask.long.tbyte 0x8 0.--23. 1. "C,Internal Counter Value" line.long 0xC "C22,UC Control 22" bitfld.long 0xC 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0xC 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0xC 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0xC 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0xC 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0xC 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0xC 19.--22. 1. "IF,Input Filter" bitfld.long 0xC 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0xC 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0xC 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0xC 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0xC 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0xC 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0xC 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0xC 0.--6. 1. "MODE,Mode Selection" line.long 0x10 "S22,UC Status 22" eventfld.long 0x10 31. "OVR,Overrun" "0: No overrun,1: Overrun" eventfld.long 0x10 15. "OVFL,Overflow" "0: No overflow,1: Overflow" newline rbitfld.long 0x10 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" rbitfld.long 0x10 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" newline eventfld.long 0x10 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x14 "ALTA22,Alternate Address 22" hexmask.long.tbyte 0x14 0.--23. 1. "ALTA,Alternate Address" line.long 0x18 "C2_22,UC Control 2 22" hexmask.long.byte 0x18 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0x18 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0x18 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x300++0x1B line.long 0x0 "A23,UC A 23" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B23,UC B 23" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" line.long 0x8 "CNT23,UC Counter 23" hexmask.long.tbyte 0x8 0.--23. 1. "C,Internal Counter Value" line.long 0xC "C23,UC Control 23" bitfld.long 0xC 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0xC 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0xC 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0xC 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0xC 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0xC 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0xC 19.--22. 1. "IF,Input Filter" bitfld.long 0xC 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0xC 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0xC 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0xC 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0xC 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0xC 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0xC 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0xC 0.--6. 1. "MODE,Mode Selection" line.long 0x10 "S23,UC Status 23" eventfld.long 0x10 31. "OVR,Overrun" "0: No overrun,1: Overrun" eventfld.long 0x10 15. "OVFL,Overflow" "0: No overflow,1: Overflow" newline rbitfld.long 0x10 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" rbitfld.long 0x10 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" newline eventfld.long 0x10 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x14 "ALTA23,Alternate Address 23" hexmask.long.tbyte 0x14 0.--23. 1. "ALTA,Alternate Address" line.long 0x18 "C2_23,UC Control 2 23" hexmask.long.byte 0x18 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0x18 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0x18 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" tree.end tree "EMIOS_2" base ad:0x40090000 group.long 0x0++0x3 line.long 0x0 "MCR,Module Configuration" bitfld.long 0x0 30. "MDIS,Module Disable" "0: Enable,1: Disable" bitfld.long 0x0 29. "FRZ,Freeze" "0: Exit Freeze state,1: Enter Freeze state" newline bitfld.long 0x0 28. "GTBE,Global Timebase Enable" "0: Deassert GTBE_OUT,1: Assert GTBE_OUT" bitfld.long 0x0 26. "GPREN,Global Prescaler Enable" "0: Disable,1: Enable" newline hexmask.long.byte 0x0 8.--15. 1. "GPRE,Global Prescaler" rgroup.long 0x4++0x3 line.long 0x0 "GFLAG,Global Flag" bitfld.long 0x0 23. "F23,Mirror of UC 23 FLAG" "0,1" bitfld.long 0x0 22. "F22,Mirror of UC 22 FLAG" "0,1" newline bitfld.long 0x0 21. "F21,Mirror of UC 21 FLAG" "0,1" bitfld.long 0x0 20. "F20,Mirror of UC 20 FLAG" "0,1" newline bitfld.long 0x0 19. "F19,Mirror of UC 19 FLAG" "0,1" bitfld.long 0x0 18. "F18,Mirror of UC 18 FLAG" "0,1" newline bitfld.long 0x0 17. "F17,Mirror of UC 17 FLAG" "0,1" bitfld.long 0x0 16. "F16,Mirror of UC 16 FLAG" "0,1" newline bitfld.long 0x0 15. "F15,Mirror of UC 15 FLAG" "0,1" bitfld.long 0x0 14. "F14,Mirror of UC 14 FLAG" "0,1" newline bitfld.long 0x0 13. "F13,Mirror of UC 13 FLAG" "0,1" bitfld.long 0x0 12. "F12,Mirror of UC 12 FLAG" "0,1" newline bitfld.long 0x0 11. "F11,Mirror of UC 11 FLAG" "0,1" bitfld.long 0x0 10. "F10,Mirror of UC 10 FLAG" "0,1" newline bitfld.long 0x0 9. "F9,Mirror of UC 9 FLAG" "0,1" bitfld.long 0x0 8. "F8,Mirror of UC 8 FLAG" "0,1" newline bitfld.long 0x0 7. "F7,Mirror of UC 7 FLAG" "0,1" bitfld.long 0x0 6. "F6,Mirror of UC 6 FLAG" "0,1" newline bitfld.long 0x0 5. "F5,Mirror of UC 5 FLAG" "0,1" bitfld.long 0x0 4. "F4,Mirror of UC 4 FLAG" "0,1" newline bitfld.long 0x0 3. "F3,Mirror of UC 3 FLAG" "0,1" bitfld.long 0x0 2. "F2,Mirror of UC 2 FLAG" "0,1" newline bitfld.long 0x0 1. "F1,Mirror of UC 1 FLAG" "0,1" bitfld.long 0x0 0. "F0,Mirror of UC 0 FLAG" "0,1" group.long 0x8++0x7 line.long 0x0 "OUDIS,Output Update Disable" bitfld.long 0x0 23. "OU23,Channel 23 Output Update Disable" "0: Enable,1: Disable" bitfld.long 0x0 22. "OU22,Channel 22 Output Update Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 21. "OU21,Channel 21 Output Update Disable" "0: Enable,1: Disable" bitfld.long 0x0 20. "OU20,Channel 20 Output Update Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 19. "OU19,Channel 19 Output Update Disable" "0: Enable,1: Disable" bitfld.long 0x0 18. "OU18,Channel 18 Output Update Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 17. "OU17,Channel 17 Output Update Disable" "0: Enable,1: Disable" bitfld.long 0x0 16. "OU16,Channel 16 Output Update Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 15. "OU15,Channel 15 Output Update Disable" "0: Enable,1: Disable" bitfld.long 0x0 14. "OU14,Channel 14 Output Update Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 13. "OU13,Channel 13 Output Update Disable" "0: Enable,1: Disable" bitfld.long 0x0 12. "OU12,Channel 12 Output Update Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 11. "OU11,Channel 11 Output Update Disable" "0: Enable,1: Disable" bitfld.long 0x0 10. "OU10,Channel 10 Output Update Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 9. "OU9,Channel 9 Output Update Disable" "0: Enable,1: Disable" bitfld.long 0x0 8. "OU8,Channel 8 Output Update Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 7. "OU7,Channel 7 Output Update Disable" "0: Enable,1: Disable" bitfld.long 0x0 6. "OU6,Channel 6 Output Update Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 5. "OU5,Channel 5 Output Update Disable" "0: Enable,1: Disable" bitfld.long 0x0 4. "OU4,Channel 4 Output Update Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 3. "OU3,Channel 3 Output Update Disable" "0: Enable,1: Disable" bitfld.long 0x0 2. "OU2,Channel 2 Output Update Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 1. "OU1,Channel 1 Output Update Disable" "0: Enable,1: Disable" bitfld.long 0x0 0. "OU0,Channel 0 Output Update Disable" "0: Enable,1: Disable" line.long 0x4 "UCDIS,Disable Channel" bitfld.long 0x4 23. "UCDIS23,Disable UC 23" "0: Enable,1: Disable" bitfld.long 0x4 22. "UCDIS22,Disable UC 22" "0: Enable,1: Disable" newline bitfld.long 0x4 21. "UCDIS21,Disable UC 21" "0: Enable,1: Disable" bitfld.long 0x4 20. "UCDIS20,Disable UC 20" "0: Enable,1: Disable" newline bitfld.long 0x4 19. "UCDIS19,Disable UC 19" "0: Enable,1: Disable" bitfld.long 0x4 18. "UCDIS18,Disable UC 18" "0: Enable,1: Disable" newline bitfld.long 0x4 17. "UCDIS17,Disable UC 17" "0: Enable,1: Disable" bitfld.long 0x4 16. "UCDIS16,Disable UC 16" "0: Enable,1: Disable" newline bitfld.long 0x4 15. "UCDIS15,Disable UC 15" "0: Enable,1: Disable" bitfld.long 0x4 14. "UCDIS14,Disable UC 14" "0: Enable,1: Disable" newline bitfld.long 0x4 13. "UCDIS13,Disable UC 13" "0: Enable,1: Disable" bitfld.long 0x4 12. "UCDIS12,Disable UC 12" "0: Enable,1: Disable" newline bitfld.long 0x4 11. "UCDIS11,Disable UC 11" "0: Enable,1: Disable" bitfld.long 0x4 10. "UCDIS10,Disable UC 10" "0: Enable,1: Disable" newline bitfld.long 0x4 9. "UCDIS9,Disable UC 9" "0: Enable,1: Disable" bitfld.long 0x4 8. "UCDIS8,Disable UC 8" "0: Enable,1: Disable" newline bitfld.long 0x4 7. "UCDIS7,Disable UC 7" "0: Enable,1: Disable" bitfld.long 0x4 6. "UCDIS6,Disable UC 6" "0: Enable,1: Disable" newline bitfld.long 0x4 5. "UCDIS5,Disable UC 5" "0: Enable,1: Disable" bitfld.long 0x4 4. "UCDIS4,Disable UC 4" "0: Enable,1: Disable" newline bitfld.long 0x4 3. "UCDIS3,Disable UC 3" "0: Enable,1: Disable" bitfld.long 0x4 2. "UCDIS2,Disable UC 2" "0: Enable,1: Disable" newline bitfld.long 0x4 1. "UCDIS1,Disable UC 1" "0: Enable,1: Disable" bitfld.long 0x4 0. "UCDIS0,Disable UC 0" "0: Enable,1: Disable" group.long 0x20++0x1B line.long 0x0 "A0,UC A 0" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B0,UC B 0" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" line.long 0x8 "CNT0,UC Counter 0" hexmask.long.tbyte 0x8 0.--23. 1. "C,Internal Counter Value" line.long 0xC "C0,UC Control 0" bitfld.long 0xC 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0xC 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0xC 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0xC 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0xC 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0xC 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0xC 19.--22. 1. "IF,Input Filter" bitfld.long 0xC 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0xC 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0xC 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0xC 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0xC 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0xC 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0xC 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0xC 0.--6. 1. "MODE,Mode Selection" line.long 0x10 "S0,UC Status 0" eventfld.long 0x10 31. "OVR,Overrun" "0: No overrun,1: Overrun" eventfld.long 0x10 15. "OVFL,Overflow" "0: No overflow,1: Overflow" newline rbitfld.long 0x10 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" rbitfld.long 0x10 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" newline eventfld.long 0x10 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x14 "ALTA0,Alternate Address 0" hexmask.long.tbyte 0x14 0.--23. 1. "ALTA,Alternate Address" line.long 0x18 "C2_0,UC Control 2 0" hexmask.long.byte 0x18 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0x18 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0x18 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x40++0x7 line.long 0x0 "A1,UC A 1" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B1,UC B 1" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x4C++0xF line.long 0x0 "C1,UC Control 1" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S1,UC Status 1" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA1,Alternate Address 1" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_1,UC Control 2 1" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x60++0x7 line.long 0x0 "A2,UC A 2" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B2,UC B 2" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x6C++0xF line.long 0x0 "C2,UC Control 2" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S2,UC Status 2" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA2,Alternate Address 2" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_2,UC Control 2 2" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x80++0x7 line.long 0x0 "A3,UC A 3" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B3,UC B 3" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x8C++0xF line.long 0x0 "C3,UC Control 3" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S3,UC Status 3" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA3,Alternate Address 3" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_3,UC Control 2 3" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0xA0++0x7 line.long 0x0 "A4,UC A 4" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B4,UC B 4" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0xAC++0xF line.long 0x0 "C4,UC Control 4" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S4,UC Status 4" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA4,Alternate Address 4" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_4,UC Control 2 4" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0xC0++0x7 line.long 0x0 "A5,UC A 5" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B5,UC B 5" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0xCC++0xF line.long 0x0 "C5,UC Control 5" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S5,UC Status 5" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA5,Alternate Address 5" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_5,UC Control 2 5" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0xE0++0x7 line.long 0x0 "A6,UC A 6" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B6,UC B 6" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0xEC++0xF line.long 0x0 "C6,UC Control 6" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S6,UC Status 6" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA6,Alternate Address 6" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_6,UC Control 2 6" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x100++0x7 line.long 0x0 "A7,UC A 7" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B7,UC B 7" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x10C++0xF line.long 0x0 "C7,UC Control 7" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S7,UC Status 7" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA7,Alternate Address 7" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_7,UC Control 2 7" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x120++0x1B line.long 0x0 "A8,UC A 8" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B8,UC B 8" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" line.long 0x8 "CNT8,UC Counter 8" hexmask.long.tbyte 0x8 0.--23. 1. "C,Internal Counter Value" line.long 0xC "C8,UC Control 8" bitfld.long 0xC 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0xC 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0xC 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0xC 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0xC 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0xC 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0xC 19.--22. 1. "IF,Input Filter" bitfld.long 0xC 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0xC 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0xC 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0xC 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0xC 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0xC 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0xC 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0xC 0.--6. 1. "MODE,Mode Selection" line.long 0x10 "S8,UC Status 8" eventfld.long 0x10 31. "OVR,Overrun" "0: No overrun,1: Overrun" eventfld.long 0x10 15. "OVFL,Overflow" "0: No overflow,1: Overflow" newline rbitfld.long 0x10 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" rbitfld.long 0x10 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" newline eventfld.long 0x10 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x14 "ALTA8,Alternate Address 8" hexmask.long.tbyte 0x14 0.--23. 1. "ALTA,Alternate Address" line.long 0x18 "C2_8,UC Control 2 8" hexmask.long.byte 0x18 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0x18 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0x18 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x140++0x7 line.long 0x0 "A9,UC A 9" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B9,UC B 9" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x14C++0xF line.long 0x0 "C9,UC Control 9" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S9,UC Status 9" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA9,Alternate Address 9" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_9,UC Control 2 9" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x160++0x7 line.long 0x0 "A10,UC A 10" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B10,UC B 10" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x16C++0xF line.long 0x0 "C10,UC Control 10" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S10,UC Status 10" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA10,Alternate Address 10" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_10,UC Control 2 10" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x180++0x7 line.long 0x0 "A11,UC A 11" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B11,UC B 11" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x18C++0xF line.long 0x0 "C11,UC Control 11" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S11,UC Status 11" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA11,Alternate Address 11" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_11,UC Control 2 11" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x1A0++0x7 line.long 0x0 "A12,UC A 12" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B12,UC B 12" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x1AC++0xF line.long 0x0 "C12,UC Control 12" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S12,UC Status 12" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA12,Alternate Address 12" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_12,UC Control 2 12" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x1C0++0x7 line.long 0x0 "A13,UC A 13" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B13,UC B 13" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x1CC++0xF line.long 0x0 "C13,UC Control 13" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S13,UC Status 13" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA13,Alternate Address 13" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_13,UC Control 2 13" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x1E0++0x7 line.long 0x0 "A14,UC A 14" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B14,UC B 14" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x1EC++0xF line.long 0x0 "C14,UC Control 14" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S14,UC Status 14" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA14,Alternate Address 14" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_14,UC Control 2 14" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x200++0x7 line.long 0x0 "A15,UC A 15" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B15,UC B 15" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x20C++0xF line.long 0x0 "C15,UC Control 15" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S15,UC Status 15" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA15,Alternate Address 15" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_15,UC Control 2 15" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x220++0x1B line.long 0x0 "A16,UC A 16" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B16,UC B 16" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" line.long 0x8 "CNT16,UC Counter 16" hexmask.long.tbyte 0x8 0.--23. 1. "C,Internal Counter Value" line.long 0xC "C16,UC Control 16" bitfld.long 0xC 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0xC 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0xC 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0xC 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0xC 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0xC 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0xC 19.--22. 1. "IF,Input Filter" bitfld.long 0xC 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0xC 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0xC 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0xC 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0xC 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0xC 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0xC 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0xC 0.--6. 1. "MODE,Mode Selection" line.long 0x10 "S16,UC Status 16" eventfld.long 0x10 31. "OVR,Overrun" "0: No overrun,1: Overrun" eventfld.long 0x10 15. "OVFL,Overflow" "0: No overflow,1: Overflow" newline rbitfld.long 0x10 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" rbitfld.long 0x10 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" newline eventfld.long 0x10 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x14 "ALTA16,Alternate Address 16" hexmask.long.tbyte 0x14 0.--23. 1. "ALTA,Alternate Address" line.long 0x18 "C2_16,UC Control 2 16" hexmask.long.byte 0x18 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0x18 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0x18 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x240++0x7 line.long 0x0 "A17,UC A 17" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B17,UC B 17" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x24C++0xF line.long 0x0 "C17,UC Control 17" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S17,UC Status 17" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA17,Alternate Address 17" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_17,UC Control 2 17" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x260++0x7 line.long 0x0 "A18,UC A 18" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B18,UC B 18" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x26C++0xF line.long 0x0 "C18,UC Control 18" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S18,UC Status 18" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA18,Alternate Address 18" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_18,UC Control 2 18" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x280++0x7 line.long 0x0 "A19,UC A 19" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B19,UC B 19" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x28C++0xF line.long 0x0 "C19,UC Control 19" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S19,UC Status 19" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA19,Alternate Address 19" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_19,UC Control 2 19" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x2A0++0x7 line.long 0x0 "A20,UC A 20" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B20,UC B 20" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x2AC++0xF line.long 0x0 "C20,UC Control 20" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S20,UC Status 20" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA20,Alternate Address 20" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_20,UC Control 2 20" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x2C0++0x7 line.long 0x0 "A21,UC A 21" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B21,UC B 21" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" group.long 0x2CC++0xF line.long 0x0 "C21,UC Control 21" bitfld.long 0x0 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0x0 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0x0 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0x0 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0x0 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0x0 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0x0 19.--22. 1. "IF,Input Filter" bitfld.long 0x0 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0x0 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0x0 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0x0 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0x0 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0x0 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "MODE,Mode Selection" line.long 0x4 "S21,UC Status 21" eventfld.long 0x4 31. "OVR,Overrun" "0: No overrun,1: Overrun" rbitfld.long 0x4 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" newline rbitfld.long 0x4 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" eventfld.long 0x4 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x8 "ALTA21,Alternate Address 21" hexmask.long.tbyte 0x8 0.--23. 1. "ALTA,Alternate Address" line.long 0xC "C2_21,UC Control 2 21" hexmask.long.byte 0xC 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0xC 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0xC 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x2E0++0x1B line.long 0x0 "A22,UC A 22" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B22,UC B 22" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" line.long 0x8 "CNT22,UC Counter 22" hexmask.long.tbyte 0x8 0.--23. 1. "C,Internal Counter Value" line.long 0xC "C22,UC Control 22" bitfld.long 0xC 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0xC 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0xC 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0xC 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0xC 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0xC 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0xC 19.--22. 1. "IF,Input Filter" bitfld.long 0xC 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0xC 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0xC 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0xC 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0xC 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0xC 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0xC 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0xC 0.--6. 1. "MODE,Mode Selection" line.long 0x10 "S22,UC Status 22" eventfld.long 0x10 31. "OVR,Overrun" "0: No overrun,1: Overrun" eventfld.long 0x10 15. "OVFL,Overflow" "0: No overflow,1: Overflow" newline rbitfld.long 0x10 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" rbitfld.long 0x10 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" newline eventfld.long 0x10 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x14 "ALTA22,Alternate Address 22" hexmask.long.tbyte 0x14 0.--23. 1. "ALTA,Alternate Address" line.long 0x18 "C2_22,UC Control 2 22" hexmask.long.byte 0x18 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0x18 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0x18 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" group.long 0x300++0x1B line.long 0x0 "A23,UC A 23" rbitfld.long 0x0 31. "RISE_FALL,Rising and falling edge detection" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "A,A" line.long 0x4 "B23,UC B 23" hexmask.long.tbyte 0x4 0.--23. 1. "B,B" line.long 0x8 "CNT23,UC Counter 23" hexmask.long.tbyte 0x8 0.--23. 1. "C,Internal Counter Value" line.long 0xC "C23,UC Control 23" bitfld.long 0xC 31. "FREN,Freeze Enable" "0: Disable,1: Enable" bitfld.long 0xC 30. "ODIS,Output Disable" "0: Enables output pin (the output pin operates..,1: Disables output pin" newline bitfld.long 0xC 28.--29. "ODISSL,Output Disable Select" "0: 0,1: 1,2: 2,3: 3" bitfld.long 0xC 26.--27. "UCPRE,Prescaler" "0: 1,1: 2,2: 3,3: 4" newline bitfld.long 0xC 25. "UCPREN,Prescaler Enable" "0: Disable (no clock),1: Enable" bitfld.long 0xC 24. "DMA,Direct Memory Access" "0: Interrupt request,1: DMA request" newline hexmask.long.byte 0xC 19.--22. 1. "IF,Input Filter" bitfld.long 0xC 18. "FCK,Filter Clock Select" "0: Prescaled clock,1: eMIOS module clock" newline bitfld.long 0xC 17. "FEN,Flag Enable" "0: Disable,1: Enable" bitfld.long 0xC 13. "FORCMA,Force Match A" "0: No effect,1: Force a match at comparator A" newline bitfld.long 0xC 12. "FORCMB,Force Match B" "0: No effect,1: Force a match at comparator B" bitfld.long 0xC 9.--10. "BSL,Bus Select" "0,1,2,3" newline bitfld.long 0xC 8. "EDSEL,Edge Selection" "0,1" bitfld.long 0xC 7. "EDPOL,Edge Polarity" "0,1" newline hexmask.long.byte 0xC 0.--6. 1. "MODE,Mode Selection" line.long 0x10 "S23,UC Status 23" eventfld.long 0x10 31. "OVR,Overrun" "0: No overrun,1: Overrun" eventfld.long 0x10 15. "OVFL,Overflow" "0: No overflow,1: Overflow" newline rbitfld.long 0x10 2. "UCIN,UC Input Pin" "0: Negated,1: Asserted" rbitfld.long 0x10 1. "UCOUT,UC Output Pin" "0: Negated,1: Asserted" newline eventfld.long 0x10 0. "FLAG,Flag" "0: No event,1: Event has occurred" line.long 0x14 "ALTA23,Alternate Address 23" hexmask.long.tbyte 0x14 0.--23. 1. "ALTA,Alternate Address" line.long 0x18 "C2_23,UC Control 2 23" hexmask.long.byte 0x18 16.--19. 1. "UCEXTPRE,Extended Prescaler" bitfld.long 0x18 14. "UCPRECLK,Prescaler Clock Source" "0: Prescaled clock,1: eMIOS module clock" newline hexmask.long.byte 0x18 0.--4. 1. "UCRELDEL_INT,Reload Signal Output Delay Interval" tree.end tree.end tree "ERM (Error Reporting Module)" base ad:0x0 tree "ERM_0" base ad:0x4025C000 group.long 0x0++0xB line.long 0x0 "CR0,ERM Configuration Register 0" bitfld.long 0x0 31. "ESCIE0,ESCIE0" "0: Interrupt notification of Memory 0 single-bit..,1: Interrupt notification of Memory 0 single-bit.." bitfld.long 0x0 30. "ENCIE0,ENCIE0" "0: Interrupt notification of Memory 0..,1: Interrupt notification of Memory 0.." newline bitfld.long 0x0 27. "ESCIE1,ESCIE1" "0: Interrupt notification of Memory 1 single-bit..,1: Interrupt notification of Memory 1 single-bit.." bitfld.long 0x0 26. "ENCIE1,ENCIE1" "0: Interrupt notification of Memory 1..,1: Interrupt notification of Memory 1.." newline bitfld.long 0x0 23. "ESCIE2,ESCIE2" "0: Interrupt notification of Memory 2 single-bit..,1: Interrupt notification of Memory 2 single-bit.." bitfld.long 0x0 22. "ENCIE2,ENCIE2" "0: Interrupt notification of Memory 2..,1: Interrupt notification of Memory 2.." newline bitfld.long 0x0 19. "ESCIE3,ESCIE3" "0: Interrupt notification of Memory 3 single-bit..,1: Interrupt notification of Memory 3 single-bit.." bitfld.long 0x0 18. "ENCIE3,ENCIE3" "0: Interrupt notification of Memory 3..,1: Interrupt notification of Memory 3.." newline bitfld.long 0x0 15. "ESCIE4,ESCIE4" "0: Interrupt notification of Memory 4 single-bit..,1: Interrupt notification of Memory 4 single-bit.." bitfld.long 0x0 14. "ENCIE4,ENCIE4" "0: Interrupt notification of Memory 4..,1: Interrupt notification of Memory 4.." newline bitfld.long 0x0 11. "ESCIE5,ESCIE5" "0: Interrupt notification of Memory 5 single-bit..,1: Interrupt notification of Memory 5 single-bit.." bitfld.long 0x0 10. "ENCIE5,ENCIE5" "0: Interrupt notification of Memory 5..,1: Interrupt notification of Memory 5.." newline bitfld.long 0x0 7. "ESCIE6,ESCIE6" "0: Interrupt notification of Memory 6 single-bit..,1: Interrupt notification of Memory 6 single-bit.." bitfld.long 0x0 6. "ENCIE6,ENCIE6" "0: Interrupt notification of Memory 6..,1: Interrupt notification of Memory 6.." newline bitfld.long 0x0 3. "ESCIE7,ESCIE7" "0: Interrupt notification of Memory 7 single-bit..,1: Interrupt notification of Memory 7 single-bit.." bitfld.long 0x0 2. "ENCIE7,ENCIE7" "0: Interrupt notification of Memory 7..,1: Interrupt notification of Memory 7.." line.long 0x4 "CR1,ERM Configuration Register 1" bitfld.long 0x4 31. "ESCIE8,ESCIE8" "0: Interrupt notification of Memory 8 single-bit..,1: Interrupt notification of Memory 8 single-bit.." bitfld.long 0x4 30. "ENCIE8,ENCIE8" "0: Interrupt notification of Memory 8..,1: Interrupt notification of Memory 8.." newline bitfld.long 0x4 27. "ESCIE9,ESCIE9" "0: Interrupt notification of Memory 9 single-bit..,1: Interrupt notification of Memory 9 single-bit.." bitfld.long 0x4 26. "ENCIE9,ENCIE9" "0: Interrupt notification of Memory 9..,1: Interrupt notification of Memory 9.." newline bitfld.long 0x4 23. "ESCIE10,ESCIE10" "0: Interrupt notification of Memory 10 single-bit..,1: Interrupt notification of Memory 10 single-bit.." bitfld.long 0x4 22. "ENCIE10,ENCIE10" "0: Interrupt notification of Memory 10..,1: Interrupt notification of Memory 10.." newline bitfld.long 0x4 19. "ESCIE11,ESCIE11" "0: Interrupt notification of Memory 11 single-bit..,1: Interrupt notification of Memory 11 single-bit.." bitfld.long 0x4 18. "ENCIE11,ENCIE11" "0: Interrupt notification of Memory 11..,1: Interrupt notification of Memory 11.." newline bitfld.long 0x4 15. "ESCIE12,ESCIE12" "0: Interrupt notification of Memory 12 single-bit..,1: Interrupt notification of Memory 12 single-bit.." bitfld.long 0x4 14. "ENCIE12,ENCIE12" "0: Interrupt notification of Memory 12..,1: Interrupt notification of Memory 12.." newline bitfld.long 0x4 11. "ESCIE13,ESCIE13" "0: Interrupt notification of Memory 13 single-bit..,1: Interrupt notification of Memory 13 single-bit.." bitfld.long 0x4 10. "ENCIE13,ENCIE13" "0: Interrupt notification of Memory 13..,1: Interrupt notification of Memory 13.." newline bitfld.long 0x4 7. "ESCIE14,ESCIE14" "0: Interrupt notification of Memory 14 single-bit..,1: Interrupt notification of Memory 14 single-bit.." bitfld.long 0x4 6. "ENCIE14,ENCIE14" "0: Interrupt notification of Memory 14..,1: Interrupt notification of Memory 14.." newline bitfld.long 0x4 3. "ESCIE15,ESCIE15" "0: Interrupt notification of Memory 15 single-bit..,1: Interrupt notification of Memory 15 single-bit.." bitfld.long 0x4 2. "ENCIE15,ENCIE15" "0: Interrupt notification of Memory 15..,1: Interrupt notification of Memory 15.." line.long 0x8 "CR2,ERM Configuration Register 2" bitfld.long 0x8 31. "ESCIE16,ESCIE16" "0: Interrupt notification of Memory 16 single-bit..,1: Interrupt notification of Memory 16 single-bit.." bitfld.long 0x8 30. "ENCIE16,ENCIE16" "0: Interrupt notification of Memory 16..,1: Interrupt notification of Memory 16.." newline bitfld.long 0x8 27. "ESCIE17,ESCIE17" "0: Interrupt notification of Memory 17 single-bit..,1: Interrupt notification of Memory 17 single-bit.." bitfld.long 0x8 26. "ENCIE17,ENCIE17" "0: Interrupt notification of Memory 17..,1: Interrupt notification of Memory 17.." newline bitfld.long 0x8 23. "ESCIE18,ESCIE18" "0: Interrupt notification of Memory 18 single-bit..,1: Interrupt notification of Memory 18 single-bit.." bitfld.long 0x8 22. "ENCIE18,ENCIE18" "0: Interrupt notification of Memory 18..,1: Interrupt notification of Memory 18.." newline bitfld.long 0x8 19. "ESCIE19,ESCIE19" "0: Interrupt notification of Memory 19 single-bit..,1: Interrupt notification of Memory 19 single-bit.." bitfld.long 0x8 18. "ENCIE19,ENCIE19" "0: Interrupt notification of Memory 19..,1: Interrupt notification of Memory 19.." group.long 0x10++0xB line.long 0x0 "SR0,ERM Status Register 0" eventfld.long 0x0 31. "SBC0,SBC0" "0: No single-bit correction event on Memory 0..,1: Single-bit correction event on Memory 0 detected." eventfld.long 0x0 30. "NCE0,NCE0" "0: No non-correctable error event on Memory 0..,1: Non-correctable error event on Memory 0 detected." newline eventfld.long 0x0 27. "SBC1,SBC1" "0: No single-bit correction event on Memory 1..,1: Single-bit correction event on Memory 1 detected." eventfld.long 0x0 26. "NCE1,NCE1" "0: No non-correctable error event on Memory 1..,1: Non-correctable error event on Memory 1 detected." newline eventfld.long 0x0 23. "SBC2,SBC2" "0: No single-bit correction event on Memory 2..,1: Single-bit correction event on Memory 2 detected." eventfld.long 0x0 22. "NCE2,NCE2" "0: No non-correctable error event on Memory 2..,1: Non-correctable error event on Memory 2 detected." newline eventfld.long 0x0 19. "SBC3,SBC3" "0: No single-bit correction event on Memory 3..,1: Single-bit correction event on Memory 3 detected." eventfld.long 0x0 18. "NCE3,NCE3" "0: No non-correctable error event on Memory 3..,1: Non-correctable error event on Memory 3 detected." newline eventfld.long 0x0 15. "SBC4,SBC4" "0: No single-bit correction event on Memory 4..,1: Single-bit correction event on Memory 4 detected." eventfld.long 0x0 14. "NCE4,NCE4" "0: No non-correctable error event on Memory 4..,1: Non-correctable error event on Memory 4 detected." newline eventfld.long 0x0 11. "SBC5,SBC5" "0: No single-bit correction event on Memory 5..,1: Single-bit correction event on Memory 5 detected." eventfld.long 0x0 10. "NCE5,NCE5" "0: No non-correctable error event on Memory 5..,1: Non-correctable error event on Memory 5 detected." newline eventfld.long 0x0 7. "SBC6,SBC6" "0: No single-bit correction event on Memory 6..,1: Single-bit correction event on Memory 6 detected." eventfld.long 0x0 6. "NCE6,NCE6" "0: No non-correctable error event on Memory 6..,1: Non-correctable error event on Memory 6 detected." newline eventfld.long 0x0 3. "SBC7,SBC7" "0: No single-bit correction event on Memory 7..,1: Single-bit correction event on Memory 7 detected." eventfld.long 0x0 2. "NCE7,NCE7" "0: No non-correctable error event on Memory 7..,1: Non-correctable error event on Memory 7 detected." line.long 0x4 "SR1,ERM Status Register 1" eventfld.long 0x4 31. "SBC8,SBC8" "0: No single-bit correction event on Memory 8..,1: Single-bit correction event on Memory 8 detected." eventfld.long 0x4 30. "NCE8,NCE8" "0: No non-correctable error event on Memory 8..,1: Non-correctable error event on Memory 8 detected." newline eventfld.long 0x4 27. "SBC9,SBC9" "0: No single-bit correction event on Memory 9..,1: Single-bit correction event on Memory 9 detected." eventfld.long 0x4 26. "NCE9,NCE9" "0: No non-correctable error event on Memory 9..,1: Non-correctable error event on Memory 9 detected." newline eventfld.long 0x4 23. "SBC10,SBC10" "0: No single-bit correction event on Memory 10..,1: Single-bit correction event on Memory 10 detected." eventfld.long 0x4 22. "NCE10,NCE10" "0: No non-correctable error event on Memory 10..,1: Non-correctable error event on Memory 10 detected." newline eventfld.long 0x4 19. "SBC11,SBC11" "0: No single-bit correction event on Memory 11..,1: Single-bit correction event on Memory 11 detected." eventfld.long 0x4 18. "NCE11,NCE11" "0: No non-correctable error event on Memory 11..,1: Non-correctable error event on Memory 11 detected." newline eventfld.long 0x4 15. "SBC12,SBC12" "0: No single-bit correction event on Memory 12..,1: Single-bit correction event on Memory 12 detected." eventfld.long 0x4 14. "NCE12,NCE12" "0: No non-correctable error event on Memory 12..,1: Non-correctable error event on Memory 12 detected." newline eventfld.long 0x4 11. "SBC13,SBC13" "0: No single-bit correction event on Memory 13..,1: Single-bit correction event on Memory 13 detected." eventfld.long 0x4 10. "NCE13,NCE13" "0: No non-correctable error event on Memory 13..,1: Non-correctable error event on Memory 13 detected." newline eventfld.long 0x4 7. "SBC14,SBC14" "0: No single-bit correction event on Memory 14..,1: Single-bit correction event on Memory 14 detected." eventfld.long 0x4 6. "NCE14,NCE14" "0: No non-correctable error event on Memory 14..,1: Non-correctable error event on Memory 14 detected." newline eventfld.long 0x4 3. "SBC15,SBC15" "0: No single-bit correction event on Memory 15..,1: Single-bit correction event on Memory 15 detected." eventfld.long 0x4 2. "NCE15,NCE15" "0: No non-correctable error event on Memory 15..,1: Non-correctable error event on Memory 15 detected." line.long 0x8 "SR2,ERM Status Register 2" eventfld.long 0x8 31. "SBC16,SBC16" "0: No single-bit correction event on Memory 16..,1: Single-bit correction event on Memory 16 detected." eventfld.long 0x8 30. "NCE16,NCE16" "0: No non-correctable error event on Memory 16..,1: Non-correctable error event on Memory 16 detected." newline eventfld.long 0x8 27. "SBC17,SBC17" "0: No single-bit correction event on Memory 17..,1: Single-bit correction event on Memory 17 detected." eventfld.long 0x8 26. "NCE17,NCE17" "0: No non-correctable error event on Memory 17..,1: Non-correctable error event on Memory 17 detected." newline eventfld.long 0x8 23. "SBC18,SBC18" "0: No single-bit correction event on Memory 18..,1: Single-bit correction event on Memory 18 detected." eventfld.long 0x8 22. "NCE18,NCE18" "0: No non-correctable error event on Memory 18..,1: Non-correctable error event on Memory 18 detected." newline eventfld.long 0x8 19. "SBC19,SBC19" "0: No single-bit correction event on Memory 19..,1: Single-bit correction event on Memory 19 detected." eventfld.long 0x8 18. "NCE19,NCE19" "0: No non-correctable error event on Memory 19..,1: Non-correctable error event on Memory 19 detected." rgroup.long 0x100++0x7 line.long 0x0 "EAR0,ERM Memory 0 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN0,ERM Memory 0 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x108++0x3 line.long 0x0 "CORR_ERR_CNT0,ERM Memory 0 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x110++0x7 line.long 0x0 "EAR1,ERM Memory 1 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN1,ERM Memory 1 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x118++0x3 line.long 0x0 "CORR_ERR_CNT1,ERM Memory 1 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" group.long 0x128++0x3 line.long 0x0 "CORR_ERR_CNT2,ERM Memory 2 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" group.long 0x138++0x3 line.long 0x0 "CORR_ERR_CNT3,ERM Memory 3 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" group.long 0x148++0x3 line.long 0x0 "CORR_ERR_CNT4,ERM Memory 4 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" group.long 0x158++0x3 line.long 0x0 "CORR_ERR_CNT5,ERM Memory 5 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" group.long 0x168++0x3 line.long 0x0 "CORR_ERR_CNT6,ERM Memory 6 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" group.long 0x178++0x3 line.long 0x0 "CORR_ERR_CNT7,ERM Memory 7 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" group.long 0x188++0x3 line.long 0x0 "CORR_ERR_CNT8,ERM Memory 8 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" group.long 0x198++0x3 line.long 0x0 "CORR_ERR_CNT9,ERM Memory 9 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1A0++0x7 line.long 0x0 "EAR10,ERM Memory 10 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN10,ERM Memory 10 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1A8++0x3 line.long 0x0 "CORR_ERR_CNT10,ERM Memory 10 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1B0++0x7 line.long 0x0 "EAR11,ERM Memory 11 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN11,ERM Memory 11 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1B8++0x3 line.long 0x0 "CORR_ERR_CNT11,ERM Memory 11 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1C0++0x7 line.long 0x0 "EAR12,ERM Memory 12 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN12,ERM Memory 12 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1C8++0x3 line.long 0x0 "CORR_ERR_CNT12,ERM Memory 12 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1D0++0x7 line.long 0x0 "EAR13,ERM Memory 13 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN13,ERM Memory 13 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1D8++0x3 line.long 0x0 "CORR_ERR_CNT13,ERM Memory 13 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1E0++0x7 line.long 0x0 "EAR14,ERM Memory 14 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN14,ERM Memory 14 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1E8++0x3 line.long 0x0 "CORR_ERR_CNT14,ERM Memory 14 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1F0++0x7 line.long 0x0 "EAR15,ERM Memory 15 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN15,ERM Memory 15 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1F8++0x3 line.long 0x0 "CORR_ERR_CNT15,ERM Memory 15 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x200++0x7 line.long 0x0 "EAR16,ERM Memory 16 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN16,ERM Memory 16 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x208++0x3 line.long 0x0 "CORR_ERR_CNT16,ERM Memory 16 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x210++0x3 line.long 0x0 "EAR17,ERM Memory 17 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" group.long 0x218++0x3 line.long 0x0 "CORR_ERR_CNT17,ERM Memory 17 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x220++0x3 line.long 0x0 "EAR18,ERM Memory 18 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" group.long 0x228++0x3 line.long 0x0 "CORR_ERR_CNT18,ERM Memory 18 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x230++0x3 line.long 0x0 "EAR19,ERM Memory 19 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" group.long 0x238++0x3 line.long 0x0 "CORR_ERR_CNT19,ERM Memory 19 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" tree.end tree "ERM_1" base ad:0x4000C000 group.long 0x0++0xB line.long 0x0 "CR0,ERM Configuration Register 0" bitfld.long 0x0 31. "ESCIE0,ESCIE0" "0: Interrupt notification of Memory 0 single-bit..,1: Interrupt notification of Memory 0 single-bit.." bitfld.long 0x0 30. "ENCIE0,ENCIE0" "0: Interrupt notification of Memory 0..,1: Interrupt notification of Memory 0.." newline bitfld.long 0x0 27. "ESCIE1,ESCIE1" "0: Interrupt notification of Memory 1 single-bit..,1: Interrupt notification of Memory 1 single-bit.." bitfld.long 0x0 26. "ENCIE1,ENCIE1" "0: Interrupt notification of Memory 1..,1: Interrupt notification of Memory 1.." newline bitfld.long 0x0 23. "ESCIE2,ESCIE2" "0: Interrupt notification of Memory 2 single-bit..,1: Interrupt notification of Memory 2 single-bit.." bitfld.long 0x0 22. "ENCIE2,ENCIE2" "0: Interrupt notification of Memory 2..,1: Interrupt notification of Memory 2.." newline bitfld.long 0x0 19. "ESCIE3,ESCIE3" "0: Interrupt notification of Memory 3 single-bit..,1: Interrupt notification of Memory 3 single-bit.." bitfld.long 0x0 18. "ENCIE3,ENCIE3" "0: Interrupt notification of Memory 3..,1: Interrupt notification of Memory 3.." newline bitfld.long 0x0 15. "ESCIE4,ESCIE4" "0: Interrupt notification of Memory 4 single-bit..,1: Interrupt notification of Memory 4 single-bit.." bitfld.long 0x0 14. "ENCIE4,ENCIE4" "0: Interrupt notification of Memory 4..,1: Interrupt notification of Memory 4.." newline bitfld.long 0x0 11. "ESCIE5,ESCIE5" "0: Interrupt notification of Memory 5 single-bit..,1: Interrupt notification of Memory 5 single-bit.." bitfld.long 0x0 10. "ENCIE5,ENCIE5" "0: Interrupt notification of Memory 5..,1: Interrupt notification of Memory 5.." newline bitfld.long 0x0 7. "ESCIE6,ESCIE6" "0: Interrupt notification of Memory 6 single-bit..,1: Interrupt notification of Memory 6 single-bit.." bitfld.long 0x0 6. "ENCIE6,ENCIE6" "0: Interrupt notification of Memory 6..,1: Interrupt notification of Memory 6.." newline bitfld.long 0x0 3. "ESCIE7,ESCIE7" "0: Interrupt notification of Memory 7 single-bit..,1: Interrupt notification of Memory 7 single-bit.." bitfld.long 0x0 2. "ENCIE7,ENCIE7" "0: Interrupt notification of Memory 7..,1: Interrupt notification of Memory 7.." line.long 0x4 "CR1,ERM Configuration Register 1" bitfld.long 0x4 31. "ESCIE8,ESCIE8" "0: Interrupt notification of Memory 8 single-bit..,1: Interrupt notification of Memory 8 single-bit.." bitfld.long 0x4 30. "ENCIE8,ENCIE8" "0: Interrupt notification of Memory 8..,1: Interrupt notification of Memory 8.." newline bitfld.long 0x4 27. "ESCIE9,ESCIE9" "0: Interrupt notification of Memory 9 single-bit..,1: Interrupt notification of Memory 9 single-bit.." bitfld.long 0x4 26. "ENCIE9,ENCIE9" "0: Interrupt notification of Memory 9..,1: Interrupt notification of Memory 9.." newline bitfld.long 0x4 23. "ESCIE10,ESCIE10" "0: Interrupt notification of Memory 10 single-bit..,1: Interrupt notification of Memory 10 single-bit.." bitfld.long 0x4 22. "ENCIE10,ENCIE10" "0: Interrupt notification of Memory 10..,1: Interrupt notification of Memory 10.." newline bitfld.long 0x4 19. "ESCIE11,ESCIE11" "0: Interrupt notification of Memory 11 single-bit..,1: Interrupt notification of Memory 11 single-bit.." bitfld.long 0x4 18. "ENCIE11,ENCIE11" "0: Interrupt notification of Memory 11..,1: Interrupt notification of Memory 11.." newline bitfld.long 0x4 15. "ESCIE12,ESCIE12" "0: Interrupt notification of Memory 12 single-bit..,1: Interrupt notification of Memory 12 single-bit.." bitfld.long 0x4 14. "ENCIE12,ENCIE12" "0: Interrupt notification of Memory 12..,1: Interrupt notification of Memory 12.." newline bitfld.long 0x4 11. "ESCIE13,ESCIE13" "0: Interrupt notification of Memory 13 single-bit..,1: Interrupt notification of Memory 13 single-bit.." bitfld.long 0x4 10. "ENCIE13,ENCIE13" "0: Interrupt notification of Memory 13..,1: Interrupt notification of Memory 13.." newline bitfld.long 0x4 7. "ESCIE14,ESCIE14" "0: Interrupt notification of Memory 14 single-bit..,1: Interrupt notification of Memory 14 single-bit.." bitfld.long 0x4 6. "ENCIE14,ENCIE14" "0: Interrupt notification of Memory 14..,1: Interrupt notification of Memory 14.." newline bitfld.long 0x4 3. "ESCIE15,ESCIE15" "0: Interrupt notification of Memory 15 single-bit..,1: Interrupt notification of Memory 15 single-bit.." bitfld.long 0x4 2. "ENCIE15,ENCIE15" "0: Interrupt notification of Memory 15..,1: Interrupt notification of Memory 15.." line.long 0x8 "CR2,ERM Configuration Register 2" bitfld.long 0x8 31. "ESCIE16,ESCIE16" "0: Interrupt notification of Memory 16 single-bit..,1: Interrupt notification of Memory 16 single-bit.." bitfld.long 0x8 30. "ENCIE16,ENCIE16" "0: Interrupt notification of Memory 16..,1: Interrupt notification of Memory 16.." newline bitfld.long 0x8 27. "ESCIE17,ESCIE17" "0: Interrupt notification of Memory 17 single-bit..,1: Interrupt notification of Memory 17 single-bit.." bitfld.long 0x8 26. "ENCIE17,ENCIE17" "0: Interrupt notification of Memory 17..,1: Interrupt notification of Memory 17.." newline bitfld.long 0x8 23. "ESCIE18,ESCIE18" "0: Interrupt notification of Memory 18 single-bit..,1: Interrupt notification of Memory 18 single-bit.." bitfld.long 0x8 22. "ENCIE18,ENCIE18" "0: Interrupt notification of Memory 18..,1: Interrupt notification of Memory 18.." newline bitfld.long 0x8 19. "ESCIE19,ESCIE19" "0: Interrupt notification of Memory 19 single-bit..,1: Interrupt notification of Memory 19 single-bit.." bitfld.long 0x8 18. "ENCIE19,ENCIE19" "0: Interrupt notification of Memory 19..,1: Interrupt notification of Memory 19.." group.long 0x10++0xB line.long 0x0 "SR0,ERM Status Register 0" eventfld.long 0x0 31. "SBC0,SBC0" "0: No single-bit correction event on Memory 0..,1: Single-bit correction event on Memory 0 detected." eventfld.long 0x0 30. "NCE0,NCE0" "0: No non-correctable error event on Memory 0..,1: Non-correctable error event on Memory 0 detected." newline eventfld.long 0x0 27. "SBC1,SBC1" "0: No single-bit correction event on Memory 1..,1: Single-bit correction event on Memory 1 detected." eventfld.long 0x0 26. "NCE1,NCE1" "0: No non-correctable error event on Memory 1..,1: Non-correctable error event on Memory 1 detected." newline eventfld.long 0x0 23. "SBC2,SBC2" "0: No single-bit correction event on Memory 2..,1: Single-bit correction event on Memory 2 detected." eventfld.long 0x0 22. "NCE2,NCE2" "0: No non-correctable error event on Memory 2..,1: Non-correctable error event on Memory 2 detected." newline eventfld.long 0x0 19. "SBC3,SBC3" "0: No single-bit correction event on Memory 3..,1: Single-bit correction event on Memory 3 detected." eventfld.long 0x0 18. "NCE3,NCE3" "0: No non-correctable error event on Memory 3..,1: Non-correctable error event on Memory 3 detected." newline eventfld.long 0x0 15. "SBC4,SBC4" "0: No single-bit correction event on Memory 4..,1: Single-bit correction event on Memory 4 detected." eventfld.long 0x0 14. "NCE4,NCE4" "0: No non-correctable error event on Memory 4..,1: Non-correctable error event on Memory 4 detected." newline eventfld.long 0x0 11. "SBC5,SBC5" "0: No single-bit correction event on Memory 5..,1: Single-bit correction event on Memory 5 detected." eventfld.long 0x0 10. "NCE5,NCE5" "0: No non-correctable error event on Memory 5..,1: Non-correctable error event on Memory 5 detected." newline eventfld.long 0x0 7. "SBC6,SBC6" "0: No single-bit correction event on Memory 6..,1: Single-bit correction event on Memory 6 detected." eventfld.long 0x0 6. "NCE6,NCE6" "0: No non-correctable error event on Memory 6..,1: Non-correctable error event on Memory 6 detected." newline eventfld.long 0x0 3. "SBC7,SBC7" "0: No single-bit correction event on Memory 7..,1: Single-bit correction event on Memory 7 detected." eventfld.long 0x0 2. "NCE7,NCE7" "0: No non-correctable error event on Memory 7..,1: Non-correctable error event on Memory 7 detected." line.long 0x4 "SR1,ERM Status Register 1" eventfld.long 0x4 31. "SBC8,SBC8" "0: No single-bit correction event on Memory 8..,1: Single-bit correction event on Memory 8 detected." eventfld.long 0x4 30. "NCE8,NCE8" "0: No non-correctable error event on Memory 8..,1: Non-correctable error event on Memory 8 detected." newline eventfld.long 0x4 27. "SBC9,SBC9" "0: No single-bit correction event on Memory 9..,1: Single-bit correction event on Memory 9 detected." eventfld.long 0x4 26. "NCE9,NCE9" "0: No non-correctable error event on Memory 9..,1: Non-correctable error event on Memory 9 detected." newline eventfld.long 0x4 23. "SBC10,SBC10" "0: No single-bit correction event on Memory 10..,1: Single-bit correction event on Memory 10 detected." eventfld.long 0x4 22. "NCE10,NCE10" "0: No non-correctable error event on Memory 10..,1: Non-correctable error event on Memory 10 detected." newline eventfld.long 0x4 19. "SBC11,SBC11" "0: No single-bit correction event on Memory 11..,1: Single-bit correction event on Memory 11 detected." eventfld.long 0x4 18. "NCE11,NCE11" "0: No non-correctable error event on Memory 11..,1: Non-correctable error event on Memory 11 detected." newline eventfld.long 0x4 15. "SBC12,SBC12" "0: No single-bit correction event on Memory 12..,1: Single-bit correction event on Memory 12 detected." eventfld.long 0x4 14. "NCE12,NCE12" "0: No non-correctable error event on Memory 12..,1: Non-correctable error event on Memory 12 detected." newline eventfld.long 0x4 11. "SBC13,SBC13" "0: No single-bit correction event on Memory 13..,1: Single-bit correction event on Memory 13 detected." eventfld.long 0x4 10. "NCE13,NCE13" "0: No non-correctable error event on Memory 13..,1: Non-correctable error event on Memory 13 detected." newline eventfld.long 0x4 7. "SBC14,SBC14" "0: No single-bit correction event on Memory 14..,1: Single-bit correction event on Memory 14 detected." eventfld.long 0x4 6. "NCE14,NCE14" "0: No non-correctable error event on Memory 14..,1: Non-correctable error event on Memory 14 detected." newline eventfld.long 0x4 3. "SBC15,SBC15" "0: No single-bit correction event on Memory 15..,1: Single-bit correction event on Memory 15 detected." eventfld.long 0x4 2. "NCE15,NCE15" "0: No non-correctable error event on Memory 15..,1: Non-correctable error event on Memory 15 detected." line.long 0x8 "SR2,ERM Status Register 2" eventfld.long 0x8 31. "SBC16,SBC16" "0: No single-bit correction event on Memory 16..,1: Single-bit correction event on Memory 16 detected." eventfld.long 0x8 30. "NCE16,NCE16" "0: No non-correctable error event on Memory 16..,1: Non-correctable error event on Memory 16 detected." newline eventfld.long 0x8 27. "SBC17,SBC17" "0: No single-bit correction event on Memory 17..,1: Single-bit correction event on Memory 17 detected." eventfld.long 0x8 26. "NCE17,NCE17" "0: No non-correctable error event on Memory 17..,1: Non-correctable error event on Memory 17 detected." newline eventfld.long 0x8 23. "SBC18,SBC18" "0: No single-bit correction event on Memory 18..,1: Single-bit correction event on Memory 18 detected." eventfld.long 0x8 22. "NCE18,NCE18" "0: No non-correctable error event on Memory 18..,1: Non-correctable error event on Memory 18 detected." newline eventfld.long 0x8 19. "SBC19,SBC19" "0: No single-bit correction event on Memory 19..,1: Single-bit correction event on Memory 19 detected." eventfld.long 0x8 18. "NCE19,NCE19" "0: No non-correctable error event on Memory 19..,1: Non-correctable error event on Memory 19 detected." rgroup.long 0x100++0x7 line.long 0x0 "EAR0,ERM Memory 0 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN0,ERM Memory 0 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x108++0x3 line.long 0x0 "CORR_ERR_CNT0,ERM Memory 0 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" group.long 0x118++0x3 line.long 0x0 "CORR_ERR_CNT1,ERM Memory 1 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" group.long 0x128++0x3 line.long 0x0 "CORR_ERR_CNT2,ERM Memory 2 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" group.long 0x138++0x3 line.long 0x0 "CORR_ERR_CNT3,ERM Memory 3 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" group.long 0x148++0x3 line.long 0x0 "CORR_ERR_CNT4,ERM Memory 4 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" group.long 0x158++0x3 line.long 0x0 "CORR_ERR_CNT5,ERM Memory 5 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" group.long 0x168++0x3 line.long 0x0 "CORR_ERR_CNT6,ERM Memory 6 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" group.long 0x178++0x3 line.long 0x0 "CORR_ERR_CNT7,ERM Memory 7 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" group.long 0x188++0x3 line.long 0x0 "CORR_ERR_CNT8,ERM Memory 8 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" group.long 0x198++0x3 line.long 0x0 "CORR_ERR_CNT9,ERM Memory 9 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1A0++0x7 line.long 0x0 "EAR10,ERM Memory 10 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN10,ERM Memory 10 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1A8++0x3 line.long 0x0 "CORR_ERR_CNT10,ERM Memory 10 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1B0++0x7 line.long 0x0 "EAR11,ERM Memory 11 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN11,ERM Memory 11 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1B8++0x3 line.long 0x0 "CORR_ERR_CNT11,ERM Memory 11 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1C0++0x7 line.long 0x0 "EAR12,ERM Memory 12 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN12,ERM Memory 12 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1C8++0x3 line.long 0x0 "CORR_ERR_CNT12,ERM Memory 12 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1D0++0x7 line.long 0x0 "EAR13,ERM Memory 13 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN13,ERM Memory 13 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1D8++0x3 line.long 0x0 "CORR_ERR_CNT13,ERM Memory 13 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1E0++0x7 line.long 0x0 "EAR14,ERM Memory 14 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN14,ERM Memory 14 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1E8++0x3 line.long 0x0 "CORR_ERR_CNT14,ERM Memory 14 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x1F0++0x7 line.long 0x0 "EAR15,ERM Memory 15 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN15,ERM Memory 15 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x1F8++0x3 line.long 0x0 "CORR_ERR_CNT15,ERM Memory 15 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" group.long 0x208++0x3 line.long 0x0 "CORR_ERR_CNT16,ERM Memory 16 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x210++0x3 line.long 0x0 "EAR17,ERM Memory 17 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" group.long 0x218++0x3 line.long 0x0 "CORR_ERR_CNT17,ERM Memory 17 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x220++0x7 line.long 0x0 "EAR18,ERM Memory 18 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN18,ERM Memory 18 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x228++0x3 line.long 0x0 "CORR_ERR_CNT18,ERM Memory 18 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" rgroup.long 0x230++0x7 line.long 0x0 "EAR19,ERM Memory 19 Error Address Register" hexmask.long 0x0 0.--31. 1. "EAR,EAR" line.long 0x4 "SYN19,ERM Memory 19 Syndrome Register" hexmask.long.byte 0x4 24.--31. 1. "SYNDROME,SYNDROME" group.long 0x238++0x3 line.long 0x0 "CORR_ERR_CNT19,ERM Memory 19 Correctable Error Count Register" hexmask.long.byte 0x0 0.--7. 1. "COUNT,Memory n Correctable Error Count" tree.end tree.end tree "FCCU (Fault Collection and Control Unit)" base ad:0x40384000 group.long 0x0++0x3 line.long 0x0 "CTRL,Control" bitfld.long 0x0 9. "DEBUG,Debug Mode Enable" "0: Disabled,1: Enabled" newline rbitfld.long 0x0 6.--7. "OPS,Operation Status" "0: Idle,1: In progress,2: Aborted,3: Successful" newline hexmask.long.byte 0x0 0.--4. 1. "OPR,Operation Run" wgroup.long 0x4++0x3 line.long 0x0 "CTRLK,Control Key" hexmask.long 0x0 0.--31. 1. "CTRLK,Locked-Operation Control Key" group.long 0x8++0x3 line.long 0x0 "CFG,Configuration" bitfld.long 0x0 24. "FCCU_SET_AFTER_RESET,Fault-Output (EOUT) Activate" "0: Inactive (the EOUT signals are in a..,1: Active (the EOUT signals indicate FCCU's.." newline bitfld.long 0x0 22.--23. "FCCU_SET_CLEAR,Fault-Output (EOUT) Control" "0: Controlled by the FSM,1: Always low,2: Controlled by the FSM,3: High until a fault occurs on a channel.." newline bitfld.long 0x0 11. "CM,Fault-Output (EOUT) Configuration-Indication Mode" "0: Different,1: Same" newline bitfld.long 0x0 9. "PS,Fault-Output (EOUT) Polarity Selection" "0: For the faulty indication EOUT1 is high and..,1: For the faulty indication EOUT1 is low and EOUT0.." newline bitfld.long 0x0 6.--8. "FOM,Fault-Output (EOUT) Mode" "?,?,2: Bi-Stable,3: Fault-Toggle,?,5: Test 0 (controlled by the EINOUT register; EOUT1..,6: Test 1 (controlled by the EINOUT register; EOUT1..,7: Test 2 (controlled by the EINOUT register; EOUT1.." group.long 0x1C++0x3 line.long 0x0 "NCF_CFG0,Non-critical Fault Configuration" bitfld.long 0x0 7. "NCFC7,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x0 6. "NCFC6,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x0 5. "NCFC5,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x0 4. "NCFC4,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x0 3. "NCFC3,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x0 2. "NCFC2,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x0 1. "NCFC1,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" newline bitfld.long 0x0 0. "NCFC0,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable" group.long 0x4C++0x3 line.long 0x0 "NCFS_CFG0,Non-critical Fault-State Configuration" bitfld.long 0x0 14.--15. "NCFSC7,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x0 12.--13. "NCFSC6,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x0 10.--11. "NCFSC5,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x0 8.--9. "NCFSC4,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x0 6.--7. "NCFSC3,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x0 4.--5. "NCFSC2,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x0 2.--3. "NCFSC1,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" newline bitfld.long 0x0 0.--1. "NCFSC0,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),?,3: Disabled" group.long 0x80++0x3 line.long 0x0 "NCF_S0,Non-critical Fault Status" eventfld.long 0x0 7. "NCFS7,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" newline eventfld.long 0x0 6. "NCFS6,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" newline eventfld.long 0x0 5. "NCFS5,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" newline eventfld.long 0x0 4. "NCFS4,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" newline eventfld.long 0x0 3. "NCFS3,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" newline eventfld.long 0x0 2. "NCFS2,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" newline eventfld.long 0x0 1. "NCFS1,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" newline eventfld.long 0x0 0. "NCFS0,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault" group.long 0x90++0x7 line.long 0x0 "NCFK,Non-critical Fault Key" hexmask.long 0x0 0.--31. 1. "NCFK,Non-critical Fault Key" line.long 0x4 "NCF_E0,Non-critical Fault Enable" bitfld.long 0x4 7. "NCFE7,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 6. "NCFE6,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 5. "NCFE5,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 4. "NCFE4,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 3. "NCFE3,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 2. "NCFE2,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 1. "NCFE1,Non-critical Fault Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 0. "NCFE0,Non-critical Fault Enable n" "0: Disabled,1: Enabled" group.long 0xA4++0x3 line.long 0x0 "NCF_TOE0,Non-critical-Fault Alarm-State Timeout Enable" bitfld.long 0x0 7. "NCFTOE7,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 6. "NCFTOE6,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 5. "NCFTOE5,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 4. "NCFTOE4,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 3. "NCFTOE3,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 2. "NCFTOE2,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 1. "NCFTOE1,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 0. "NCFTOE0,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled" group.long 0xB4++0xB line.long 0x0 "NCF_TO,Non-critical-Fault Alarm-State Timeout Interval" hexmask.long 0x0 0.--31. 1. "TO,Non-critical-Fault Alarm-State Timeout Interval" line.long 0x4 "CFG_TO,Configuration-State Timeout Interval" bitfld.long 0x4 0.--2. "TO,Configuration-State Timeout Interval" "0,1,2,3,4,5,6,7" line.long 0x8 "EINOUT,IO Control" rbitfld.long 0x8 5. "EIN1,Error Input 1" "0: Low,1: High" newline rbitfld.long 0x8 4. "EIN0,Error Input 0" "0: Low,1: High" newline bitfld.long 0x8 1. "EOUT1,EOUT1" "0: force EOUT[1] = 0,1: force EOUT[1] = 1" newline bitfld.long 0x8 0. "EOUT0,EOUT0" "0: force EOUT[0] = 0,1: force EOUT[0] = 1" rgroup.long 0xC0++0x13 line.long 0x0 "STAT,Status" bitfld.long 0x0 4.--5. "PhysicErrorPin,EOUT Signal States" "0: EOUT1 is low; EOUT0 is low.,1: EOUT1 is low; EOUT0 is high.,2: EOUT1 is high; EOUT0 is low.,3: EOUT1 is high; EOUT0 is high." newline bitfld.long 0x0 3. "ESTAT,FCCU Faulty Condition" "0: Not in faulty condition (in non-faulty or..,1: In faulty condition" newline bitfld.long 0x0 0.--2. "STATUS,FCCU State" "0: NORMAL,1: CONFIG,2: ALARM,3: FAULT,?,?,?,?" line.long 0x4 "N2AF_STATUS,Normal-to-Alarm Freeze Status" hexmask.long.byte 0x4 0.--7. 1. "NAFS,Normal-to-Alarm Freeze Status" line.long 0x8 "A2FF_STATUS,Alarm-to-Fault Freeze Status" bitfld.long 0x8 8.--9. "AF_SRC,Alarm-to-Fault Source" "0: No Alarm-to-Fault-state fault,?,2: Non-critical fault,3: Multiple Alarm-to-Fault-state faults" newline hexmask.long.byte 0x8 0.--7. 1. "AFFS,Alarm-to-Fault Freeze Status" line.long 0xC "N2FF_STATUS,Normal-to-Fault Freeze Status" bitfld.long 0xC 8.--9. "NF_SRC,Normal-to-Fault Source" "0: No Normal-to-Fault-state fault,?,2: Non-critical fault,3: Multiple Normal-to-Fault-state faults" newline hexmask.long.byte 0xC 0.--7. 1. "NFFS,Normal-to-Fault Freeze Status" line.long 0x10 "F2AF_STATUS,Fault-to-Alarm Freeze Status" hexmask.long.word 0x10 0.--8. 1. "FAFS,Fault-to-Alarm Freeze Status" wgroup.long 0xDC++0x3 line.long 0x0 "NCFF,Non-critical Fault Fake" hexmask.long.byte 0x0 0.--6. 1. "FNCFC,FNCFC" group.long 0xE0++0x7 line.long 0x0 "IRQ_STAT,IRQ Status" rbitfld.long 0x0 2. "NMI_STAT,NMI Interrupt Status" "0: NMI interrupt is OFF,1: NMI interrupt is ON" newline rbitfld.long 0x0 1. "ALRM_STAT,Alarm Interrupt Status" "0: Alarm interrupt is OFF,1: Alarm interrupt is ON" newline eventfld.long 0x0 0. "CFG_TO_STAT,Configuration-State Timeout Status" "0: No configuration-stat timeout error,1: Configuration-state timeout error" line.long 0x4 "IRQ_EN,IRQ Enable" bitfld.long 0x4 0. "CFG_TO_IEN,Configuration-State Timeout Interrupt Enable" "0: Configuration-state timeout interrupt disabled,1: Configuration-state timeout interrupt enabled" wgroup.long 0xF0++0x7 line.long 0x0 "TRANS_LOCK,Transient Configuration Lock" hexmask.long.word 0x0 0.--8. 1. "TRANSKEY,Transient Configuration Lock" line.long 0x4 "PERMNT_LOCK,Permanent Configuration Lock" hexmask.long.word 0x4 0.--8. 1. "PERMNTKEY,Permanent Configuration Lock" group.long 0xF8++0x7 line.long 0x0 "DELTA_T,Delta T" hexmask.long.word 0x0 0.--13. 1. "DELTA_T,Minimum Fault-Output (EOUT) Timer Interval" line.long 0x4 "IRQ_ALARM_EN0,Non-critical Alarm-State Interrupt-Request Enable" bitfld.long 0x4 7. "IRQEN7,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 6. "IRQEN6,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 5. "IRQEN5,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 4. "IRQEN4,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 3. "IRQEN3,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 2. "IRQEN2,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 1. "IRQEN1,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x4 0. "IRQEN0,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled" group.long 0x10C++0x3 line.long 0x0 "NMI_EN0,Non-critical Fault-State Non-maskable-Interrupt-Request Enable" bitfld.long 0x0 7. "NMIEN7,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 6. "NMIEN6,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 5. "NMIEN5,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 4. "NMIEN4,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 3. "NMIEN3,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 2. "NMIEN2,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 1. "NMIEN1,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" newline bitfld.long 0x0 0. "NMIEN0,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled" group.long 0x11C++0x3 line.long 0x0 "EOUT_SIG_EN0,Non-critical Fault-State EOUT Signaling Enable" bitfld.long 0x0 7. "EOUTEN7,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." newline bitfld.long 0x0 6. "EOUTEN6,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." newline bitfld.long 0x0 5. "EOUTEN5,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." newline bitfld.long 0x0 4. "EOUTEN4,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." newline bitfld.long 0x0 3. "EOUTEN3,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." newline bitfld.long 0x0 2. "EOUTEN2,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." newline bitfld.long 0x0 1. "EOUTEN1,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." newline bitfld.long 0x0 0. "EOUTEN0,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.." rgroup.long 0x12C++0x3 line.long 0x0 "TMR_ALARM,Alarm-State Timer" hexmask.long 0x0 0.--31. 1. "COUNT,Alarm-State Timer Count" rgroup.long 0x134++0x7 line.long 0x0 "TMR_CFG,Configuration-State Timer" hexmask.long 0x0 0.--31. 1. "COUNT,Configuration-State Timer Count" line.long 0x4 "TMR_ETMR,Fault-Output Timer" hexmask.long 0x4 0.--31. 1. "COUNT,Fault-Output Timer Count" tree.end tree "FIRC (Fast Internal RC Oscillator)" base ad:0x402D0000 rgroup.long 0x4++0x3 line.long 0x0 "Status_Register,Status Register" bitfld.long 0x0 0. "STATUS,Status bit for FIRC" "0: FIRC is off or unstable.,1: FIRC is on and stable." group.long 0x8++0x3 line.long 0x0 "STDBY_ENABLE,Standby Enable Register" bitfld.long 0x0 0. "STDBY_EN,Enables or disables FIRC in chip's Standby mode." "0: Disabled,1: Enabled" tree.end tree "FLASH (Embedded Flash Memory)" base ad:0x402EC000 group.long 0x0++0x7 line.long 0x0 "MCR,Module Configuration" hexmask.long.byte 0x0 16.--23. 1. "PEID,Program and Erase Master/Domain ID" bitfld.long 0x0 15. "PECIE,Program/Erase Complete Interrupt Enable" "0: Interrupt request not generated when MCRS[DONE]..,1: Interrupt request generated when MCRS[DONE] is 1" newline bitfld.long 0x0 12. "WDIE,Watch Dog Interrupt Enable" "0: Watchdog interrupt not enabled,1: Watchdog interrupt enabled" bitfld.long 0x0 8. "PGM,Program" "0: Flash memory not executing a program sequence,1: Flash memory executing a program sequence" newline bitfld.long 0x0 5. "ESS,Erase Size Select" "0: Flash memory erase is on a sector,1: Flash memory erase is on a block" bitfld.long 0x0 4. "ERS,Erase" "0: Flash memory not executing an erase sequence,1: Flash memory executing an erase sequence" newline bitfld.long 0x0 0. "EHV,Enable High Voltage" "0: Flash memory is not enabled to perform a high..,1: Flash memory is enabled to perform a high.." line.long 0x4 "MCRS,Module Configuration Status" eventfld.long 0x4 31. "EER,ECC Event Error" "0: Reads occurring normally,1: ECC error occurred during a previous read" eventfld.long 0x4 30. "SBC,Single Bit Correction" "0: Reads occurring without corrections,1: Single bit correction occurred during a previous.." newline eventfld.long 0x4 29. "AEE,Address Encode Error" "0: Reads are occurring without address encode..,1: Previous read may be corrupted based on address.." eventfld.long 0x4 28. "EEE,EDC after ECC Error" "0: Reads are occurring without EDC after ECC..,1: Previous read may be corrupted based on ECC.." newline eventfld.long 0x4 25. "RVE,Read Voltage Error" "0: Reads are occurring without voltage issues,1: A previous read may have been corrupted due to.." eventfld.long 0x4 24. "RRE,Read Reference Error" "0: Reads occur without reference issues,1: Previous read may be corrupted because of read.." newline eventfld.long 0x4 20. "RWE,Read-While-Write Event Error" "0: Reads occur normally,1: RWW error occurred during a previous read" eventfld.long 0x4 17. "PEP,Program and Erase Protection Error" "0: Program and erase protection errors do not exist,1: Previous program or erase protection error.." newline eventfld.long 0x4 16. "PES,Program and Erase Sequence Error" "0: Program and erase sequence errors do not exist,1: Previous program or erase sequence encountered.." rbitfld.long 0x4 15. "DONE,State Machine Status" "0: Performing a high voltage operation,1: Not executing a high voltage operation" newline rbitfld.long 0x4 14. "PEG,Program/Erase Good" "0: Program or erase operation failed,1: Program or erase operation successful" rbitfld.long 0x4 12. "WDI,Watch Dog Interrupt" "0: Normal Operation Watchdog Timer has not expired.,1: Program Watchdog Timer has expired." newline rbitfld.long 0x4 9. "EPEG,ECC Enabled Program/Erase Good" "0: Program or erase operation did not require ECC..,1: Program or erase operation required ECC Enabled.." rbitfld.long 0x4 8. "TSPELOCK,UTest NVM Program and Erase Lock" "0: Corresponding sector not locked and may be..,1: Corresponding sector protected from the program.." newline rbitfld.long 0x4 0. "RE,Reset Error" "0: Reset occurred without errors,1: Reset error encountered" rgroup.long 0x8++0x3 line.long 0x0 "MCRE,Extended Module Configuration" bitfld.long 0x0 29.--31. "n2M,Number of 2 MB Blocks" "0: Zero 2 MB blocks,1: One 2 MB block,2: Two 2 MB blocks,3: Three 2 MB blocks,4: Four 2 MB blocks,?,?,?" bitfld.long 0x0 21.--23. "n1M,Number of 1 MB Blocks" "0: Zero 1 MB blocks,1: One 1 MB block,2: Two 1 MB blocks,3: Three 1 MB blocks,4: Four 1 MB blocks,?,?,?" newline bitfld.long 0x0 14.--15. "n512K,Number of 512 KB Blocks" "0: Zero 512 KB blocks,1: One 512 KB block,2: Two 512 KB blocks,3: Four 512 KB blocks" bitfld.long 0x0 6.--7. "n256K,Number of 256 KB Blocks" "0: Zero 256 KB blocks,1: One 256 KB block,2: Two 256 KB blocks,3: Four 256 KB blocks" group.long 0xC++0x7 line.long 0x0 "CTL,Module Control" bitfld.long 0x0 15. "RWSL,Read Wait State Lock" "0: RWSC not locked and available for writing,1: RWSC locked and unavailable for writing" hexmask.long.byte 0x0 8.--12. 1. "RWSC,Wait State Control" line.long 0x4 "ADR,Address" bitfld.long 0x4 31. "SAD,UTest NVM Address" "0: Address captured or to be accessed is from the..,1: Address captured or to be accessed is from the.." bitfld.long 0x4 24. "A5,Address Region 5" "0: Address captured or to be accessed is not from..,1: Address captured or to be accessed is from.." newline bitfld.long 0x4 21. "A2,Address Region 2" "0: Address captured or to be accessed is not from..,1: Address captured or to be accessed is from.." bitfld.long 0x4 20. "A1,Address Region 1" "0: Address captured or to be accessed is not from..,1: Address captured or to be accessed is from.." newline bitfld.long 0x4 19. "A0,Address Region 0" "0: Address captured or to be accessed is not from..,1: Address captured or to be accessed is from.." hexmask.long.tbyte 0x4 1.--18. 1. "ADDR,Address" rgroup.long 0x14++0x3 line.long 0x0 "PEADR,Program and Erase Address" bitfld.long 0x0 31. "PEASAD,UTest NVM Program and Erase Address" "0: Address accessed is from the main array space,1: Address accessed is from the UTest NVM array space" bitfld.long 0x0 24. "PEA5,Program and Erase Address Region 5" "0: Address accessed is not from region 5,1: Address accessed is from region 5" newline bitfld.long 0x0 23. "PEA4,Program and Erase Address Region 4" "0: Address accessed is not from region 4,1: Adrress accessed is from region 4" bitfld.long 0x0 22. "PEA3,Program and Erase Address Region 3" "0: Address accessed is not from region 3,1: Address accessed is from region 3" newline bitfld.long 0x0 21. "PEA2,Program and Erase Address Region 2" "0: Address accessed is not from region 2,1: Address accessed is from region 2" bitfld.long 0x0 20. "PEA1,Program and Erase Address Region 1" "0: Address accessed is not from region 1,1: Address accessed is from region 1" newline bitfld.long 0x0 19. "PEA0,Program and Erase Address Region 0" "0: Address accessed is not from region 0,1: Address accessed is from region 0" hexmask.long.word 0x0 5.--18. 1. "PEADDR,Program and Erase Address" rgroup.long 0x50++0x7 line.long 0x0 "SPELOCK,Sector Program and Erase Hardware Lock" hexmask.long 0x0 0.--31. 1. "SPELOCK,Sector Program and Erase Lock [31:0]" line.long 0x4 "SSPELOCK,Super Sector Program and Erase Hardware Lock" hexmask.long 0x4 0.--27. 1. "SSPELOCK,Super Sector Program and Erase Lock [27:0]" rgroup.long 0x70++0x7 line.long 0x0 "XSPELOCK,Express Sector Program and Erase Hardware Lock" hexmask.long 0x0 0.--31. 1. "XSPELOCK,Express Sector Program and Erase Lock [31:0]" line.long 0x4 "XSSPELOCK,Express Super Sector Program and Erase Hardware Lock" hexmask.long 0x4 0.--27. 1. "XSSPELOCK,Express Super Sector Program and Erase Lock [27:0]" group.long 0x90++0x7 line.long 0x0 "TMD,Test Mode Disable Password Check" hexmask.long 0x0 0.--31. 1. "PWD,Password Challenge" line.long 0x4 "UT0,UTest 0" bitfld.long 0x4 31. "UTE,UTest Enable" "0: U-Test mode is not enabled.,1: U-Test mode is enabled." bitfld.long 0x4 30. "SBCE,Single Bit Correction Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4 15. "RRIE,Read Reference Input Enable" "0: Read reference input disabled,1: Read reference input enabled" bitfld.long 0x4 14. "AEIE,Address Encode Invert Enable" "0: Address encode invert is disabled,1: Address encode values are inverted based on.." newline bitfld.long 0x4 13. "EDIE,EDC after ECC Data Input Enable" "0: EDC after ECC data input is disabled,1: Data read is from UD3[EDDATA] and UD5[EDDATAC]" bitfld.long 0x4 12. "EIE,ECC Data Input Enable" "0: ECC data input is disabled,1: Data read is from UD0[EDATA] and UD2[EDATAC]" newline bitfld.long 0x4 9. "NAIBP,Next Array Integrity Break Point" "0: Array integrity state machine is not currently..,1: Array integrity state machine is at a breakpoint" bitfld.long 0x4 8. "AIBPE,Array Integrity Break Point Enable" "0: Array integrity breakpoints disabled,1: Array integrity breakpoints enabled during array.." newline bitfld.long 0x4 6. "AISUS,Array Integrity Suspend" "0: Array integrity sequence not suspended.,1: Array integrity sequence is suspended." bitfld.long 0x4 5. "MRE,Margin Read Enable" "0: Margin reads are not enabled.,1: Margin reads are enabled." newline bitfld.long 0x4 4. "MRV,Margin Read Value" "0: Zero's margin reads are requested.,1: One's margin reads are requested." bitfld.long 0x4 2. "AIS,Array Integrity Sequence" "0: Array integrity sequence is proprietary sequence,1: Array integrity sequence is sequential" newline bitfld.long 0x4 1. "AIE,Array Integrity Enable" "0: Array integrity checks not enabled,1: Array integrity checks enabled" rbitfld.long 0x4 0. "AID,Array Integrity Done" "0: Array integrity check ongoing,1: Array integrity check complete" repeat 9. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x98)++0x3 line.long 0x0 "UM[$1],UMISRn" hexmask.long 0x0 0.--31. 1. "MISR,MISR[31:0]" repeat.end group.long 0xBC++0x3 line.long 0x0 "UM9,UMISR9" bitfld.long 0x0 0. "MISR,MISR[288]" "0,1" group.long 0xD0++0x23 line.long 0x0 "UD0,UTest Data 0" hexmask.long 0x0 0.--31. 1. "EDATA,ECC Data [31:0]" line.long 0x4 "UD1,UTest Data 1" hexmask.long 0x4 0.--31. 1. "EDATA,ECC Data [63:32]" line.long 0x8 "UD2,UTest Data 2" bitfld.long 0x8 27. "ED3,ECC Logic Check Double Word 3" "0,1" bitfld.long 0x8 26. "ED2,ECC Logic Check Double Word 2" "0,1" newline bitfld.long 0x8 25. "ED1,ECC Logic Check Double Word 1" "0,1" bitfld.long 0x8 24. "ED0,ECC Logic Check Double Word 0" "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "EDATAC,ECC Data Check Bits [7:0]" line.long 0xC "UD3,UTest Data 3" hexmask.long 0xC 0.--31. 1. "EDDATA,EDC After ECC Data [31:0]" line.long 0x10 "UD4,UTest Data 4" hexmask.long 0x10 0.--31. 1. "EDDATA,EDC After ECC Data [63:31]" line.long 0x14 "UD5,UTest Data 5" bitfld.long 0x14 27. "EDD3,EDC After ECC Logic Check Double Word 3" "0,1" bitfld.long 0x14 26. "EDD2,EDC after ECC Logic Check Double Word 2" "0,1" newline bitfld.long 0x14 25. "EDD1,EDC After ECC Logic Check Double Word 1" "0,1" bitfld.long 0x14 24. "EDD0,EDC After ECC Logic Check Double Word 0" "0,1" newline hexmask.long.byte 0x14 0.--7. 1. "EDDATAC,EDC After ECC Data Check Bits [7:0]" line.long 0x18 "UA0,UTest Address 0" hexmask.long 0x18 0.--31. 1. "AEI,Address Encode Invert [31:0]" line.long 0x1C "UA1,UTest Address 1" hexmask.long.tbyte 0x1C 0.--19. 1. "AEI,Address Encode Invert [51:32]" line.long 0x20 "XMCR,Express Module Configuration" hexmask.long.byte 0x20 16.--23. 1. "XPEID,Express Program Master/Domain ID" rbitfld.long 0x20 15. "XDONE,Express State Machine Status" "0: Executing an express program operation,1: Not executing an express program operation" newline rbitfld.long 0x20 14. "XPEG,Express Program Good" "0: Program operation failed,1: Program operation successful" rbitfld.long 0x20 13. "XDOK,Express Data OK" "0: Flash memory not ready to accept writes to the..,1: Writes to DATA registers allowed" newline rbitfld.long 0x20 12. "XWDI,Express Watch Dog Interrupt" "0: Normal Operation Watchdog Timer has not expired.,1: Express Program Watchdog Timer has expired." bitfld.long 0x20 11. "XWDIE,Express Watch Dog Interrupt Enable" "0: Express watchdog interrupt disabled,1: Express watchdog interrupt enabled" newline rbitfld.long 0x20 9. "XEPEG,Express ECC Enabled Program Good" "0: Program operation did not require ECC-enabled..,1: Program operation required ECC-enabled verifies.." bitfld.long 0x20 8. "XPGM,Express Program" "0: Flash memory not executing an express program..,1: Flash memory executing an express program sequence" newline bitfld.long 0x20 0. "XEHV,Express Enable High Voltage" "0: Flash memory is not enabled to perform an..,1: Flash memory is enabled to perform an express.." rgroup.long 0xF4++0x3 line.long 0x0 "XPEADR,Express Program Address" bitfld.long 0x0 24. "XPEA5,Express Program Address Region 5" "0: Address accessed is not from region 5,1: Address accessed is from region 5" bitfld.long 0x0 23. "XPEA4,Express Program Address Region 4" "0: Address accessed is not from region 4,1: Address accessed is from region 4" newline bitfld.long 0x0 22. "XPEA3,Express Program Address Region 3" "0: Address accessed is not from region 3,1: Address accessed is from region 3" bitfld.long 0x0 21. "XPEA2,Express Program Address Region 2" "0: Address accessed is not from region 2,1: Address accessed is from region 2" newline bitfld.long 0x0 20. "XPEA1,Express Program Address Region 1" "0: Address accessed is not from region 1,1: Address accessed is from region 1" bitfld.long 0x0 19. "XPEA0,Express Program Address Region 0" "0: Address accessed is not from region 0,1: Address accessed is from region 0" newline hexmask.long.word 0x0 5.--18. 1. "XPEADDR,Express Program Address" repeat 32. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x100)++0x3 line.long 0x0 "DATA[$1],Program Data" hexmask.long 0x0 0.--31. 1. "PDATA,Program Data" repeat.end tree.end tree "FLEXCAN (Controller Area Network)" base ad:0x0 tree "CAN_0" base ad:0x40304000 group.long 0x0++0xB line.long 0x0 "MCR,Module Configuration" bitfld.long 0x0 31. "MDIS,Module Disable" "0: Enable,1: Disable" bitfld.long 0x0 30. "FRZ,Freeze Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 29. "RFEN,Legacy RX FIFO Enable" "0: Disable,1: Enable" bitfld.long 0x0 28. "HALT,Halt FlexCAN" "0: No request,1: Enter Freeze mode if MCR[FRZ] = 1." newline rbitfld.long 0x0 27. "NOTRDY,FlexCAN Not Ready" "0: FlexCAN is in Normal mode Listen-Only mode or..,1: FlexCAN is in Disable mode or Freeze mode." bitfld.long 0x0 25. "SOFTRST,Soft Reset" "0: No reset,1: Soft reset affects reset registers" newline rbitfld.long 0x0 24. "FRZACK,Freeze Mode Acknowledge" "0: Not in Freeze mode prescaler running.,1: In Freeze mode prescaler stopped." bitfld.long 0x0 23. "SUPV,Supervisor Mode" "0: User mode,1: Supervisor mode" newline bitfld.long 0x0 21. "WRNEN,Warning Interrupt Enable" "0: Disable,1: Enable" rbitfld.long 0x0 20. "LPMACK,Low-Power Mode Acknowledge" "0: Not in a low-power mode,1: In a low-power mode" newline bitfld.long 0x0 17. "SRXDIS,Self-Reception Disable" "0: Enable,1: Disable" bitfld.long 0x0 16. "IRMQ,Individual RX Masking and Queue Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 15. "DMA,DMA Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "LPRIOEN,Local Priority Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 12. "AEN,Abort Enable" "0: Disabled,1: Enabled" bitfld.long 0x0 11. "FDEN,CAN FD Operation Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 8.--9. "IDAM,ID Acceptance Mode" "0: Format A: One full ID (standard and extended)..,1: Format B: Two full standard IDs or two partial..,2: Format C: Four partial 8-bit standard IDs per ID..,3: Format D: All frames rejected." hexmask.long.byte 0x0 0.--6. 1. "MAXMB,Number of the Last Message Buffer" line.long 0x4 "CTRL1,Control 1" hexmask.long.byte 0x4 24.--31. 1. "PRESDIV,Prescaler Division Factor" bitfld.long 0x4 22.--23. "RJW,Resync Jump Width" "0,1,2,3" newline bitfld.long 0x4 19.--21. "PSEG1,Phase Segment 1" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "PSEG2,Phase Segment 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 15. "BOFFMSK,Bus Off Interrupt Mask" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 14. "ERRMSK,Error Interrupt Mask" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 12. "LPB,Loopback Mode" "0: Disabled,1: Enabled" bitfld.long 0x4 11. "TWRNMSK,TX Warning Interrupt Mask" "0: Disabled,1: Enabled" newline bitfld.long 0x4 10. "RWRNMSK,RX Warning Interrupt Mask" "0: Disabled,1: Enabled" bitfld.long 0x4 7. "SMP,CAN Bit Sampling" "0: One sample is used to determine the bit value.,1: Three samples are used to determine the value of.." newline bitfld.long 0x4 6. "BOFFREC,Bus Off Recovery" "0: Enabled,1: Disabled" bitfld.long 0x4 5. "TSYN,Timer Sync" "0: Disable,1: Enable" newline bitfld.long 0x4 4. "LBUF,Lowest Buffer Transmitted First" "0: Buffer with highest priority is transmitted first.,1: Lowest number buffer is transmitted first." bitfld.long 0x4 3. "LOM,Listen-Only Mode" "0: Listen-Only mode is deactivated.,1: FlexCAN module operates in Listen-Only mode." newline bitfld.long 0x4 0.--2. "PROPSEG,Propagation Segment" "0,1,2,3,4,5,6,7" line.long 0x8 "TIMER,Free-Running Timer" hexmask.long.word 0x8 0.--15. 1. "TIMER,Timer Value" group.long 0x10++0x27 line.long 0x0 "RXMGMASK,RX Message Buffers Global Mask" hexmask.long 0x0 0.--31. 1. "MG,Global Mask for RX Message Buffers" line.long 0x4 "RX14MASK,Receive 14 Mask" hexmask.long 0x4 0.--31. 1. "RX14M,RX Buffer 14 Mask Bits" line.long 0x8 "RX15MASK,Receive 15 Mask" hexmask.long 0x8 0.--31. 1. "RX15M,RX Buffer 15 Mask Bits" line.long 0xC "ECR,Error Counter" hexmask.long.byte 0xC 24.--31. 1. "RXERRCNT_FAST,Receive Error Counter for Fast Bits" hexmask.long.byte 0xC 16.--23. 1. "TXERRCNT_FAST,Transmit Error Counter for Fast Bits" newline hexmask.long.byte 0xC 8.--15. 1. "RXERRCNT,Receive Error Counter" hexmask.long.byte 0xC 0.--7. 1. "TXERRCNT,Transmit Error Counter" line.long 0x10 "ESR1,Error and Status 1" rbitfld.long 0x10 31. "BIT1ERR_FAST,Fast Bit1 Error Flag" "0: No such occurrence.,1: At least one bit sent as recessive is received.." rbitfld.long 0x10 30. "BIT0ERR_FAST,Fast Bit0 Error Flag" "0: No such occurrence.,1: At least one bit sent as dominant is received as.." newline rbitfld.long 0x10 28. "CRCERR_FAST,Fast Cyclic Redundancy Check Error Flag" "0: No such occurrence.,1: A CRC error occurred since last read of this.." rbitfld.long 0x10 27. "FRMERR_FAST,Fast Form Error Flag" "0: No such occurrence.,1: A form error occurred since last read of this.." newline rbitfld.long 0x10 26. "STFERR_FAST,Fast Stuffing Error Flag" "0: No such occurrence.,1: A stuffing error occurred since last read of.." eventfld.long 0x10 21. "ERROVR,Error Overrun Flag" "0: No overrun,1: Overrun" newline eventfld.long 0x10 20. "ERRINT_FAST,Fast Error Interrupt Flag" "0: No such occurrence.,1: Error flag set in the data phase of CAN FD.." eventfld.long 0x10 19. "BOFFDONEINT,Bus Off Done Interrupt Flag" "0: No such occurrence,1: FlexCAN module has completed Bus Off process." newline rbitfld.long 0x10 18. "SYNCH,CAN Synchronization Status Flag" "0: Not synchronized,1: Synchronized" eventfld.long 0x10 17. "TWRNINT,TX Warning Interrupt Flag" "0: No such occurrence,1: TX error counter changed from less than 96 to.." newline eventfld.long 0x10 16. "RWRNINT,RX Warning Interrupt Flag" "0: No such occurrence,1: RX error counter changed from less than 96 to.." rbitfld.long 0x10 15. "BIT1ERR,Bit1 Error Flag" "0: No such occurrence.,1: At least one bit sent as recessive is received.." newline rbitfld.long 0x10 14. "BIT0ERR,Bit0 Error Flag" "0: No such occurrence.,1: At least one bit sent as dominant is received as.." rbitfld.long 0x10 13. "ACKERR,Acknowledge Error Flag" "0: No error,1: An ACK error occurred since last read of this.." newline rbitfld.long 0x10 12. "CRCERR,Cyclic Redundancy Check Error Flag" "0: No error,1: A CRC error occurred since last read of this.." rbitfld.long 0x10 11. "FRMERR,Form Error Flag" "0: No error,1: A Form Error occurred since last read of this.." newline rbitfld.long 0x10 10. "STFERR,Stuffing Error Flag" "0: No error,1: Error occurred since last read of this register." rbitfld.long 0x10 9. "TXWRN,TX Error Warning Flag" "0: No such occurrence.,1: TXERRCNT is 96 or greater." newline rbitfld.long 0x10 8. "RXWRN,RX Error Warning Flag" "0: No such occurrence.,1: RXERRCNT is greater than or equal to 96." rbitfld.long 0x10 7. "IDLE,Idle" "0: Not IDLE,1: IDLE" newline rbitfld.long 0x10 6. "TX,FlexCAN In Transmission" "0: Not transmitting,1: Transmitting" rbitfld.long 0x10 4.--5. "FLTCONF,Fault Confinement State" "0: Bus Off,1: Error Passive,2: Bus Off,3: Bus Off" newline rbitfld.long 0x10 3. "RX,FlexCAN in Reception Flag" "0: Not receiving,1: Receiving" eventfld.long 0x10 2. "BOFFINT,Bus Off Interrupt Flag" "0: No such occurrence.,1: FlexCAN module entered Bus Off state." newline eventfld.long 0x10 1. "ERRINT,Error Interrupt Flag" "0: No such occurrence.,1: Indicates setting of any error flag in the Error.." line.long 0x14 "IMASK2,Interrupt Masks 2" hexmask.long 0x14 0.--31. 1. "BUF63TO32M,Buffer MBi Mask" line.long 0x18 "IMASK1,Interrupt Masks 1" hexmask.long 0x18 0.--31. 1. "BUF31TO0M,Buffer MBi Mask" line.long 0x1C "IFLAG2,Interrupt Flags 2" hexmask.long 0x1C 0.--31. 1. "BUF63TO32I,Buffer MBi Interrupt" line.long 0x20 "IFLAG1,Interrupt Flags 1" hexmask.long.tbyte 0x20 8.--31. 1. "BUF31TO8I,Buffer MBi Interrupt" eventfld.long 0x20 7. "BUF7I,Buffer MB7 Interrupt or Legacy RX FIFO Overflow" "0: No occurrence of MB7 completing transmission or..,1: MB7 completed transmission or reception or FIFO.." newline eventfld.long 0x20 6. "BUF6I,Buffer MB6 Interrupt or Legacy RX FIFO Warning" "0: No occurrence of MB6 completing transmission or..,1: MB6 completed transmission or reception or FIFO.." eventfld.long 0x20 5. "BUF5I,Buffer MB5 Interrupt or Frames available in Legacy RX FIFO" "0: No occurrence of completed transmission or..,1: MB5 completed transmission or reception or.." newline hexmask.long.byte 0x20 1.--4. 1. "BUF4TO1I,Buffer MBi Interrupt or Reserved" eventfld.long 0x20 0. "BUF0I,Buffer MB0 Interrupt or Clear Legacy FIFO bit" "0: MB0 has no occurrence of successfully completed..,1: MB0 has successfully completed transmission or.." line.long 0x24 "CTRL2,Control 2" bitfld.long 0x24 31. "ERRMSK_FAST,Error Interrupt Mask for Errors Detected in the Data Phase of Fast CAN FD Frames" "0: Disable,1: Enable" bitfld.long 0x24 30. "BOFFDONEMSK,Bus Off Done Interrupt Mask" "0: Disable,1: Enable" newline bitfld.long 0x24 29. "ECRWRE,Error Correction Configuration Register Write Enable" "0: Disable,1: Enable" bitfld.long 0x24 28. "WRMFRZ,Write Access to Memory in Freeze Mode" "0: Disable,1: Enable" newline hexmask.long.byte 0x24 24.--27. 1. "RFFN,Number of Legacy Receive FIFO Filters" hexmask.long.byte 0x24 19.--23. 1. "TASD,Transmission Arbitration Start Delay" newline bitfld.long 0x24 18. "MRP,Message Buffers Reception Priority" "0: Matching starts from Legacy RX FIFO or Enhanced..,1: Matching starts from message buffers and.." bitfld.long 0x24 17. "RRS,Remote Request Storing" "0: Generated,1: Stored" newline bitfld.long 0x24 16. "EACEN,Entire Frame Arbitration Field Comparison Enable for RX Message Buffers" "0: Disable,1: Enable" bitfld.long 0x24 15. "TIMER_SRC,Timer Source" "0: CAN bit clock,1: External time tick" newline bitfld.long 0x24 14. "PREXCEN,Protocol Exception Enable" "0: Disabled,1: Enabled" bitfld.long 0x24 13. "BTE,Bit Timing Expansion Enable" "0: Disable,1: Enable" newline bitfld.long 0x24 12. "ISOCANFDEN,ISO CAN FD Enable" "0: Disable. FlexCAN operates using the non-ISO CAN..,1: Enable. FlexCAN operates using the ISO CAN FD.." bitfld.long 0x24 11. "EDFLTDIS,Edge Filter Disable" "0: Enabled,1: Disabled" newline bitfld.long 0x24 8.--9. "MBTSBASE,Message Buffer Timestamp Base" "0: TIMER,1: Lower 16 bits of high-resolution timer,2: Upper 16 bits of high-resolution timer,?" bitfld.long 0x24 6.--7. "TSTAMPCAP,Timestamp Capture Point" "0: Disabled,1: End of the CAN frame,2: Start of the CAN frame,3: Start of frame for classical CAN frames; res bit.." rgroup.long 0x38++0x3 line.long 0x0 "ESR2,Error and Status 2" hexmask.long.byte 0x0 16.--22. 1. "LPTM,Lowest Priority TX Message Buffer" bitfld.long 0x0 14. "VPS,Valid Priority Status" "0: Invalid,1: Valid" newline bitfld.long 0x0 13. "IMB,Inactive Message Buffer" "0: Message buffer indicated by ESR2[LPTM] is not..,1: At least one message buffer is inactive." rgroup.long 0x44++0x3 line.long 0x0 "CRCR,Cyclic Redundancy Check" hexmask.long.byte 0x0 16.--22. 1. "MBCRC,CRC Message Buffer" hexmask.long.word 0x0 0.--14. 1. "TXCRC,Transmitted CRC value" group.long 0x48++0x3 line.long 0x0 "RXFGMASK,Legacy RX FIFO Global Mask" hexmask.long 0x0 0.--31. 1. "FGM,Legacy RX FIFO Global Mask Bits" rgroup.long 0x4C++0x3 line.long 0x0 "RXFIR,Legacy RX FIFO Information" hexmask.long.word 0x0 0.--8. 1. "IDHIT,Identifier Acceptance Filter Hit Indicator" group.long 0x50++0x3 line.long 0x0 "CBT,CAN Bit Timing" bitfld.long 0x0 31. "BTF,Bit Timing Format Enable" "0: Disable,1: Enable" hexmask.long.word 0x0 21.--30. 1. "EPRESDIV,Extended Prescaler Division Factor" newline hexmask.long.byte 0x0 16.--20. 1. "ERJW,Extended Resync Jump Width" hexmask.long.byte 0x0 10.--15. 1. "EPROPSEG,Extended Propagation Segment" newline hexmask.long.byte 0x0 5.--9. 1. "EPSEG1,Extended Phase Segment 1" hexmask.long.byte 0x0 0.--4. 1. "EPSEG2,Extended Phase Segment 2" group.long 0x6C++0x3 line.long 0x0 "IMASK3,Interrupt Masks 3" hexmask.long 0x0 0.--31. 1. "BUF95TO64M,Buffer MBi Mask" group.long 0x74++0x3 line.long 0x0 "IFLAG3,Interrupt Flags 3" hexmask.long 0x0 0.--31. 1. "BUF95TO64,Buffer MBi Interrupt" repeat 96. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x880)++0x3 line.long 0x0 "RXIMR[$1],Receive Individual Mask" hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits" repeat.end group.long 0xAE0++0xF line.long 0x0 "MECR,Memory Error Control" bitfld.long 0x0 31. "ECRWRDIS,Error Configuration Register Write Disable" "0: Enable,1: Disable" bitfld.long 0x0 19. "HANCEI_MSK,Host Access with Non-Correctable Errors Interrupt Mask" "0: Disable,1: Enable" newline bitfld.long 0x0 18. "FANCEI_MSK,FlexCAN Access with Non-Correctable Errors Interrupt Mask" "0: Disable,1: Enable" bitfld.long 0x0 16. "CEI_MSK,Correctable Errors Interrupt Mask" "0: Disable,1: Enable" newline bitfld.long 0x0 15. "HAERRIE,Host Access Error Injection Enable" "0: Disable,1: Enable" bitfld.long 0x0 14. "FAERRIE,FlexCAN Access Error Injection Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 13. "EXTERRIE,Extended Error Injection Enable" "0: Disable. Apply error injection only to the..,1: Enable. Apply error injection to the 64-bit word." bitfld.long 0x0 9. "RERRDIS,Error Report Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 8. "ECCDIS,Error Correction Disable" "0: Enable,1: Disable" bitfld.long 0x0 7. "NCEFAFRZ,Non-Correctable Errors in FlexCAN Access Put Device in Freeze Mode" "0: Keep normal operation.,1: Put FlexCAN in Freeze mode (see section 'Freeze.." line.long 0x4 "ERRIAR,Error Injection Address" hexmask.long.word 0x4 2.--13. 1. "INJADDR_H,Error Injection Address High" rbitfld.long 0x4 0.--1. "INJADDR_L,Error Injection Address Low" "0,1,2,3" line.long 0x8 "ERRIDPR,Error Injection Data Pattern" hexmask.long 0x8 0.--31. 1. "DFLIP,Data Flip Pattern" line.long 0xC "ERRIPPR,Error Injection Parity Pattern" hexmask.long.byte 0xC 24.--28. 1. "PFLIP3,Parity Flip Pattern for Byte 3 (Most Significant)" hexmask.long.byte 0xC 16.--20. 1. "PFLIP2,Parity Flip Pattern for Byte 2" newline hexmask.long.byte 0xC 8.--12. 1. "PFLIP1,Parity Flip Pattern for Byte 1" hexmask.long.byte 0xC 0.--4. 1. "PFLIP0,Parity Flip Pattern for Byte 0 (Least Significant)" rgroup.long 0xAF0++0xB line.long 0x0 "RERRAR,Error Report Address" bitfld.long 0x0 24. "NCE,Non-Correctable Error" "0: Reporting a correctable error,1: Reporting a non-correctable error" bitfld.long 0x0 16.--18. "SAID,SAID" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--13. 1. "ERRADDR,Address Where Error Detected" line.long 0x4 "RERRDR,Error Report Data" hexmask.long 0x4 0.--31. 1. "RDATA,Raw Data Word Read from Memory with Error" line.long 0x8 "RERRSYNR,Error Report Syndrome" bitfld.long 0x8 31. "BE3,Byte Enabled for Byte 3 (Most Significant)" "0: Byte was not read.,1: Byte was read." hexmask.long.byte 0x8 24.--28. 1. "SYND3,Error Syndrome for Byte 3 (Most Significant)" newline bitfld.long 0x8 23. "BE2,Byte Enabled for Byte 2" "0: Byte was not read.,1: Byte was read." hexmask.long.byte 0x8 16.--20. 1. "SYND2,Error Syndrome for Byte 2" newline bitfld.long 0x8 15. "BE1,Byte Enabled for Byte 1" "0: Byte was not read.,1: Byte was read." hexmask.long.byte 0x8 8.--12. 1. "SYND1,Error Syndrome for Byte 1" newline bitfld.long 0x8 7. "BE0,Byte Enabled for Byte 0 (Least Significant)" "0: Byte was not read.,1: Byte was read." hexmask.long.byte 0x8 0.--4. 1. "SYND0,Error Syndrome for Byte 0 (Least Significant)" group.long 0xAFC++0x3 line.long 0x0 "ERRSR,Error Status" eventfld.long 0x0 19. "HANCEIF,Host Access with Noncorrectable Error Interrupt Flag" "0: No errors detected,1: Error detected" eventfld.long 0x0 18. "FANCEIF,FlexCAN Access with Non-Correctable Error Interrupt Flag" "0: No errors detected,1: Error detected" newline eventfld.long 0x0 16. "CEIF,Correctable Error Interrupt Flag" "0: No errors detected,1: Error detected" eventfld.long 0x0 3. "HANCEIOF,Host Access With Non-Correctable Error Interrupt Overrun Flag" "0: No errors detected,1: Error detected" newline eventfld.long 0x0 2. "FANCEIOF,FlexCAN Access with Non-Correctable Error Interrupt Overrun Flag" "0: No errors detected,1: Error detected" eventfld.long 0x0 0. "CEIOF,Correctable Error Interrupt Overrun Flag" "0: No errors detected,1: Error detected" group.long 0xBF0++0x17 line.long 0x0 "EPRS,Enhanced CAN Bit Timing Prescalers" hexmask.long.word 0x0 16.--25. 1. "EDPRESDIV,Extended Data Phase Prescaler Division Factor" hexmask.long.word 0x0 0.--9. 1. "ENPRESDIV,Extended Nominal Prescaler Division Factor" line.long 0x4 "ENCBT,Enhanced Nominal CAN Bit Timing" hexmask.long.byte 0x4 22.--28. 1. "NRJW,Nominal Resynchronization Jump Width" hexmask.long.byte 0x4 12.--18. 1. "NTSEG2,Nominal Time Segment 2" newline hexmask.long.byte 0x4 0.--7. 1. "NTSEG1,Nominal Time Segment 1" line.long 0x8 "EDCBT,Enhanced Data Phase CAN Bit Timing" hexmask.long.byte 0x8 22.--25. 1. "DRJW,Data Phase Resynchronization Jump Width" hexmask.long.byte 0x8 12.--15. 1. "DTSEG2,Data Phase Time Segment 2" newline hexmask.long.byte 0x8 0.--4. 1. "DTSEG1,Data Phase Segment 1" line.long 0xC "ETDC,Enhanced Transceiver Delay Compensation" bitfld.long 0xC 31. "ETDCEN,Transceiver Delay Compensation Enable" "0: Disable,1: Enable" bitfld.long 0xC 30. "TDMDIS,Transceiver Delay Measurement Disable" "0: Enable,1: Disable" newline hexmask.long.byte 0xC 16.--22. 1. "ETDCOFF,Enhanced Transceiver Delay Compensation Offset" eventfld.long 0xC 15. "ETDCFAIL,Transceiver Delay Compensation Fail" "0: In range,1: Out of range" newline hexmask.long.byte 0xC 0.--7. 1. "ETDCVAL,Enhanced Transceiver Delay Compensation Value" line.long 0x10 "FDCTRL,CAN FD Control" bitfld.long 0x10 31. "FDRATE,Bit Rate Switch Enable" "0: Disable,1: Enable" bitfld.long 0x10 22.--23. "MBDSR2,Message Buffer Data Size for Region 2" "0: 8 bytes,1: 16 bytes,2: 32 bytes,3: 64 bytes" newline bitfld.long 0x10 19.--20. "MBDSR1,Message Buffer Data Size for Region 1" "0: 8 bytes,1: 16 bytes,2: 32 bytes,3: 64 bytes" bitfld.long 0x10 16.--17. "MBDSR0,Message Buffer Data Size for Region 0" "0: 8 bytes,1: 16 bytes,2: 32 bytes,3: 64 bytes" newline bitfld.long 0x10 15. "TDCEN,Transceiver Delay Compensation Enable" "0: Disable,1: Enable" eventfld.long 0x10 14. "TDCFAIL,Transceiver Delay Compensation Fail" "0: In range,1: Out of range" newline hexmask.long.byte 0x10 8.--12. 1. "TDCOFF,Transceiver Delay Compensation Offset" hexmask.long.byte 0x10 0.--5. 1. "TDCVAL,Transceiver Delay Compensation Value" line.long 0x14 "FDCBT,CAN FD Bit Timing" hexmask.long.word 0x14 20.--29. 1. "FPRESDIV,Fast Prescaler Division Factor" bitfld.long 0x14 16.--18. "FRJW,Fast Resync Jump Width" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 10.--14. 1. "FPROPSEG,Fast Propagation Segment" bitfld.long 0x14 5.--7. "FPSEG1,Fast Phase Segment 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 0.--2. "FPSEG2,Fast Phase Segment 2" "0,1,2,3,4,5,6,7" rgroup.long 0xC08++0x3 line.long 0x0 "FDCRC,CAN FD CRC" hexmask.long.byte 0x0 24.--30. 1. "FD_MBCRC,CRC Message Buffer Number for FD_TXCRC" hexmask.long.tbyte 0x0 0.--20. 1. "FD_TXCRC,Extended Transmitted CRC value" group.long 0xC0C++0xB line.long 0x0 "ERFCR,Enhanced RX FIFO Control" bitfld.long 0x0 31. "ERFEN,Enhanced RX FIFO enable" "0: Disable,1: Enable" hexmask.long.byte 0x0 26.--30. 1. "DMALW,DMA Last Word" newline hexmask.long.byte 0x0 16.--22. 1. "NEXIF,Number of Extended ID Filter Elements" hexmask.long.byte 0x0 8.--13. 1. "NFE,Number of Enhanced RX FIFO Filter Elements" newline hexmask.long.byte 0x0 0.--4. 1. "ERFWM,Enhanced RX FIFO Watermark" line.long 0x4 "ERFIER,Enhanced RX FIFO Interrupt Enable" bitfld.long 0x4 31. "ERFUFWIE,Enhanced RX FIFO Underflow Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x4 30. "ERFOVFIE,Enhanced RX FIFO Overflow Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x4 29. "ERFWMIIE,Enhanced RX FIFO Watermark Indication Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x4 28. "ERFDAIE,Enhanced RX FIFO Data Available Interrupt Enable" "0: Disable,1: Enable" line.long 0x8 "ERFSR,Enhanced RX FIFO Status" eventfld.long 0x8 31. "ERFUFW,Enhanced RX FIFO Underflow Flag" "0: No such occurrence,1: Underflow" eventfld.long 0x8 30. "ERFOVF,Enhanced RX FIFO Overflow Flag" "0: No such occurrence,1: Overflow" newline eventfld.long 0x8 29. "ERFWMI,Enhanced RX FIFO Watermark Indication Flag" "0: No such occurrence,1: Number of messages in FIFO is greater than the.." eventfld.long 0x8 28. "ERFDA,Enhanced RX FIFO Data Available Flag" "0: No such occurrence,1: At least one message stored in Enhanced RX FIFO" newline bitfld.long 0x8 27. "ERFCLR,Enhanced RX FIFO Clear" "0: No effect,1: Clear enhanced RX FIFO content" rbitfld.long 0x8 17. "ERFE,Enhanced RX FIFO Empty Flag" "0: Not empty,1: Empty" newline rbitfld.long 0x8 16. "ERFF,Enhanced RX FIFO Full Flag" "0: Not full,1: Full" hexmask.long.byte 0x8 0.--5. 1. "ERFEL,Enhanced RX FIFO Elements" repeat 96. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xC30)++0x3 line.long 0x0 "HR_TIME_STAMP[$1],High-Resolution Timestamp" hexmask.long 0x0 0.--31. 1. "TS,High-Resolution Timestamp" repeat.end repeat 128. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x3000)++0x3 line.long 0x0 "ERFFEL[$1],Enhanced RX FIFO Filter Element" hexmask.long 0x0 0.--31. 1. "FEL,Filter Element Bits" repeat.end tree.end tree "CAN_1" base ad:0x40308000 group.long 0x0++0xB line.long 0x0 "MCR,Module Configuration" bitfld.long 0x0 31. "MDIS,Module Disable" "0: Enable,1: Disable" bitfld.long 0x0 30. "FRZ,Freeze Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 29. "RFEN,Legacy RX FIFO Enable" "0: Disable,1: Enable" bitfld.long 0x0 28. "HALT,Halt FlexCAN" "0: No request,1: Enter Freeze mode if MCR[FRZ] = 1." newline rbitfld.long 0x0 27. "NOTRDY,FlexCAN Not Ready" "0: FlexCAN is in Normal mode Listen-Only mode or..,1: FlexCAN is in Disable mode or Freeze mode." bitfld.long 0x0 25. "SOFTRST,Soft Reset" "0: No reset,1: Soft reset affects reset registers" newline rbitfld.long 0x0 24. "FRZACK,Freeze Mode Acknowledge" "0: Not in Freeze mode prescaler running.,1: In Freeze mode prescaler stopped." bitfld.long 0x0 23. "SUPV,Supervisor Mode" "0: User mode,1: Supervisor mode" newline bitfld.long 0x0 21. "WRNEN,Warning Interrupt Enable" "0: Disable,1: Enable" rbitfld.long 0x0 20. "LPMACK,Low-Power Mode Acknowledge" "0: Not in a low-power mode,1: In a low-power mode" newline bitfld.long 0x0 17. "SRXDIS,Self-Reception Disable" "0: Enable,1: Disable" bitfld.long 0x0 16. "IRMQ,Individual RX Masking and Queue Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 15. "DMA,DMA Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "LPRIOEN,Local Priority Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 12. "AEN,Abort Enable" "0: Disabled,1: Enabled" bitfld.long 0x0 11. "FDEN,CAN FD Operation Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 8.--9. "IDAM,ID Acceptance Mode" "0: Format A: One full ID (standard and extended)..,1: Format B: Two full standard IDs or two partial..,2: Format C: Four partial 8-bit standard IDs per ID..,3: Format D: All frames rejected." hexmask.long.byte 0x0 0.--6. 1. "MAXMB,Number of the Last Message Buffer" line.long 0x4 "CTRL1,Control 1" hexmask.long.byte 0x4 24.--31. 1. "PRESDIV,Prescaler Division Factor" bitfld.long 0x4 22.--23. "RJW,Resync Jump Width" "0,1,2,3" newline bitfld.long 0x4 19.--21. "PSEG1,Phase Segment 1" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "PSEG2,Phase Segment 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 15. "BOFFMSK,Bus Off Interrupt Mask" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 14. "ERRMSK,Error Interrupt Mask" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 12. "LPB,Loopback Mode" "0: Disabled,1: Enabled" bitfld.long 0x4 11. "TWRNMSK,TX Warning Interrupt Mask" "0: Disabled,1: Enabled" newline bitfld.long 0x4 10. "RWRNMSK,RX Warning Interrupt Mask" "0: Disabled,1: Enabled" bitfld.long 0x4 7. "SMP,CAN Bit Sampling" "0: One sample is used to determine the bit value.,1: Three samples are used to determine the value of.." newline bitfld.long 0x4 6. "BOFFREC,Bus Off Recovery" "0: Enabled,1: Disabled" bitfld.long 0x4 5. "TSYN,Timer Sync" "0: Disable,1: Enable" newline bitfld.long 0x4 4. "LBUF,Lowest Buffer Transmitted First" "0: Buffer with highest priority is transmitted first.,1: Lowest number buffer is transmitted first." bitfld.long 0x4 3. "LOM,Listen-Only Mode" "0: Listen-Only mode is deactivated.,1: FlexCAN module operates in Listen-Only mode." newline bitfld.long 0x4 0.--2. "PROPSEG,Propagation Segment" "0,1,2,3,4,5,6,7" line.long 0x8 "TIMER,Free-Running Timer" hexmask.long.word 0x8 0.--15. 1. "TIMER,Timer Value" group.long 0x10++0x27 line.long 0x0 "RXMGMASK,RX Message Buffers Global Mask" hexmask.long 0x0 0.--31. 1. "MG,Global Mask for RX Message Buffers" line.long 0x4 "RX14MASK,Receive 14 Mask" hexmask.long 0x4 0.--31. 1. "RX14M,RX Buffer 14 Mask Bits" line.long 0x8 "RX15MASK,Receive 15 Mask" hexmask.long 0x8 0.--31. 1. "RX15M,RX Buffer 15 Mask Bits" line.long 0xC "ECR,Error Counter" hexmask.long.byte 0xC 24.--31. 1. "RXERRCNT_FAST,Receive Error Counter for Fast Bits" hexmask.long.byte 0xC 16.--23. 1. "TXERRCNT_FAST,Transmit Error Counter for Fast Bits" newline hexmask.long.byte 0xC 8.--15. 1. "RXERRCNT,Receive Error Counter" hexmask.long.byte 0xC 0.--7. 1. "TXERRCNT,Transmit Error Counter" line.long 0x10 "ESR1,Error and Status 1" rbitfld.long 0x10 31. "BIT1ERR_FAST,Fast Bit1 Error Flag" "0: No such occurrence.,1: At least one bit sent as recessive is received.." rbitfld.long 0x10 30. "BIT0ERR_FAST,Fast Bit0 Error Flag" "0: No such occurrence.,1: At least one bit sent as dominant is received as.." newline rbitfld.long 0x10 28. "CRCERR_FAST,Fast Cyclic Redundancy Check Error Flag" "0: No such occurrence.,1: A CRC error occurred since last read of this.." rbitfld.long 0x10 27. "FRMERR_FAST,Fast Form Error Flag" "0: No such occurrence.,1: A form error occurred since last read of this.." newline rbitfld.long 0x10 26. "STFERR_FAST,Fast Stuffing Error Flag" "0: No such occurrence.,1: A stuffing error occurred since last read of.." eventfld.long 0x10 21. "ERROVR,Error Overrun Flag" "0: No overrun,1: Overrun" newline eventfld.long 0x10 20. "ERRINT_FAST,Fast Error Interrupt Flag" "0: No such occurrence.,1: Error flag set in the data phase of CAN FD.." eventfld.long 0x10 19. "BOFFDONEINT,Bus Off Done Interrupt Flag" "0: No such occurrence,1: FlexCAN module has completed Bus Off process." newline rbitfld.long 0x10 18. "SYNCH,CAN Synchronization Status Flag" "0: Not synchronized,1: Synchronized" eventfld.long 0x10 17. "TWRNINT,TX Warning Interrupt Flag" "0: No such occurrence,1: TX error counter changed from less than 96 to.." newline eventfld.long 0x10 16. "RWRNINT,RX Warning Interrupt Flag" "0: No such occurrence,1: RX error counter changed from less than 96 to.." rbitfld.long 0x10 15. "BIT1ERR,Bit1 Error Flag" "0: No such occurrence.,1: At least one bit sent as recessive is received.." newline rbitfld.long 0x10 14. "BIT0ERR,Bit0 Error Flag" "0: No such occurrence.,1: At least one bit sent as dominant is received as.." rbitfld.long 0x10 13. "ACKERR,Acknowledge Error Flag" "0: No error,1: An ACK error occurred since last read of this.." newline rbitfld.long 0x10 12. "CRCERR,Cyclic Redundancy Check Error Flag" "0: No error,1: A CRC error occurred since last read of this.." rbitfld.long 0x10 11. "FRMERR,Form Error Flag" "0: No error,1: A Form Error occurred since last read of this.." newline rbitfld.long 0x10 10. "STFERR,Stuffing Error Flag" "0: No error,1: Error occurred since last read of this register." rbitfld.long 0x10 9. "TXWRN,TX Error Warning Flag" "0: No such occurrence.,1: TXERRCNT is 96 or greater." newline rbitfld.long 0x10 8. "RXWRN,RX Error Warning Flag" "0: No such occurrence.,1: RXERRCNT is greater than or equal to 96." rbitfld.long 0x10 7. "IDLE,Idle" "0: Not IDLE,1: IDLE" newline rbitfld.long 0x10 6. "TX,FlexCAN In Transmission" "0: Not transmitting,1: Transmitting" rbitfld.long 0x10 4.--5. "FLTCONF,Fault Confinement State" "0: Bus Off,1: Error Passive,2: Bus Off,3: Bus Off" newline rbitfld.long 0x10 3. "RX,FlexCAN in Reception Flag" "0: Not receiving,1: Receiving" eventfld.long 0x10 2. "BOFFINT,Bus Off Interrupt Flag" "0: No such occurrence.,1: FlexCAN module entered Bus Off state." newline eventfld.long 0x10 1. "ERRINT,Error Interrupt Flag" "0: No such occurrence.,1: Indicates setting of any error flag in the Error.." line.long 0x14 "IMASK2,Interrupt Masks 2" hexmask.long 0x14 0.--31. 1. "BUF63TO32M,Buffer MBi Mask" line.long 0x18 "IMASK1,Interrupt Masks 1" hexmask.long 0x18 0.--31. 1. "BUF31TO0M,Buffer MBi Mask" line.long 0x1C "IFLAG2,Interrupt Flags 2" hexmask.long 0x1C 0.--31. 1. "BUF63TO32I,Buffer MBi Interrupt" line.long 0x20 "IFLAG1,Interrupt Flags 1" hexmask.long.tbyte 0x20 8.--31. 1. "BUF31TO8I,Buffer MBi Interrupt" eventfld.long 0x20 7. "BUF7I,Buffer MB7 Interrupt or Legacy RX FIFO Overflow" "0: No occurrence of MB7 completing transmission or..,1: MB7 completed transmission or reception or FIFO.." newline eventfld.long 0x20 6. "BUF6I,Buffer MB6 Interrupt or Legacy RX FIFO Warning" "0: No occurrence of MB6 completing transmission or..,1: MB6 completed transmission or reception or FIFO.." eventfld.long 0x20 5. "BUF5I,Buffer MB5 Interrupt or Frames available in Legacy RX FIFO" "0: No occurrence of completed transmission or..,1: MB5 completed transmission or reception or.." newline hexmask.long.byte 0x20 1.--4. 1. "BUF4TO1I,Buffer MBi Interrupt or Reserved" eventfld.long 0x20 0. "BUF0I,Buffer MB0 Interrupt or Clear Legacy FIFO bit" "0: MB0 has no occurrence of successfully completed..,1: MB0 has successfully completed transmission or.." line.long 0x24 "CTRL2,Control 2" bitfld.long 0x24 31. "ERRMSK_FAST,Error Interrupt Mask for Errors Detected in the Data Phase of Fast CAN FD Frames" "0: Disable,1: Enable" bitfld.long 0x24 30. "BOFFDONEMSK,Bus Off Done Interrupt Mask" "0: Disable,1: Enable" newline bitfld.long 0x24 29. "ECRWRE,Error Correction Configuration Register Write Enable" "0: Disable,1: Enable" bitfld.long 0x24 28. "WRMFRZ,Write Access to Memory in Freeze Mode" "0: Disable,1: Enable" newline hexmask.long.byte 0x24 24.--27. 1. "RFFN,Number of Legacy Receive FIFO Filters" hexmask.long.byte 0x24 19.--23. 1. "TASD,Transmission Arbitration Start Delay" newline bitfld.long 0x24 18. "MRP,Message Buffers Reception Priority" "0: Matching starts from Legacy RX FIFO or Enhanced..,1: Matching starts from message buffers and.." bitfld.long 0x24 17. "RRS,Remote Request Storing" "0: Generated,1: Stored" newline bitfld.long 0x24 16. "EACEN,Entire Frame Arbitration Field Comparison Enable for RX Message Buffers" "0: Disable,1: Enable" bitfld.long 0x24 15. "TIMER_SRC,Timer Source" "0: CAN bit clock,1: External time tick" newline bitfld.long 0x24 14. "PREXCEN,Protocol Exception Enable" "0: Disabled,1: Enabled" bitfld.long 0x24 13. "BTE,Bit Timing Expansion Enable" "0: Disable,1: Enable" newline bitfld.long 0x24 12. "ISOCANFDEN,ISO CAN FD Enable" "0: Disable. FlexCAN operates using the non-ISO CAN..,1: Enable. FlexCAN operates using the ISO CAN FD.." bitfld.long 0x24 11. "EDFLTDIS,Edge Filter Disable" "0: Enabled,1: Disabled" newline bitfld.long 0x24 8.--9. "MBTSBASE,Message Buffer Timestamp Base" "0: TIMER,1: Lower 16 bits of high-resolution timer,2: Upper 16 bits of high-resolution timer,?" bitfld.long 0x24 6.--7. "TSTAMPCAP,Timestamp Capture Point" "0: Disabled,1: End of the CAN frame,2: Start of the CAN frame,3: Start of frame for classical CAN frames; res bit.." rgroup.long 0x38++0x3 line.long 0x0 "ESR2,Error and Status 2" hexmask.long.byte 0x0 16.--22. 1. "LPTM,Lowest Priority TX Message Buffer" bitfld.long 0x0 14. "VPS,Valid Priority Status" "0: Invalid,1: Valid" newline bitfld.long 0x0 13. "IMB,Inactive Message Buffer" "0: Message buffer indicated by ESR2[LPTM] is not..,1: At least one message buffer is inactive." rgroup.long 0x44++0x3 line.long 0x0 "CRCR,Cyclic Redundancy Check" hexmask.long.byte 0x0 16.--22. 1. "MBCRC,CRC Message Buffer" hexmask.long.word 0x0 0.--14. 1. "TXCRC,Transmitted CRC value" group.long 0x48++0x3 line.long 0x0 "RXFGMASK,Legacy RX FIFO Global Mask" hexmask.long 0x0 0.--31. 1. "FGM,Legacy RX FIFO Global Mask Bits" rgroup.long 0x4C++0x3 line.long 0x0 "RXFIR,Legacy RX FIFO Information" hexmask.long.word 0x0 0.--8. 1. "IDHIT,Identifier Acceptance Filter Hit Indicator" group.long 0x50++0x3 line.long 0x0 "CBT,CAN Bit Timing" bitfld.long 0x0 31. "BTF,Bit Timing Format Enable" "0: Disable,1: Enable" hexmask.long.word 0x0 21.--30. 1. "EPRESDIV,Extended Prescaler Division Factor" newline hexmask.long.byte 0x0 16.--20. 1. "ERJW,Extended Resync Jump Width" hexmask.long.byte 0x0 10.--15. 1. "EPROPSEG,Extended Propagation Segment" newline hexmask.long.byte 0x0 5.--9. 1. "EPSEG1,Extended Phase Segment 1" hexmask.long.byte 0x0 0.--4. 1. "EPSEG2,Extended Phase Segment 2" group.long 0x6C++0x3 line.long 0x0 "IMASK3,Interrupt Masks 3" hexmask.long 0x0 0.--31. 1. "BUF95TO64M,Buffer MBi Mask" group.long 0x74++0x3 line.long 0x0 "IFLAG3,Interrupt Flags 3" hexmask.long 0x0 0.--31. 1. "BUF95TO64,Buffer MBi Interrupt" repeat 96. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x880)++0x3 line.long 0x0 "RXIMR[$1],Receive Individual Mask" hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits" repeat.end group.long 0xAE0++0xF line.long 0x0 "MECR,Memory Error Control" bitfld.long 0x0 31. "ECRWRDIS,Error Configuration Register Write Disable" "0: Enable,1: Disable" bitfld.long 0x0 19. "HANCEI_MSK,Host Access with Non-Correctable Errors Interrupt Mask" "0: Disable,1: Enable" newline bitfld.long 0x0 18. "FANCEI_MSK,FlexCAN Access with Non-Correctable Errors Interrupt Mask" "0: Disable,1: Enable" bitfld.long 0x0 16. "CEI_MSK,Correctable Errors Interrupt Mask" "0: Disable,1: Enable" newline bitfld.long 0x0 15. "HAERRIE,Host Access Error Injection Enable" "0: Disable,1: Enable" bitfld.long 0x0 14. "FAERRIE,FlexCAN Access Error Injection Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 13. "EXTERRIE,Extended Error Injection Enable" "0: Disable. Apply error injection only to the..,1: Enable. Apply error injection to the 64-bit word." bitfld.long 0x0 9. "RERRDIS,Error Report Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 8. "ECCDIS,Error Correction Disable" "0: Enable,1: Disable" bitfld.long 0x0 7. "NCEFAFRZ,Non-Correctable Errors in FlexCAN Access Put Device in Freeze Mode" "0: Keep normal operation.,1: Put FlexCAN in Freeze mode (see section 'Freeze.." line.long 0x4 "ERRIAR,Error Injection Address" hexmask.long.word 0x4 2.--13. 1. "INJADDR_H,Error Injection Address High" rbitfld.long 0x4 0.--1. "INJADDR_L,Error Injection Address Low" "0,1,2,3" line.long 0x8 "ERRIDPR,Error Injection Data Pattern" hexmask.long 0x8 0.--31. 1. "DFLIP,Data Flip Pattern" line.long 0xC "ERRIPPR,Error Injection Parity Pattern" hexmask.long.byte 0xC 24.--28. 1. "PFLIP3,Parity Flip Pattern for Byte 3 (Most Significant)" hexmask.long.byte 0xC 16.--20. 1. "PFLIP2,Parity Flip Pattern for Byte 2" newline hexmask.long.byte 0xC 8.--12. 1. "PFLIP1,Parity Flip Pattern for Byte 1" hexmask.long.byte 0xC 0.--4. 1. "PFLIP0,Parity Flip Pattern for Byte 0 (Least Significant)" rgroup.long 0xAF0++0xB line.long 0x0 "RERRAR,Error Report Address" bitfld.long 0x0 24. "NCE,Non-Correctable Error" "0: Reporting a correctable error,1: Reporting a non-correctable error" bitfld.long 0x0 16.--18. "SAID,SAID" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--13. 1. "ERRADDR,Address Where Error Detected" line.long 0x4 "RERRDR,Error Report Data" hexmask.long 0x4 0.--31. 1. "RDATA,Raw Data Word Read from Memory with Error" line.long 0x8 "RERRSYNR,Error Report Syndrome" bitfld.long 0x8 31. "BE3,Byte Enabled for Byte 3 (Most Significant)" "0: Byte was not read.,1: Byte was read." hexmask.long.byte 0x8 24.--28. 1. "SYND3,Error Syndrome for Byte 3 (Most Significant)" newline bitfld.long 0x8 23. "BE2,Byte Enabled for Byte 2" "0: Byte was not read.,1: Byte was read." hexmask.long.byte 0x8 16.--20. 1. "SYND2,Error Syndrome for Byte 2" newline bitfld.long 0x8 15. "BE1,Byte Enabled for Byte 1" "0: Byte was not read.,1: Byte was read." hexmask.long.byte 0x8 8.--12. 1. "SYND1,Error Syndrome for Byte 1" newline bitfld.long 0x8 7. "BE0,Byte Enabled for Byte 0 (Least Significant)" "0: Byte was not read.,1: Byte was read." hexmask.long.byte 0x8 0.--4. 1. "SYND0,Error Syndrome for Byte 0 (Least Significant)" group.long 0xAFC++0x3 line.long 0x0 "ERRSR,Error Status" eventfld.long 0x0 19. "HANCEIF,Host Access with Noncorrectable Error Interrupt Flag" "0: No errors detected,1: Error detected" eventfld.long 0x0 18. "FANCEIF,FlexCAN Access with Non-Correctable Error Interrupt Flag" "0: No errors detected,1: Error detected" newline eventfld.long 0x0 16. "CEIF,Correctable Error Interrupt Flag" "0: No errors detected,1: Error detected" eventfld.long 0x0 3. "HANCEIOF,Host Access With Non-Correctable Error Interrupt Overrun Flag" "0: No errors detected,1: Error detected" newline eventfld.long 0x0 2. "FANCEIOF,FlexCAN Access with Non-Correctable Error Interrupt Overrun Flag" "0: No errors detected,1: Error detected" eventfld.long 0x0 0. "CEIOF,Correctable Error Interrupt Overrun Flag" "0: No errors detected,1: Error detected" group.long 0xBF0++0x17 line.long 0x0 "EPRS,Enhanced CAN Bit Timing Prescalers" hexmask.long.word 0x0 16.--25. 1. "EDPRESDIV,Extended Data Phase Prescaler Division Factor" hexmask.long.word 0x0 0.--9. 1. "ENPRESDIV,Extended Nominal Prescaler Division Factor" line.long 0x4 "ENCBT,Enhanced Nominal CAN Bit Timing" hexmask.long.byte 0x4 22.--28. 1. "NRJW,Nominal Resynchronization Jump Width" hexmask.long.byte 0x4 12.--18. 1. "NTSEG2,Nominal Time Segment 2" newline hexmask.long.byte 0x4 0.--7. 1. "NTSEG1,Nominal Time Segment 1" line.long 0x8 "EDCBT,Enhanced Data Phase CAN Bit Timing" hexmask.long.byte 0x8 22.--25. 1. "DRJW,Data Phase Resynchronization Jump Width" hexmask.long.byte 0x8 12.--15. 1. "DTSEG2,Data Phase Time Segment 2" newline hexmask.long.byte 0x8 0.--4. 1. "DTSEG1,Data Phase Segment 1" line.long 0xC "ETDC,Enhanced Transceiver Delay Compensation" bitfld.long 0xC 31. "ETDCEN,Transceiver Delay Compensation Enable" "0: Disable,1: Enable" bitfld.long 0xC 30. "TDMDIS,Transceiver Delay Measurement Disable" "0: Enable,1: Disable" newline hexmask.long.byte 0xC 16.--22. 1. "ETDCOFF,Enhanced Transceiver Delay Compensation Offset" eventfld.long 0xC 15. "ETDCFAIL,Transceiver Delay Compensation Fail" "0: In range,1: Out of range" newline hexmask.long.byte 0xC 0.--7. 1. "ETDCVAL,Enhanced Transceiver Delay Compensation Value" line.long 0x10 "FDCTRL,CAN FD Control" bitfld.long 0x10 31. "FDRATE,Bit Rate Switch Enable" "0: Disable,1: Enable" bitfld.long 0x10 22.--23. "MBDSR2,Message Buffer Data Size for Region 2" "0: 8 bytes,1: 16 bytes,2: 32 bytes,3: 64 bytes" newline bitfld.long 0x10 19.--20. "MBDSR1,Message Buffer Data Size for Region 1" "0: 8 bytes,1: 16 bytes,2: 32 bytes,3: 64 bytes" bitfld.long 0x10 16.--17. "MBDSR0,Message Buffer Data Size for Region 0" "0: 8 bytes,1: 16 bytes,2: 32 bytes,3: 64 bytes" newline bitfld.long 0x10 15. "TDCEN,Transceiver Delay Compensation Enable" "0: Disable,1: Enable" eventfld.long 0x10 14. "TDCFAIL,Transceiver Delay Compensation Fail" "0: In range,1: Out of range" newline hexmask.long.byte 0x10 8.--12. 1. "TDCOFF,Transceiver Delay Compensation Offset" hexmask.long.byte 0x10 0.--5. 1. "TDCVAL,Transceiver Delay Compensation Value" line.long 0x14 "FDCBT,CAN FD Bit Timing" hexmask.long.word 0x14 20.--29. 1. "FPRESDIV,Fast Prescaler Division Factor" bitfld.long 0x14 16.--18. "FRJW,Fast Resync Jump Width" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 10.--14. 1. "FPROPSEG,Fast Propagation Segment" bitfld.long 0x14 5.--7. "FPSEG1,Fast Phase Segment 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 0.--2. "FPSEG2,Fast Phase Segment 2" "0,1,2,3,4,5,6,7" rgroup.long 0xC08++0x3 line.long 0x0 "FDCRC,CAN FD CRC" hexmask.long.byte 0x0 24.--30. 1. "FD_MBCRC,CRC Message Buffer Number for FD_TXCRC" hexmask.long.tbyte 0x0 0.--20. 1. "FD_TXCRC,Extended Transmitted CRC value" group.long 0xC0C++0xB line.long 0x0 "ERFCR,Enhanced RX FIFO Control" bitfld.long 0x0 31. "ERFEN,Enhanced RX FIFO enable" "0: Disable,1: Enable" hexmask.long.byte 0x0 26.--30. 1. "DMALW,DMA Last Word" newline hexmask.long.byte 0x0 16.--22. 1. "NEXIF,Number of Extended ID Filter Elements" hexmask.long.byte 0x0 8.--13. 1. "NFE,Number of Enhanced RX FIFO Filter Elements" newline hexmask.long.byte 0x0 0.--4. 1. "ERFWM,Enhanced RX FIFO Watermark" line.long 0x4 "ERFIER,Enhanced RX FIFO Interrupt Enable" bitfld.long 0x4 31. "ERFUFWIE,Enhanced RX FIFO Underflow Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x4 30. "ERFOVFIE,Enhanced RX FIFO Overflow Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x4 29. "ERFWMIIE,Enhanced RX FIFO Watermark Indication Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x4 28. "ERFDAIE,Enhanced RX FIFO Data Available Interrupt Enable" "0: Disable,1: Enable" line.long 0x8 "ERFSR,Enhanced RX FIFO Status" eventfld.long 0x8 31. "ERFUFW,Enhanced RX FIFO Underflow Flag" "0: No such occurrence,1: Underflow" eventfld.long 0x8 30. "ERFOVF,Enhanced RX FIFO Overflow Flag" "0: No such occurrence,1: Overflow" newline eventfld.long 0x8 29. "ERFWMI,Enhanced RX FIFO Watermark Indication Flag" "0: No such occurrence,1: Number of messages in FIFO is greater than the.." eventfld.long 0x8 28. "ERFDA,Enhanced RX FIFO Data Available Flag" "0: No such occurrence,1: At least one message stored in Enhanced RX FIFO" newline bitfld.long 0x8 27. "ERFCLR,Enhanced RX FIFO Clear" "0: No effect,1: Clear enhanced RX FIFO content" rbitfld.long 0x8 17. "ERFE,Enhanced RX FIFO Empty Flag" "0: Not empty,1: Empty" newline rbitfld.long 0x8 16. "ERFF,Enhanced RX FIFO Full Flag" "0: Not full,1: Full" hexmask.long.byte 0x8 0.--5. 1. "ERFEL,Enhanced RX FIFO Elements" repeat 96. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xC30)++0x3 line.long 0x0 "HR_TIME_STAMP[$1],High-Resolution Timestamp" hexmask.long 0x0 0.--31. 1. "TS,High-Resolution Timestamp" repeat.end repeat 128. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x3000)++0x3 line.long 0x0 "ERFFEL[$1],Enhanced RX FIFO Filter Element" hexmask.long 0x0 0.--31. 1. "FEL,Filter Element Bits" repeat.end tree.end tree "CAN_2" base ad:0x4030C000 group.long 0x0++0xB line.long 0x0 "MCR,Module Configuration" bitfld.long 0x0 31. "MDIS,Module Disable" "0: Enable,1: Disable" bitfld.long 0x0 30. "FRZ,Freeze Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 29. "RFEN,Legacy RX FIFO Enable" "0: Disable,1: Enable" bitfld.long 0x0 28. "HALT,Halt FlexCAN" "0: No request,1: Enter Freeze mode if MCR[FRZ] = 1." newline rbitfld.long 0x0 27. "NOTRDY,FlexCAN Not Ready" "0: FlexCAN is in Normal mode Listen-Only mode or..,1: FlexCAN is in Disable mode or Freeze mode." bitfld.long 0x0 25. "SOFTRST,Soft Reset" "0: No reset,1: Soft reset affects reset registers" newline rbitfld.long 0x0 24. "FRZACK,Freeze Mode Acknowledge" "0: Not in Freeze mode prescaler running.,1: In Freeze mode prescaler stopped." bitfld.long 0x0 23. "SUPV,Supervisor Mode" "0: User mode,1: Supervisor mode" newline bitfld.long 0x0 21. "WRNEN,Warning Interrupt Enable" "0: Disable,1: Enable" rbitfld.long 0x0 20. "LPMACK,Low-Power Mode Acknowledge" "0: Not in a low-power mode,1: In a low-power mode" newline bitfld.long 0x0 17. "SRXDIS,Self-Reception Disable" "0: Enable,1: Disable" bitfld.long 0x0 16. "IRMQ,Individual RX Masking and Queue Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 15. "DMA,DMA Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "LPRIOEN,Local Priority Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 12. "AEN,Abort Enable" "0: Disabled,1: Enabled" bitfld.long 0x0 11. "FDEN,CAN FD Operation Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 8.--9. "IDAM,ID Acceptance Mode" "0: Format A: One full ID (standard and extended)..,1: Format B: Two full standard IDs or two partial..,2: Format C: Four partial 8-bit standard IDs per ID..,3: Format D: All frames rejected." hexmask.long.byte 0x0 0.--6. 1. "MAXMB,Number of the Last Message Buffer" line.long 0x4 "CTRL1,Control 1" hexmask.long.byte 0x4 24.--31. 1. "PRESDIV,Prescaler Division Factor" bitfld.long 0x4 22.--23. "RJW,Resync Jump Width" "0,1,2,3" newline bitfld.long 0x4 19.--21. "PSEG1,Phase Segment 1" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "PSEG2,Phase Segment 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 15. "BOFFMSK,Bus Off Interrupt Mask" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 14. "ERRMSK,Error Interrupt Mask" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 12. "LPB,Loopback Mode" "0: Disabled,1: Enabled" bitfld.long 0x4 11. "TWRNMSK,TX Warning Interrupt Mask" "0: Disabled,1: Enabled" newline bitfld.long 0x4 10. "RWRNMSK,RX Warning Interrupt Mask" "0: Disabled,1: Enabled" bitfld.long 0x4 7. "SMP,CAN Bit Sampling" "0: One sample is used to determine the bit value.,1: Three samples are used to determine the value of.." newline bitfld.long 0x4 6. "BOFFREC,Bus Off Recovery" "0: Enabled,1: Disabled" bitfld.long 0x4 5. "TSYN,Timer Sync" "0: Disable,1: Enable" newline bitfld.long 0x4 4. "LBUF,Lowest Buffer Transmitted First" "0: Buffer with highest priority is transmitted first.,1: Lowest number buffer is transmitted first." bitfld.long 0x4 3. "LOM,Listen-Only Mode" "0: Listen-Only mode is deactivated.,1: FlexCAN module operates in Listen-Only mode." newline bitfld.long 0x4 0.--2. "PROPSEG,Propagation Segment" "0,1,2,3,4,5,6,7" line.long 0x8 "TIMER,Free-Running Timer" hexmask.long.word 0x8 0.--15. 1. "TIMER,Timer Value" group.long 0x10++0x27 line.long 0x0 "RXMGMASK,RX Message Buffers Global Mask" hexmask.long 0x0 0.--31. 1. "MG,Global Mask for RX Message Buffers" line.long 0x4 "RX14MASK,Receive 14 Mask" hexmask.long 0x4 0.--31. 1. "RX14M,RX Buffer 14 Mask Bits" line.long 0x8 "RX15MASK,Receive 15 Mask" hexmask.long 0x8 0.--31. 1. "RX15M,RX Buffer 15 Mask Bits" line.long 0xC "ECR,Error Counter" hexmask.long.byte 0xC 24.--31. 1. "RXERRCNT_FAST,Receive Error Counter for Fast Bits" hexmask.long.byte 0xC 16.--23. 1. "TXERRCNT_FAST,Transmit Error Counter for Fast Bits" newline hexmask.long.byte 0xC 8.--15. 1. "RXERRCNT,Receive Error Counter" hexmask.long.byte 0xC 0.--7. 1. "TXERRCNT,Transmit Error Counter" line.long 0x10 "ESR1,Error and Status 1" rbitfld.long 0x10 31. "BIT1ERR_FAST,Fast Bit1 Error Flag" "0: No such occurrence.,1: At least one bit sent as recessive is received.." rbitfld.long 0x10 30. "BIT0ERR_FAST,Fast Bit0 Error Flag" "0: No such occurrence.,1: At least one bit sent as dominant is received as.." newline rbitfld.long 0x10 28. "CRCERR_FAST,Fast Cyclic Redundancy Check Error Flag" "0: No such occurrence.,1: A CRC error occurred since last read of this.." rbitfld.long 0x10 27. "FRMERR_FAST,Fast Form Error Flag" "0: No such occurrence.,1: A form error occurred since last read of this.." newline rbitfld.long 0x10 26. "STFERR_FAST,Fast Stuffing Error Flag" "0: No such occurrence.,1: A stuffing error occurred since last read of.." eventfld.long 0x10 21. "ERROVR,Error Overrun Flag" "0: No overrun,1: Overrun" newline eventfld.long 0x10 20. "ERRINT_FAST,Fast Error Interrupt Flag" "0: No such occurrence.,1: Error flag set in the data phase of CAN FD.." eventfld.long 0x10 19. "BOFFDONEINT,Bus Off Done Interrupt Flag" "0: No such occurrence,1: FlexCAN module has completed Bus Off process." newline rbitfld.long 0x10 18. "SYNCH,CAN Synchronization Status Flag" "0: Not synchronized,1: Synchronized" eventfld.long 0x10 17. "TWRNINT,TX Warning Interrupt Flag" "0: No such occurrence,1: TX error counter changed from less than 96 to.." newline eventfld.long 0x10 16. "RWRNINT,RX Warning Interrupt Flag" "0: No such occurrence,1: RX error counter changed from less than 96 to.." rbitfld.long 0x10 15. "BIT1ERR,Bit1 Error Flag" "0: No such occurrence.,1: At least one bit sent as recessive is received.." newline rbitfld.long 0x10 14. "BIT0ERR,Bit0 Error Flag" "0: No such occurrence.,1: At least one bit sent as dominant is received as.." rbitfld.long 0x10 13. "ACKERR,Acknowledge Error Flag" "0: No error,1: An ACK error occurred since last read of this.." newline rbitfld.long 0x10 12. "CRCERR,Cyclic Redundancy Check Error Flag" "0: No error,1: A CRC error occurred since last read of this.." rbitfld.long 0x10 11. "FRMERR,Form Error Flag" "0: No error,1: A Form Error occurred since last read of this.." newline rbitfld.long 0x10 10. "STFERR,Stuffing Error Flag" "0: No error,1: Error occurred since last read of this register." rbitfld.long 0x10 9. "TXWRN,TX Error Warning Flag" "0: No such occurrence.,1: TXERRCNT is 96 or greater." newline rbitfld.long 0x10 8. "RXWRN,RX Error Warning Flag" "0: No such occurrence.,1: RXERRCNT is greater than or equal to 96." rbitfld.long 0x10 7. "IDLE,Idle" "0: Not IDLE,1: IDLE" newline rbitfld.long 0x10 6. "TX,FlexCAN In Transmission" "0: Not transmitting,1: Transmitting" rbitfld.long 0x10 4.--5. "FLTCONF,Fault Confinement State" "0: Bus Off,1: Error Passive,2: Bus Off,3: Bus Off" newline rbitfld.long 0x10 3. "RX,FlexCAN in Reception Flag" "0: Not receiving,1: Receiving" eventfld.long 0x10 2. "BOFFINT,Bus Off Interrupt Flag" "0: No such occurrence.,1: FlexCAN module entered Bus Off state." newline eventfld.long 0x10 1. "ERRINT,Error Interrupt Flag" "0: No such occurrence.,1: Indicates setting of any error flag in the Error.." line.long 0x14 "IMASK2,Interrupt Masks 2" hexmask.long 0x14 0.--31. 1. "BUF63TO32M,Buffer MBi Mask" line.long 0x18 "IMASK1,Interrupt Masks 1" hexmask.long 0x18 0.--31. 1. "BUF31TO0M,Buffer MBi Mask" line.long 0x1C "IFLAG2,Interrupt Flags 2" hexmask.long 0x1C 0.--31. 1. "BUF63TO32I,Buffer MBi Interrupt" line.long 0x20 "IFLAG1,Interrupt Flags 1" hexmask.long.tbyte 0x20 8.--31. 1. "BUF31TO8I,Buffer MBi Interrupt" eventfld.long 0x20 7. "BUF7I,Buffer MB7 Interrupt or Legacy RX FIFO Overflow" "0: No occurrence of MB7 completing transmission or..,1: MB7 completed transmission or reception or FIFO.." newline eventfld.long 0x20 6. "BUF6I,Buffer MB6 Interrupt or Legacy RX FIFO Warning" "0: No occurrence of MB6 completing transmission or..,1: MB6 completed transmission or reception or FIFO.." eventfld.long 0x20 5. "BUF5I,Buffer MB5 Interrupt or Frames available in Legacy RX FIFO" "0: No occurrence of completed transmission or..,1: MB5 completed transmission or reception or.." newline hexmask.long.byte 0x20 1.--4. 1. "BUF4TO1I,Buffer MBi Interrupt or Reserved" eventfld.long 0x20 0. "BUF0I,Buffer MB0 Interrupt or Clear Legacy FIFO bit" "0: MB0 has no occurrence of successfully completed..,1: MB0 has successfully completed transmission or.." line.long 0x24 "CTRL2,Control 2" bitfld.long 0x24 31. "ERRMSK_FAST,Error Interrupt Mask for Errors Detected in the Data Phase of Fast CAN FD Frames" "0: Disable,1: Enable" bitfld.long 0x24 30. "BOFFDONEMSK,Bus Off Done Interrupt Mask" "0: Disable,1: Enable" newline bitfld.long 0x24 29. "ECRWRE,Error Correction Configuration Register Write Enable" "0: Disable,1: Enable" bitfld.long 0x24 28. "WRMFRZ,Write Access to Memory in Freeze Mode" "0: Disable,1: Enable" newline hexmask.long.byte 0x24 24.--27. 1. "RFFN,Number of Legacy Receive FIFO Filters" hexmask.long.byte 0x24 19.--23. 1. "TASD,Transmission Arbitration Start Delay" newline bitfld.long 0x24 18. "MRP,Message Buffers Reception Priority" "0: Matching starts from Legacy RX FIFO or Enhanced..,1: Matching starts from message buffers and.." bitfld.long 0x24 17. "RRS,Remote Request Storing" "0: Generated,1: Stored" newline bitfld.long 0x24 16. "EACEN,Entire Frame Arbitration Field Comparison Enable for RX Message Buffers" "0: Disable,1: Enable" bitfld.long 0x24 15. "TIMER_SRC,Timer Source" "0: CAN bit clock,1: External time tick" newline bitfld.long 0x24 14. "PREXCEN,Protocol Exception Enable" "0: Disabled,1: Enabled" bitfld.long 0x24 13. "BTE,Bit Timing Expansion Enable" "0: Disable,1: Enable" newline bitfld.long 0x24 12. "ISOCANFDEN,ISO CAN FD Enable" "0: Disable. FlexCAN operates using the non-ISO CAN..,1: Enable. FlexCAN operates using the ISO CAN FD.." bitfld.long 0x24 11. "EDFLTDIS,Edge Filter Disable" "0: Enabled,1: Disabled" newline bitfld.long 0x24 8.--9. "MBTSBASE,Message Buffer Timestamp Base" "0: TIMER,1: Lower 16 bits of high-resolution timer,2: Upper 16 bits of high-resolution timer,?" bitfld.long 0x24 6.--7. "TSTAMPCAP,Timestamp Capture Point" "0: Disabled,1: End of the CAN frame,2: Start of the CAN frame,3: Start of frame for classical CAN frames; res bit.." rgroup.long 0x38++0x3 line.long 0x0 "ESR2,Error and Status 2" hexmask.long.byte 0x0 16.--22. 1. "LPTM,Lowest Priority TX Message Buffer" bitfld.long 0x0 14. "VPS,Valid Priority Status" "0: Invalid,1: Valid" newline bitfld.long 0x0 13. "IMB,Inactive Message Buffer" "0: Message buffer indicated by ESR2[LPTM] is not..,1: At least one message buffer is inactive." rgroup.long 0x44++0x3 line.long 0x0 "CRCR,Cyclic Redundancy Check" hexmask.long.byte 0x0 16.--22. 1. "MBCRC,CRC Message Buffer" hexmask.long.word 0x0 0.--14. 1. "TXCRC,Transmitted CRC value" group.long 0x48++0x3 line.long 0x0 "RXFGMASK,Legacy RX FIFO Global Mask" hexmask.long 0x0 0.--31. 1. "FGM,Legacy RX FIFO Global Mask Bits" rgroup.long 0x4C++0x3 line.long 0x0 "RXFIR,Legacy RX FIFO Information" hexmask.long.word 0x0 0.--8. 1. "IDHIT,Identifier Acceptance Filter Hit Indicator" group.long 0x50++0x3 line.long 0x0 "CBT,CAN Bit Timing" bitfld.long 0x0 31. "BTF,Bit Timing Format Enable" "0: Disable,1: Enable" hexmask.long.word 0x0 21.--30. 1. "EPRESDIV,Extended Prescaler Division Factor" newline hexmask.long.byte 0x0 16.--20. 1. "ERJW,Extended Resync Jump Width" hexmask.long.byte 0x0 10.--15. 1. "EPROPSEG,Extended Propagation Segment" newline hexmask.long.byte 0x0 5.--9. 1. "EPSEG1,Extended Phase Segment 1" hexmask.long.byte 0x0 0.--4. 1. "EPSEG2,Extended Phase Segment 2" group.long 0x6C++0x3 line.long 0x0 "IMASK3,Interrupt Masks 3" hexmask.long 0x0 0.--31. 1. "BUF95TO64M,Buffer MBi Mask" group.long 0x74++0x3 line.long 0x0 "IFLAG3,Interrupt Flags 3" hexmask.long 0x0 0.--31. 1. "BUF95TO64,Buffer MBi Interrupt" repeat 96. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x880)++0x3 line.long 0x0 "RXIMR[$1],Receive Individual Mask" hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits" repeat.end group.long 0xAE0++0xF line.long 0x0 "MECR,Memory Error Control" bitfld.long 0x0 31. "ECRWRDIS,Error Configuration Register Write Disable" "0: Enable,1: Disable" bitfld.long 0x0 19. "HANCEI_MSK,Host Access with Non-Correctable Errors Interrupt Mask" "0: Disable,1: Enable" newline bitfld.long 0x0 18. "FANCEI_MSK,FlexCAN Access with Non-Correctable Errors Interrupt Mask" "0: Disable,1: Enable" bitfld.long 0x0 16. "CEI_MSK,Correctable Errors Interrupt Mask" "0: Disable,1: Enable" newline bitfld.long 0x0 15. "HAERRIE,Host Access Error Injection Enable" "0: Disable,1: Enable" bitfld.long 0x0 14. "FAERRIE,FlexCAN Access Error Injection Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 13. "EXTERRIE,Extended Error Injection Enable" "0: Disable. Apply error injection only to the..,1: Enable. Apply error injection to the 64-bit word." bitfld.long 0x0 9. "RERRDIS,Error Report Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 8. "ECCDIS,Error Correction Disable" "0: Enable,1: Disable" bitfld.long 0x0 7. "NCEFAFRZ,Non-Correctable Errors in FlexCAN Access Put Device in Freeze Mode" "0: Keep normal operation.,1: Put FlexCAN in Freeze mode (see section 'Freeze.." line.long 0x4 "ERRIAR,Error Injection Address" hexmask.long.word 0x4 2.--13. 1. "INJADDR_H,Error Injection Address High" rbitfld.long 0x4 0.--1. "INJADDR_L,Error Injection Address Low" "0,1,2,3" line.long 0x8 "ERRIDPR,Error Injection Data Pattern" hexmask.long 0x8 0.--31. 1. "DFLIP,Data Flip Pattern" line.long 0xC "ERRIPPR,Error Injection Parity Pattern" hexmask.long.byte 0xC 24.--28. 1. "PFLIP3,Parity Flip Pattern for Byte 3 (Most Significant)" hexmask.long.byte 0xC 16.--20. 1. "PFLIP2,Parity Flip Pattern for Byte 2" newline hexmask.long.byte 0xC 8.--12. 1. "PFLIP1,Parity Flip Pattern for Byte 1" hexmask.long.byte 0xC 0.--4. 1. "PFLIP0,Parity Flip Pattern for Byte 0 (Least Significant)" rgroup.long 0xAF0++0xB line.long 0x0 "RERRAR,Error Report Address" bitfld.long 0x0 24. "NCE,Non-Correctable Error" "0: Reporting a correctable error,1: Reporting a non-correctable error" bitfld.long 0x0 16.--18. "SAID,SAID" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--13. 1. "ERRADDR,Address Where Error Detected" line.long 0x4 "RERRDR,Error Report Data" hexmask.long 0x4 0.--31. 1. "RDATA,Raw Data Word Read from Memory with Error" line.long 0x8 "RERRSYNR,Error Report Syndrome" bitfld.long 0x8 31. "BE3,Byte Enabled for Byte 3 (Most Significant)" "0: Byte was not read.,1: Byte was read." hexmask.long.byte 0x8 24.--28. 1. "SYND3,Error Syndrome for Byte 3 (Most Significant)" newline bitfld.long 0x8 23. "BE2,Byte Enabled for Byte 2" "0: Byte was not read.,1: Byte was read." hexmask.long.byte 0x8 16.--20. 1. "SYND2,Error Syndrome for Byte 2" newline bitfld.long 0x8 15. "BE1,Byte Enabled for Byte 1" "0: Byte was not read.,1: Byte was read." hexmask.long.byte 0x8 8.--12. 1. "SYND1,Error Syndrome for Byte 1" newline bitfld.long 0x8 7. "BE0,Byte Enabled for Byte 0 (Least Significant)" "0: Byte was not read.,1: Byte was read." hexmask.long.byte 0x8 0.--4. 1. "SYND0,Error Syndrome for Byte 0 (Least Significant)" group.long 0xAFC++0x3 line.long 0x0 "ERRSR,Error Status" eventfld.long 0x0 19. "HANCEIF,Host Access with Noncorrectable Error Interrupt Flag" "0: No errors detected,1: Error detected" eventfld.long 0x0 18. "FANCEIF,FlexCAN Access with Non-Correctable Error Interrupt Flag" "0: No errors detected,1: Error detected" newline eventfld.long 0x0 16. "CEIF,Correctable Error Interrupt Flag" "0: No errors detected,1: Error detected" eventfld.long 0x0 3. "HANCEIOF,Host Access With Non-Correctable Error Interrupt Overrun Flag" "0: No errors detected,1: Error detected" newline eventfld.long 0x0 2. "FANCEIOF,FlexCAN Access with Non-Correctable Error Interrupt Overrun Flag" "0: No errors detected,1: Error detected" eventfld.long 0x0 0. "CEIOF,Correctable Error Interrupt Overrun Flag" "0: No errors detected,1: Error detected" group.long 0xBF0++0x17 line.long 0x0 "EPRS,Enhanced CAN Bit Timing Prescalers" hexmask.long.word 0x0 16.--25. 1. "EDPRESDIV,Extended Data Phase Prescaler Division Factor" hexmask.long.word 0x0 0.--9. 1. "ENPRESDIV,Extended Nominal Prescaler Division Factor" line.long 0x4 "ENCBT,Enhanced Nominal CAN Bit Timing" hexmask.long.byte 0x4 22.--28. 1. "NRJW,Nominal Resynchronization Jump Width" hexmask.long.byte 0x4 12.--18. 1. "NTSEG2,Nominal Time Segment 2" newline hexmask.long.byte 0x4 0.--7. 1. "NTSEG1,Nominal Time Segment 1" line.long 0x8 "EDCBT,Enhanced Data Phase CAN Bit Timing" hexmask.long.byte 0x8 22.--25. 1. "DRJW,Data Phase Resynchronization Jump Width" hexmask.long.byte 0x8 12.--15. 1. "DTSEG2,Data Phase Time Segment 2" newline hexmask.long.byte 0x8 0.--4. 1. "DTSEG1,Data Phase Segment 1" line.long 0xC "ETDC,Enhanced Transceiver Delay Compensation" bitfld.long 0xC 31. "ETDCEN,Transceiver Delay Compensation Enable" "0: Disable,1: Enable" bitfld.long 0xC 30. "TDMDIS,Transceiver Delay Measurement Disable" "0: Enable,1: Disable" newline hexmask.long.byte 0xC 16.--22. 1. "ETDCOFF,Enhanced Transceiver Delay Compensation Offset" eventfld.long 0xC 15. "ETDCFAIL,Transceiver Delay Compensation Fail" "0: In range,1: Out of range" newline hexmask.long.byte 0xC 0.--7. 1. "ETDCVAL,Enhanced Transceiver Delay Compensation Value" line.long 0x10 "FDCTRL,CAN FD Control" bitfld.long 0x10 31. "FDRATE,Bit Rate Switch Enable" "0: Disable,1: Enable" bitfld.long 0x10 22.--23. "MBDSR2,Message Buffer Data Size for Region 2" "0: 8 bytes,1: 16 bytes,2: 32 bytes,3: 64 bytes" newline bitfld.long 0x10 19.--20. "MBDSR1,Message Buffer Data Size for Region 1" "0: 8 bytes,1: 16 bytes,2: 32 bytes,3: 64 bytes" bitfld.long 0x10 16.--17. "MBDSR0,Message Buffer Data Size for Region 0" "0: 8 bytes,1: 16 bytes,2: 32 bytes,3: 64 bytes" newline bitfld.long 0x10 15. "TDCEN,Transceiver Delay Compensation Enable" "0: Disable,1: Enable" eventfld.long 0x10 14. "TDCFAIL,Transceiver Delay Compensation Fail" "0: In range,1: Out of range" newline hexmask.long.byte 0x10 8.--12. 1. "TDCOFF,Transceiver Delay Compensation Offset" hexmask.long.byte 0x10 0.--5. 1. "TDCVAL,Transceiver Delay Compensation Value" line.long 0x14 "FDCBT,CAN FD Bit Timing" hexmask.long.word 0x14 20.--29. 1. "FPRESDIV,Fast Prescaler Division Factor" bitfld.long 0x14 16.--18. "FRJW,Fast Resync Jump Width" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 10.--14. 1. "FPROPSEG,Fast Propagation Segment" bitfld.long 0x14 5.--7. "FPSEG1,Fast Phase Segment 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 0.--2. "FPSEG2,Fast Phase Segment 2" "0,1,2,3,4,5,6,7" rgroup.long 0xC08++0x3 line.long 0x0 "FDCRC,CAN FD CRC" hexmask.long.byte 0x0 24.--30. 1. "FD_MBCRC,CRC Message Buffer Number for FD_TXCRC" hexmask.long.tbyte 0x0 0.--20. 1. "FD_TXCRC,Extended Transmitted CRC value" group.long 0xC0C++0xB line.long 0x0 "ERFCR,Enhanced RX FIFO Control" bitfld.long 0x0 31. "ERFEN,Enhanced RX FIFO enable" "0: Disable,1: Enable" hexmask.long.byte 0x0 26.--30. 1. "DMALW,DMA Last Word" newline hexmask.long.byte 0x0 16.--22. 1. "NEXIF,Number of Extended ID Filter Elements" hexmask.long.byte 0x0 8.--13. 1. "NFE,Number of Enhanced RX FIFO Filter Elements" newline hexmask.long.byte 0x0 0.--4. 1. "ERFWM,Enhanced RX FIFO Watermark" line.long 0x4 "ERFIER,Enhanced RX FIFO Interrupt Enable" bitfld.long 0x4 31. "ERFUFWIE,Enhanced RX FIFO Underflow Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x4 30. "ERFOVFIE,Enhanced RX FIFO Overflow Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x4 29. "ERFWMIIE,Enhanced RX FIFO Watermark Indication Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x4 28. "ERFDAIE,Enhanced RX FIFO Data Available Interrupt Enable" "0: Disable,1: Enable" line.long 0x8 "ERFSR,Enhanced RX FIFO Status" eventfld.long 0x8 31. "ERFUFW,Enhanced RX FIFO Underflow Flag" "0: No such occurrence,1: Underflow" eventfld.long 0x8 30. "ERFOVF,Enhanced RX FIFO Overflow Flag" "0: No such occurrence,1: Overflow" newline eventfld.long 0x8 29. "ERFWMI,Enhanced RX FIFO Watermark Indication Flag" "0: No such occurrence,1: Number of messages in FIFO is greater than the.." eventfld.long 0x8 28. "ERFDA,Enhanced RX FIFO Data Available Flag" "0: No such occurrence,1: At least one message stored in Enhanced RX FIFO" newline bitfld.long 0x8 27. "ERFCLR,Enhanced RX FIFO Clear" "0: No effect,1: Clear enhanced RX FIFO content" rbitfld.long 0x8 17. "ERFE,Enhanced RX FIFO Empty Flag" "0: Not empty,1: Empty" newline rbitfld.long 0x8 16. "ERFF,Enhanced RX FIFO Full Flag" "0: Not full,1: Full" hexmask.long.byte 0x8 0.--5. 1. "ERFEL,Enhanced RX FIFO Elements" repeat 96. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xC30)++0x3 line.long 0x0 "HR_TIME_STAMP[$1],High-Resolution Timestamp" hexmask.long 0x0 0.--31. 1. "TS,High-Resolution Timestamp" repeat.end repeat 128. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x3000)++0x3 line.long 0x0 "ERFFEL[$1],Enhanced RX FIFO Filter Element" hexmask.long 0x0 0.--31. 1. "FEL,Filter Element Bits" repeat.end tree.end tree "CAN_3" base ad:0x40310000 group.long 0x0++0xB line.long 0x0 "MCR,Module Configuration" bitfld.long 0x0 31. "MDIS,Module Disable" "0: Enable,1: Disable" bitfld.long 0x0 30. "FRZ,Freeze Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 29. "RFEN,RX FIFO Enable" "0: Disable,1: Enable" bitfld.long 0x0 28. "HALT,Halt FlexCAN" "0: No request,1: Enter Freeze mode if MCR[FRZ] = 1." newline rbitfld.long 0x0 27. "NOTRDY,FlexCAN Not Ready" "0: FlexCAN is in Normal mode Listen-Only mode or..,1: FlexCAN is in Disable mode or Freeze mode." bitfld.long 0x0 25. "SOFTRST,Soft Reset" "0: No reset,1: Soft reset affects reset registers" newline rbitfld.long 0x0 24. "FRZACK,Freeze Mode Acknowledge" "0: Not in Freeze mode prescaler running.,1: In Freeze mode prescaler stopped." bitfld.long 0x0 23. "SUPV,Supervisor Mode" "0: User mode,1: Supervisor mode" newline bitfld.long 0x0 21. "WRNEN,Warning Interrupt Enable" "0: Disable,1: Enable" rbitfld.long 0x0 20. "LPMACK,Low-Power Mode Acknowledge" "0: Not in a low-power mode,1: In a low-power mode" newline bitfld.long 0x0 17. "SRXDIS,Self-Reception Disable" "0: Enable,1: Disable" bitfld.long 0x0 16. "IRMQ,Individual RX Masking and Queue Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 15. "DMA,DMA Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "LPRIOEN,Local Priority Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 12. "AEN,Abort Enable" "0: Disabled,1: Enabled" bitfld.long 0x0 11. "FDEN,CAN FD Operation Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 8.--9. "IDAM,ID Acceptance Mode" "0: Format A: One full ID (standard and extended)..,1: Format B: Two full standard IDs or two partial..,2: Format C: Four partial 8-bit standard IDs per ID..,3: Format D: All frames rejected." hexmask.long.byte 0x0 0.--6. 1. "MAXMB,Number of the Last Message Buffer" line.long 0x4 "CTRL1,Control 1" hexmask.long.byte 0x4 24.--31. 1. "PRESDIV,Prescaler Division Factor" bitfld.long 0x4 22.--23. "RJW,Resync Jump Width" "0,1,2,3" newline bitfld.long 0x4 19.--21. "PSEG1,Phase Segment 1" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "PSEG2,Phase Segment 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 15. "BOFFMSK,Bus Off Interrupt Mask" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 14. "ERRMSK,Error Interrupt Mask" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 12. "LPB,Loopback Mode" "0: Disabled,1: Enabled" bitfld.long 0x4 11. "TWRNMSK,TX Warning Interrupt Mask" "0: Disabled,1: Enabled" newline bitfld.long 0x4 10. "RWRNMSK,RX Warning Interrupt Mask" "0: Disabled,1: Enabled" bitfld.long 0x4 7. "SMP,CAN Bit Sampling" "0: One sample is used to determine the bit value.,1: Three samples are used to determine the value of.." newline bitfld.long 0x4 6. "BOFFREC,Bus Off Recovery" "0: Enabled,1: Disabled" bitfld.long 0x4 5. "TSYN,Timer Sync" "0: Disable,1: Enable" newline bitfld.long 0x4 4. "LBUF,Lowest Buffer Transmitted First" "0: Buffer with highest priority is transmitted first.,1: Lowest number buffer is transmitted first." bitfld.long 0x4 3. "LOM,Listen-Only Mode" "0: Listen-Only mode is deactivated.,1: FlexCAN module operates in Listen-Only mode." newline bitfld.long 0x4 0.--2. "PROPSEG,Propagation Segment" "0,1,2,3,4,5,6,7" line.long 0x8 "TIMER,Free-Running Timer" hexmask.long.word 0x8 0.--15. 1. "TIMER,Timer Value" group.long 0x10++0x27 line.long 0x0 "RXMGMASK,RX Message Buffers Global Mask" hexmask.long 0x0 0.--31. 1. "MG,Global Mask for RX Message Buffers" line.long 0x4 "RX14MASK,Receive 14 Mask" hexmask.long 0x4 0.--31. 1. "RX14M,RX Buffer 14 Mask Bits" line.long 0x8 "RX15MASK,Receive 15 Mask" hexmask.long 0x8 0.--31. 1. "RX15M,RX Buffer 15 Mask Bits" line.long 0xC "ECR,Error Counter" hexmask.long.byte 0xC 24.--31. 1. "RXERRCNT_FAST,Receive Error Counter for Fast Bits" hexmask.long.byte 0xC 16.--23. 1. "TXERRCNT_FAST,Transmit Error Counter for Fast Bits" newline hexmask.long.byte 0xC 8.--15. 1. "RXERRCNT,Receive Error Counter" hexmask.long.byte 0xC 0.--7. 1. "TXERRCNT,Transmit Error Counter" line.long 0x10 "ESR1,Error and Status 1" rbitfld.long 0x10 31. "BIT1ERR_FAST,Fast Bit1 Error Flag" "0: No such occurrence.,1: At least one bit sent as recessive is received.." rbitfld.long 0x10 30. "BIT0ERR_FAST,Fast Bit0 Error Flag" "0: No such occurrence.,1: At least one bit sent as dominant is received as.." newline rbitfld.long 0x10 28. "CRCERR_FAST,Fast Cyclic Redundancy Check Error Flag" "0: No such occurrence.,1: A CRC error occurred since last read of this.." rbitfld.long 0x10 27. "FRMERR_FAST,Fast Form Error Flag" "0: No such occurrence.,1: A form error occurred since last read of this.." newline rbitfld.long 0x10 26. "STFERR_FAST,Fast Stuffing Error Flag" "0: No such occurrence.,1: A stuffing error occurred since last read of.." eventfld.long 0x10 21. "ERROVR,Error Overrun Flag" "0: No overrun,1: Overrun" newline eventfld.long 0x10 20. "ERRINT_FAST,Fast Error Interrupt Flag" "0: No such occurrence.,1: Error flag set in the data phase of CAN FD.." eventfld.long 0x10 19. "BOFFDONEINT,Bus Off Done Interrupt Flag" "0: No such occurrence,1: FlexCAN module has completed Bus Off process." newline rbitfld.long 0x10 18. "SYNCH,CAN Synchronization Status Flag" "0: Not synchronized,1: Synchronized" eventfld.long 0x10 17. "TWRNINT,TX Warning Interrupt Flag" "0: No such occurrence,1: TX error counter changed from less than 96 to.." newline eventfld.long 0x10 16. "RWRNINT,RX Warning Interrupt Flag" "0: No such occurrence,1: RX error counter changed from less than 96 to.." rbitfld.long 0x10 15. "BIT1ERR,Bit1 Error Flag" "0: No such occurrence.,1: At least one bit sent as recessive is received.." newline rbitfld.long 0x10 14. "BIT0ERR,Bit0 Error Flag" "0: No such occurrence.,1: At least one bit sent as dominant is received as.." rbitfld.long 0x10 13. "ACKERR,Acknowledge Error Flag" "0: No error,1: An ACK error occurred since last read of this.." newline rbitfld.long 0x10 12. "CRCERR,Cyclic Redundancy Check Error Flag" "0: No error,1: A CRC error occurred since last read of this.." rbitfld.long 0x10 11. "FRMERR,Form Error Flag" "0: No error,1: A Form Error occurred since last read of this.." newline rbitfld.long 0x10 10. "STFERR,Stuffing Error Flag" "0: No error,1: Error occurred since last read of this register." rbitfld.long 0x10 9. "TXWRN,TX Error Warning Flag" "0: No such occurrence.,1: TXERRCNT is 96 or greater." newline rbitfld.long 0x10 8. "RXWRN,RX Error Warning Flag" "0: No such occurrence.,1: RXERRCNT is greater than or equal to 96." rbitfld.long 0x10 7. "IDLE,Idle" "0: Not IDLE,1: IDLE" newline rbitfld.long 0x10 6. "TX,FlexCAN In Transmission" "0: Not transmitting,1: Transmitting" rbitfld.long 0x10 4.--5. "FLTCONF,Fault Confinement State" "0: Bus Off,1: Error Passive,2: Bus Off,3: Bus Off" newline rbitfld.long 0x10 3. "RX,FlexCAN in Reception Flag" "0: Not receiving,1: Receiving" eventfld.long 0x10 2. "BOFFINT,Bus Off Interrupt Flag" "0: No such occurrence.,1: FlexCAN module entered Bus Off state." newline eventfld.long 0x10 1. "ERRINT,Error Interrupt Flag" "0: No such occurrence.,1: Indicates setting of any error flag in the Error.." line.long 0x14 "IMASK2,Interrupt Masks 2" hexmask.long 0x14 0.--31. 1. "BUF63TO32M,Buffer MBi Mask" line.long 0x18 "IMASK1,Interrupt Masks 1" hexmask.long 0x18 0.--31. 1. "BUF31TO0M,Buffer MBi Mask" line.long 0x1C "IFLAG2,Interrupt Flags 2" hexmask.long 0x1C 0.--31. 1. "BUF63TO32I,Buffer MBi Interrupt" line.long 0x20 "IFLAG1,Interrupt Flags 1" hexmask.long.tbyte 0x20 8.--31. 1. "BUF31TO8I,Buffer MBi Interrupt" eventfld.long 0x20 7. "BUF7I,Buffer MB7 Interrupt or RX FIFO Overflow" "0: No occurrence of MB7 completing transmission or..,1: MB7 completed transmission or reception or FIFO.." newline eventfld.long 0x20 6. "BUF6I,Buffer MB6 Interrupt or RX FIFO Warning" "0: No occurrence of MB6 completing transmission or..,1: MB6 completed transmission or reception or FIFO.." eventfld.long 0x20 5. "BUF5I,Buffer MB5 Interrupt or Frames available in RX FIFO" "0: No occurrence of completed transmission or..,1: MB5 completed transmission or reception or.." newline hexmask.long.byte 0x20 1.--4. 1. "BUF4TO1I,Buffer MBi Interrupt or Reserved" eventfld.long 0x20 0. "BUF0I,Buffer MB0 Interrupt or Clear FIFO bit" "0: MB0 has no occurrence of successfully completed..,1: MB0 has successfully completed transmission or.." line.long 0x24 "CTRL2,Control 2" bitfld.long 0x24 31. "ERRMSK_FAST,Error Interrupt Mask for Errors Detected in the Data Phase of Fast CAN FD Frames" "0: Disable,1: Enable" bitfld.long 0x24 30. "BOFFDONEMSK,Bus Off Done Interrupt Mask" "0: Disable,1: Enable" newline bitfld.long 0x24 29. "ECRWRE,Error Correction Configuration Register Write Enable" "0: Disable,1: Enable" bitfld.long 0x24 28. "WRMFRZ,Write Access to Memory in Freeze Mode" "0: Disable,1: Enable" newline hexmask.long.byte 0x24 24.--27. 1. "RFFN,Number of Receive FIFO Filters" hexmask.long.byte 0x24 19.--23. 1. "TASD,Transmission Arbitration Start Delay" newline bitfld.long 0x24 18. "MRP,Message Buffers Reception Priority" "0: Matching starts from RX FIFO and continues on..,1: Matching starts from message buffers and.." bitfld.long 0x24 17. "RRS,Remote Request Storing" "0: Generated,1: Stored" newline bitfld.long 0x24 16. "EACEN,Entire Frame Arbitration Field Comparison Enable for RX Message Buffers" "0: Disable,1: Enable" bitfld.long 0x24 15. "TIMER_SRC,Timer Source" "0: CAN bit clock,1: External time tick" newline bitfld.long 0x24 14. "PREXCEN,Protocol Exception Enable" "0: Disabled,1: Enabled" bitfld.long 0x24 13. "BTE,Bit Timing Expansion Enable" "0: Disable,1: Enable" newline bitfld.long 0x24 12. "ISOCANFDEN,ISO CAN FD Enable" "0: Disable. FlexCAN operates using the non-ISO CAN..,1: Enable. FlexCAN operates using the ISO CAN FD.." bitfld.long 0x24 11. "EDFLTDIS,Edge Filter Disable" "0: Enabled,1: Disabled" newline bitfld.long 0x24 8.--9. "MBTSBASE,Message Buffer Timestamp Base" "0: TIMER,1: Lower 16 bits of high-resolution timer,2: Upper 16 bits of high-resolution timer,?" bitfld.long 0x24 6.--7. "TSTAMPCAP,Timestamp Capture Point" "0: Disabled,1: End of the CAN frame,2: Start of the CAN frame,3: Start of frame for classical CAN frames; res bit.." rgroup.long 0x38++0x3 line.long 0x0 "ESR2,Error and Status 2" hexmask.long.byte 0x0 16.--22. 1. "LPTM,Lowest Priority TX Message Buffer" bitfld.long 0x0 14. "VPS,Valid Priority Status" "0: Invalid,1: Valid" newline bitfld.long 0x0 13. "IMB,Inactive Message Buffer" "0: Message buffer indicated by ESR2[LPTM] is not..,1: At least one message buffer is inactive." rgroup.long 0x44++0x3 line.long 0x0 "CRCR,Cyclic Redundancy Check" hexmask.long.byte 0x0 16.--22. 1. "MBCRC,CRC Message Buffer" hexmask.long.word 0x0 0.--14. 1. "TXCRC,Transmitted CRC value" group.long 0x48++0x3 line.long 0x0 "RXFGMASK,RX FIFO Global Mask" hexmask.long 0x0 0.--31. 1. "FGM,RX FIFO Global Mask Bits" rgroup.long 0x4C++0x3 line.long 0x0 "RXFIR,RX FIFO Information" hexmask.long.word 0x0 0.--8. 1. "IDHIT,Identifier Acceptance Filter Hit Indicator" group.long 0x50++0x3 line.long 0x0 "CBT,CAN Bit Timing" bitfld.long 0x0 31. "BTF,Bit Timing Format Enable" "0: Disable,1: Enable" hexmask.long.word 0x0 21.--30. 1. "EPRESDIV,Extended Prescaler Division Factor" newline hexmask.long.byte 0x0 16.--20. 1. "ERJW,Extended Resync Jump Width" hexmask.long.byte 0x0 10.--15. 1. "EPROPSEG,Extended Propagation Segment" newline hexmask.long.byte 0x0 5.--9. 1. "EPSEG1,Extended Phase Segment 1" hexmask.long.byte 0x0 0.--4. 1. "EPSEG2,Extended Phase Segment 2" repeat 64. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x880)++0x3 line.long 0x0 "RXIMR[$1],Receive Individual Mask" hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits" repeat.end group.long 0xAE0++0xF line.long 0x0 "MECR,Memory Error Control" bitfld.long 0x0 31. "ECRWRDIS,Error Configuration Register Write Disable" "0: Enable,1: Disable" bitfld.long 0x0 19. "HANCEI_MSK,Host Access with Non-Correctable Errors Interrupt Mask" "0: Disable,1: Enable" newline bitfld.long 0x0 18. "FANCEI_MSK,FlexCAN Access with Non-Correctable Errors Interrupt Mask" "0: Disable,1: Enable" bitfld.long 0x0 16. "CEI_MSK,Correctable Errors Interrupt Mask" "0: Disable,1: Enable" newline bitfld.long 0x0 15. "HAERRIE,Host Access Error Injection Enable" "0: Disable,1: Enable" bitfld.long 0x0 14. "FAERRIE,FlexCAN Access Error Injection Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 13. "EXTERRIE,Extended Error Injection Enable" "0: Disable. Apply error injection only to the..,1: Enable. Apply error injection to the 64-bit word." bitfld.long 0x0 9. "RERRDIS,Error Report Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 8. "ECCDIS,Error Correction Disable" "0: Enable,1: Disable" bitfld.long 0x0 7. "NCEFAFRZ,Non-Correctable Errors in FlexCAN Access Put Device in Freeze Mode" "0: Keep normal operation.,1: Put FlexCAN in Freeze mode (see section 'Freeze.." line.long 0x4 "ERRIAR,Error Injection Address" hexmask.long.word 0x4 2.--13. 1. "INJADDR_H,Error Injection Address High" rbitfld.long 0x4 0.--1. "INJADDR_L,Error Injection Address Low" "0,1,2,3" line.long 0x8 "ERRIDPR,Error Injection Data Pattern" hexmask.long 0x8 0.--31. 1. "DFLIP,Data Flip Pattern" line.long 0xC "ERRIPPR,Error Injection Parity Pattern" hexmask.long.byte 0xC 24.--28. 1. "PFLIP3,Parity Flip Pattern for Byte 3 (Most Significant)" hexmask.long.byte 0xC 16.--20. 1. "PFLIP2,Parity Flip Pattern for Byte 2" newline hexmask.long.byte 0xC 8.--12. 1. "PFLIP1,Parity Flip Pattern for Byte 1" hexmask.long.byte 0xC 0.--4. 1. "PFLIP0,Parity Flip Pattern for Byte 0 (Least Significant)" rgroup.long 0xAF0++0xB line.long 0x0 "RERRAR,Error Report Address" bitfld.long 0x0 24. "NCE,Non-Correctable Error" "0: Reporting a correctable error,1: Reporting a non-correctable error" bitfld.long 0x0 16.--18. "SAID,SAID" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--13. 1. "ERRADDR,Address Where Error Detected" line.long 0x4 "RERRDR,Error Report Data" hexmask.long 0x4 0.--31. 1. "RDATA,Raw Data Word Read from Memory with Error" line.long 0x8 "RERRSYNR,Error Report Syndrome" bitfld.long 0x8 31. "BE3,Byte Enabled for Byte 3 (Most Significant)" "0: Byte was not read.,1: Byte was read." hexmask.long.byte 0x8 24.--28. 1. "SYND3,Error Syndrome for Byte 3 (Most Significant)" newline bitfld.long 0x8 23. "BE2,Byte Enabled for Byte 2" "0: Byte was not read.,1: Byte was read." hexmask.long.byte 0x8 16.--20. 1. "SYND2,Error Syndrome for Byte 2" newline bitfld.long 0x8 15. "BE1,Byte Enabled for Byte 1" "0: Byte was not read.,1: Byte was read." hexmask.long.byte 0x8 8.--12. 1. "SYND1,Error Syndrome for Byte 1" newline bitfld.long 0x8 7. "BE0,Byte Enabled for Byte 0 (Least Significant)" "0: Byte was not read.,1: Byte was read." hexmask.long.byte 0x8 0.--4. 1. "SYND0,Error Syndrome for Byte 0 (Least Significant)" group.long 0xAFC++0x3 line.long 0x0 "ERRSR,Error Status" eventfld.long 0x0 19. "HANCEIF,Host Access with Noncorrectable Error Interrupt Flag" "0: No errors detected,1: Error detected" eventfld.long 0x0 18. "FANCEIF,FlexCAN Access with Non-Correctable Error Interrupt Flag" "0: No errors detected,1: Error detected" newline eventfld.long 0x0 16. "CEIF,Correctable Error Interrupt Flag" "0: No errors detected,1: Error detected" eventfld.long 0x0 3. "HANCEIOF,Host Access With Non-Correctable Error Interrupt Overrun Flag" "0: No errors detected,1: Error detected" newline eventfld.long 0x0 2. "FANCEIOF,FlexCAN Access with Non-Correctable Error Interrupt Overrun Flag" "0: No errors detected,1: Error detected" eventfld.long 0x0 0. "CEIOF,Correctable Error Interrupt Overrun Flag" "0: No errors detected,1: Error detected" group.long 0xBF0++0x17 line.long 0x0 "EPRS,Enhanced CAN Bit Timing Prescalers" hexmask.long.word 0x0 16.--25. 1. "EDPRESDIV,Extended Data Phase Prescaler Division Factor" hexmask.long.word 0x0 0.--9. 1. "ENPRESDIV,Extended Nominal Prescaler Division Factor" line.long 0x4 "ENCBT,Enhanced Nominal CAN Bit Timing" hexmask.long.byte 0x4 22.--28. 1. "NRJW,Nominal Resynchronization Jump Width" hexmask.long.byte 0x4 12.--18. 1. "NTSEG2,Nominal Time Segment 2" newline hexmask.long.byte 0x4 0.--7. 1. "NTSEG1,Nominal Time Segment 1" line.long 0x8 "EDCBT,Enhanced Data Phase CAN Bit Timing" hexmask.long.byte 0x8 22.--25. 1. "DRJW,Data Phase Resynchronization Jump Width" hexmask.long.byte 0x8 12.--15. 1. "DTSEG2,Data Phase Time Segment 2" newline hexmask.long.byte 0x8 0.--4. 1. "DTSEG1,Data Phase Segment 1" line.long 0xC "ETDC,Enhanced Transceiver Delay Compensation" bitfld.long 0xC 31. "ETDCEN,Transceiver Delay Compensation Enable" "0: Disable,1: Enable" bitfld.long 0xC 30. "TDMDIS,Transceiver Delay Measurement Disable" "0: Enable,1: Disable" newline hexmask.long.byte 0xC 16.--22. 1. "ETDCOFF,Enhanced Transceiver Delay Compensation Offset" eventfld.long 0xC 15. "ETDCFAIL,Transceiver Delay Compensation Fail" "0: In range,1: Out of range" newline hexmask.long.byte 0xC 0.--7. 1. "ETDCVAL,Enhanced Transceiver Delay Compensation Value" line.long 0x10 "FDCTRL,CAN FD Control" bitfld.long 0x10 31. "FDRATE,Bit Rate Switch Enable" "0: Disable,1: Enable" bitfld.long 0x10 19.--20. "MBDSR1,Message Buffer Data Size for Region 1" "0: 8 bytes,1: 16 bytes,2: 32 bytes,3: 64 bytes" newline bitfld.long 0x10 16.--17. "MBDSR0,Message Buffer Data Size for Region 0" "0: 8 bytes,1: 16 bytes,2: 32 bytes,3: 64 bytes" bitfld.long 0x10 15. "TDCEN,Transceiver Delay Compensation Enable" "0: Disable,1: Enable" newline eventfld.long 0x10 14. "TDCFAIL,Transceiver Delay Compensation Fail" "0: In range,1: Out of range" hexmask.long.byte 0x10 8.--12. 1. "TDCOFF,Transceiver Delay Compensation Offset" newline hexmask.long.byte 0x10 0.--5. 1. "TDCVAL,Transceiver Delay Compensation Value" line.long 0x14 "FDCBT,CAN FD Bit Timing" hexmask.long.word 0x14 20.--29. 1. "FPRESDIV,Fast Prescaler Division Factor" bitfld.long 0x14 16.--18. "FRJW,Fast Resync Jump Width" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 10.--14. 1. "FPROPSEG,Fast Propagation Segment" bitfld.long 0x14 5.--7. "FPSEG1,Fast Phase Segment 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 0.--2. "FPSEG2,Fast Phase Segment 2" "0,1,2,3,4,5,6,7" rgroup.long 0xC08++0x3 line.long 0x0 "FDCRC,CAN FD CRC" hexmask.long.byte 0x0 24.--30. 1. "FD_MBCRC,CRC Message Buffer Number for FD_TXCRC" hexmask.long.tbyte 0x0 0.--20. 1. "FD_TXCRC,Extended Transmitted CRC value" repeat 64. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xC30)++0x3 line.long 0x0 "HR_TIME_STAMP[$1],High-Resolution Timestamp" hexmask.long 0x0 0.--31. 1. "TS,High-Resolution Timestamp" repeat.end tree.end tree "CAN_4" base ad:0x40314000 group.long 0x0++0xB line.long 0x0 "MCR,Module Configuration" bitfld.long 0x0 31. "MDIS,Module Disable" "0: Enable,1: Disable" bitfld.long 0x0 30. "FRZ,Freeze Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 29. "RFEN,RX FIFO Enable" "0: Disable,1: Enable" bitfld.long 0x0 28. "HALT,Halt FlexCAN" "0: No request,1: Enter Freeze mode if MCR[FRZ] = 1." newline rbitfld.long 0x0 27. "NOTRDY,FlexCAN Not Ready" "0: FlexCAN is in Normal mode Listen-Only mode or..,1: FlexCAN is in Disable mode or Freeze mode." bitfld.long 0x0 25. "SOFTRST,Soft Reset" "0: No reset,1: Soft reset affects reset registers" newline rbitfld.long 0x0 24. "FRZACK,Freeze Mode Acknowledge" "0: Not in Freeze mode prescaler running.,1: In Freeze mode prescaler stopped." bitfld.long 0x0 23. "SUPV,Supervisor Mode" "0: User mode,1: Supervisor mode" newline bitfld.long 0x0 21. "WRNEN,Warning Interrupt Enable" "0: Disable,1: Enable" rbitfld.long 0x0 20. "LPMACK,Low-Power Mode Acknowledge" "0: Not in a low-power mode,1: In a low-power mode" newline bitfld.long 0x0 17. "SRXDIS,Self-Reception Disable" "0: Enable,1: Disable" bitfld.long 0x0 16. "IRMQ,Individual RX Masking and Queue Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 15. "DMA,DMA Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "LPRIOEN,Local Priority Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 12. "AEN,Abort Enable" "0: Disabled,1: Enabled" bitfld.long 0x0 11. "FDEN,CAN FD Operation Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 8.--9. "IDAM,ID Acceptance Mode" "0: Format A: One full ID (standard and extended)..,1: Format B: Two full standard IDs or two partial..,2: Format C: Four partial 8-bit standard IDs per ID..,3: Format D: All frames rejected." hexmask.long.byte 0x0 0.--6. 1. "MAXMB,Number of the Last Message Buffer" line.long 0x4 "CTRL1,Control 1" hexmask.long.byte 0x4 24.--31. 1. "PRESDIV,Prescaler Division Factor" bitfld.long 0x4 22.--23. "RJW,Resync Jump Width" "0,1,2,3" newline bitfld.long 0x4 19.--21. "PSEG1,Phase Segment 1" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "PSEG2,Phase Segment 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 15. "BOFFMSK,Bus Off Interrupt Mask" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 14. "ERRMSK,Error Interrupt Mask" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 12. "LPB,Loopback Mode" "0: Disabled,1: Enabled" bitfld.long 0x4 11. "TWRNMSK,TX Warning Interrupt Mask" "0: Disabled,1: Enabled" newline bitfld.long 0x4 10. "RWRNMSK,RX Warning Interrupt Mask" "0: Disabled,1: Enabled" bitfld.long 0x4 7. "SMP,CAN Bit Sampling" "0: One sample is used to determine the bit value.,1: Three samples are used to determine the value of.." newline bitfld.long 0x4 6. "BOFFREC,Bus Off Recovery" "0: Enabled,1: Disabled" bitfld.long 0x4 5. "TSYN,Timer Sync" "0: Disable,1: Enable" newline bitfld.long 0x4 4. "LBUF,Lowest Buffer Transmitted First" "0: Buffer with highest priority is transmitted first.,1: Lowest number buffer is transmitted first." bitfld.long 0x4 3. "LOM,Listen-Only Mode" "0: Listen-Only mode is deactivated.,1: FlexCAN module operates in Listen-Only mode." newline bitfld.long 0x4 0.--2. "PROPSEG,Propagation Segment" "0,1,2,3,4,5,6,7" line.long 0x8 "TIMER,Free-Running Timer" hexmask.long.word 0x8 0.--15. 1. "TIMER,Timer Value" group.long 0x10++0x27 line.long 0x0 "RXMGMASK,RX Message Buffers Global Mask" hexmask.long 0x0 0.--31. 1. "MG,Global Mask for RX Message Buffers" line.long 0x4 "RX14MASK,Receive 14 Mask" hexmask.long 0x4 0.--31. 1. "RX14M,RX Buffer 14 Mask Bits" line.long 0x8 "RX15MASK,Receive 15 Mask" hexmask.long 0x8 0.--31. 1. "RX15M,RX Buffer 15 Mask Bits" line.long 0xC "ECR,Error Counter" hexmask.long.byte 0xC 24.--31. 1. "RXERRCNT_FAST,Receive Error Counter for Fast Bits" hexmask.long.byte 0xC 16.--23. 1. "TXERRCNT_FAST,Transmit Error Counter for Fast Bits" newline hexmask.long.byte 0xC 8.--15. 1. "RXERRCNT,Receive Error Counter" hexmask.long.byte 0xC 0.--7. 1. "TXERRCNT,Transmit Error Counter" line.long 0x10 "ESR1,Error and Status 1" rbitfld.long 0x10 31. "BIT1ERR_FAST,Fast Bit1 Error Flag" "0: No such occurrence.,1: At least one bit sent as recessive is received.." rbitfld.long 0x10 30. "BIT0ERR_FAST,Fast Bit0 Error Flag" "0: No such occurrence.,1: At least one bit sent as dominant is received as.." newline rbitfld.long 0x10 28. "CRCERR_FAST,Fast Cyclic Redundancy Check Error Flag" "0: No such occurrence.,1: A CRC error occurred since last read of this.." rbitfld.long 0x10 27. "FRMERR_FAST,Fast Form Error Flag" "0: No such occurrence.,1: A form error occurred since last read of this.." newline rbitfld.long 0x10 26. "STFERR_FAST,Fast Stuffing Error Flag" "0: No such occurrence.,1: A stuffing error occurred since last read of.." eventfld.long 0x10 21. "ERROVR,Error Overrun Flag" "0: No overrun,1: Overrun" newline eventfld.long 0x10 20. "ERRINT_FAST,Fast Error Interrupt Flag" "0: No such occurrence.,1: Error flag set in the data phase of CAN FD.." eventfld.long 0x10 19. "BOFFDONEINT,Bus Off Done Interrupt Flag" "0: No such occurrence,1: FlexCAN module has completed Bus Off process." newline rbitfld.long 0x10 18. "SYNCH,CAN Synchronization Status Flag" "0: Not synchronized,1: Synchronized" eventfld.long 0x10 17. "TWRNINT,TX Warning Interrupt Flag" "0: No such occurrence,1: TX error counter changed from less than 96 to.." newline eventfld.long 0x10 16. "RWRNINT,RX Warning Interrupt Flag" "0: No such occurrence,1: RX error counter changed from less than 96 to.." rbitfld.long 0x10 15. "BIT1ERR,Bit1 Error Flag" "0: No such occurrence.,1: At least one bit sent as recessive is received.." newline rbitfld.long 0x10 14. "BIT0ERR,Bit0 Error Flag" "0: No such occurrence.,1: At least one bit sent as dominant is received as.." rbitfld.long 0x10 13. "ACKERR,Acknowledge Error Flag" "0: No error,1: An ACK error occurred since last read of this.." newline rbitfld.long 0x10 12. "CRCERR,Cyclic Redundancy Check Error Flag" "0: No error,1: A CRC error occurred since last read of this.." rbitfld.long 0x10 11. "FRMERR,Form Error Flag" "0: No error,1: A Form Error occurred since last read of this.." newline rbitfld.long 0x10 10. "STFERR,Stuffing Error Flag" "0: No error,1: Error occurred since last read of this register." rbitfld.long 0x10 9. "TXWRN,TX Error Warning Flag" "0: No such occurrence.,1: TXERRCNT is 96 or greater." newline rbitfld.long 0x10 8. "RXWRN,RX Error Warning Flag" "0: No such occurrence.,1: RXERRCNT is greater than or equal to 96." rbitfld.long 0x10 7. "IDLE,Idle" "0: Not IDLE,1: IDLE" newline rbitfld.long 0x10 6. "TX,FlexCAN In Transmission" "0: Not transmitting,1: Transmitting" rbitfld.long 0x10 4.--5. "FLTCONF,Fault Confinement State" "0: Bus Off,1: Error Passive,2: Bus Off,3: Bus Off" newline rbitfld.long 0x10 3. "RX,FlexCAN in Reception Flag" "0: Not receiving,1: Receiving" eventfld.long 0x10 2. "BOFFINT,Bus Off Interrupt Flag" "0: No such occurrence.,1: FlexCAN module entered Bus Off state." newline eventfld.long 0x10 1. "ERRINT,Error Interrupt Flag" "0: No such occurrence.,1: Indicates setting of any error flag in the Error.." line.long 0x14 "IMASK2,Interrupt Masks 2" hexmask.long 0x14 0.--31. 1. "BUF63TO32M,Buffer MBi Mask" line.long 0x18 "IMASK1,Interrupt Masks 1" hexmask.long 0x18 0.--31. 1. "BUF31TO0M,Buffer MBi Mask" line.long 0x1C "IFLAG2,Interrupt Flags 2" hexmask.long 0x1C 0.--31. 1. "BUF63TO32I,Buffer MBi Interrupt" line.long 0x20 "IFLAG1,Interrupt Flags 1" hexmask.long.tbyte 0x20 8.--31. 1. "BUF31TO8I,Buffer MBi Interrupt" eventfld.long 0x20 7. "BUF7I,Buffer MB7 Interrupt or RX FIFO Overflow" "0: No occurrence of MB7 completing transmission or..,1: MB7 completed transmission or reception or FIFO.." newline eventfld.long 0x20 6. "BUF6I,Buffer MB6 Interrupt or RX FIFO Warning" "0: No occurrence of MB6 completing transmission or..,1: MB6 completed transmission or reception or FIFO.." eventfld.long 0x20 5. "BUF5I,Buffer MB5 Interrupt or Frames available in RX FIFO" "0: No occurrence of completed transmission or..,1: MB5 completed transmission or reception or.." newline hexmask.long.byte 0x20 1.--4. 1. "BUF4TO1I,Buffer MBi Interrupt or Reserved" eventfld.long 0x20 0. "BUF0I,Buffer MB0 Interrupt or Clear FIFO bit" "0: MB0 has no occurrence of successfully completed..,1: MB0 has successfully completed transmission or.." line.long 0x24 "CTRL2,Control 2" bitfld.long 0x24 31. "ERRMSK_FAST,Error Interrupt Mask for Errors Detected in the Data Phase of Fast CAN FD Frames" "0: Disable,1: Enable" bitfld.long 0x24 30. "BOFFDONEMSK,Bus Off Done Interrupt Mask" "0: Disable,1: Enable" newline bitfld.long 0x24 29. "ECRWRE,Error Correction Configuration Register Write Enable" "0: Disable,1: Enable" bitfld.long 0x24 28. "WRMFRZ,Write Access to Memory in Freeze Mode" "0: Disable,1: Enable" newline hexmask.long.byte 0x24 24.--27. 1. "RFFN,Number of Receive FIFO Filters" hexmask.long.byte 0x24 19.--23. 1. "TASD,Transmission Arbitration Start Delay" newline bitfld.long 0x24 18. "MRP,Message Buffers Reception Priority" "0: Matching starts from RX FIFO and continues on..,1: Matching starts from message buffers and.." bitfld.long 0x24 17. "RRS,Remote Request Storing" "0: Generated,1: Stored" newline bitfld.long 0x24 16. "EACEN,Entire Frame Arbitration Field Comparison Enable for RX Message Buffers" "0: Disable,1: Enable" bitfld.long 0x24 15. "TIMER_SRC,Timer Source" "0: CAN bit clock,1: External time tick" newline bitfld.long 0x24 14. "PREXCEN,Protocol Exception Enable" "0: Disabled,1: Enabled" bitfld.long 0x24 13. "BTE,Bit Timing Expansion Enable" "0: Disable,1: Enable" newline bitfld.long 0x24 12. "ISOCANFDEN,ISO CAN FD Enable" "0: Disable. FlexCAN operates using the non-ISO CAN..,1: Enable. FlexCAN operates using the ISO CAN FD.." bitfld.long 0x24 11. "EDFLTDIS,Edge Filter Disable" "0: Enabled,1: Disabled" newline bitfld.long 0x24 8.--9. "MBTSBASE,Message Buffer Timestamp Base" "0: TIMER,1: Lower 16 bits of high-resolution timer,2: Upper 16 bits of high-resolution timer,?" bitfld.long 0x24 6.--7. "TSTAMPCAP,Timestamp Capture Point" "0: Disabled,1: End of the CAN frame,2: Start of the CAN frame,3: Start of frame for classical CAN frames; res bit.." rgroup.long 0x38++0x3 line.long 0x0 "ESR2,Error and Status 2" hexmask.long.byte 0x0 16.--22. 1. "LPTM,Lowest Priority TX Message Buffer" bitfld.long 0x0 14. "VPS,Valid Priority Status" "0: Invalid,1: Valid" newline bitfld.long 0x0 13. "IMB,Inactive Message Buffer" "0: Message buffer indicated by ESR2[LPTM] is not..,1: At least one message buffer is inactive." rgroup.long 0x44++0x3 line.long 0x0 "CRCR,Cyclic Redundancy Check" hexmask.long.byte 0x0 16.--22. 1. "MBCRC,CRC Message Buffer" hexmask.long.word 0x0 0.--14. 1. "TXCRC,Transmitted CRC value" group.long 0x48++0x3 line.long 0x0 "RXFGMASK,RX FIFO Global Mask" hexmask.long 0x0 0.--31. 1. "FGM,RX FIFO Global Mask Bits" rgroup.long 0x4C++0x3 line.long 0x0 "RXFIR,RX FIFO Information" hexmask.long.word 0x0 0.--8. 1. "IDHIT,Identifier Acceptance Filter Hit Indicator" group.long 0x50++0x3 line.long 0x0 "CBT,CAN Bit Timing" bitfld.long 0x0 31. "BTF,Bit Timing Format Enable" "0: Disable,1: Enable" hexmask.long.word 0x0 21.--30. 1. "EPRESDIV,Extended Prescaler Division Factor" newline hexmask.long.byte 0x0 16.--20. 1. "ERJW,Extended Resync Jump Width" hexmask.long.byte 0x0 10.--15. 1. "EPROPSEG,Extended Propagation Segment" newline hexmask.long.byte 0x0 5.--9. 1. "EPSEG1,Extended Phase Segment 1" hexmask.long.byte 0x0 0.--4. 1. "EPSEG2,Extended Phase Segment 2" repeat 64. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x880)++0x3 line.long 0x0 "RXIMR[$1],Receive Individual Mask" hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits" repeat.end group.long 0xAE0++0xF line.long 0x0 "MECR,Memory Error Control" bitfld.long 0x0 31. "ECRWRDIS,Error Configuration Register Write Disable" "0: Enable,1: Disable" bitfld.long 0x0 19. "HANCEI_MSK,Host Access with Non-Correctable Errors Interrupt Mask" "0: Disable,1: Enable" newline bitfld.long 0x0 18. "FANCEI_MSK,FlexCAN Access with Non-Correctable Errors Interrupt Mask" "0: Disable,1: Enable" bitfld.long 0x0 16. "CEI_MSK,Correctable Errors Interrupt Mask" "0: Disable,1: Enable" newline bitfld.long 0x0 15. "HAERRIE,Host Access Error Injection Enable" "0: Disable,1: Enable" bitfld.long 0x0 14. "FAERRIE,FlexCAN Access Error Injection Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 13. "EXTERRIE,Extended Error Injection Enable" "0: Disable. Apply error injection only to the..,1: Enable. Apply error injection to the 64-bit word." bitfld.long 0x0 9. "RERRDIS,Error Report Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 8. "ECCDIS,Error Correction Disable" "0: Enable,1: Disable" bitfld.long 0x0 7. "NCEFAFRZ,Non-Correctable Errors in FlexCAN Access Put Device in Freeze Mode" "0: Keep normal operation.,1: Put FlexCAN in Freeze mode (see section 'Freeze.." line.long 0x4 "ERRIAR,Error Injection Address" hexmask.long.word 0x4 2.--13. 1. "INJADDR_H,Error Injection Address High" rbitfld.long 0x4 0.--1. "INJADDR_L,Error Injection Address Low" "0,1,2,3" line.long 0x8 "ERRIDPR,Error Injection Data Pattern" hexmask.long 0x8 0.--31. 1. "DFLIP,Data Flip Pattern" line.long 0xC "ERRIPPR,Error Injection Parity Pattern" hexmask.long.byte 0xC 24.--28. 1. "PFLIP3,Parity Flip Pattern for Byte 3 (Most Significant)" hexmask.long.byte 0xC 16.--20. 1. "PFLIP2,Parity Flip Pattern for Byte 2" newline hexmask.long.byte 0xC 8.--12. 1. "PFLIP1,Parity Flip Pattern for Byte 1" hexmask.long.byte 0xC 0.--4. 1. "PFLIP0,Parity Flip Pattern for Byte 0 (Least Significant)" rgroup.long 0xAF0++0xB line.long 0x0 "RERRAR,Error Report Address" bitfld.long 0x0 24. "NCE,Non-Correctable Error" "0: Reporting a correctable error,1: Reporting a non-correctable error" bitfld.long 0x0 16.--18. "SAID,SAID" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--13. 1. "ERRADDR,Address Where Error Detected" line.long 0x4 "RERRDR,Error Report Data" hexmask.long 0x4 0.--31. 1. "RDATA,Raw Data Word Read from Memory with Error" line.long 0x8 "RERRSYNR,Error Report Syndrome" bitfld.long 0x8 31. "BE3,Byte Enabled for Byte 3 (Most Significant)" "0: Byte was not read.,1: Byte was read." hexmask.long.byte 0x8 24.--28. 1. "SYND3,Error Syndrome for Byte 3 (Most Significant)" newline bitfld.long 0x8 23. "BE2,Byte Enabled for Byte 2" "0: Byte was not read.,1: Byte was read." hexmask.long.byte 0x8 16.--20. 1. "SYND2,Error Syndrome for Byte 2" newline bitfld.long 0x8 15. "BE1,Byte Enabled for Byte 1" "0: Byte was not read.,1: Byte was read." hexmask.long.byte 0x8 8.--12. 1. "SYND1,Error Syndrome for Byte 1" newline bitfld.long 0x8 7. "BE0,Byte Enabled for Byte 0 (Least Significant)" "0: Byte was not read.,1: Byte was read." hexmask.long.byte 0x8 0.--4. 1. "SYND0,Error Syndrome for Byte 0 (Least Significant)" group.long 0xAFC++0x3 line.long 0x0 "ERRSR,Error Status" eventfld.long 0x0 19. "HANCEIF,Host Access with Noncorrectable Error Interrupt Flag" "0: No errors detected,1: Error detected" eventfld.long 0x0 18. "FANCEIF,FlexCAN Access with Non-Correctable Error Interrupt Flag" "0: No errors detected,1: Error detected" newline eventfld.long 0x0 16. "CEIF,Correctable Error Interrupt Flag" "0: No errors detected,1: Error detected" eventfld.long 0x0 3. "HANCEIOF,Host Access With Non-Correctable Error Interrupt Overrun Flag" "0: No errors detected,1: Error detected" newline eventfld.long 0x0 2. "FANCEIOF,FlexCAN Access with Non-Correctable Error Interrupt Overrun Flag" "0: No errors detected,1: Error detected" eventfld.long 0x0 0. "CEIOF,Correctable Error Interrupt Overrun Flag" "0: No errors detected,1: Error detected" group.long 0xBF0++0x17 line.long 0x0 "EPRS,Enhanced CAN Bit Timing Prescalers" hexmask.long.word 0x0 16.--25. 1. "EDPRESDIV,Extended Data Phase Prescaler Division Factor" hexmask.long.word 0x0 0.--9. 1. "ENPRESDIV,Extended Nominal Prescaler Division Factor" line.long 0x4 "ENCBT,Enhanced Nominal CAN Bit Timing" hexmask.long.byte 0x4 22.--28. 1. "NRJW,Nominal Resynchronization Jump Width" hexmask.long.byte 0x4 12.--18. 1. "NTSEG2,Nominal Time Segment 2" newline hexmask.long.byte 0x4 0.--7. 1. "NTSEG1,Nominal Time Segment 1" line.long 0x8 "EDCBT,Enhanced Data Phase CAN Bit Timing" hexmask.long.byte 0x8 22.--25. 1. "DRJW,Data Phase Resynchronization Jump Width" hexmask.long.byte 0x8 12.--15. 1. "DTSEG2,Data Phase Time Segment 2" newline hexmask.long.byte 0x8 0.--4. 1. "DTSEG1,Data Phase Segment 1" line.long 0xC "ETDC,Enhanced Transceiver Delay Compensation" bitfld.long 0xC 31. "ETDCEN,Transceiver Delay Compensation Enable" "0: Disable,1: Enable" bitfld.long 0xC 30. "TDMDIS,Transceiver Delay Measurement Disable" "0: Enable,1: Disable" newline hexmask.long.byte 0xC 16.--22. 1. "ETDCOFF,Enhanced Transceiver Delay Compensation Offset" eventfld.long 0xC 15. "ETDCFAIL,Transceiver Delay Compensation Fail" "0: In range,1: Out of range" newline hexmask.long.byte 0xC 0.--7. 1. "ETDCVAL,Enhanced Transceiver Delay Compensation Value" line.long 0x10 "FDCTRL,CAN FD Control" bitfld.long 0x10 31. "FDRATE,Bit Rate Switch Enable" "0: Disable,1: Enable" bitfld.long 0x10 19.--20. "MBDSR1,Message Buffer Data Size for Region 1" "0: 8 bytes,1: 16 bytes,2: 32 bytes,3: 64 bytes" newline bitfld.long 0x10 16.--17. "MBDSR0,Message Buffer Data Size for Region 0" "0: 8 bytes,1: 16 bytes,2: 32 bytes,3: 64 bytes" bitfld.long 0x10 15. "TDCEN,Transceiver Delay Compensation Enable" "0: Disable,1: Enable" newline eventfld.long 0x10 14. "TDCFAIL,Transceiver Delay Compensation Fail" "0: In range,1: Out of range" hexmask.long.byte 0x10 8.--12. 1. "TDCOFF,Transceiver Delay Compensation Offset" newline hexmask.long.byte 0x10 0.--5. 1. "TDCVAL,Transceiver Delay Compensation Value" line.long 0x14 "FDCBT,CAN FD Bit Timing" hexmask.long.word 0x14 20.--29. 1. "FPRESDIV,Fast Prescaler Division Factor" bitfld.long 0x14 16.--18. "FRJW,Fast Resync Jump Width" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 10.--14. 1. "FPROPSEG,Fast Propagation Segment" bitfld.long 0x14 5.--7. "FPSEG1,Fast Phase Segment 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 0.--2. "FPSEG2,Fast Phase Segment 2" "0,1,2,3,4,5,6,7" rgroup.long 0xC08++0x3 line.long 0x0 "FDCRC,CAN FD CRC" hexmask.long.byte 0x0 24.--30. 1. "FD_MBCRC,CRC Message Buffer Number for FD_TXCRC" hexmask.long.tbyte 0x0 0.--20. 1. "FD_TXCRC,Extended Transmitted CRC value" repeat 64. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xC30)++0x3 line.long 0x0 "HR_TIME_STAMP[$1],High-Resolution Timestamp" hexmask.long 0x0 0.--31. 1. "TS,High-Resolution Timestamp" repeat.end tree.end tree "CAN_5" base ad:0x40318000 group.long 0x0++0xB line.long 0x0 "MCR,Module Configuration" bitfld.long 0x0 31. "MDIS,Module Disable" "0: Enable,1: Disable" bitfld.long 0x0 30. "FRZ,Freeze Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 29. "RFEN,RX FIFO Enable" "0: Disable,1: Enable" bitfld.long 0x0 28. "HALT,Halt FlexCAN" "0: No request,1: Enter Freeze mode if MCR[FRZ] = 1." newline rbitfld.long 0x0 27. "NOTRDY,FlexCAN Not Ready" "0: FlexCAN is in Normal mode Listen-Only mode or..,1: FlexCAN is in Disable mode or Freeze mode." bitfld.long 0x0 25. "SOFTRST,Soft Reset" "0: No reset,1: Soft reset affects reset registers" newline rbitfld.long 0x0 24. "FRZACK,Freeze Mode Acknowledge" "0: Not in Freeze mode prescaler running.,1: In Freeze mode prescaler stopped." bitfld.long 0x0 23. "SUPV,Supervisor Mode" "0: User mode,1: Supervisor mode" newline bitfld.long 0x0 21. "WRNEN,Warning Interrupt Enable" "0: Disable,1: Enable" rbitfld.long 0x0 20. "LPMACK,Low-Power Mode Acknowledge" "0: Not in a low-power mode,1: In a low-power mode" newline bitfld.long 0x0 17. "SRXDIS,Self-Reception Disable" "0: Enable,1: Disable" bitfld.long 0x0 16. "IRMQ,Individual RX Masking and Queue Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 15. "DMA,DMA Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "LPRIOEN,Local Priority Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 12. "AEN,Abort Enable" "0: Disabled,1: Enabled" bitfld.long 0x0 11. "FDEN,CAN FD Operation Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 8.--9. "IDAM,ID Acceptance Mode" "0: Format A: One full ID (standard and extended)..,1: Format B: Two full standard IDs or two partial..,2: Format C: Four partial 8-bit standard IDs per ID..,3: Format D: All frames rejected." hexmask.long.byte 0x0 0.--6. 1. "MAXMB,Number of the Last Message Buffer" line.long 0x4 "CTRL1,Control 1" hexmask.long.byte 0x4 24.--31. 1. "PRESDIV,Prescaler Division Factor" bitfld.long 0x4 22.--23. "RJW,Resync Jump Width" "0,1,2,3" newline bitfld.long 0x4 19.--21. "PSEG1,Phase Segment 1" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "PSEG2,Phase Segment 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 15. "BOFFMSK,Bus Off Interrupt Mask" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 14. "ERRMSK,Error Interrupt Mask" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 12. "LPB,Loopback Mode" "0: Disabled,1: Enabled" bitfld.long 0x4 11. "TWRNMSK,TX Warning Interrupt Mask" "0: Disabled,1: Enabled" newline bitfld.long 0x4 10. "RWRNMSK,RX Warning Interrupt Mask" "0: Disabled,1: Enabled" bitfld.long 0x4 7. "SMP,CAN Bit Sampling" "0: One sample is used to determine the bit value.,1: Three samples are used to determine the value of.." newline bitfld.long 0x4 6. "BOFFREC,Bus Off Recovery" "0: Enabled,1: Disabled" bitfld.long 0x4 5. "TSYN,Timer Sync" "0: Disable,1: Enable" newline bitfld.long 0x4 4. "LBUF,Lowest Buffer Transmitted First" "0: Buffer with highest priority is transmitted first.,1: Lowest number buffer is transmitted first." bitfld.long 0x4 3. "LOM,Listen-Only Mode" "0: Listen-Only mode is deactivated.,1: FlexCAN module operates in Listen-Only mode." newline bitfld.long 0x4 0.--2. "PROPSEG,Propagation Segment" "0,1,2,3,4,5,6,7" line.long 0x8 "TIMER,Free-Running Timer" hexmask.long.word 0x8 0.--15. 1. "TIMER,Timer Value" group.long 0x10++0x27 line.long 0x0 "RXMGMASK,RX Message Buffers Global Mask" hexmask.long 0x0 0.--31. 1. "MG,Global Mask for RX Message Buffers" line.long 0x4 "RX14MASK,Receive 14 Mask" hexmask.long 0x4 0.--31. 1. "RX14M,RX Buffer 14 Mask Bits" line.long 0x8 "RX15MASK,Receive 15 Mask" hexmask.long 0x8 0.--31. 1. "RX15M,RX Buffer 15 Mask Bits" line.long 0xC "ECR,Error Counter" hexmask.long.byte 0xC 24.--31. 1. "RXERRCNT_FAST,Receive Error Counter for Fast Bits" hexmask.long.byte 0xC 16.--23. 1. "TXERRCNT_FAST,Transmit Error Counter for Fast Bits" newline hexmask.long.byte 0xC 8.--15. 1. "RXERRCNT,Receive Error Counter" hexmask.long.byte 0xC 0.--7. 1. "TXERRCNT,Transmit Error Counter" line.long 0x10 "ESR1,Error and Status 1" rbitfld.long 0x10 31. "BIT1ERR_FAST,Fast Bit1 Error Flag" "0: No such occurrence.,1: At least one bit sent as recessive is received.." rbitfld.long 0x10 30. "BIT0ERR_FAST,Fast Bit0 Error Flag" "0: No such occurrence.,1: At least one bit sent as dominant is received as.." newline rbitfld.long 0x10 28. "CRCERR_FAST,Fast Cyclic Redundancy Check Error Flag" "0: No such occurrence.,1: A CRC error occurred since last read of this.." rbitfld.long 0x10 27. "FRMERR_FAST,Fast Form Error Flag" "0: No such occurrence.,1: A form error occurred since last read of this.." newline rbitfld.long 0x10 26. "STFERR_FAST,Fast Stuffing Error Flag" "0: No such occurrence.,1: A stuffing error occurred since last read of.." eventfld.long 0x10 21. "ERROVR,Error Overrun Flag" "0: No overrun,1: Overrun" newline eventfld.long 0x10 20. "ERRINT_FAST,Fast Error Interrupt Flag" "0: No such occurrence.,1: Error flag set in the data phase of CAN FD.." eventfld.long 0x10 19. "BOFFDONEINT,Bus Off Done Interrupt Flag" "0: No such occurrence,1: FlexCAN module has completed Bus Off process." newline rbitfld.long 0x10 18. "SYNCH,CAN Synchronization Status Flag" "0: Not synchronized,1: Synchronized" eventfld.long 0x10 17. "TWRNINT,TX Warning Interrupt Flag" "0: No such occurrence,1: TX error counter changed from less than 96 to.." newline eventfld.long 0x10 16. "RWRNINT,RX Warning Interrupt Flag" "0: No such occurrence,1: RX error counter changed from less than 96 to.." rbitfld.long 0x10 15. "BIT1ERR,Bit1 Error Flag" "0: No such occurrence.,1: At least one bit sent as recessive is received.." newline rbitfld.long 0x10 14. "BIT0ERR,Bit0 Error Flag" "0: No such occurrence.,1: At least one bit sent as dominant is received as.." rbitfld.long 0x10 13. "ACKERR,Acknowledge Error Flag" "0: No error,1: An ACK error occurred since last read of this.." newline rbitfld.long 0x10 12. "CRCERR,Cyclic Redundancy Check Error Flag" "0: No error,1: A CRC error occurred since last read of this.." rbitfld.long 0x10 11. "FRMERR,Form Error Flag" "0: No error,1: A Form Error occurred since last read of this.." newline rbitfld.long 0x10 10. "STFERR,Stuffing Error Flag" "0: No error,1: Error occurred since last read of this register." rbitfld.long 0x10 9. "TXWRN,TX Error Warning Flag" "0: No such occurrence.,1: TXERRCNT is 96 or greater." newline rbitfld.long 0x10 8. "RXWRN,RX Error Warning Flag" "0: No such occurrence.,1: RXERRCNT is greater than or equal to 96." rbitfld.long 0x10 7. "IDLE,Idle" "0: Not IDLE,1: IDLE" newline rbitfld.long 0x10 6. "TX,FlexCAN In Transmission" "0: Not transmitting,1: Transmitting" rbitfld.long 0x10 4.--5. "FLTCONF,Fault Confinement State" "0: Bus Off,1: Error Passive,2: Bus Off,3: Bus Off" newline rbitfld.long 0x10 3. "RX,FlexCAN in Reception Flag" "0: Not receiving,1: Receiving" eventfld.long 0x10 2. "BOFFINT,Bus Off Interrupt Flag" "0: No such occurrence.,1: FlexCAN module entered Bus Off state." newline eventfld.long 0x10 1. "ERRINT,Error Interrupt Flag" "0: No such occurrence.,1: Indicates setting of any error flag in the Error.." line.long 0x14 "IMASK2,Interrupt Masks 2" hexmask.long 0x14 0.--31. 1. "BUF63TO32M,Buffer MBi Mask" line.long 0x18 "IMASK1,Interrupt Masks 1" hexmask.long 0x18 0.--31. 1. "BUF31TO0M,Buffer MBi Mask" line.long 0x1C "IFLAG2,Interrupt Flags 2" hexmask.long 0x1C 0.--31. 1. "BUF63TO32I,Buffer MBi Interrupt" line.long 0x20 "IFLAG1,Interrupt Flags 1" hexmask.long.tbyte 0x20 8.--31. 1. "BUF31TO8I,Buffer MBi Interrupt" eventfld.long 0x20 7. "BUF7I,Buffer MB7 Interrupt or RX FIFO Overflow" "0: No occurrence of MB7 completing transmission or..,1: MB7 completed transmission or reception or FIFO.." newline eventfld.long 0x20 6. "BUF6I,Buffer MB6 Interrupt or RX FIFO Warning" "0: No occurrence of MB6 completing transmission or..,1: MB6 completed transmission or reception or FIFO.." eventfld.long 0x20 5. "BUF5I,Buffer MB5 Interrupt or Frames available in RX FIFO" "0: No occurrence of completed transmission or..,1: MB5 completed transmission or reception or.." newline hexmask.long.byte 0x20 1.--4. 1. "BUF4TO1I,Buffer MBi Interrupt or Reserved" eventfld.long 0x20 0. "BUF0I,Buffer MB0 Interrupt or Clear FIFO bit" "0: MB0 has no occurrence of successfully completed..,1: MB0 has successfully completed transmission or.." line.long 0x24 "CTRL2,Control 2" bitfld.long 0x24 31. "ERRMSK_FAST,Error Interrupt Mask for Errors Detected in the Data Phase of Fast CAN FD Frames" "0: Disable,1: Enable" bitfld.long 0x24 30. "BOFFDONEMSK,Bus Off Done Interrupt Mask" "0: Disable,1: Enable" newline bitfld.long 0x24 29. "ECRWRE,Error Correction Configuration Register Write Enable" "0: Disable,1: Enable" bitfld.long 0x24 28. "WRMFRZ,Write Access to Memory in Freeze Mode" "0: Disable,1: Enable" newline hexmask.long.byte 0x24 24.--27. 1. "RFFN,Number of Receive FIFO Filters" hexmask.long.byte 0x24 19.--23. 1. "TASD,Transmission Arbitration Start Delay" newline bitfld.long 0x24 18. "MRP,Message Buffers Reception Priority" "0: Matching starts from RX FIFO and continues on..,1: Matching starts from message buffers and.." bitfld.long 0x24 17. "RRS,Remote Request Storing" "0: Generated,1: Stored" newline bitfld.long 0x24 16. "EACEN,Entire Frame Arbitration Field Comparison Enable for RX Message Buffers" "0: Disable,1: Enable" bitfld.long 0x24 15. "TIMER_SRC,Timer Source" "0: CAN bit clock,1: External time tick" newline bitfld.long 0x24 14. "PREXCEN,Protocol Exception Enable" "0: Disabled,1: Enabled" bitfld.long 0x24 13. "BTE,Bit Timing Expansion Enable" "0: Disable,1: Enable" newline bitfld.long 0x24 12. "ISOCANFDEN,ISO CAN FD Enable" "0: Disable. FlexCAN operates using the non-ISO CAN..,1: Enable. FlexCAN operates using the ISO CAN FD.." bitfld.long 0x24 11. "EDFLTDIS,Edge Filter Disable" "0: Enabled,1: Disabled" newline bitfld.long 0x24 8.--9. "MBTSBASE,Message Buffer Timestamp Base" "0: TIMER,1: Lower 16 bits of high-resolution timer,2: Upper 16 bits of high-resolution timer,?" bitfld.long 0x24 6.--7. "TSTAMPCAP,Timestamp Capture Point" "0: Disabled,1: End of the CAN frame,2: Start of the CAN frame,3: Start of frame for classical CAN frames; res bit.." rgroup.long 0x38++0x3 line.long 0x0 "ESR2,Error and Status 2" hexmask.long.byte 0x0 16.--22. 1. "LPTM,Lowest Priority TX Message Buffer" bitfld.long 0x0 14. "VPS,Valid Priority Status" "0: Invalid,1: Valid" newline bitfld.long 0x0 13. "IMB,Inactive Message Buffer" "0: Message buffer indicated by ESR2[LPTM] is not..,1: At least one message buffer is inactive." rgroup.long 0x44++0x3 line.long 0x0 "CRCR,Cyclic Redundancy Check" hexmask.long.byte 0x0 16.--22. 1. "MBCRC,CRC Message Buffer" hexmask.long.word 0x0 0.--14. 1. "TXCRC,Transmitted CRC value" group.long 0x48++0x3 line.long 0x0 "RXFGMASK,RX FIFO Global Mask" hexmask.long 0x0 0.--31. 1. "FGM,RX FIFO Global Mask Bits" rgroup.long 0x4C++0x3 line.long 0x0 "RXFIR,RX FIFO Information" hexmask.long.word 0x0 0.--8. 1. "IDHIT,Identifier Acceptance Filter Hit Indicator" group.long 0x50++0x3 line.long 0x0 "CBT,CAN Bit Timing" bitfld.long 0x0 31. "BTF,Bit Timing Format Enable" "0: Disable,1: Enable" hexmask.long.word 0x0 21.--30. 1. "EPRESDIV,Extended Prescaler Division Factor" newline hexmask.long.byte 0x0 16.--20. 1. "ERJW,Extended Resync Jump Width" hexmask.long.byte 0x0 10.--15. 1. "EPROPSEG,Extended Propagation Segment" newline hexmask.long.byte 0x0 5.--9. 1. "EPSEG1,Extended Phase Segment 1" hexmask.long.byte 0x0 0.--4. 1. "EPSEG2,Extended Phase Segment 2" repeat 64. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x880)++0x3 line.long 0x0 "RXIMR[$1],Receive Individual Mask" hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits" repeat.end group.long 0xAE0++0xF line.long 0x0 "MECR,Memory Error Control" bitfld.long 0x0 31. "ECRWRDIS,Error Configuration Register Write Disable" "0: Enable,1: Disable" bitfld.long 0x0 19. "HANCEI_MSK,Host Access with Non-Correctable Errors Interrupt Mask" "0: Disable,1: Enable" newline bitfld.long 0x0 18. "FANCEI_MSK,FlexCAN Access with Non-Correctable Errors Interrupt Mask" "0: Disable,1: Enable" bitfld.long 0x0 16. "CEI_MSK,Correctable Errors Interrupt Mask" "0: Disable,1: Enable" newline bitfld.long 0x0 15. "HAERRIE,Host Access Error Injection Enable" "0: Disable,1: Enable" bitfld.long 0x0 14. "FAERRIE,FlexCAN Access Error Injection Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 13. "EXTERRIE,Extended Error Injection Enable" "0: Disable. Apply error injection only to the..,1: Enable. Apply error injection to the 64-bit word." bitfld.long 0x0 9. "RERRDIS,Error Report Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 8. "ECCDIS,Error Correction Disable" "0: Enable,1: Disable" bitfld.long 0x0 7. "NCEFAFRZ,Non-Correctable Errors in FlexCAN Access Put Device in Freeze Mode" "0: Keep normal operation.,1: Put FlexCAN in Freeze mode (see section 'Freeze.." line.long 0x4 "ERRIAR,Error Injection Address" hexmask.long.word 0x4 2.--13. 1. "INJADDR_H,Error Injection Address High" rbitfld.long 0x4 0.--1. "INJADDR_L,Error Injection Address Low" "0,1,2,3" line.long 0x8 "ERRIDPR,Error Injection Data Pattern" hexmask.long 0x8 0.--31. 1. "DFLIP,Data Flip Pattern" line.long 0xC "ERRIPPR,Error Injection Parity Pattern" hexmask.long.byte 0xC 24.--28. 1. "PFLIP3,Parity Flip Pattern for Byte 3 (Most Significant)" hexmask.long.byte 0xC 16.--20. 1. "PFLIP2,Parity Flip Pattern for Byte 2" newline hexmask.long.byte 0xC 8.--12. 1. "PFLIP1,Parity Flip Pattern for Byte 1" hexmask.long.byte 0xC 0.--4. 1. "PFLIP0,Parity Flip Pattern for Byte 0 (Least Significant)" rgroup.long 0xAF0++0xB line.long 0x0 "RERRAR,Error Report Address" bitfld.long 0x0 24. "NCE,Non-Correctable Error" "0: Reporting a correctable error,1: Reporting a non-correctable error" bitfld.long 0x0 16.--18. "SAID,SAID" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--13. 1. "ERRADDR,Address Where Error Detected" line.long 0x4 "RERRDR,Error Report Data" hexmask.long 0x4 0.--31. 1. "RDATA,Raw Data Word Read from Memory with Error" line.long 0x8 "RERRSYNR,Error Report Syndrome" bitfld.long 0x8 31. "BE3,Byte Enabled for Byte 3 (Most Significant)" "0: Byte was not read.,1: Byte was read." hexmask.long.byte 0x8 24.--28. 1. "SYND3,Error Syndrome for Byte 3 (Most Significant)" newline bitfld.long 0x8 23. "BE2,Byte Enabled for Byte 2" "0: Byte was not read.,1: Byte was read." hexmask.long.byte 0x8 16.--20. 1. "SYND2,Error Syndrome for Byte 2" newline bitfld.long 0x8 15. "BE1,Byte Enabled for Byte 1" "0: Byte was not read.,1: Byte was read." hexmask.long.byte 0x8 8.--12. 1. "SYND1,Error Syndrome for Byte 1" newline bitfld.long 0x8 7. "BE0,Byte Enabled for Byte 0 (Least Significant)" "0: Byte was not read.,1: Byte was read." hexmask.long.byte 0x8 0.--4. 1. "SYND0,Error Syndrome for Byte 0 (Least Significant)" group.long 0xAFC++0x3 line.long 0x0 "ERRSR,Error Status" eventfld.long 0x0 19. "HANCEIF,Host Access with Noncorrectable Error Interrupt Flag" "0: No errors detected,1: Error detected" eventfld.long 0x0 18. "FANCEIF,FlexCAN Access with Non-Correctable Error Interrupt Flag" "0: No errors detected,1: Error detected" newline eventfld.long 0x0 16. "CEIF,Correctable Error Interrupt Flag" "0: No errors detected,1: Error detected" eventfld.long 0x0 3. "HANCEIOF,Host Access With Non-Correctable Error Interrupt Overrun Flag" "0: No errors detected,1: Error detected" newline eventfld.long 0x0 2. "FANCEIOF,FlexCAN Access with Non-Correctable Error Interrupt Overrun Flag" "0: No errors detected,1: Error detected" eventfld.long 0x0 0. "CEIOF,Correctable Error Interrupt Overrun Flag" "0: No errors detected,1: Error detected" group.long 0xBF0++0x17 line.long 0x0 "EPRS,Enhanced CAN Bit Timing Prescalers" hexmask.long.word 0x0 16.--25. 1. "EDPRESDIV,Extended Data Phase Prescaler Division Factor" hexmask.long.word 0x0 0.--9. 1. "ENPRESDIV,Extended Nominal Prescaler Division Factor" line.long 0x4 "ENCBT,Enhanced Nominal CAN Bit Timing" hexmask.long.byte 0x4 22.--28. 1. "NRJW,Nominal Resynchronization Jump Width" hexmask.long.byte 0x4 12.--18. 1. "NTSEG2,Nominal Time Segment 2" newline hexmask.long.byte 0x4 0.--7. 1. "NTSEG1,Nominal Time Segment 1" line.long 0x8 "EDCBT,Enhanced Data Phase CAN Bit Timing" hexmask.long.byte 0x8 22.--25. 1. "DRJW,Data Phase Resynchronization Jump Width" hexmask.long.byte 0x8 12.--15. 1. "DTSEG2,Data Phase Time Segment 2" newline hexmask.long.byte 0x8 0.--4. 1. "DTSEG1,Data Phase Segment 1" line.long 0xC "ETDC,Enhanced Transceiver Delay Compensation" bitfld.long 0xC 31. "ETDCEN,Transceiver Delay Compensation Enable" "0: Disable,1: Enable" bitfld.long 0xC 30. "TDMDIS,Transceiver Delay Measurement Disable" "0: Enable,1: Disable" newline hexmask.long.byte 0xC 16.--22. 1. "ETDCOFF,Enhanced Transceiver Delay Compensation Offset" eventfld.long 0xC 15. "ETDCFAIL,Transceiver Delay Compensation Fail" "0: In range,1: Out of range" newline hexmask.long.byte 0xC 0.--7. 1. "ETDCVAL,Enhanced Transceiver Delay Compensation Value" line.long 0x10 "FDCTRL,CAN FD Control" bitfld.long 0x10 31. "FDRATE,Bit Rate Switch Enable" "0: Disable,1: Enable" bitfld.long 0x10 19.--20. "MBDSR1,Message Buffer Data Size for Region 1" "0: 8 bytes,1: 16 bytes,2: 32 bytes,3: 64 bytes" newline bitfld.long 0x10 16.--17. "MBDSR0,Message Buffer Data Size for Region 0" "0: 8 bytes,1: 16 bytes,2: 32 bytes,3: 64 bytes" bitfld.long 0x10 15. "TDCEN,Transceiver Delay Compensation Enable" "0: Disable,1: Enable" newline eventfld.long 0x10 14. "TDCFAIL,Transceiver Delay Compensation Fail" "0: In range,1: Out of range" hexmask.long.byte 0x10 8.--12. 1. "TDCOFF,Transceiver Delay Compensation Offset" newline hexmask.long.byte 0x10 0.--5. 1. "TDCVAL,Transceiver Delay Compensation Value" line.long 0x14 "FDCBT,CAN FD Bit Timing" hexmask.long.word 0x14 20.--29. 1. "FPRESDIV,Fast Prescaler Division Factor" bitfld.long 0x14 16.--18. "FRJW,Fast Resync Jump Width" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 10.--14. 1. "FPROPSEG,Fast Propagation Segment" bitfld.long 0x14 5.--7. "FPSEG1,Fast Phase Segment 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 0.--2. "FPSEG2,Fast Phase Segment 2" "0,1,2,3,4,5,6,7" rgroup.long 0xC08++0x3 line.long 0x0 "FDCRC,CAN FD CRC" hexmask.long.byte 0x0 24.--30. 1. "FD_MBCRC,CRC Message Buffer Number for FD_TXCRC" hexmask.long.tbyte 0x0 0.--20. 1. "FD_TXCRC,Extended Transmitted CRC value" repeat 64. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xC30)++0x3 line.long 0x0 "HR_TIME_STAMP[$1],High-Resolution Timestamp" hexmask.long 0x0 0.--31. 1. "TS,High-Resolution Timestamp" repeat.end tree.end tree "CAN_6" base ad:0x4031C000 group.long 0x0++0xB line.long 0x0 "MCR,Module Configuration" bitfld.long 0x0 31. "MDIS,Module Disable" "0: Enable,1: Disable" bitfld.long 0x0 30. "FRZ,Freeze Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 29. "RFEN,RX FIFO Enable" "0: Disable,1: Enable" bitfld.long 0x0 28. "HALT,Halt FlexCAN" "0: No request,1: Enter Freeze mode if MCR[FRZ] = 1." newline rbitfld.long 0x0 27. "NOTRDY,FlexCAN Not Ready" "0: FlexCAN is in Normal mode Listen-Only mode or..,1: FlexCAN is in Disable mode or Freeze mode." bitfld.long 0x0 25. "SOFTRST,Soft Reset" "0: No reset,1: Soft reset affects reset registers" newline rbitfld.long 0x0 24. "FRZACK,Freeze Mode Acknowledge" "0: Not in Freeze mode prescaler running.,1: In Freeze mode prescaler stopped." bitfld.long 0x0 23. "SUPV,Supervisor Mode" "0: User mode,1: Supervisor mode" newline bitfld.long 0x0 21. "WRNEN,Warning Interrupt Enable" "0: Disable,1: Enable" rbitfld.long 0x0 20. "LPMACK,Low-Power Mode Acknowledge" "0: Not in a low-power mode,1: In a low-power mode" newline bitfld.long 0x0 17. "SRXDIS,Self-Reception Disable" "0: Enable,1: Disable" bitfld.long 0x0 16. "IRMQ,Individual RX Masking and Queue Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 15. "DMA,DMA Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "LPRIOEN,Local Priority Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 12. "AEN,Abort Enable" "0: Disabled,1: Enabled" bitfld.long 0x0 11. "FDEN,CAN FD Operation Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 8.--9. "IDAM,ID Acceptance Mode" "0: Format A: One full ID (standard and extended)..,1: Format B: Two full standard IDs or two partial..,2: Format C: Four partial 8-bit standard IDs per ID..,3: Format D: All frames rejected." hexmask.long.byte 0x0 0.--6. 1. "MAXMB,Number of the Last Message Buffer" line.long 0x4 "CTRL1,Control 1" hexmask.long.byte 0x4 24.--31. 1. "PRESDIV,Prescaler Division Factor" bitfld.long 0x4 22.--23. "RJW,Resync Jump Width" "0,1,2,3" newline bitfld.long 0x4 19.--21. "PSEG1,Phase Segment 1" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "PSEG2,Phase Segment 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 15. "BOFFMSK,Bus Off Interrupt Mask" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 14. "ERRMSK,Error Interrupt Mask" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 12. "LPB,Loopback Mode" "0: Disabled,1: Enabled" bitfld.long 0x4 11. "TWRNMSK,TX Warning Interrupt Mask" "0: Disabled,1: Enabled" newline bitfld.long 0x4 10. "RWRNMSK,RX Warning Interrupt Mask" "0: Disabled,1: Enabled" bitfld.long 0x4 7. "SMP,CAN Bit Sampling" "0: One sample is used to determine the bit value.,1: Three samples are used to determine the value of.." newline bitfld.long 0x4 6. "BOFFREC,Bus Off Recovery" "0: Enabled,1: Disabled" bitfld.long 0x4 5. "TSYN,Timer Sync" "0: Disable,1: Enable" newline bitfld.long 0x4 4. "LBUF,Lowest Buffer Transmitted First" "0: Buffer with highest priority is transmitted first.,1: Lowest number buffer is transmitted first." bitfld.long 0x4 3. "LOM,Listen-Only Mode" "0: Listen-Only mode is deactivated.,1: FlexCAN module operates in Listen-Only mode." newline bitfld.long 0x4 0.--2. "PROPSEG,Propagation Segment" "0,1,2,3,4,5,6,7" line.long 0x8 "TIMER,Free-Running Timer" hexmask.long.word 0x8 0.--15. 1. "TIMER,Timer Value" group.long 0x10++0x27 line.long 0x0 "RXMGMASK,RX Message Buffers Global Mask" hexmask.long 0x0 0.--31. 1. "MG,Global Mask for RX Message Buffers" line.long 0x4 "RX14MASK,Receive 14 Mask" hexmask.long 0x4 0.--31. 1. "RX14M,RX Buffer 14 Mask Bits" line.long 0x8 "RX15MASK,Receive 15 Mask" hexmask.long 0x8 0.--31. 1. "RX15M,RX Buffer 15 Mask Bits" line.long 0xC "ECR,Error Counter" hexmask.long.byte 0xC 24.--31. 1. "RXERRCNT_FAST,Receive Error Counter for Fast Bits" hexmask.long.byte 0xC 16.--23. 1. "TXERRCNT_FAST,Transmit Error Counter for Fast Bits" newline hexmask.long.byte 0xC 8.--15. 1. "RXERRCNT,Receive Error Counter" hexmask.long.byte 0xC 0.--7. 1. "TXERRCNT,Transmit Error Counter" line.long 0x10 "ESR1,Error and Status 1" rbitfld.long 0x10 31. "BIT1ERR_FAST,Fast Bit1 Error Flag" "0: No such occurrence.,1: At least one bit sent as recessive is received.." rbitfld.long 0x10 30. "BIT0ERR_FAST,Fast Bit0 Error Flag" "0: No such occurrence.,1: At least one bit sent as dominant is received as.." newline rbitfld.long 0x10 28. "CRCERR_FAST,Fast Cyclic Redundancy Check Error Flag" "0: No such occurrence.,1: A CRC error occurred since last read of this.." rbitfld.long 0x10 27. "FRMERR_FAST,Fast Form Error Flag" "0: No such occurrence.,1: A form error occurred since last read of this.." newline rbitfld.long 0x10 26. "STFERR_FAST,Fast Stuffing Error Flag" "0: No such occurrence.,1: A stuffing error occurred since last read of.." eventfld.long 0x10 21. "ERROVR,Error Overrun Flag" "0: No overrun,1: Overrun" newline eventfld.long 0x10 20. "ERRINT_FAST,Fast Error Interrupt Flag" "0: No such occurrence.,1: Error flag set in the data phase of CAN FD.." eventfld.long 0x10 19. "BOFFDONEINT,Bus Off Done Interrupt Flag" "0: No such occurrence,1: FlexCAN module has completed Bus Off process." newline rbitfld.long 0x10 18. "SYNCH,CAN Synchronization Status Flag" "0: Not synchronized,1: Synchronized" eventfld.long 0x10 17. "TWRNINT,TX Warning Interrupt Flag" "0: No such occurrence,1: TX error counter changed from less than 96 to.." newline eventfld.long 0x10 16. "RWRNINT,RX Warning Interrupt Flag" "0: No such occurrence,1: RX error counter changed from less than 96 to.." rbitfld.long 0x10 15. "BIT1ERR,Bit1 Error Flag" "0: No such occurrence.,1: At least one bit sent as recessive is received.." newline rbitfld.long 0x10 14. "BIT0ERR,Bit0 Error Flag" "0: No such occurrence.,1: At least one bit sent as dominant is received as.." rbitfld.long 0x10 13. "ACKERR,Acknowledge Error Flag" "0: No error,1: An ACK error occurred since last read of this.." newline rbitfld.long 0x10 12. "CRCERR,Cyclic Redundancy Check Error Flag" "0: No error,1: A CRC error occurred since last read of this.." rbitfld.long 0x10 11. "FRMERR,Form Error Flag" "0: No error,1: A Form Error occurred since last read of this.." newline rbitfld.long 0x10 10. "STFERR,Stuffing Error Flag" "0: No error,1: Error occurred since last read of this register." rbitfld.long 0x10 9. "TXWRN,TX Error Warning Flag" "0: No such occurrence.,1: TXERRCNT is 96 or greater." newline rbitfld.long 0x10 8. "RXWRN,RX Error Warning Flag" "0: No such occurrence.,1: RXERRCNT is greater than or equal to 96." rbitfld.long 0x10 7. "IDLE,Idle" "0: Not IDLE,1: IDLE" newline rbitfld.long 0x10 6. "TX,FlexCAN In Transmission" "0: Not transmitting,1: Transmitting" rbitfld.long 0x10 4.--5. "FLTCONF,Fault Confinement State" "0: Bus Off,1: Error Passive,2: Bus Off,3: Bus Off" newline rbitfld.long 0x10 3. "RX,FlexCAN in Reception Flag" "0: Not receiving,1: Receiving" eventfld.long 0x10 2. "BOFFINT,Bus Off Interrupt Flag" "0: No such occurrence.,1: FlexCAN module entered Bus Off state." newline eventfld.long 0x10 1. "ERRINT,Error Interrupt Flag" "0: No such occurrence.,1: Indicates setting of any error flag in the Error.." line.long 0x14 "IMASK2,Interrupt Masks 2" hexmask.long 0x14 0.--31. 1. "BUF63TO32M,Buffer MBi Mask" line.long 0x18 "IMASK1,Interrupt Masks 1" hexmask.long 0x18 0.--31. 1. "BUF31TO0M,Buffer MBi Mask" line.long 0x1C "IFLAG2,Interrupt Flags 2" hexmask.long 0x1C 0.--31. 1. "BUF63TO32I,Buffer MBi Interrupt" line.long 0x20 "IFLAG1,Interrupt Flags 1" hexmask.long.tbyte 0x20 8.--31. 1. "BUF31TO8I,Buffer MBi Interrupt" eventfld.long 0x20 7. "BUF7I,Buffer MB7 Interrupt or RX FIFO Overflow" "0: No occurrence of MB7 completing transmission or..,1: MB7 completed transmission or reception or FIFO.." newline eventfld.long 0x20 6. "BUF6I,Buffer MB6 Interrupt or RX FIFO Warning" "0: No occurrence of MB6 completing transmission or..,1: MB6 completed transmission or reception or FIFO.." eventfld.long 0x20 5. "BUF5I,Buffer MB5 Interrupt or Frames available in RX FIFO" "0: No occurrence of completed transmission or..,1: MB5 completed transmission or reception or.." newline hexmask.long.byte 0x20 1.--4. 1. "BUF4TO1I,Buffer MBi Interrupt or Reserved" eventfld.long 0x20 0. "BUF0I,Buffer MB0 Interrupt or Clear FIFO bit" "0: MB0 has no occurrence of successfully completed..,1: MB0 has successfully completed transmission or.." line.long 0x24 "CTRL2,Control 2" bitfld.long 0x24 31. "ERRMSK_FAST,Error Interrupt Mask for Errors Detected in the Data Phase of Fast CAN FD Frames" "0: Disable,1: Enable" bitfld.long 0x24 30. "BOFFDONEMSK,Bus Off Done Interrupt Mask" "0: Disable,1: Enable" newline bitfld.long 0x24 29. "ECRWRE,Error Correction Configuration Register Write Enable" "0: Disable,1: Enable" bitfld.long 0x24 28. "WRMFRZ,Write Access to Memory in Freeze Mode" "0: Disable,1: Enable" newline hexmask.long.byte 0x24 24.--27. 1. "RFFN,Number of Receive FIFO Filters" hexmask.long.byte 0x24 19.--23. 1. "TASD,Transmission Arbitration Start Delay" newline bitfld.long 0x24 18. "MRP,Message Buffers Reception Priority" "0: Matching starts from RX FIFO and continues on..,1: Matching starts from message buffers and.." bitfld.long 0x24 17. "RRS,Remote Request Storing" "0: Generated,1: Stored" newline bitfld.long 0x24 16. "EACEN,Entire Frame Arbitration Field Comparison Enable for RX Message Buffers" "0: Disable,1: Enable" bitfld.long 0x24 15. "TIMER_SRC,Timer Source" "0: CAN bit clock,1: External time tick" newline bitfld.long 0x24 14. "PREXCEN,Protocol Exception Enable" "0: Disabled,1: Enabled" bitfld.long 0x24 13. "BTE,Bit Timing Expansion Enable" "0: Disable,1: Enable" newline bitfld.long 0x24 12. "ISOCANFDEN,ISO CAN FD Enable" "0: Disable. FlexCAN operates using the non-ISO CAN..,1: Enable. FlexCAN operates using the ISO CAN FD.." bitfld.long 0x24 11. "EDFLTDIS,Edge Filter Disable" "0: Enabled,1: Disabled" newline bitfld.long 0x24 8.--9. "MBTSBASE,Message Buffer Timestamp Base" "0: TIMER,1: Lower 16 bits of high-resolution timer,2: Upper 16 bits of high-resolution timer,?" bitfld.long 0x24 6.--7. "TSTAMPCAP,Timestamp Capture Point" "0: Disabled,1: End of the CAN frame,2: Start of the CAN frame,3: Start of frame for classical CAN frames; res bit.." rgroup.long 0x38++0x3 line.long 0x0 "ESR2,Error and Status 2" hexmask.long.byte 0x0 16.--22. 1. "LPTM,Lowest Priority TX Message Buffer" bitfld.long 0x0 14. "VPS,Valid Priority Status" "0: Invalid,1: Valid" newline bitfld.long 0x0 13. "IMB,Inactive Message Buffer" "0: Message buffer indicated by ESR2[LPTM] is not..,1: At least one message buffer is inactive." rgroup.long 0x44++0x3 line.long 0x0 "CRCR,Cyclic Redundancy Check" hexmask.long.byte 0x0 16.--22. 1. "MBCRC,CRC Message Buffer" hexmask.long.word 0x0 0.--14. 1. "TXCRC,Transmitted CRC value" group.long 0x48++0x3 line.long 0x0 "RXFGMASK,RX FIFO Global Mask" hexmask.long 0x0 0.--31. 1. "FGM,RX FIFO Global Mask Bits" rgroup.long 0x4C++0x3 line.long 0x0 "RXFIR,RX FIFO Information" hexmask.long.word 0x0 0.--8. 1. "IDHIT,Identifier Acceptance Filter Hit Indicator" group.long 0x50++0x3 line.long 0x0 "CBT,CAN Bit Timing" bitfld.long 0x0 31. "BTF,Bit Timing Format Enable" "0: Disable,1: Enable" hexmask.long.word 0x0 21.--30. 1. "EPRESDIV,Extended Prescaler Division Factor" newline hexmask.long.byte 0x0 16.--20. 1. "ERJW,Extended Resync Jump Width" hexmask.long.byte 0x0 10.--15. 1. "EPROPSEG,Extended Propagation Segment" newline hexmask.long.byte 0x0 5.--9. 1. "EPSEG1,Extended Phase Segment 1" hexmask.long.byte 0x0 0.--4. 1. "EPSEG2,Extended Phase Segment 2" repeat 64. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x880)++0x3 line.long 0x0 "RXIMR[$1],Receive Individual Mask" hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits" repeat.end group.long 0xAE0++0xF line.long 0x0 "MECR,Memory Error Control" bitfld.long 0x0 31. "ECRWRDIS,Error Configuration Register Write Disable" "0: Enable,1: Disable" bitfld.long 0x0 19. "HANCEI_MSK,Host Access with Non-Correctable Errors Interrupt Mask" "0: Disable,1: Enable" newline bitfld.long 0x0 18. "FANCEI_MSK,FlexCAN Access with Non-Correctable Errors Interrupt Mask" "0: Disable,1: Enable" bitfld.long 0x0 16. "CEI_MSK,Correctable Errors Interrupt Mask" "0: Disable,1: Enable" newline bitfld.long 0x0 15. "HAERRIE,Host Access Error Injection Enable" "0: Disable,1: Enable" bitfld.long 0x0 14. "FAERRIE,FlexCAN Access Error Injection Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 13. "EXTERRIE,Extended Error Injection Enable" "0: Disable. Apply error injection only to the..,1: Enable. Apply error injection to the 64-bit word." bitfld.long 0x0 9. "RERRDIS,Error Report Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 8. "ECCDIS,Error Correction Disable" "0: Enable,1: Disable" bitfld.long 0x0 7. "NCEFAFRZ,Non-Correctable Errors in FlexCAN Access Put Device in Freeze Mode" "0: Keep normal operation.,1: Put FlexCAN in Freeze mode (see section 'Freeze.." line.long 0x4 "ERRIAR,Error Injection Address" hexmask.long.word 0x4 2.--13. 1. "INJADDR_H,Error Injection Address High" rbitfld.long 0x4 0.--1. "INJADDR_L,Error Injection Address Low" "0,1,2,3" line.long 0x8 "ERRIDPR,Error Injection Data Pattern" hexmask.long 0x8 0.--31. 1. "DFLIP,Data Flip Pattern" line.long 0xC "ERRIPPR,Error Injection Parity Pattern" hexmask.long.byte 0xC 24.--28. 1. "PFLIP3,Parity Flip Pattern for Byte 3 (Most Significant)" hexmask.long.byte 0xC 16.--20. 1. "PFLIP2,Parity Flip Pattern for Byte 2" newline hexmask.long.byte 0xC 8.--12. 1. "PFLIP1,Parity Flip Pattern for Byte 1" hexmask.long.byte 0xC 0.--4. 1. "PFLIP0,Parity Flip Pattern for Byte 0 (Least Significant)" rgroup.long 0xAF0++0xB line.long 0x0 "RERRAR,Error Report Address" bitfld.long 0x0 24. "NCE,Non-Correctable Error" "0: Reporting a correctable error,1: Reporting a non-correctable error" bitfld.long 0x0 16.--18. "SAID,SAID" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--13. 1. "ERRADDR,Address Where Error Detected" line.long 0x4 "RERRDR,Error Report Data" hexmask.long 0x4 0.--31. 1. "RDATA,Raw Data Word Read from Memory with Error" line.long 0x8 "RERRSYNR,Error Report Syndrome" bitfld.long 0x8 31. "BE3,Byte Enabled for Byte 3 (Most Significant)" "0: Byte was not read.,1: Byte was read." hexmask.long.byte 0x8 24.--28. 1. "SYND3,Error Syndrome for Byte 3 (Most Significant)" newline bitfld.long 0x8 23. "BE2,Byte Enabled for Byte 2" "0: Byte was not read.,1: Byte was read." hexmask.long.byte 0x8 16.--20. 1. "SYND2,Error Syndrome for Byte 2" newline bitfld.long 0x8 15. "BE1,Byte Enabled for Byte 1" "0: Byte was not read.,1: Byte was read." hexmask.long.byte 0x8 8.--12. 1. "SYND1,Error Syndrome for Byte 1" newline bitfld.long 0x8 7. "BE0,Byte Enabled for Byte 0 (Least Significant)" "0: Byte was not read.,1: Byte was read." hexmask.long.byte 0x8 0.--4. 1. "SYND0,Error Syndrome for Byte 0 (Least Significant)" group.long 0xAFC++0x3 line.long 0x0 "ERRSR,Error Status" eventfld.long 0x0 19. "HANCEIF,Host Access with Noncorrectable Error Interrupt Flag" "0: No errors detected,1: Error detected" eventfld.long 0x0 18. "FANCEIF,FlexCAN Access with Non-Correctable Error Interrupt Flag" "0: No errors detected,1: Error detected" newline eventfld.long 0x0 16. "CEIF,Correctable Error Interrupt Flag" "0: No errors detected,1: Error detected" eventfld.long 0x0 3. "HANCEIOF,Host Access With Non-Correctable Error Interrupt Overrun Flag" "0: No errors detected,1: Error detected" newline eventfld.long 0x0 2. "FANCEIOF,FlexCAN Access with Non-Correctable Error Interrupt Overrun Flag" "0: No errors detected,1: Error detected" eventfld.long 0x0 0. "CEIOF,Correctable Error Interrupt Overrun Flag" "0: No errors detected,1: Error detected" group.long 0xBF0++0x17 line.long 0x0 "EPRS,Enhanced CAN Bit Timing Prescalers" hexmask.long.word 0x0 16.--25. 1. "EDPRESDIV,Extended Data Phase Prescaler Division Factor" hexmask.long.word 0x0 0.--9. 1. "ENPRESDIV,Extended Nominal Prescaler Division Factor" line.long 0x4 "ENCBT,Enhanced Nominal CAN Bit Timing" hexmask.long.byte 0x4 22.--28. 1. "NRJW,Nominal Resynchronization Jump Width" hexmask.long.byte 0x4 12.--18. 1. "NTSEG2,Nominal Time Segment 2" newline hexmask.long.byte 0x4 0.--7. 1. "NTSEG1,Nominal Time Segment 1" line.long 0x8 "EDCBT,Enhanced Data Phase CAN Bit Timing" hexmask.long.byte 0x8 22.--25. 1. "DRJW,Data Phase Resynchronization Jump Width" hexmask.long.byte 0x8 12.--15. 1. "DTSEG2,Data Phase Time Segment 2" newline hexmask.long.byte 0x8 0.--4. 1. "DTSEG1,Data Phase Segment 1" line.long 0xC "ETDC,Enhanced Transceiver Delay Compensation" bitfld.long 0xC 31. "ETDCEN,Transceiver Delay Compensation Enable" "0: Disable,1: Enable" bitfld.long 0xC 30. "TDMDIS,Transceiver Delay Measurement Disable" "0: Enable,1: Disable" newline hexmask.long.byte 0xC 16.--22. 1. "ETDCOFF,Enhanced Transceiver Delay Compensation Offset" eventfld.long 0xC 15. "ETDCFAIL,Transceiver Delay Compensation Fail" "0: In range,1: Out of range" newline hexmask.long.byte 0xC 0.--7. 1. "ETDCVAL,Enhanced Transceiver Delay Compensation Value" line.long 0x10 "FDCTRL,CAN FD Control" bitfld.long 0x10 31. "FDRATE,Bit Rate Switch Enable" "0: Disable,1: Enable" bitfld.long 0x10 19.--20. "MBDSR1,Message Buffer Data Size for Region 1" "0: 8 bytes,1: 16 bytes,2: 32 bytes,3: 64 bytes" newline bitfld.long 0x10 16.--17. "MBDSR0,Message Buffer Data Size for Region 0" "0: 8 bytes,1: 16 bytes,2: 32 bytes,3: 64 bytes" bitfld.long 0x10 15. "TDCEN,Transceiver Delay Compensation Enable" "0: Disable,1: Enable" newline eventfld.long 0x10 14. "TDCFAIL,Transceiver Delay Compensation Fail" "0: In range,1: Out of range" hexmask.long.byte 0x10 8.--12. 1. "TDCOFF,Transceiver Delay Compensation Offset" newline hexmask.long.byte 0x10 0.--5. 1. "TDCVAL,Transceiver Delay Compensation Value" line.long 0x14 "FDCBT,CAN FD Bit Timing" hexmask.long.word 0x14 20.--29. 1. "FPRESDIV,Fast Prescaler Division Factor" bitfld.long 0x14 16.--18. "FRJW,Fast Resync Jump Width" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 10.--14. 1. "FPROPSEG,Fast Propagation Segment" bitfld.long 0x14 5.--7. "FPSEG1,Fast Phase Segment 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 0.--2. "FPSEG2,Fast Phase Segment 2" "0,1,2,3,4,5,6,7" rgroup.long 0xC08++0x3 line.long 0x0 "FDCRC,CAN FD CRC" hexmask.long.byte 0x0 24.--30. 1. "FD_MBCRC,CRC Message Buffer Number for FD_TXCRC" hexmask.long.tbyte 0x0 0.--20. 1. "FD_TXCRC,Extended Transmitted CRC value" repeat 64. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xC30)++0x3 line.long 0x0 "HR_TIME_STAMP[$1],High-Resolution Timestamp" hexmask.long 0x0 0.--31. 1. "TS,High-Resolution Timestamp" repeat.end tree.end tree "CAN_7" base ad:0x40320000 group.long 0x0++0xB line.long 0x0 "MCR,Module Configuration" bitfld.long 0x0 31. "MDIS,Module Disable" "0: Enable,1: Disable" bitfld.long 0x0 30. "FRZ,Freeze Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 29. "RFEN,RX FIFO Enable" "0: Disable,1: Enable" bitfld.long 0x0 28. "HALT,Halt FlexCAN" "0: No request,1: Enter Freeze mode if MCR[FRZ] = 1." newline rbitfld.long 0x0 27. "NOTRDY,FlexCAN Not Ready" "0: FlexCAN is in Normal mode Listen-Only mode or..,1: FlexCAN is in Disable mode or Freeze mode." bitfld.long 0x0 25. "SOFTRST,Soft Reset" "0: No reset,1: Soft reset affects reset registers" newline rbitfld.long 0x0 24. "FRZACK,Freeze Mode Acknowledge" "0: Not in Freeze mode prescaler running.,1: In Freeze mode prescaler stopped." bitfld.long 0x0 23. "SUPV,Supervisor Mode" "0: User mode,1: Supervisor mode" newline bitfld.long 0x0 21. "WRNEN,Warning Interrupt Enable" "0: Disable,1: Enable" rbitfld.long 0x0 20. "LPMACK,Low-Power Mode Acknowledge" "0: Not in a low-power mode,1: In a low-power mode" newline bitfld.long 0x0 17. "SRXDIS,Self-Reception Disable" "0: Enable,1: Disable" bitfld.long 0x0 16. "IRMQ,Individual RX Masking and Queue Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 15. "DMA,DMA Enable" "0: Disable,1: Enable" bitfld.long 0x0 13. "LPRIOEN,Local Priority Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 12. "AEN,Abort Enable" "0: Disabled,1: Enabled" bitfld.long 0x0 11. "FDEN,CAN FD Operation Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 8.--9. "IDAM,ID Acceptance Mode" "0: Format A: One full ID (standard and extended)..,1: Format B: Two full standard IDs or two partial..,2: Format C: Four partial 8-bit standard IDs per ID..,3: Format D: All frames rejected." hexmask.long.byte 0x0 0.--6. 1. "MAXMB,Number of the Last Message Buffer" line.long 0x4 "CTRL1,Control 1" hexmask.long.byte 0x4 24.--31. 1. "PRESDIV,Prescaler Division Factor" bitfld.long 0x4 22.--23. "RJW,Resync Jump Width" "0,1,2,3" newline bitfld.long 0x4 19.--21. "PSEG1,Phase Segment 1" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "PSEG2,Phase Segment 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 15. "BOFFMSK,Bus Off Interrupt Mask" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 14. "ERRMSK,Error Interrupt Mask" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 12. "LPB,Loopback Mode" "0: Disabled,1: Enabled" bitfld.long 0x4 11. "TWRNMSK,TX Warning Interrupt Mask" "0: Disabled,1: Enabled" newline bitfld.long 0x4 10. "RWRNMSK,RX Warning Interrupt Mask" "0: Disabled,1: Enabled" bitfld.long 0x4 7. "SMP,CAN Bit Sampling" "0: One sample is used to determine the bit value.,1: Three samples are used to determine the value of.." newline bitfld.long 0x4 6. "BOFFREC,Bus Off Recovery" "0: Enabled,1: Disabled" bitfld.long 0x4 5. "TSYN,Timer Sync" "0: Disable,1: Enable" newline bitfld.long 0x4 4. "LBUF,Lowest Buffer Transmitted First" "0: Buffer with highest priority is transmitted first.,1: Lowest number buffer is transmitted first." bitfld.long 0x4 3. "LOM,Listen-Only Mode" "0: Listen-Only mode is deactivated.,1: FlexCAN module operates in Listen-Only mode." newline bitfld.long 0x4 0.--2. "PROPSEG,Propagation Segment" "0,1,2,3,4,5,6,7" line.long 0x8 "TIMER,Free-Running Timer" hexmask.long.word 0x8 0.--15. 1. "TIMER,Timer Value" group.long 0x10++0x27 line.long 0x0 "RXMGMASK,RX Message Buffers Global Mask" hexmask.long 0x0 0.--31. 1. "MG,Global Mask for RX Message Buffers" line.long 0x4 "RX14MASK,Receive 14 Mask" hexmask.long 0x4 0.--31. 1. "RX14M,RX Buffer 14 Mask Bits" line.long 0x8 "RX15MASK,Receive 15 Mask" hexmask.long 0x8 0.--31. 1. "RX15M,RX Buffer 15 Mask Bits" line.long 0xC "ECR,Error Counter" hexmask.long.byte 0xC 24.--31. 1. "RXERRCNT_FAST,Receive Error Counter for Fast Bits" hexmask.long.byte 0xC 16.--23. 1. "TXERRCNT_FAST,Transmit Error Counter for Fast Bits" newline hexmask.long.byte 0xC 8.--15. 1. "RXERRCNT,Receive Error Counter" hexmask.long.byte 0xC 0.--7. 1. "TXERRCNT,Transmit Error Counter" line.long 0x10 "ESR1,Error and Status 1" rbitfld.long 0x10 31. "BIT1ERR_FAST,Fast Bit1 Error Flag" "0: No such occurrence.,1: At least one bit sent as recessive is received.." rbitfld.long 0x10 30. "BIT0ERR_FAST,Fast Bit0 Error Flag" "0: No such occurrence.,1: At least one bit sent as dominant is received as.." newline rbitfld.long 0x10 28. "CRCERR_FAST,Fast Cyclic Redundancy Check Error Flag" "0: No such occurrence.,1: A CRC error occurred since last read of this.." rbitfld.long 0x10 27. "FRMERR_FAST,Fast Form Error Flag" "0: No such occurrence.,1: A form error occurred since last read of this.." newline rbitfld.long 0x10 26. "STFERR_FAST,Fast Stuffing Error Flag" "0: No such occurrence.,1: A stuffing error occurred since last read of.." eventfld.long 0x10 21. "ERROVR,Error Overrun Flag" "0: No overrun,1: Overrun" newline eventfld.long 0x10 20. "ERRINT_FAST,Fast Error Interrupt Flag" "0: No such occurrence.,1: Error flag set in the data phase of CAN FD.." eventfld.long 0x10 19. "BOFFDONEINT,Bus Off Done Interrupt Flag" "0: No such occurrence,1: FlexCAN module has completed Bus Off process." newline rbitfld.long 0x10 18. "SYNCH,CAN Synchronization Status Flag" "0: Not synchronized,1: Synchronized" eventfld.long 0x10 17. "TWRNINT,TX Warning Interrupt Flag" "0: No such occurrence,1: TX error counter changed from less than 96 to.." newline eventfld.long 0x10 16. "RWRNINT,RX Warning Interrupt Flag" "0: No such occurrence,1: RX error counter changed from less than 96 to.." rbitfld.long 0x10 15. "BIT1ERR,Bit1 Error Flag" "0: No such occurrence.,1: At least one bit sent as recessive is received.." newline rbitfld.long 0x10 14. "BIT0ERR,Bit0 Error Flag" "0: No such occurrence.,1: At least one bit sent as dominant is received as.." rbitfld.long 0x10 13. "ACKERR,Acknowledge Error Flag" "0: No error,1: An ACK error occurred since last read of this.." newline rbitfld.long 0x10 12. "CRCERR,Cyclic Redundancy Check Error Flag" "0: No error,1: A CRC error occurred since last read of this.." rbitfld.long 0x10 11. "FRMERR,Form Error Flag" "0: No error,1: A Form Error occurred since last read of this.." newline rbitfld.long 0x10 10. "STFERR,Stuffing Error Flag" "0: No error,1: Error occurred since last read of this register." rbitfld.long 0x10 9. "TXWRN,TX Error Warning Flag" "0: No such occurrence.,1: TXERRCNT is 96 or greater." newline rbitfld.long 0x10 8. "RXWRN,RX Error Warning Flag" "0: No such occurrence.,1: RXERRCNT is greater than or equal to 96." rbitfld.long 0x10 7. "IDLE,Idle" "0: Not IDLE,1: IDLE" newline rbitfld.long 0x10 6. "TX,FlexCAN In Transmission" "0: Not transmitting,1: Transmitting" rbitfld.long 0x10 4.--5. "FLTCONF,Fault Confinement State" "0: Bus Off,1: Error Passive,2: Bus Off,3: Bus Off" newline rbitfld.long 0x10 3. "RX,FlexCAN in Reception Flag" "0: Not receiving,1: Receiving" eventfld.long 0x10 2. "BOFFINT,Bus Off Interrupt Flag" "0: No such occurrence.,1: FlexCAN module entered Bus Off state." newline eventfld.long 0x10 1. "ERRINT,Error Interrupt Flag" "0: No such occurrence.,1: Indicates setting of any error flag in the Error.." line.long 0x14 "IMASK2,Interrupt Masks 2" hexmask.long 0x14 0.--31. 1. "BUF63TO32M,Buffer MBi Mask" line.long 0x18 "IMASK1,Interrupt Masks 1" hexmask.long 0x18 0.--31. 1. "BUF31TO0M,Buffer MBi Mask" line.long 0x1C "IFLAG2,Interrupt Flags 2" hexmask.long 0x1C 0.--31. 1. "BUF63TO32I,Buffer MBi Interrupt" line.long 0x20 "IFLAG1,Interrupt Flags 1" hexmask.long.tbyte 0x20 8.--31. 1. "BUF31TO8I,Buffer MBi Interrupt" eventfld.long 0x20 7. "BUF7I,Buffer MB7 Interrupt or RX FIFO Overflow" "0: No occurrence of MB7 completing transmission or..,1: MB7 completed transmission or reception or FIFO.." newline eventfld.long 0x20 6. "BUF6I,Buffer MB6 Interrupt or RX FIFO Warning" "0: No occurrence of MB6 completing transmission or..,1: MB6 completed transmission or reception or FIFO.." eventfld.long 0x20 5. "BUF5I,Buffer MB5 Interrupt or Frames available in RX FIFO" "0: No occurrence of completed transmission or..,1: MB5 completed transmission or reception or.." newline hexmask.long.byte 0x20 1.--4. 1. "BUF4TO1I,Buffer MBi Interrupt or Reserved" eventfld.long 0x20 0. "BUF0I,Buffer MB0 Interrupt or Clear FIFO bit" "0: MB0 has no occurrence of successfully completed..,1: MB0 has successfully completed transmission or.." line.long 0x24 "CTRL2,Control 2" bitfld.long 0x24 31. "ERRMSK_FAST,Error Interrupt Mask for Errors Detected in the Data Phase of Fast CAN FD Frames" "0: Disable,1: Enable" bitfld.long 0x24 30. "BOFFDONEMSK,Bus Off Done Interrupt Mask" "0: Disable,1: Enable" newline bitfld.long 0x24 29. "ECRWRE,Error Correction Configuration Register Write Enable" "0: Disable,1: Enable" bitfld.long 0x24 28. "WRMFRZ,Write Access to Memory in Freeze Mode" "0: Disable,1: Enable" newline hexmask.long.byte 0x24 24.--27. 1. "RFFN,Number of Receive FIFO Filters" hexmask.long.byte 0x24 19.--23. 1. "TASD,Transmission Arbitration Start Delay" newline bitfld.long 0x24 18. "MRP,Message Buffers Reception Priority" "0: Matching starts from RX FIFO and continues on..,1: Matching starts from message buffers and.." bitfld.long 0x24 17. "RRS,Remote Request Storing" "0: Generated,1: Stored" newline bitfld.long 0x24 16. "EACEN,Entire Frame Arbitration Field Comparison Enable for RX Message Buffers" "0: Disable,1: Enable" bitfld.long 0x24 15. "TIMER_SRC,Timer Source" "0: CAN bit clock,1: External time tick" newline bitfld.long 0x24 14. "PREXCEN,Protocol Exception Enable" "0: Disabled,1: Enabled" bitfld.long 0x24 13. "BTE,Bit Timing Expansion Enable" "0: Disable,1: Enable" newline bitfld.long 0x24 12. "ISOCANFDEN,ISO CAN FD Enable" "0: Disable. FlexCAN operates using the non-ISO CAN..,1: Enable. FlexCAN operates using the ISO CAN FD.." bitfld.long 0x24 11. "EDFLTDIS,Edge Filter Disable" "0: Enabled,1: Disabled" newline bitfld.long 0x24 8.--9. "MBTSBASE,Message Buffer Timestamp Base" "0: TIMER,1: Lower 16 bits of high-resolution timer,2: Upper 16 bits of high-resolution timer,?" bitfld.long 0x24 6.--7. "TSTAMPCAP,Timestamp Capture Point" "0: Disabled,1: End of the CAN frame,2: Start of the CAN frame,3: Start of frame for classical CAN frames; res bit.." rgroup.long 0x38++0x3 line.long 0x0 "ESR2,Error and Status 2" hexmask.long.byte 0x0 16.--22. 1. "LPTM,Lowest Priority TX Message Buffer" bitfld.long 0x0 14. "VPS,Valid Priority Status" "0: Invalid,1: Valid" newline bitfld.long 0x0 13. "IMB,Inactive Message Buffer" "0: Message buffer indicated by ESR2[LPTM] is not..,1: At least one message buffer is inactive." rgroup.long 0x44++0x3 line.long 0x0 "CRCR,Cyclic Redundancy Check" hexmask.long.byte 0x0 16.--22. 1. "MBCRC,CRC Message Buffer" hexmask.long.word 0x0 0.--14. 1. "TXCRC,Transmitted CRC value" group.long 0x48++0x3 line.long 0x0 "RXFGMASK,RX FIFO Global Mask" hexmask.long 0x0 0.--31. 1. "FGM,RX FIFO Global Mask Bits" rgroup.long 0x4C++0x3 line.long 0x0 "RXFIR,RX FIFO Information" hexmask.long.word 0x0 0.--8. 1. "IDHIT,Identifier Acceptance Filter Hit Indicator" group.long 0x50++0x3 line.long 0x0 "CBT,CAN Bit Timing" bitfld.long 0x0 31. "BTF,Bit Timing Format Enable" "0: Disable,1: Enable" hexmask.long.word 0x0 21.--30. 1. "EPRESDIV,Extended Prescaler Division Factor" newline hexmask.long.byte 0x0 16.--20. 1. "ERJW,Extended Resync Jump Width" hexmask.long.byte 0x0 10.--15. 1. "EPROPSEG,Extended Propagation Segment" newline hexmask.long.byte 0x0 5.--9. 1. "EPSEG1,Extended Phase Segment 1" hexmask.long.byte 0x0 0.--4. 1. "EPSEG2,Extended Phase Segment 2" repeat 64. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x880)++0x3 line.long 0x0 "RXIMR[$1],Receive Individual Mask" hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits" repeat.end group.long 0xAE0++0xF line.long 0x0 "MECR,Memory Error Control" bitfld.long 0x0 31. "ECRWRDIS,Error Configuration Register Write Disable" "0: Enable,1: Disable" bitfld.long 0x0 19. "HANCEI_MSK,Host Access with Non-Correctable Errors Interrupt Mask" "0: Disable,1: Enable" newline bitfld.long 0x0 18. "FANCEI_MSK,FlexCAN Access with Non-Correctable Errors Interrupt Mask" "0: Disable,1: Enable" bitfld.long 0x0 16. "CEI_MSK,Correctable Errors Interrupt Mask" "0: Disable,1: Enable" newline bitfld.long 0x0 15. "HAERRIE,Host Access Error Injection Enable" "0: Disable,1: Enable" bitfld.long 0x0 14. "FAERRIE,FlexCAN Access Error Injection Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 13. "EXTERRIE,Extended Error Injection Enable" "0: Disable. Apply error injection only to the..,1: Enable. Apply error injection to the 64-bit word." bitfld.long 0x0 9. "RERRDIS,Error Report Disable" "0: Enable,1: Disable" newline bitfld.long 0x0 8. "ECCDIS,Error Correction Disable" "0: Enable,1: Disable" bitfld.long 0x0 7. "NCEFAFRZ,Non-Correctable Errors in FlexCAN Access Put Device in Freeze Mode" "0: Keep normal operation.,1: Put FlexCAN in Freeze mode (see section 'Freeze.." line.long 0x4 "ERRIAR,Error Injection Address" hexmask.long.word 0x4 2.--13. 1. "INJADDR_H,Error Injection Address High" rbitfld.long 0x4 0.--1. "INJADDR_L,Error Injection Address Low" "0,1,2,3" line.long 0x8 "ERRIDPR,Error Injection Data Pattern" hexmask.long 0x8 0.--31. 1. "DFLIP,Data Flip Pattern" line.long 0xC "ERRIPPR,Error Injection Parity Pattern" hexmask.long.byte 0xC 24.--28. 1. "PFLIP3,Parity Flip Pattern for Byte 3 (Most Significant)" hexmask.long.byte 0xC 16.--20. 1. "PFLIP2,Parity Flip Pattern for Byte 2" newline hexmask.long.byte 0xC 8.--12. 1. "PFLIP1,Parity Flip Pattern for Byte 1" hexmask.long.byte 0xC 0.--4. 1. "PFLIP0,Parity Flip Pattern for Byte 0 (Least Significant)" rgroup.long 0xAF0++0xB line.long 0x0 "RERRAR,Error Report Address" bitfld.long 0x0 24. "NCE,Non-Correctable Error" "0: Reporting a correctable error,1: Reporting a non-correctable error" bitfld.long 0x0 16.--18. "SAID,SAID" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--13. 1. "ERRADDR,Address Where Error Detected" line.long 0x4 "RERRDR,Error Report Data" hexmask.long 0x4 0.--31. 1. "RDATA,Raw Data Word Read from Memory with Error" line.long 0x8 "RERRSYNR,Error Report Syndrome" bitfld.long 0x8 31. "BE3,Byte Enabled for Byte 3 (Most Significant)" "0: Byte was not read.,1: Byte was read." hexmask.long.byte 0x8 24.--28. 1. "SYND3,Error Syndrome for Byte 3 (Most Significant)" newline bitfld.long 0x8 23. "BE2,Byte Enabled for Byte 2" "0: Byte was not read.,1: Byte was read." hexmask.long.byte 0x8 16.--20. 1. "SYND2,Error Syndrome for Byte 2" newline bitfld.long 0x8 15. "BE1,Byte Enabled for Byte 1" "0: Byte was not read.,1: Byte was read." hexmask.long.byte 0x8 8.--12. 1. "SYND1,Error Syndrome for Byte 1" newline bitfld.long 0x8 7. "BE0,Byte Enabled for Byte 0 (Least Significant)" "0: Byte was not read.,1: Byte was read." hexmask.long.byte 0x8 0.--4. 1. "SYND0,Error Syndrome for Byte 0 (Least Significant)" group.long 0xAFC++0x3 line.long 0x0 "ERRSR,Error Status" eventfld.long 0x0 19. "HANCEIF,Host Access with Noncorrectable Error Interrupt Flag" "0: No errors detected,1: Error detected" eventfld.long 0x0 18. "FANCEIF,FlexCAN Access with Non-Correctable Error Interrupt Flag" "0: No errors detected,1: Error detected" newline eventfld.long 0x0 16. "CEIF,Correctable Error Interrupt Flag" "0: No errors detected,1: Error detected" eventfld.long 0x0 3. "HANCEIOF,Host Access With Non-Correctable Error Interrupt Overrun Flag" "0: No errors detected,1: Error detected" newline eventfld.long 0x0 2. "FANCEIOF,FlexCAN Access with Non-Correctable Error Interrupt Overrun Flag" "0: No errors detected,1: Error detected" eventfld.long 0x0 0. "CEIOF,Correctable Error Interrupt Overrun Flag" "0: No errors detected,1: Error detected" group.long 0xBF0++0x17 line.long 0x0 "EPRS,Enhanced CAN Bit Timing Prescalers" hexmask.long.word 0x0 16.--25. 1. "EDPRESDIV,Extended Data Phase Prescaler Division Factor" hexmask.long.word 0x0 0.--9. 1. "ENPRESDIV,Extended Nominal Prescaler Division Factor" line.long 0x4 "ENCBT,Enhanced Nominal CAN Bit Timing" hexmask.long.byte 0x4 22.--28. 1. "NRJW,Nominal Resynchronization Jump Width" hexmask.long.byte 0x4 12.--18. 1. "NTSEG2,Nominal Time Segment 2" newline hexmask.long.byte 0x4 0.--7. 1. "NTSEG1,Nominal Time Segment 1" line.long 0x8 "EDCBT,Enhanced Data Phase CAN Bit Timing" hexmask.long.byte 0x8 22.--25. 1. "DRJW,Data Phase Resynchronization Jump Width" hexmask.long.byte 0x8 12.--15. 1. "DTSEG2,Data Phase Time Segment 2" newline hexmask.long.byte 0x8 0.--4. 1. "DTSEG1,Data Phase Segment 1" line.long 0xC "ETDC,Enhanced Transceiver Delay Compensation" bitfld.long 0xC 31. "ETDCEN,Transceiver Delay Compensation Enable" "0: Disable,1: Enable" bitfld.long 0xC 30. "TDMDIS,Transceiver Delay Measurement Disable" "0: Enable,1: Disable" newline hexmask.long.byte 0xC 16.--22. 1. "ETDCOFF,Enhanced Transceiver Delay Compensation Offset" eventfld.long 0xC 15. "ETDCFAIL,Transceiver Delay Compensation Fail" "0: In range,1: Out of range" newline hexmask.long.byte 0xC 0.--7. 1. "ETDCVAL,Enhanced Transceiver Delay Compensation Value" line.long 0x10 "FDCTRL,CAN FD Control" bitfld.long 0x10 31. "FDRATE,Bit Rate Switch Enable" "0: Disable,1: Enable" bitfld.long 0x10 19.--20. "MBDSR1,Message Buffer Data Size for Region 1" "0: 8 bytes,1: 16 bytes,2: 32 bytes,3: 64 bytes" newline bitfld.long 0x10 16.--17. "MBDSR0,Message Buffer Data Size for Region 0" "0: 8 bytes,1: 16 bytes,2: 32 bytes,3: 64 bytes" bitfld.long 0x10 15. "TDCEN,Transceiver Delay Compensation Enable" "0: Disable,1: Enable" newline eventfld.long 0x10 14. "TDCFAIL,Transceiver Delay Compensation Fail" "0: In range,1: Out of range" hexmask.long.byte 0x10 8.--12. 1. "TDCOFF,Transceiver Delay Compensation Offset" newline hexmask.long.byte 0x10 0.--5. 1. "TDCVAL,Transceiver Delay Compensation Value" line.long 0x14 "FDCBT,CAN FD Bit Timing" hexmask.long.word 0x14 20.--29. 1. "FPRESDIV,Fast Prescaler Division Factor" bitfld.long 0x14 16.--18. "FRJW,Fast Resync Jump Width" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 10.--14. 1. "FPROPSEG,Fast Propagation Segment" bitfld.long 0x14 5.--7. "FPSEG1,Fast Phase Segment 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 0.--2. "FPSEG2,Fast Phase Segment 2" "0,1,2,3,4,5,6,7" rgroup.long 0xC08++0x3 line.long 0x0 "FDCRC,CAN FD CRC" hexmask.long.byte 0x0 24.--30. 1. "FD_MBCRC,CRC Message Buffer Number for FD_TXCRC" hexmask.long.tbyte 0x0 0.--20. 1. "FD_TXCRC,Extended Transmitted CRC value" repeat 64. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xC30)++0x3 line.long 0x0 "HR_TIME_STAMP[$1],High-Resolution Timestamp" hexmask.long 0x0 0.--31. 1. "TS,High-Resolution Timestamp" repeat.end tree.end tree.end tree "FLEXIO (Flexible I/O)" base ad:0x40324000 rgroup.long 0x0++0x7 line.long 0x0 "VERID,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Specification Number" line.long 0x4 "PARAM,Parameter" hexmask.long.byte 0x4 24.--31. 1. "TRIGGER,Trigger Number" hexmask.long.byte 0x4 16.--23. 1. "PIN,Pin Number" newline hexmask.long.byte 0x4 8.--15. 1. "TIMER,Timer Number" hexmask.long.byte 0x4 0.--7. 1. "SHIFTER,Shifter Number" group.long 0x8++0x3 line.long 0x0 "CTRL,FLEXIO Control" bitfld.long 0x0 30. "DBGE,Debug Enable" "0: FLEXIO is disabled in Debug modes.,1: FLEXIO is enabled in Debug modes." bitfld.long 0x0 1. "SWRST,Software Reset" "0: Software reset is disabled,1: Software reset is enabled. All FLEXIO registers.." newline bitfld.long 0x0 0. "FLEXEN,FLEXIO Enable" "0: FLEXIO module is disabled.,1: FLEXIO module is enabled." rgroup.long 0xC++0x3 line.long 0x0 "PIN,Pin State" hexmask.long 0x0 0.--31. 1. "PDI,Pin Data Input" group.long 0x10++0xB line.long 0x0 "SHIFTSTAT,Shifter Status" hexmask.long.byte 0x0 0.--7. 1. "SSF,Shifter Status Flag" line.long 0x4 "SHIFTERR,Shifter Error" hexmask.long.byte 0x4 0.--7. 1. "SEF,Shifter Error Flags" line.long 0x8 "TIMSTAT,Timer Status" hexmask.long.byte 0x8 0.--7. 1. "TSF,Timer Status Flags" group.long 0x20++0xB line.long 0x0 "SHIFTSIEN,Shifter Status Interrupt Enable" hexmask.long.byte 0x0 0.--7. 1. "SSIE,Shifter Status Interrupt Enable" line.long 0x4 "SHIFTEIEN,Shifter Error Interrupt Enable" hexmask.long.byte 0x4 0.--7. 1. "SEIE,Shifter Error Interrupt Enable" line.long 0x8 "TIMIEN,Timer Interrupt Enable" hexmask.long.byte 0x8 0.--7. 1. "TEIE,Timer Status Interrupt Enable" group.long 0x30++0x3 line.long 0x0 "SHIFTSDEN,Shifter Status DMA Enable" hexmask.long.byte 0x0 0.--7. 1. "SSDE,Shifter Status DMA Enable" group.long 0x38++0x3 line.long 0x0 "TIMERSDEN,Timer Status DMA Enable" hexmask.long.byte 0x0 0.--7. 1. "TSDE,Timer Status DMA Enable" group.long 0x40++0x3 line.long 0x0 "SHIFTSTATE,Shifter State" bitfld.long 0x0 0.--2. "STATE,Current State Pointer" "0,1,2,3,4,5,6,7" group.long 0x48++0x2F line.long 0x0 "TRGSTAT,Trigger Status" hexmask.long.byte 0x0 0.--3. 1. "ETSF,External Trigger Status Flags" line.long 0x4 "TRIGIEN,External Trigger Interrupt Enable" hexmask.long.byte 0x4 0.--3. 1. "TRIE,External Trigger Interrupt Enable" line.long 0x8 "PINSTAT,Pin Status" hexmask.long 0x8 0.--31. 1. "PSF,Pin Status Flags" line.long 0xC "PINIEN,Pin Interrupt Enable" hexmask.long 0xC 0.--31. 1. "PSIE,Pin Status Interrupt Enable" line.long 0x10 "PINREN,Pin Rising Edge Enable" hexmask.long 0x10 0.--31. 1. "PRE,Pin Rising Edge" line.long 0x14 "PINFEN,Pin Falling Edge Enable" hexmask.long 0x14 0.--31. 1. "PFE,Pin Falling Edge" line.long 0x18 "PINOUTD,Pin Output Data" hexmask.long 0x18 0.--31. 1. "OUTD,Output Data" line.long 0x1C "PINOUTE,Pin Output Enable" hexmask.long 0x1C 0.--31. 1. "OUTE,Output Enable" line.long 0x20 "PINOUTDIS,Pin Output Disable" hexmask.long 0x20 0.--31. 1. "OUTDIS,Output Disable" line.long 0x24 "PINOUTCLR,Pin Output Clear" hexmask.long 0x24 0.--31. 1. "OUTCLR,Output Clear" line.long 0x28 "PINOUTSET,Pin Output Set" hexmask.long 0x28 0.--31. 1. "OUTSET,Output Set" line.long 0x2C "PINOUTTOG,Pin Output Toggle" hexmask.long 0x2C 0.--31. 1. "OUTTOG,Output Toggle" repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "SHIFTCTL[$1],Shifter Control N" bitfld.long 0x0 24.--26. "TIMSEL,Timer Select" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. "TIMPOL,Timer Polarity" "0: Shift on posedge of shift clock,1: Shift on negedge of shift clock" newline bitfld.long 0x0 16.--17. "PINCFG,Shifter Pin Configuration" "0: Shifter pin output disabled,1: Shifter pin open-drain or bidirectional output..,2: Shifter pin bidirectional output data,3: Shifter pin output" hexmask.long.byte 0x0 8.--12. 1. "PINSEL,Shifter Pin Select" newline bitfld.long 0x0 7. "PINPOL,Shifter Pin Polarity" "0: Pin is active high,1: Pin is active low" bitfld.long 0x0 0.--2. "SMOD,Shifter Mode" "0: Disabled.,1: Receive mode. Captures the current shifter..,2: Transmit mode. Load SHIFTBUF contents into the..,?,4: Match Store mode. Shifter data is compared to..,5: Match Continuous mode. Shifter data is..,6: State mode. SHIFTBUF contents are used for..,7: Logic mode. SHIFTBUF contents are used for.." repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x100)++0x3 line.long 0x0 "SHIFTCFG[$1],Shifter Configuration N" hexmask.long.byte 0x0 16.--20. 1. "PWIDTH,Parallel Width" bitfld.long 0x0 12. "SSIZE,Shifter Size" "0: Shift register is 32-bit.,1: Shift register is 24-bit." newline bitfld.long 0x0 9. "LATST,Late Store" "0: Shift register stores the pre-shift register..,1: Shift register stores the post-shift register.." bitfld.long 0x0 8. "INSRC,Input Source" "0: Pin,1: Shifter N+1 Output" newline bitfld.long 0x0 4.--5. "SSTOP,Shifter Stop bit" "0: Stop bit disabled for transmitter/receiver/match..,1: Stop bit disabled for transmitter/receiver/match..,2: Transmitter outputs stop bit value 0 on store.,3: Transmitter outputs stop bit value 1 on store." bitfld.long 0x0 0.--1. "SSTART,Shifter Start Bit" "0: Start bit disabled for..,1: Start bit disabled for..,2: Transmitter outputs start bit value 0 before..,3: Transmitter outputs start bit value 1 before.." repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x200)++0x3 line.long 0x0 "SHIFTBUF[$1],Shifter Buffer N" hexmask.long 0x0 0.--31. 1. "SHIFTBUF,Shift Buffer" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x280)++0x3 line.long 0x0 "SHIFTBUFBIS[$1],Shifter Buffer N Bit Swapped" hexmask.long 0x0 0.--31. 1. "SHIFTBUFBIS,Shift Buffer" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x300)++0x3 line.long 0x0 "SHIFTBUFBYS[$1],Shifter Buffer N Byte Swapped" hexmask.long 0x0 0.--31. 1. "SHIFTBUFBYS,Shift Buffer" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x380)++0x3 line.long 0x0 "SHIFTBUFBBS[$1],Shifter Buffer N Bit Byte Swapped" hexmask.long 0x0 0.--31. 1. "SHIFTBUFBBS,Shift Buffer" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x400)++0x3 line.long 0x0 "TIMCTL[$1],Timer Control N" hexmask.long.byte 0x0 24.--29. 1. "TRGSEL,Trigger Select" bitfld.long 0x0 23. "TRGPOL,Trigger Polarity" "0: Trigger active high,1: Trigger active low" newline bitfld.long 0x0 22. "TRGSRC,Trigger Source" "0: External trigger selected,1: Internal trigger selected" bitfld.long 0x0 16.--17. "PINCFG,Timer Pin Configuration" "0: Timer pin output disabled,1: Timer pin open-drain or bidirectional output..,2: Timer pin bidirectional output data,3: Timer pin output" newline hexmask.long.byte 0x0 8.--12. 1. "PINSEL,Timer Pin Select" bitfld.long 0x0 7. "PINPOL,Timer Pin Polarity" "0: Pin is active high,1: Pin is active low" newline bitfld.long 0x0 6. "PININS,Timer Pin Input Select" "0: Timer pin input and output are selected by PINSEL.,1: Timer pin input is selected by PINSEL+1. Timer.." bitfld.long 0x0 5. "ONETIM,Timer One Time Operation" "0: The timer enable event is generated as normal.,1: The timer enable event is blocked unless timer.." newline bitfld.long 0x0 0.--2. "TIMOD,Timer Mode" "0: Timer disabled.,1: Dual 8-bit counters baud mode.,2: Dual 8-bit counters PWM high mode.,3: Single 16-bit counter mode.,4: Single 16-bit counter disable mode.,5: Dual 8-bit counters word mode.,6: Dual 8-bit counters PWM low mode.,7: Single 16-bit input capture mode." repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x480)++0x3 line.long 0x0 "TIMCFG[$1],Timer Configuration N" bitfld.long 0x0 24.--25. "TIMOUT,Timer Output" "0: Timer output is logic one when enabled and is..,1: Timer output is logic zero when enabled and is..,2: Timer output is logic one when enabled and on..,3: Timer output is logic zero when enabled and on.." bitfld.long 0x0 20.--22. "TIMDEC,Timer Decrement" "0: Decrement counter on FLEXIO clock. Shift clock..,1: Decrement counter on trigger input (both edges).,2: Decrement counter on pin input (both edges).,3: Decrement counter on trigger input (both edges).,4: Decrement counter on FLEXIO clock divided by 16.,5: Decrement counter on FLEXIO clock divided by..,6: Decrement counter on pin input (rising edge).,7: Decrement counter on trigger input (rising.." newline bitfld.long 0x0 16.--18. "TIMRST,Timer Reset" "0: Timer never reset,1: Timer reset on timer output high.,2: Timer reset on timer pin equal to timer output,3: Timer reset on timer trigger equal to timer output,4: Timer reset on timer pin rising edge,?,6: Timer reset on trigger rising edge,7: Timer reset on trigger rising or falling edge" bitfld.long 0x0 12.--14. "TIMDIS,Timer Disable" "0: Timer never disabled,1: Timer disabled on Timer N-1 disable,2: Timer disabled on timer compare (upper 8-bits..,3: Timer disabled on timer compare (upper 8-bits..,4: Timer disabled on pin rising or falling edge,5: Timer disabled on pin rising or falling edge..,6: Timer disabled on trigger falling edge,?" newline bitfld.long 0x0 8.--10. "TIMENA,Timer Enable" "0: Timer always enabled,1: Timer enabled on Timer N-1 enable,2: Timer enabled on Trigger high,3: Timer enabled on Trigger high and Pin high,4: Timer enabled on Pin rising edge,5: Timer enabled on Pin rising edge and Trigger high,6: Timer enabled on Trigger rising edge,7: Timer enabled on Trigger rising or falling edge" bitfld.long 0x0 4.--5. "TSTOP,Timer Stop Bit" "0: Stop bit disabled,1: Stop bit is enabled on timer compare,2: Stop bit is enabled on timer disable,3: Stop bit is enabled on timer compare and timer.." newline bitfld.long 0x0 1. "TSTART,Timer Start Bit" "0: Start bit disabled,1: Start bit enabled" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x500)++0x3 line.long 0x0 "TIMCMP[$1],Timer Compare N" hexmask.long.word 0x0 0.--15. 1. "CMP,Timer Compare Value" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x680)++0x3 line.long 0x0 "SHIFTBUFNBS[$1],Shifter Buffer N Nibble Byte Swapped" hexmask.long 0x0 0.--31. 1. "SHIFTBUFNBS,Shift Buffer" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x700)++0x3 line.long 0x0 "SHIFTBUFHWS[$1],Shifter Buffer N Halfword Swapped" hexmask.long 0x0 0.--31. 1. "SHIFTBUFHWS,Shift Buffer" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x780)++0x3 line.long 0x0 "SHIFTBUFNIS[$1],Shifter Buffer N Nibble Swapped" hexmask.long 0x0 0.--31. 1. "SHIFTBUFNIS,Shift Buffer" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x800)++0x3 line.long 0x0 "SHIFTBUFOES[$1],Shifter Buffer N Odd Even Swapped" hexmask.long 0x0 0.--31. 1. "SHIFTBUFOES,Shift Buffer" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x880)++0x3 line.long 0x0 "SHIFTBUFEOS[$1],Shifter Buffer N Even Odd Swapped" hexmask.long 0x0 0.--31. 1. "SHIFTBUFEOS,Shift Buffer" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x900)++0x3 line.long 0x0 "SHIFTBUFHBS[$1],Shifter Buffer N Halfword Byte Swapped" hexmask.long 0x0 0.--31. 1. "SHIFTBUFHBS,Shift Buffer" repeat.end tree.end tree "FXOSC (Fast External Crystal Oscillator)" base ad:0x402D4000 group.long 0x0++0x3 line.long 0x0 "CTRL,FXOSC Control Register" bitfld.long 0x0 31. "OSC_BYP,Oscillator bypass" "0: Internal oscillator not bypassed,1: Internal oscillator bypassed" bitfld.long 0x0 24. "COMP_EN,Comparator enable" "0: Comparator disabled,1: Comparator enabled" hexmask.long.byte 0x0 16.--23. 1. "EOCV,End of count value" newline hexmask.long.byte 0x0 4.--7. 1. "GM_SEL,Crystal overdrive protection" bitfld.long 0x0 2. "ALC_D,Automatic level controller enable" "0: Enables automatic level controller,1: Disables automatic level controller" bitfld.long 0x0 0. "OSCON,Crystal oscillator power-down control" "0: Disables FXOSC,1: Enables FXOSC" rgroup.long 0x4++0x3 line.long 0x0 "STAT,Oscillator Status Register" bitfld.long 0x0 31. "OSC_STAT,Crystal oscillator status" "0: Crystal oscillator is off or on but not stable.,1: Crystal oscillator is on and providing a stable.." tree.end tree "GMAC" base ad:0x0 tree "GMAC_0" base ad:0x40484000 group.long 0x0++0x2F line.long 0x0 "MAC_Configuration,The MAC Configuration Register establishes the operating mode of the MAC." bitfld.long 0x0 31. "ARPEN,ARP Offload Enable When this bit is set the MAC can recognize an incoming ARP request packet and schedules the ARP packet for transmission" "0: ARP Offload is disabled,1: ARP Offload is enabled" newline bitfld.long 0x0 28.--30. "SARC,Source Address Insertion or Replacement Control This field controls the source address insertion or replacement for all transmitted packets" "0: mti_sa_ctrl_i and ati_sa_ctrl_i input signals..,?,2: Contents of MAC Addr-0 inserted in SA field,3: Contents of MAC Addr-0 replaces SA field,?,?,6: Contents of MAC Addr-1 inserted in SA field,7: Contents of MAC Addr-1 replaces SA field" newline bitfld.long 0x0 27. "IPC,Checksum Offload When set this bit enables the IPv4 header checksum checking and IPv4 or IPv6 TCP UDP or ICMP payload checksum checking" "0: IP header/payload checksum checking is disabled,1: IP header/payload checksum checking is enabled" newline bitfld.long 0x0 24.--26. "IPG,Inter-Packet Gap These bits control the minimum IPG between packets during transmission" "0: 96 bit times IPG,1: 88 bit times IPG,2: 80 bit times IPG,3: 72 bit times IPG,4: 64 bit times IPG,5: 56 bit times IPG,6: 48 bit times IPG,7: 40 bit times IPG" newline bitfld.long 0x0 23. "GPSLCE,Giant Packet Size Limit Control Enable When this bit is set the MAC considers the value in GPSL field in MAC_Ext_Configuration register to declare a received packet as Giant packet" "0: Giant Packet Size Limit Control is disabled,1: Giant Packet Size Limit Control is enabled" newline bitfld.long 0x0 22. "S2KP,IEEE 802" "0: Support upto 2K packet is disabled,1: Support upto 2K packet is Enabled" newline bitfld.long 0x0 21. "CST,CRC stripping for Type packets When this bit is set the last four bytes (FCS) of all packets of Ether type (type field greater than 1 536) are stripped and dropped before forwarding the packet to the application" "0: CRC stripping for Type packets is disabled,1: CRC stripping for Type packets is enabled" newline bitfld.long 0x0 20. "ACS,Automatic Pad or CRC Stripping When this bit is set the MAC strips the Pad or FCS field on the incoming packets only if the value of the length field is less than 1 536 bytes" "0: Automatic Pad or CRC Stripping is disabled,1: Automatic Pad or CRC Stripping is enabled" newline bitfld.long 0x0 19. "WD,Watchdog Disable When this bit is set the MAC disables the watchdog timer on the receiver" "0: Watchdog is enabled,1: Watchdog is disabled" newline bitfld.long 0x0 18. "BE,Packet Burst Enable When this bit is set the MAC allows packet bursting during transmission in the GMII half-duplex mode" "0: Packet Burst is disabled,1: Packet Burst is enabled" newline bitfld.long 0x0 17. "JD,Jabber Disable When this bit is set the MAC disables the jabber timer on the transmitter" "0: Jabber is enabled,1: Jabber is disabled" newline bitfld.long 0x0 16. "JE,Jumbo Packet Enable When this bit is set the MAC allows jumbo packets of 9 018 bytes (9 022 bytes for VLAN tagged packets) without reporting a giant packet error in the Rx packet status" "0: Jumbo packet is disabled,1: Jumbo packet is enabled" newline bitfld.long 0x0 15. "PS,Port Select This bit selects the Ethernet line speed" "0: For 1000 or 2500 Mbps operations,1: For 10 or 100 Mbps operations" newline bitfld.long 0x0 14. "FES,Speed This bit selects the speed mode. The mac_speed_o[0] signal reflects the value of this bit." "0: 10 Mbps when PS bit is 1 and 1 Gbps when PS bit..,1: 100 Mbps when PS bit is 1 and 2.5 Gbps when PS.." newline bitfld.long 0x0 13. "DM,Duplex Mode When this bit is set the MAC operates in the full-duplex mode in which it can transmit and receive simultaneously" "0: Half-duplex mode,1: Full-duplex mode" newline bitfld.long 0x0 12. "LM,Loopback Mode When this bit is set the MAC operates in the loopback mode at GMII or MII" "0: Loopback is disabled,1: Loopback is enabled" newline bitfld.long 0x0 11. "ECRSFD,Enable Carrier Sense Before Transmission in Full-Duplex Mode When this bit is set the MAC transmitter checks the CRS signal before packet transmission in the full-duplex mode" "0: ECRSFD is disabled,1: ECRSFD is enabled" newline bitfld.long 0x0 10. "DO,Disable Receive Own When this bit is set the MAC disables the reception of packets when the gmii_txen_o is asserted in the half-duplex mode" "0: Enable Receive Own,1: Disable Receive Own" newline bitfld.long 0x0 9. "DCRS,Disable Carrier Sense During Transmission When this bit is set the MAC transmitter ignores the (G)MII CRS signal during packet transmission in the half-duplex mode" "0: Enable Carrier Sense During Transmission,1: Disable Carrier Sense During Transmission" newline bitfld.long 0x0 8. "DR,Disable Retry When this bit is set the MAC attempts only one transmission" "0: Enable Retry,1: Disable Retry" newline rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1" newline bitfld.long 0x0 5.--6. "BL,Back-Off Limit The back-off limit determines the random integer number (r) of slot time delays (4 096 bit times for 1000/2500 Mbps; 512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after.." "0: k = min(n 10),1: k = min(n 8),2: k = min(n 4),3: k = min(n 1)" newline bitfld.long 0x0 4. "DC,Deferral Check When this bit is set the deferral check function is enabled in the MAC" "0: Deferral check function is disabled,1: Deferral check function is enabled" newline bitfld.long 0x0 2.--3. "PRELEN,Preamble Length for Transmit packets These bits control the number of preamble bytes that are added to the beginning of every Tx packet" "0: 7 bytes of preamble,1: 5 bytes of preamble,2: 3 bytes of preamble,?" newline bitfld.long 0x0 1. "TE,Transmitter Enable When this bit is set the Tx state machine of the MAC is enabled for transmission on the GMII or MII interface" "0: Transmitter is disabled,1: Transmitter is enabled" newline bitfld.long 0x0 0. "RE,Receiver Enable When this bit is set the Rx state machine of the MAC is enabled for receiving packets from the GMII or MII interface" "0: Receiver is disabled,1: Receiver is enabled" line.long 0x4 "MAC_Ext_Configuration,The MAC Extended Configuration Register establishes the operating mode of the MAC." rbitfld.long 0x4 31. "Reserved_FHE,Reserved." "0,1" newline bitfld.long 0x4 30. "APDIM,ARP Packet Drop if IP Address Mismatch When this bit is set Packet for which Target Protocol Address does not match IPv4 address is dropped in the MTL layer" "0: mux select to drop the arp packet if target..,1: mux select to drop the arp packet if target.." newline hexmask.long.byte 0x4 25.--29. 1. "EIPG,Extended Inter-Packet Gap The value in this field is applicable when the EIPGEN bit is set" newline bitfld.long 0x4 24. "EIPGEN,Extended Inter-Packet Gap Enable When this bit is set the MAC interprets EIPG field and IPG field in MAC_Configuration register together as minimum IPG greater than 96 bit times in steps of 8 bit times" "0: Extended Inter-Packet Gap is disabled,1: Extended Inter-Packet Gap is enabled" newline rbitfld.long 0x4 23. "Reserved_23,Reserved." "0,1" newline bitfld.long 0x4 20.--22. "HDSMS,Maximum Size for Splitting the Header Data These bits indicate the maximum header size allowed for splitting the header data in the received packet" "0: Maximum Size for Splitting the Header Data is 64..,1: Maximum Size for Splitting the Header Data is..,2: Maximum Size for Splitting the Header Data is..,3: Maximum Size for Splitting the Header Data is..,4: Maximum Size for Splitting the Header Data is..,?,?,?" newline bitfld.long 0x4 19. "PDC,Packet Duplication Control When this bit is set the received packet with Multicast/Broadcast Destination address is routed to multiple Receive DMA Channels" "0: Packet Duplication Control is disabled,1: Packet Duplication Control is enabled" newline bitfld.long 0x4 18. "USP,Unicast Slow Protocol Packet Detect When this bit is set the MAC detects the Slow Protocol packets with unicast address of the station specified in the MAC_Address0_High and MAC_Address0_Low registers" "0: Unicast Slow Protocol Packet Detection is disabled,1: Unicast Slow Protocol Packet Detection is enabled" newline bitfld.long 0x4 17. "SPEN,Slow Protocol Detection Enable When this bit is set MAC processes the Slow Protocol packets (Ether Type 0x8809) and provides the Slow Protocol Sub-Type and Code fields in Rx status" "0: Slow Protocol Detection is disabled,1: Slow Protocol Detection is enabled" newline bitfld.long 0x4 16. "DCRCC,Disable CRC Checking for Received Packets When this bit is set the MAC receiver does not check the CRC field in the received packets" "0: CRC Checking is enabled,1: CRC Checking is disabled" newline rbitfld.long 0x4 14.--15. "Reserved_15_14,Reserved." "0,1,2,3" newline hexmask.long.word 0x4 0.--13. 1. "GPSL,Giant Packet Size Limit If the received packet size is greater than the value programmed in this field in units of bytes the MAC declares the received packet as Giant packet" line.long 0x8 "MAC_Packet_Filter,The MAC Packet Filter register contains the filter controls for receiving packets. Some of the controls from this register go to the address check block of the MAC which performs the first level of address filtering. The second level of.." bitfld.long 0x8 31. "RA,Receive All When this bit is set the MAC Receiver module passes all received packets to the application irrespective of whether they pass the address filter or not" "0: Receive All is disabled,1: Receive All is enabled" newline hexmask.long.word 0x8 22.--30. 1. "Reserved_30_22,Reserved." newline bitfld.long 0x8 21. "DNTU,Drop Non-TCP/UDP over IP Packets When this bit is set the MAC drops the non-TCP or UDP over IP packets" "0: Forward Non-TCP/UDP over IP Packets,1: Drop Non-TCP/UDP over IP Packets" newline bitfld.long 0x8 20. "IPFE,Layer 3 and Layer 4 Filter Enable When this bit is set the MAC drops packets that do not match the enabled Layer 3 and Layer 4 filters" "0: Layer 3 and Layer 4 Filters are disabled,1: Layer 3 and Layer 4 Filters are enabled" newline rbitfld.long 0x8 17.--19. "Reserved_19_17,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 16. "VTFE,VLAN Tag Filter Enable When this bit is set the MAC drops the VLAN tagged packets that do not match the VLAN Tag" "0: VLAN Tag Filter is disabled,1: VLAN Tag Filter is enabled" newline hexmask.long.byte 0x8 11.--15. 1. "Reserved_15_11,Reserved." newline bitfld.long 0x8 10. "HPF,Hash or Perfect Filter When this bit is set the address filter passes a packet if it matches either the perfect filtering or hash filtering as set by the HMC or HUC bit" "0: Hash or Perfect Filter is disabled,1: Hash or Perfect Filter is enabled" newline bitfld.long 0x8 9. "SAF,Source Address Filter Enable When this bit is set the MAC compares the SA field of the received packets with the values programmed in the enabled SA registers" "0: SA Filtering is disabled,1: SA Filtering is enabled" newline bitfld.long 0x8 8. "SAIF,SA Inverse Filtering When this bit is set the Address Check block operates in the inverse filtering mode for SA address comparison" "0: SA Inverse Filtering is disabled,1: SA Inverse Filtering is enabled" newline bitfld.long 0x8 6.--7. "PCF,Pass Control Packets These bits control the forwarding of all control packets (including unicast and multicast Pause packets)" "0: MAC filters all control packets from reaching..,1: MAC forwards all control packets except Pause..,2: MAC forwards all control packets to the..,3: MAC forwards the control packets that pass the.." newline bitfld.long 0x8 5. "DBF,Disable Broadcast Packets When this bit is set the AFM module blocks all the incoming broadcast packets" "0: Enable Broadcast Packets,1: Disable Broadcast Packets" newline bitfld.long 0x8 4. "PM,Pass All Multicast When this bit is set it indicates that all the received packets with a multicast destination address (first bit in the destination address field is '1') are passed" "0: Pass All Multicast is disabled,1: Pass All Multicast is enabled" newline bitfld.long 0x8 3. "DAIF,DA Inverse Filtering When this bit is set the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast packets" "0: DA Inverse Filtering is disabled,1: DA Inverse Filtering is enabled" newline bitfld.long 0x8 2. "HMC,Hash Multicast When this bit is set the MAC performs the destination address filtering of received multicast packets according to the hash table" "0: Hash Multicast is disabled,1: Hash Multicast is enabled" newline bitfld.long 0x8 1. "HUC,Hash Unicast When this bit is set the MAC performs the destination address filtering of unicast packets according to the hash table" "0: Hash Unicast is disabled,1: Hash Unicast is enabled" newline bitfld.long 0x8 0. "PR,Promiscuous Mode When this bit is set the Address Filtering module passes all incoming packets irrespective of the destination or source address" "0: Promiscuous Mode is disabled,1: Promiscuous Mode is enabled" line.long 0xC "MAC_Watchdog_Timeout,The Watchdog Timeout register controls the watchdog timeout for received packets." hexmask.long.tbyte 0xC 9.--31. 1. "Reserved_31_9,Reserved." newline bitfld.long 0xC 8. "PWE,Programmable Watchdog Enable When this bit is set and the WD bit of the MAC_Configuration register is reset the WTO field is used as watchdog timeout for a received packet" "0: Programmable Watchdog is disabled,1: Programmable Watchdog is enabled" newline hexmask.long.byte 0xC 4.--7. 1. "Reserved_7_4,Reserved." newline hexmask.long.byte 0xC 0.--3. 1. "WTO,Watchdog Timeout When the PWE bit is set and the WD bit of the MAC_Configuration register is reset this field is used as watchdog timeout for a received packet" line.long 0x10 "MAC_Hash_Table_Reg0,The Hash Table Register 0 contains the first 32 bits of the hash table. when the width of the hash table is 128 or 256 bits. You can specify the width of the hash table by using the Hash Table Size option in coreConsultant. In this.." hexmask.long 0x10 0.--31. 1. "HT31T0,MAC Hash Table First 32 Bits This field contains the first 32 Bits [31:0] of the Hash table." line.long 0x14 "MAC_Hash_Table_Reg1,The Hash Table Register 1 contains the second 32 bits of the hash table. You can specify the width of the hash table by using the Hash Table Size option in coreConsultant. The Hash table is used for group address filtering. For hash.." hexmask.long 0x14 0.--31. 1. "HT63T32,MAC Hash Table Second 32 Bits This field contains the second 32 Bits [63:32] of the Hash table." line.long 0x18 "MAC_Hash_Table_Reg2,The Hash Table Register 2 contains the third 32 bits of the hash table. You can specify the width of the hash table by using the Hash Table Size option in coreConsultant. The Hash table is used for group address filtering. For hash.." hexmask.long 0x18 0.--31. 1. "HT95T64,MAC Hash Table Third 32 Bits This field contains the third 32 Bits [95:64] of the Hash table." line.long 0x1C "MAC_Hash_Table_Reg3,The Hash Table Register 3 contains the fourth 32 bits of the hash table. You can specify the width of the hash table by using the Hash Table Size option in coreConsultant. The Hash table is used for group address filtering. For hash.." hexmask.long 0x1C 0.--31. 1. "HT127T96,MAC Hash Table Fourth 32 Bits This field contains the fourth 32 Bits [127:96] of the Hash table." line.long 0x20 "MAC_Hash_Table_Reg4,The Hash Table Register 4 contains the fifth 32 bits of the hash table. You can specify the width of the hash table by using the Hash Table Size option in coreConsultant. The Hash table is used for group address filtering. For hash.." hexmask.long 0x20 0.--31. 1. "HT159T128,MAC Hash Table Fifth 32 Bits This field contains the fifth 32 Bits [159:128] of the Hash table." line.long 0x24 "MAC_Hash_Table_Reg5,The Hash Table Register 5 contains the sixth 32 bits of the hash table. You can specify the width of the hash table by using the Hash Table Size option in coreConsultant. The Hash table is used for group address filtering. For hash.." hexmask.long 0x24 0.--31. 1. "HT191T160,MAC Hash Table Sixth 32 Bits This field contains the sixth 32 Bits [191:160] of the Hash table." line.long 0x28 "MAC_Hash_Table_Reg6,The Hash Table Register 6 contains the seventh 32 bits of the hash table. You can specify the width of the hash table by using the Hash Table Size option in coreConsultant. The Hash table is used for group address filtering. For hash.." hexmask.long 0x28 0.--31. 1. "HT223T192,MAC Hash Table Seventh 32 Bits This field contains the seventh 32 Bits [223:192] of the Hash table." line.long 0x2C "MAC_Hash_Table_Reg7,The Hash Table Register 7 contains the eighth 32 bits of the hash table. You can specify the width of the hash table by using the Hash Table Size option in coreConsultant. The Hash table is used for group address filtering. For hash.." hexmask.long 0x2C 0.--31. 1. "HT255T224,MAC Hash Table Eighth 32 Bits This field contains the eighth 32 Bits [255:224] of the Hash table." group.long 0x50++0x7 line.long 0x0 "MAC_VLAN_Tag_Ctrl,This register is the redefined format of the MAC VLAN Tag Register. It is used for indirect addressing. It contains the address offset. command type and Busy Bit for CSR access of the Per VLAN Tag registers." bitfld.long 0x0 31. "EIVLRXS,Enable Inner VLAN Tag in Rx Status When this bit is set the MAC provides the inner VLAN Tag in the Rx status" "0: Inner VLAN Tag in Rx status is disabled,1: Inner VLAN Tag in Rx status is enabled" newline rbitfld.long 0x0 30. "Reserved_30,Reserved." "0,1" newline bitfld.long 0x0 28.--29. "EIVLS,Enable Inner VLAN Tag Stripping on Receive This field indicates the stripping operation on inner VLAN Tag in received packet" "0: Do not strip,1: Strip if VLAN filter passes,2: Strip if VLAN filter fails,3: Always strip" newline bitfld.long 0x0 27. "ERIVLT,Enable Inner VLAN Tag Comparison When this bit VTHM bit and the EDVLP field are set the MAC receiver enables VLAN Hash filtering operation on the inner VLAN Tag (if present)" "0: Inner VLAN tag is disabled,1: Inner VLAN tag is enabled" newline bitfld.long 0x0 26. "EDVLP,Enable Double VLAN Processing When this bit is set the MAC enables processing of up to two VLAN Tags on Tx and Rx (if present)" "0: Double VLAN Processing is disabled,1: Double VLAN Processing is enabled" newline bitfld.long 0x0 25. "VTHM,VLAN Tag Hash Table Match Enable When this bit is set the most significant four bits of CRC of VLAN Tag are used to index the content of the MAC_VLAN_Hash_Table register" "0: VLAN Tag Hash Table Match is disabled,1: VLAN Tag Hash Table Match is enabled" newline bitfld.long 0x0 24. "EVLRXS,Enable VLAN Tag in Rx status When this bit is set MAC provides the outer VLAN Tag in the Rx status" "0: VLAN Tag in Rx status is disabled,1: VLAN Tag in Rx status is enabled" newline rbitfld.long 0x0 23. "Reserved_23,Reserved." "0,1" newline bitfld.long 0x0 21.--22. "EVLS,Enable VLAN Tag Stripping on Receive This field indicates the stripping operation on the outer VLAN Tag in received packet" "0: Do not strip,1: Strip if VLAN filter passes,2: Strip if VLAN filter fails,3: Always strip" newline bitfld.long 0x0 20. "DOVLTC,Disable VLAN Type Check for VLAN Hash Filtering When this bit is set the MAC VLAN Hash Filter does not check whether the VLAN Tag specified by the ERIVLT bit is of type S-VLAN or C-VLAN" "0: VLAN Type Check is enabled,1: VLAN Type Check is disabled" newline bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match for VLAN Hash Filtering When this bit is set the MAC receiver enables VLAN Hash filtering or matching for S-VLAN (Type = 0x88A8) packets" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "ESVL,Enable S-VLAN When this bit is set the MAC transmitter and receiver consider the S-VLAN packets (Type = 0x88A8) as valid VLAN tagged packets" "0: S-VLAN is disabled,1: S-VLAN is enabled" newline bitfld.long 0x0 17. "VTIM,VLAN Tag Inverse Match Enable When this bit is set this bit enables the VLAN Tag inverse matching" "0: VLAN Tag Inverse Match is disabled,1: VLAN Tag Inverse Match is enabled" newline bitfld.long 0x0 16. "ETV,Enable 12-Bit VLAN Tag Comparison for VLAN Hash Filtering When this bit is set a 12-bit VLAN identifier is used for VLAN Hash filtering instead of the complete 16-bit VLAN tag" "0: 12-Bit VLAN Tag Comparison is disabled,1: 12-Bit VLAN Tag Comparison is enabled" newline hexmask.long.word 0x0 7.--15. 1. "Reserved_15_y,Reserved." newline hexmask.long.byte 0x0 2.--6. 1. "OFS,Offset This field holds the address offset of the MAC VLAN Tag Filter Register which the application is trying to access" newline bitfld.long 0x0 1. "CT,Command Type This bit indicates if the current register access is a read or a write" "0: Write operation,1: Read operation" newline bitfld.long 0x0 0. "OB,Operation Busy This bit is set along with a read or write command for initiating the indirect access to per VLAN Tag Filter register" "0: Operation Busy is disabled,1: Operation Busy is enabled" line.long 0x4 "MAC_VLAN_Tag_Data,This register holds the read/write data for Indirect Access of the Per VLAN Tag registers. During the read access. this field contains valid read data only after the OB bit is reset. During the write access. this field should be valid.." hexmask.long.byte 0x4 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x4 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x4 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x4 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x4 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x4 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x4 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x4 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x4 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter0,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter1,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter10,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter11,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter12,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter13,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter14,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter15,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter16,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter17,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter18,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter19,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter2,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter20,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter21,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter22,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter23,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter24,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter25,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter26,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter27,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter28,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter29,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter3,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter30,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter31,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter4,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter5,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter6,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter7,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter8,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x7 line.long 0x0 "MAC_VLAN_Tag_Filter9,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" line.long 0x4 "MAC_VLAN_Hash_Table,When VTHM bit of the MAC_VLAN_Tag register is set. the 16-bit VLAN Hash Table register is used for group address filtering based on the VLAN tag. For hash filtering. the content of the 16-bit VLAN tag or 12-bit VLAN ID (based on the.." hexmask.long.word 0x4 16.--31. 1. "Reserved_31_16,Reserved." newline hexmask.long.word 0x4 0.--15. 1. "VLHT,VLAN Hash Table This field contains the 16-bit VLAN Hash Table." group.long 0x60++0x3 line.long 0x0 "MAC_VLAN_Incl,The VLAN Tag Inclusion or Replacement register contains the VLAN tag for insertion or replacement in the Transmit packets. It also contains the VLAN tag insertion controls." rbitfld.long 0x0 31. "BUSY,Busy This bit indicates the status of the read/write operation of indirect access to the queue/channel specific VLAN inclusion register" "0: Busy status not detected,1: Busy status detected" newline bitfld.long 0x0 30. "RDWR,Read write control This bit controls the read or write operation for indirectly accessing the queue/channel specific VLAN Inclusion register" "0: Read operation of indirect access,1: Write operation of indirect access" newline hexmask.long.byte 0x0 26.--29. 1. "Reserved_29_y,Reserved." newline bitfld.long 0x0 24.--25. "ADDR,Address This field selects one of the queue/channel specific VLAN Inclusion register for read/write access" "0,1,2,3" newline rbitfld.long 0x0 22.--23. "Reserved_23_22,Reserved." "0,1,2,3" newline bitfld.long 0x0 21. "CBTI,Channel based tag insertion When this bit is set outer VLAN tag is inserted for every packets transmitted by the MAC" "0: Channel based tag insertion is disabled,1: Channel based tag insertion is enabled" newline bitfld.long 0x0 20. "VLTI,VLAN Tag Input When this bit is set it indicates that the VLAN tag to be inserted or replaced in Tx packet should be taken from: - The Tx descriptor" "0: VLAN Tag Input is disabled,1: VLAN Tag Input is enabled" newline bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN When this bit is set S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted packets" "0: C-VLAN type (0x8100) is inserted or replaced,1: S-VLAN type (0x88A8) is inserted or replaced" newline bitfld.long 0x0 18. "VLP,VLAN Priority Control When this bit is set the control bits[17:16] are used for VLAN deletion insertion or replacement" "0: VLAN Priority Control is disabled,1: VLAN Priority Control is enabled" newline bitfld.long 0x0 16.--17. "VLC,VLAN Tag Control in Transmit Packets - 2'b00: No VLAN tag deletion insertion or replacement - 2'b01: VLAN tag deletion The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16) of all transmitted packets with VLAN tags" "0: No VLAN tag deletion,1: VLAN tag deletion The MAC removes the VLAN type,2: VLAN tag insertion,3: VLAN tag replacement" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted or replaced" group.long 0x60++0x3 line.long 0x0 "MAC_VLAN_Incl0,The Tx Queue {i} VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from Tx Queue {i}. It also contains the VLAN tag insertion controls." hexmask.long.word 0x0 20.--31. 1. "Reserved_31_20,Reserved." newline bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN When this bit is set S-VLAN type (0x88A8) is inserted in the 13th and 14th bytes of transmitted packets" "0: C-VLAN type (0x8100) is inserted,1: S-VLAN type (0x88A8) is inserted" newline rbitfld.long 0x0 16.--18. "Reserved_18_16,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted" group.long 0x60++0x3 line.long 0x0 "MAC_VLAN_Incl1,The Tx Queue {i} VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from Tx Queue {i}. It also contains the VLAN tag insertion controls." hexmask.long.word 0x0 20.--31. 1. "Reserved_31_20,Reserved." newline bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN When this bit is set S-VLAN type (0x88A8) is inserted in the 13th and 14th bytes of transmitted packets" "0: C-VLAN type (0x8100) is inserted,1: S-VLAN type (0x88A8) is inserted" newline rbitfld.long 0x0 16.--18. "Reserved_18_16,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted" group.long 0x60++0x3 line.long 0x0 "MAC_VLAN_Incl2,The Tx Queue {i} VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from Tx Queue {i}. It also contains the VLAN tag insertion controls." hexmask.long.word 0x0 20.--31. 1. "Reserved_31_20,Reserved." newline bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN When this bit is set S-VLAN type (0x88A8) is inserted in the 13th and 14th bytes of transmitted packets" "0: C-VLAN type (0x8100) is inserted,1: S-VLAN type (0x88A8) is inserted" newline rbitfld.long 0x0 16.--18. "Reserved_18_16,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted" group.long 0x60++0x3 line.long 0x0 "MAC_VLAN_Incl3,The Tx Queue {i} VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from Tx Queue {i}. It also contains the VLAN tag insertion controls." hexmask.long.word 0x0 20.--31. 1. "Reserved_31_20,Reserved." newline bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN When this bit is set S-VLAN type (0x88A8) is inserted in the 13th and 14th bytes of transmitted packets" "0: C-VLAN type (0x8100) is inserted,1: S-VLAN type (0x88A8) is inserted" newline rbitfld.long 0x0 16.--18. "Reserved_18_16,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted" group.long 0x60++0x3 line.long 0x0 "MAC_VLAN_Incl4,The Tx Queue {i} VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from Tx Queue {i}. It also contains the VLAN tag insertion controls." hexmask.long.word 0x0 20.--31. 1. "Reserved_31_20,Reserved." newline bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN When this bit is set S-VLAN type (0x88A8) is inserted in the 13th and 14th bytes of transmitted packets" "0: C-VLAN type (0x8100) is inserted,1: S-VLAN type (0x88A8) is inserted" newline rbitfld.long 0x0 16.--18. "Reserved_18_16,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted" group.long 0x60++0x3 line.long 0x0 "MAC_VLAN_Incl5,The Tx Queue {i} VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from Tx Queue {i}. It also contains the VLAN tag insertion controls." hexmask.long.word 0x0 20.--31. 1. "Reserved_31_20,Reserved." newline bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN When this bit is set S-VLAN type (0x88A8) is inserted in the 13th and 14th bytes of transmitted packets" "0: C-VLAN type (0x8100) is inserted,1: S-VLAN type (0x88A8) is inserted" newline rbitfld.long 0x0 16.--18. "Reserved_18_16,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted" group.long 0x60++0x3 line.long 0x0 "MAC_VLAN_Incl6,The Tx Queue {i} VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from Tx Queue {i}. It also contains the VLAN tag insertion controls." hexmask.long.word 0x0 20.--31. 1. "Reserved_31_20,Reserved." newline bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN When this bit is set S-VLAN type (0x88A8) is inserted in the 13th and 14th bytes of transmitted packets" "0: C-VLAN type (0x8100) is inserted,1: S-VLAN type (0x88A8) is inserted" newline rbitfld.long 0x0 16.--18. "Reserved_18_16,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted" group.long 0x60++0x7 line.long 0x0 "MAC_VLAN_Incl7,The Tx Queue {i} VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from Tx Queue {i}. It also contains the VLAN tag insertion controls." hexmask.long.word 0x0 20.--31. 1. "Reserved_31_20,Reserved." newline bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN When this bit is set S-VLAN type (0x88A8) is inserted in the 13th and 14th bytes of transmitted packets" "0: C-VLAN type (0x8100) is inserted,1: S-VLAN type (0x88A8) is inserted" newline rbitfld.long 0x0 16.--18. "Reserved_18_16,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted" line.long 0x4 "MAC_Inner_VLAN_Incl,The Inner VLAN Tag Inclusion or Replacement register contains the inner VLAN tag to be inserted or replaced in the Transmit packet. It also contains the inner VLAN tag insertion controls." hexmask.long.word 0x4 21.--31. 1. "Reserved_31_21,Reserved." newline bitfld.long 0x4 20. "VLTI,VLAN Tag Input When this bit is set it indicates that the VLAN tag to be inserted or replaced in Tx packet should be taken from: - The Tx descriptor" "0: VLAN Tag Input is disabled,1: VLAN Tag Input is enabled" newline bitfld.long 0x4 19. "CSVL,C-VLAN or S-VLAN When this bit is set S-VLAN type (0x88A8) is inserted or replaced in the 17th and 18th bytes of transmitted packets" "0: C-VLAN type (0x8100) is inserted,1: S-VLAN type (0x88A8) is inserted" newline bitfld.long 0x4 18. "VLP,VLAN Priority Control When this bit is set the VLC field is used for VLAN deletion insertion or replacement" "0: VLAN Priority Control is disabled,1: VLAN Priority Control is enabled" newline bitfld.long 0x4 16.--17. "VLC,VLAN Tag Control in Transmit Packets - 2'b00: No VLAN tag deletion insertion or replacement - 2'b01: VLAN tag deletion The MAC removes the VLAN type (bytes 17 and 18) and VLAN tag (bytes 19 and 20) of all transmitted packets with VLAN tags" "0: No VLAN tag deletion,1: VLAN tag deletion The MAC removes the VLAN type,2: VLAN tag insertion,3: VLAN tag replacement" newline hexmask.long.word 0x4 0.--15. 1. "VLT,VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted or replaced" group.long 0x70++0xB line.long 0x0 "MAC_Q0_Tx_Flow_Ctrl,The Flow Control register controls the generation and reception of the Control (Pause Command) packets by the Flow control module of the MAC. A Write to a register with the Busy bit set to 1 triggers the Flow Control block to generate.." hexmask.long.word 0x0 16.--31. 1. "PT,Pause Time This field holds the value to be used in the Pause Time field in the Tx control packet" newline hexmask.long.byte 0x0 8.--15. 1. "Reserved_15_8,Reserved." newline bitfld.long 0x0 7. "DZPQ,Disable Zero-Quanta Pause When this bit is set it disables the automatic generation of the zero-quanta Pause packets on de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i or.." "0: Zero-Quanta Pause packet generation is enabled,1: Zero-Quanta Pause packet generation is disabled" newline bitfld.long 0x0 4.--6. "PLT,Pause Low Threshold This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause packet" "0: Pause Time minus 4 Slot Times (PT -4 slot times),1: Pause Time minus 28 Slot Times (PT -28 slot times),2: Pause Time minus 36 Slot Times (PT -36 slot times),3: Pause Time minus 144 Slot Times (PT -144 slot..,4: Pause Time minus 256 Slot Times (PT -256 slot..,5: Pause Time minus 512 Slot Times (PT -512 slot..,?,?" newline rbitfld.long 0x0 2.--3. "Reserved_3_2,Reserved." "0,1,2,3" newline bitfld.long 0x0 1. "TFE,Transmit Flow Control Enable Full-Duplex Mode: In the full-duplex mode when this bit is set the MAC enables the flow control operation to Tx Pause packets" "0: Transmit Flow Control is disabled,1: Transmit Flow Control is enabled" newline bitfld.long 0x0 0. "FCB_BPA,Flow Control Busy or Backpressure Activate This bit initiates a Pause packet in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set" "0: Flow Control Busy or Backpressure Activate is..,1: Flow Control Busy or Backpressure Activate is.." line.long 0x4 "MAC_Q1_Tx_Flow_Ctrl,This register controls the generation of PFC Control packets of priorities mapped as per the PSRQi field in the MAC_RxQ_Ctrl2/MAC_RxQ_Ctrl3 registers." hexmask.long.word 0x4 16.--31. 1. "PT,Pause Time This field holds the value to be used in the Pause Time field in the Tx control packet" newline hexmask.long.byte 0x4 8.--15. 1. "Reserved_15_8,Reserved." newline bitfld.long 0x4 7. "DZPQ,Disable Zero-Quanta Pause When this bit is set it disables the automatic generation of the zero-quanta Pause packets on de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i or.." "0: Zero-Quanta Pause packet generation is enabled,1: Zero-Quanta Pause packet generation is disabled" newline bitfld.long 0x4 4.--6. "PLT,Pause Low Threshold This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause packet" "0: Pause Time minus 4 Slot Times (PT -4 slot times),1: Pause Time minus 28 Slot Times (PT -28 slot times),2: Pause Time minus 36 Slot Times (PT -36 slot times),3: Pause Time minus 144 Slot Times (PT -144 slot..,4: Pause Time minus 256 Slot Times (PT -256 slot..,5: Pause Time minus 512 Slot Times (PT -512 slot..,?,?" newline rbitfld.long 0x4 2.--3. "Reserved_3_2,Reserved." "0,1,2,3" newline bitfld.long 0x4 1. "TFE,Transmit Flow Control Enable When this bit is set in full-duplex mode the MAC enables the flow control operation to Tx pause packets" "0: Transmit Flow Control is disabled,1: Transmit Flow Control is enabled" newline bitfld.long 0x4 0. "FCB_BPA,Flow Control Busy This bit initiates a PFC packet if the TFE bit is set" "0: Flow Control Busy or Backpressure Activate is..,1: Flow Control Busy or Backpressure Activate is.." line.long 0x8 "MAC_Q2_Tx_Flow_Ctrl,This register controls the generation of PFC Control packets of priorities mapped as per the PSRQi field in the MAC_RxQ_Ctrl2/MAC_RxQ_Ctrl3 registers." hexmask.long.word 0x8 16.--31. 1. "PT,Pause Time This field holds the value to be used in the Pause Time field in the Tx control packet" newline hexmask.long.byte 0x8 8.--15. 1. "Reserved_15_8,Reserved." newline bitfld.long 0x8 7. "DZPQ,Disable Zero-Quanta Pause When this bit is set it disables the automatic generation of the zero-quanta Pause packets on de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i or.." "0: Zero-Quanta Pause packet generation is enabled,1: Zero-Quanta Pause packet generation is disabled" newline bitfld.long 0x8 4.--6. "PLT,Pause Low Threshold This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause packet" "0: Pause Time minus 4 Slot Times (PT -4 slot times),1: Pause Time minus 28 Slot Times (PT -28 slot times),2: Pause Time minus 36 Slot Times (PT -36 slot times),3: Pause Time minus 144 Slot Times (PT -144 slot..,4: Pause Time minus 256 Slot Times (PT -256 slot..,5: Pause Time minus 512 Slot Times (PT -512 slot..,?,?" newline rbitfld.long 0x8 2.--3. "Reserved_3_2,Reserved." "0,1,2,3" newline bitfld.long 0x8 1. "TFE,Transmit Flow Control Enable When this bit is set in full-duplex mode the MAC enables the flow control operation to Tx pause packets" "0: Transmit Flow Control is disabled,1: Transmit Flow Control is enabled" newline bitfld.long 0x8 0. "FCB_BPA,Flow Control Busy This bit initiates a PFC packet if the TFE bit is set" "0: Flow Control Busy or Backpressure Activate is..,1: Flow Control Busy or Backpressure Activate is.." group.long 0x90++0xB line.long 0x0 "MAC_Rx_Flow_Ctrl,The Receive Flow Control register controls the pausing of MAC Transmit based on the received Pause packet." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_31_9,Reserved." newline bitfld.long 0x0 8. "PFCE,Priority Based Flow Control Enable When this bit is set it enables generation and reception of priority-based flow control (PFC) packets" "0: Priority Based Flow Control is disabled,1: Priority Based Flow Control is enabled" newline hexmask.long.byte 0x0 2.--7. 1. "Reserved_7_2,Reserved." newline bitfld.long 0x0 1. "UP,Unicast Pause Packet Detect A pause packet is processed when it has the unique multicast address specified in the IEEE 802" "0: Unicast Pause Packet Detect disabled,1: Unicast Pause Packet Detect enabled" newline bitfld.long 0x0 0. "RFE,Receive Flow Control Enable When this bit is set and the MAC is operating in full-duplex mode the MAC decodes the received Pause packet and disables its transmitter for a specified (Pause) time" "0: Receive Flow Control is disabled,1: Receive Flow Control is enabled" line.long 0x4 "MAC_RxQ_Ctrl4,The Receive Queue Control 4 register controls the routing of unicast and multicast packets that fail the Destination or Source address filter to the Rx queues." hexmask.long.word 0x4 19.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x4 17.--18. "VFFQ,VLAN Tag Filter Fail Packets Queue This field holds the Rx queue number to which the tagged packets failing the Destination or Source Address filter (and UFFQE/MFFQE not enabled) or failing the VLAN tag filter must be routed to" "0,1,2,3" newline bitfld.long 0x4 16. "VFFQE,VLAN Tag Filter Fail Packets Queuing Enable When this bit is set the tagged packets which fail the Destination or Source address filter or fail the VLAN tag filter are routed to the Rx Queue Number programmed in the VFFQ" "0: VLAN tag Filter Fail Packets Queuing is disabled,1: VLAN tag Filter Fail Packets Queuing is enabled" newline hexmask.long.byte 0x4 11.--15. 1. "Reserved_15_y,Reserved." newline bitfld.long 0x4 9.--10. "MFFQ,Multicast Address Filter Fail Packets Queue" "0,1,2,3" newline bitfld.long 0x4 8. "MFFQE,Multicast Address Filter Fail Packets Queuing Enable" "0: Multicast Address Filter Fail Packets Queuing is..,1: Multicast Address Filter Fail Packets Queuing is.." newline hexmask.long.byte 0x4 3.--7. 1. "Reserved_7_y,Reserved." newline bitfld.long 0x4 1.--2. "UFFQ,Unicast Address Filter Fail Packets Queue" "0,1,2,3" newline bitfld.long 0x4 0. "UFFQE,Unicast Address Filter Fail Packets Queuing Enable" "0: Unicast Address Filter Fail Packets Queuing is..,1: Unicast Address Filter Fail Packets Queuing is.." line.long 0x8 "MAC_TxQ_Prty_Map0,The Transmit Queue Priority Mapping 0 register contains the priority values assigned to Tx Queue 0 through Tx Queue 3." hexmask.long.byte 0x8 24.--31. 1. "Reserved_PSTQ3,Reserved." newline hexmask.long.byte 0x8 16.--23. 1. "PSTQ2,Priorities Selected in Transmit Queue 2 This bit is similar to the PSTQ0 bit." newline hexmask.long.byte 0x8 8.--15. 1. "PSTQ1,Priorities Selected in Transmit Queue 1 This bit is similar to the PSTQ0 bit." newline hexmask.long.byte 0x8 0.--7. 1. "PSTQ0,Priorities Selected in Transmit Queue 0 This field holds the priorities assigned to Tx Queue 0 by the software" group.long 0xA0++0xB line.long 0x0 "MAC_RxQ_Ctrl0,The Receive Queue Control 0 register controls the queue management in the MAC Receiver. Note: In multiple Rx queues configuration. all the queues are disabled by default. Enable the Rx queue by programming the corresponding field in this.." hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved." newline rbitfld.long 0x0 14.--15. "Reserved_RXQ7EN,Reserved." "0,1,2,3" newline rbitfld.long 0x0 12.--13. "Reserved_RXQ6EN,Reserved." "0,1,2,3" newline rbitfld.long 0x0 10.--11. "Reserved_RXQ5EN,Reserved." "0,1,2,3" newline rbitfld.long 0x0 8.--9. "Reserved_RXQ4EN,Reserved." "0,1,2,3" newline rbitfld.long 0x0 6.--7. "Reserved_RXQ3EN,Reserved." "0,1,2,3" newline bitfld.long 0x0 4.--5. "RXQ2EN,Receive Queue 2 Enable This field is similar to the RXQ0EN field." "0: Queue not enabled,1: Queue enabled for AV,2: Queue enabled for DCB/Generic,?" newline bitfld.long 0x0 2.--3. "RXQ1EN,Receive Queue 1 Enable This field is similar to the RXQ0EN field." "0: Queue not enabled,1: Queue enabled for AV,2: Queue enabled for DCB/Generic,?" newline bitfld.long 0x0 0.--1. "RXQ0EN,Receive Queue 0 Enable This field indicates whether Rx Queue 0 is enabled for AV or DCB." "0: Queue not enabled,1: Queue enabled for AV,2: Queue enabled for DCB/Generic,?" line.long 0x4 "MAC_RxQ_Ctrl1,The Receive Queue Control 1 register controls the routing of multicast. broadcast. AV. DCB. and untagged packets to the Rx queues." rbitfld.long 0x4 30.--31. "Reserved_31_30,Reserved." "0,1,2,3" newline bitfld.long 0x4 29. "TBRQE,Type Field Based Rx Queuing Enable When this bit is set it enables Type Field based Rx Queuing where the Type field of received packet is compared with programmed TYP field in MAC_TMRQ_Regs(#i) and if a match occurs the packet is routed to the.." "0,1" newline bitfld.long 0x4 28. "OMCBCQ,Over-riding MC-BC queue priority select - 1: Priority of MCBCQ is reduced and the received packet is first routed to PTPQ AVCPQ DCBCPQ depending on packet type" "0: overriding MCBCQ priority disabled,1: Priority of MCBCQ is reduced and the received.." newline rbitfld.long 0x4 27. "Reserved_27,Reserved." "0,1" newline bitfld.long 0x4 24.--26. "FPRQ,Frame Preemption Residue Queue This field holds the Rx queue number to which the residual preemption frames must be forwarded" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 22.--23. "TPQC,Tagged PTP over Ethernet Packets Queuing Control" "0,1,2,3" newline bitfld.long 0x4 21. "TACPQE,Tagged AV Control Packets Queuing Enable" "0: Tagged AV Control Packets Queuing is disabled,1: Tagged AV Control Packets Queuing is enabled" newline bitfld.long 0x4 20. "MCBCQEN,Multicast and Broadcast Queue Enable This bit specifies that Multicast or Broadcast packets routing to the Rx Queue is enabled and the Multicast or Broadcast packets must be routed to Rx Queue specified in MCBCQ field" "0: Multicast and Broadcast Queue is disabled,1: Multicast and Broadcast Queue is enabled" newline rbitfld.long 0x4 19. "Reserved_19,Reserved." "0,1" newline bitfld.long 0x4 16.--18. "MCBCQ,Multicast and Broadcast Queue This field specifies the Rx Queue onto which Multicast or Broadcast Packets are routed" "0: Receive Queue 0,1: Receive Queue 1,2: Receive Queue 2,3: Receive Queue 3,4: Receive Queue 4,5: Receive Queue 5,6: Receive Queue 6,7: Receive Queue 7" newline rbitfld.long 0x4 15. "Reserved_15,Reserved." "0,1" newline bitfld.long 0x4 12.--14. "UPQ,Untagged Packet Queue This field indicates the Rx Queue to which Untagged Packets are to be routed" "0: Receive Queue 0,1: Receive Queue 1,2: Receive Queue 2,3: Receive Queue 3,4: Receive Queue 4,5: Receive Queue 5,6: Receive Queue 6,7: Receive Queue 7" newline rbitfld.long 0x4 11. "Reserved_11,Reserved." "0,1" newline bitfld.long 0x4 8.--10. "DCBCPQ,DCB Control Packets Queue This field specifies the Rx queue on which the received DCB control packets are routed" "0: Receive Queue 0,1: Receive Queue 1,2: Receive Queue 2,3: Receive Queue 3,4: Receive Queue 4,5: Receive Queue 5,6: Receive Queue 6,7: Receive Queue 7" newline rbitfld.long 0x4 7. "Reserved_7,Reserved." "0,1" newline bitfld.long 0x4 4.--6. "PTPQ,PTP Packets Queue This field specifies the Rx queue on which the PTP packets sent over the Ethernet payload (not over IPv4 or IPv6) are routed" "0: Receive Queue 0,1: Receive Queue 1,2: Receive Queue 2,3: Receive Queue 3,4: Receive Queue 4,5: Receive Queue 5,6: Receive Queue 6,7: Receive Queue 7" newline rbitfld.long 0x4 3. "Reserved_3,Reserved." "0,1" newline bitfld.long 0x4 0.--2. "AVCPQ,AV Untagged Control Packets Queue This field specifies the Receive queue on which the received AV tagged and untagged control packets are routed" "0: Receive Queue 0,1: Receive Queue 1,2: Receive Queue 2,3: Receive Queue 3,4: Receive Queue 4,5: Receive Queue 5,6: Receive Queue 6,7: Receive Queue 7" line.long 0x8 "MAC_RxQ_Ctrl2,This register controls the routing of tagged packets based on the USP (user Priority) field of the received packets to the RxQueues 0 to 3." hexmask.long.byte 0x8 24.--31. 1. "Reserved_PSRQ3,Reserved." newline hexmask.long.byte 0x8 16.--23. 1. "PSRQ2,Priorities Selected in the Receive Queue 2 This field decides the priorities assigned to Rx Queue 2" newline hexmask.long.byte 0x8 8.--15. 1. "PSRQ1,Priorities Selected in the Receive Queue 1 This field decides the priorities assigned to Rx Queue 1" newline hexmask.long.byte 0x8 0.--7. 1. "PSRQ0,Priorities Selected in the Receive Queue 0 This field decides the priorities assigned to Rx Queue 0" rgroup.long 0xB0++0x3 line.long 0x0 "MAC_Interrupt_Status,The Interrupt Status register contains the status of interrupts." hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved." newline bitfld.long 0x0 20. "MFRIS,MMC FPE Receive Interrupt Status This bit is set high when an interrupt is generated in the MMC FPE Receive Interrupt Register" "0: MMC FPE Receive Interrupt status not active,1: MMC FPE Receive Interrupt status active" newline bitfld.long 0x0 19. "MFTIS,MMC FPE Transmit Interrupt Status This bit is set high when an interrupt is generated in the MMC FPE Transmit Interrupt Register" "0: MMC FPE Transmit Interrupt status not active,1: MMC FPE Transmit Interrupt status active" newline bitfld.long 0x0 18. "MDIOIS,MDIO Interrupt Status This bit indicates an interrupt event after the completion of MDIO operation" "0: MDIO Interrupt status not active,1: MDIO Interrupt status active" newline bitfld.long 0x0 17. "FPEIS,Frame Preemption Interrupt Status This bit indicates an interrupt event during the operation of Frame Preemption (Bits[19:16] of MAC_FPE_CTRL_STS register is set)" "0: Frame Preemption Interrupt status not active,1: Frame Preemption Interrupt status active" newline bitfld.long 0x0 16. "Reserved_16,Reserved." "0,1" newline bitfld.long 0x0 15. "Reserved_GPIIS,Reserved." "0,1" newline bitfld.long 0x0 14. "RXSTSIS,Receive Status Interrupt This bit indicates the status of received packets" "0: Receive Interrupt status not active,1: Receive Interrupt status active" newline bitfld.long 0x0 13. "TXSTSIS,Transmit Status Interrupt This bit indicates the status of transmitted packets" "0: Transmit Interrupt status not active,1: Transmit Interrupt status active" newline bitfld.long 0x0 12. "TSIS,Timestamp Interrupt Status If the Timestamp feature is enabled this bit is set when any of the following conditions is true: - The system time value is equal to or exceeds the value specified in the Target Time High and Low registers" "0: Timestamp Interrupt status not active,1: Timestamp Interrupt status active" newline bitfld.long 0x0 11. "Reserved_MMCRXIPIS,Reserved." "0,1" newline bitfld.long 0x0 10. "MMCTXIS,MMC Transmit Interrupt Status This bit is set high when an interrupt is generated in the MMC Transmit Interrupt Register" "0: MMC Transmit Interrupt status not active,1: MMC Transmit Interrupt status active" newline bitfld.long 0x0 9. "MMCRXIS,MMC Receive Interrupt Status This bit is set high when an interrupt is generated in the MMC Receive Interrupt Register" "0: MMC Receive Interrupt status not active,1: MMC Receive Interrupt status active" newline bitfld.long 0x0 8. "MMCIS,MMC Interrupt Status This bit is set high when Bit 11 Bit 10 or Bit 9 is set high" "0: MMC Interrupt status not active,1: MMC Interrupt status active" newline bitfld.long 0x0 6.--7. "Reserved_7_6,Reserved." "0,1,2,3" newline bitfld.long 0x0 5. "Reserved_LPIIS,Reserved." "0,1" newline bitfld.long 0x0 4. "Reserved_PMTIS,Reserved." "0,1" newline bitfld.long 0x0 3. "PHYIS,PHY Interrupt This bit is set when rising edge is detected on the phy_intr_i input" "0: PHY Interrupt not detected,1: PHY Interrupt detected" newline bitfld.long 0x0 2. "Reserved_PCSANCIS,Reserved." "0,1" newline bitfld.long 0x0 1. "Reserved_PCSLCHGIS,Reserved." "0,1" newline bitfld.long 0x0 0. "RGSMIIIS,RGMII or SMII Interrupt Status This bit is set because of any change in value of the Link Status of RGMII or SMII interface (LNKSTS bit in MAC_PHYIF_Control_Status register)" "0: RGMII or SMII Interrupt Status is not active,1: RGMII or SMII Interrupt Status is active" group.long 0xB4++0x3 line.long 0x0 "MAC_Interrupt_Enable,The Interrupt Enable register contains the masks for generating the interrupts." hexmask.long.word 0x0 19.--31. 1. "Reserved_31_19,Reserved." newline bitfld.long 0x0 18. "MDIOIE,MDIO Interrupt Enable When this bit is set it enables the assertion of the interrupt when MDIOIS field is set in the MAC_Interrupt_Status register" "0: MDIO Interrupt is disabled,1: MDIO Interrupt is enabled" newline bitfld.long 0x0 17. "FPEIE,Frame Preemption Interrupt Enable When this bit is set it enables the assertion of the interrupt when FPEIS field is set in the MAC_Interrupt_Status register" "0: Frame Preemption Interrupt is disabled,1: Frame Preemption Interrupt is enabled" newline rbitfld.long 0x0 16. "Reserved_16,Reserved." "0,1" newline rbitfld.long 0x0 15. "Reserved_15,Reserved." "0,1" newline bitfld.long 0x0 14. "RXSTSIE,Receive Status Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of RXSTSIS bit in the MAC_Interrupt_Status register" "0: Receive Status Interrupt is disabled,1: Receive Status Interrupt is enabled" newline bitfld.long 0x0 13. "TXSTSIE,Transmit Status Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of TXSTSIS bit in the MAC_Interrupt_Status register" "0: Timestamp Status Interrupt is disabled,1: Timestamp Status Interrupt is enabled" newline bitfld.long 0x0 12. "TSIE,Timestamp Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of TSIS bit in MAC_Interrupt_Status register" "0: Timestamp Interrupt is disabled,1: Timestamp Interrupt is enabled" newline hexmask.long.byte 0x0 6.--11. 1. "Reserved_11_6,Reserved." newline rbitfld.long 0x0 5. "Reserved_LPIIE,Reserved." "0,1" newline rbitfld.long 0x0 4. "Reserved_PMTIE,Reserved." "0,1" newline bitfld.long 0x0 3. "PHYIE,PHY Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of PHYIS bit in MAC_Interrupt_Status register" "0: PHY Interrupt is disabled,1: PHY Interrupt is enabled" newline rbitfld.long 0x0 2. "Reserved_PCSANCIE,Reserved." "0,1" newline rbitfld.long 0x0 1. "Reserved_PCSLCHGIE,Reserved." "0,1" newline bitfld.long 0x0 0. "RGSMIIIE,RGMII or SMII Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of RGSMIIIS bit in MAC_Interrupt_Status register" "0: RGMII or SMII Interrupt is disabled,1: RGMII or SMII Interrupt is enabled" rgroup.long 0xB8++0x3 line.long 0x0 "MAC_Rx_Tx_Status,The Receive Transmit Status register contains the Receive and Transmit Error status." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_31_9,Reserved." newline bitfld.long 0x0 8. "RWT,Receive Watchdog Timeout This bit is set when a packet with length greater than 2 048 bytes is received (10 240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the MAC_Configuration register" "0: No receive watchdog timeout,1: Receive watchdog timed out" newline bitfld.long 0x0 6.--7. "Reserved_7_6,Reserved." "0,1,2,3" newline bitfld.long 0x0 5. "EXCOL,Excessive Collisions When the DTXSTS bit is set in the MTL_Operation_Mode register this bit indicates that the transmission aborted after 16 successive collisions while attempting to transmit the current packet" "0: No collision,1: Excessive collision is sensed" newline bitfld.long 0x0 4. "LCOL,Late Collision When the DTXSTS bit is set in the MTL_Operation_Mode register this bit indicates that the packet transmission aborted because a collision occurred after the collision window (64 bytes including Preamble in MII mode; 512 bytes.." "0: No collision,1: Late collision is sensed" newline bitfld.long 0x0 3. "EXDEF,Excessive Deferral When the DTXSTS bit is set in the MTL_Operation_Mode register and the DC bit is set in the MAC_Configuration register this bit indicates that the transmission ended because of excessive deferral of over 24 288 bit times (155 680.." "0: No Excessive deferral,1: Excessive deferral" newline bitfld.long 0x0 2. "LCARR,Loss of Carrier When the DTXSTS bit is set in the MTL_Operation_Mode register this bit indicates that the loss of carrier occurred during packet transmission that is the phy_crs_i signal was inactive for one or more transmission clock periods.." "0: Carrier is present,1: Loss of carrier" newline bitfld.long 0x0 1. "NCARR,No Carrier When the DTXSTS bit is set in the MTL_Operation_Mode register this bit indicates that the carrier signal from the PHY is not present at the end of preamble transmission" "0: Carrier is present,1: No carrier" newline bitfld.long 0x0 0. "TJT,Transmit Jabber Timeout This bit indicates that the Transmit Jabber Timer expired which happens when the packet size exceeds 2 048 bytes (10 240 bytes when the Jumbo packet is enabled) and JD bit is reset in the MAC_Configuration register" "0: No Transmit Jabber Timeout,1: Transmit Jabber Timeout occurred" group.long 0xF8++0x3 line.long 0x0 "MAC_PHYIF_Control_Status,The PHY Interface Control and Status register indicates the status signals received by the SGMII. RGMII. or SMII interface (selected at reset) from the PHY. This register is optional." hexmask.long.word 0x0 22.--31. 1. "Reserved_31_22,Reserved." newline rbitfld.long 0x0 21. "Reserved_FALSCARDET,Reserved." "0,1" newline rbitfld.long 0x0 20. "Reserved_JABTO,Reserved." "0,1" newline rbitfld.long 0x0 19. "LNKSTS,Link Status This bit indicates whether the link is up (1'b1) or down (1'b0)." "0: Link down,1: Link up" newline rbitfld.long 0x0 17.--18. "LNKSPEED,Link Speed This bit indicates the current speed of the link." "0: 2.5 MHz,1: 25 MHz,2: 125 MHz,?" newline rbitfld.long 0x0 16. "LNKMOD,Link Mode This bit indicates the current mode of operation of the link." "0: Half-duplex mode,1: Full-duplex mode" newline hexmask.long.word 0x0 5.--15. 1. "Reserved_15_5,Reserved." newline rbitfld.long 0x0 4. "Reserved_SMIDRXS,Reserved." "0,1" newline rbitfld.long 0x0 3. "Reserved_3,Reserved." "0,1" newline rbitfld.long 0x0 2. "Reserved_SFTERR,Reserved." "0,1" newline bitfld.long 0x0 1. "LUD,Link Up or Down This bit indicates whether the link is up or down during transmission of configuration in the RGMII SGMII or SMII interface" "0: Link down,1: Link up" newline bitfld.long 0x0 0. "TC,Transmit Configuration in RGMII SGMII or SMII When set this bit enables the transmission of duplex mode link speed and link up or down information to the PHY in the RGMII SMII or SGMII port" "0: Disable Transmit Configuration in RGMII SGMII or..,1: Enable Transmit Configuration in RGMII SGMII or.." rgroup.long 0x110++0x7 line.long 0x0 "MAC_Version,Identifies the version of the module." hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved." newline hexmask.long.byte 0x0 8.--15. 1. "USERVER,User-defined Version (configured with coreConsultant)" newline hexmask.long.byte 0x0 0.--7. 1. "IPVER,IP version" line.long 0x4 "MAC_Debug,The Debug register provides the debug status of various MAC blocks." hexmask.long.word 0x4 19.--31. 1. "Reserved_31_19,Reserved." newline bitfld.long 0x4 17.--18. "TFCSTS,MAC Transmit Packet Controller Status This field indicates the state of the MAC Transmit Packet Controller module" "0: Idle state,1: Waiting for one of the following: Status of the..,2: Generating and transmitting a Pause control..,3: Transferring input packet for transmission" newline bitfld.long 0x4 16. "TPESTS,MAC GMII or MII Transmit Protocol Engine Status When this bit is set it indicates that the MAC GMII or MII transmit protocol engine is actively transmitting data and it is not in the Idle state" "0: MAC GMII or MII Transmit Protocol Engine Status..,1: MAC GMII or MII Transmit Protocol Engine Status.." newline hexmask.long.word 0x4 3.--15. 1. "Reserved_15_3,Reserved." newline bitfld.long 0x4 1.--2. "RFCFCSTS,MAC Receive Packet Controller FIFO Status When this bit is set this field indicates the active state of the small FIFO Read and Write controllers of the MAC Receive Packet Controller module" "0,1,2,3" newline bitfld.long 0x4 0. "RPESTS,MAC GMII or MII Receive Protocol Engine Status When this bit is set it indicates that the MAC GMII or MII receive protocol engine is actively receiving data and it is not in the Idle state" "0: MAC GMII or MII Receive Protocol Engine Status..,1: MAC GMII or MII Receive Protocol Engine Status.." rgroup.long 0x11C++0xF line.long 0x0 "MAC_HW_Feature0,This register indicates the presence of first set of the optional features or functions of the DWC_ether_qos. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks. Note:.." bitfld.long 0x0 31. "Reserved_31,Reserved." "0,1" newline bitfld.long 0x0 28.--30. "ACTPHYSEL,Active PHY Selected When you have multiple PHY interfaces in your configuration this field indicates the sampled value of phy_intf_sel_i during reset de-assertion" "0: GMII or MII,1: RGMII,2: SGMII,3: TBI,4: RMII,5: RTBI,6: SMII,7: RevMII" newline bitfld.long 0x0 27. "SAVLANINS,Source Address or VLAN Insertion Enable This bit is set to 1 when the Enable SA and VLAN Insertion on Tx option is selected" "0: Source Address or VLAN Insertion Enable option..,1: Source Address or VLAN Insertion Enable option.." newline bitfld.long 0x0 25.--26. "TSSTSSEL,Timestamp System Time Source This bit indicates the source of the Timestamp system time: This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected" "0: Internal,1: External,2: Both,?" newline bitfld.long 0x0 24. "MACADR64SEL,MAC Addresses 64-127 Selected This bit is set to 1 when the Enable Additional 64 MAC Address Registers (64-127) option is selected" "0: MAC Addresses 64-127 Select option is not selected,1: MAC Addresses 64-127 Select option is selected" newline bitfld.long 0x0 23. "MACADR32SEL,MAC Addresses 32-63 Selected This bit is set to 1 when the Enable Additional 32 MAC Address Registers (32-63) option is selected" "0: MAC Addresses 32-63 Select option is not selected,1: MAC Addresses 32-63 Select option is selected" newline hexmask.long.byte 0x0 18.--22. 1. "ADDMACADRSEL,MAC Addresses 1-31 Selected This bit is set to 1 when the non-zero value is selected for Enable Additional 1-31 MAC Address Registers option" newline bitfld.long 0x0 17. "Reserved_17,Reserved." "0,1" newline bitfld.long 0x0 16. "RXCOESEL,Receive Checksum Offload Enabled This bit is set to 1 when the Enable Receive TCP/IP Checksum Check option is selected" "0: Receive Checksum Offload Enable option is not..,1: Receive Checksum Offload Enable option is selected" newline bitfld.long 0x0 15. "Reserved_15,Reserved." "0,1" newline bitfld.long 0x0 14. "TXCOESEL,Transmit Checksum Offload Enabled This bit is set to 1 when the Enable Transmit TCP/IP Checksum Insertion option is selected" "0: Transmit Checksum Offload Enable option is not..,1: Transmit Checksum Offload Enable option is.." newline bitfld.long 0x0 13. "EEESEL,Energy Efficient Ethernet Enabled This bit is set to 1 when the Enable Energy Efficient Ethernet (EEE) option is selected" "0: Energy Efficient Ethernet Enable option is not..,1: Energy Efficient Ethernet Enable option is.." newline bitfld.long 0x0 12. "TSSEL,IEEE 1588-2008 Timestamp Enabled This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected" "0: IEEE 1588-2008 Timestamp Enable option is not..,1: IEEE 1588-2008 Timestamp Enable option is selected" newline bitfld.long 0x0 10.--11. "Reserved_11_10,Reserved." "0,1,2,3" newline bitfld.long 0x0 9. "ARPOFFSEL,ARP Offload Enabled This bit is set to 1 when the Enable IPv4 ARP Offload option is selected" "0: ARP Offload Enable option is not selected,1: ARP Offload Enable option is selected" newline bitfld.long 0x0 8. "MMCSEL,RMON Module Enable This bit is set to 1 when the Enable MAC Management Counters (MMC) option is selected" "0: RMON Module Enable option is not selected,1: RMON Module Enable option is selected" newline bitfld.long 0x0 7. "MGKSEL,PMT Magic Packet Enable This bit is set to 1 when the Enable Magic Packet Detection option is selected" "0: PMT Magic Packet Enable option is not selected,1: PMT Magic Packet Enable option is selected" newline bitfld.long 0x0 6. "RWKSEL,PMT Remote Wake-up Packet Enable This bit is set to 1 when the Enable Remote Wake-Up Packet Detection option is selected" "0: PMT Remote Wake-up Packet Enable option is not..,1: PMT Remote Wake-up Packet Enable option is.." newline bitfld.long 0x0 5. "SMASEL,SMA (MDIO) Interface This bit is set to 1 when the Enable Station Management (MDIO Interface) option is selected" "0: SMA (MDIO) Interface not selected,1: SMA (MDIO) Interface selected" newline bitfld.long 0x0 4. "VLHASH,VLAN Hash Filter Selected This bit is set to 1 when the Enable VLAN Hash Table Based Filtering option is selected" "0: VLAN Hash Filter not selected,1: VLAN Hash Filter selected" newline bitfld.long 0x0 3. "PCSSEL,PCS Registers (TBI SGMII or RTBI PHY interface) This bit is set to 1 when the TBI SGMII or RTBI PHY interface option is selected" "0: No PCS Registers (TBI SGMII or RTBI PHY interface),1: PCS Registers (TBI SGMII or RTBI PHY interface)" newline bitfld.long 0x0 2. "HDSEL,Half-duplex Support This bit is set to 1 when the half-duplex mode is selected" "0: No Half-duplex support,1: Half-duplex support" newline bitfld.long 0x0 1. "GMIISEL,1000 Mbps Support This bit is set to 1 when 1000 Mbps is selected as the Mode of Operation" "0: No 1000 Mbps support,1: 1000 Mbps support" newline bitfld.long 0x0 0. "MIISEL,10 or 100 Mbps Support This bit is set to 1 when 10/100 Mbps is selected as the Mode of Operation" "0: No 10 or 100 Mbps support,1: 10 or 100 Mbps support" line.long 0x4 "MAC_HW_Feature1,This register indicates the presence of second set of the optional features or functions of the DWC_ether_qos. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks. Note:.." bitfld.long 0x4 31. "Reserved_31,Reserved." "0,1" newline hexmask.long.byte 0x4 27.--30. 1. "L3L4FNUM,Total number of L3 or L4 Filters This field indicates the total number of L3 or L4 filters:" newline bitfld.long 0x4 26. "Reserved_26,Reserved." "0,1" newline bitfld.long 0x4 24.--25. "HASHTBLSZ,Hash Table Size This field indicates the size of the hash table:" "0: No hash table,1: 64,2: 128,3: 256" newline bitfld.long 0x4 23. "POUOST,One Step for PTP over UDP/IP Feature Enable This bit is set to 1 when the Enable One step timestamp for PTP over UDP/IP feature is selected" "0: One Step for PTP over UDP/IP Feature is not..,1: One Step for PTP over UDP/IP Feature is selected" newline bitfld.long 0x4 22. "Reserved_22,Reserved." "0,1" newline bitfld.long 0x4 21. "RAVSEL,Rx Side Only AV Feature Enable This bit is set to 1 when the Enable Audio Video Bridging option on Rx Side Only is selected" "0: Rx Side Only AV Feature is not selected,1: Rx Side Only AV Feature is selected" newline bitfld.long 0x4 20. "AVSEL,AV Feature Enable This bit is set to 1 when the Enable Audio Video Bridging option is selected." "0: AV Feature is not selected,1: AV Feature is selected" newline bitfld.long 0x4 19. "DBGMEMA,DMA Debug Registers Enable This bit is set to 1 when the Debug Mode Enable option is selected" "0: DMA Debug Registers option is not selected,1: DMA Debug Registers option is selected" newline bitfld.long 0x4 18. "TSOEN,TCP Segmentation Offload Enable This bit is set to 1 when the Enable TCP Segmentation Offloading for TCP/IP Packets option is selected" "0: TCP Segmentation Offload Feature is not selected,1: TCP Segmentation Offload Feature is selected" newline bitfld.long 0x4 17. "SPHEN,Split Header Feature Enable This bit is set to 1 when the Enable Split Header Structure option is selected" "0: Split Header Feature is not selected,1: Split Header Feature is selected" newline bitfld.long 0x4 16. "DCBEN,DCB Feature Enable This bit is set to 1 when the Enable Data Center Bridging option is selected" "0: DCB Feature is not selected,1: DCB Feature is selected" newline bitfld.long 0x4 14.--15. "ADDR64,Address Width. This field indicates the configured address width:" "0: 32,1: 40,2: 48,?" newline bitfld.long 0x4 13. "ADVTHWORD,IEEE 1588 High Word Register Enable This bit is set to 1 when the Add IEEE 1588 Higher Word Register option is selected" "0: IEEE 1588 High Word Register option is not..,1: IEEE 1588 High Word Register option is selected" newline bitfld.long 0x4 12. "PTOEN,PTP Offload Enable This bit is set to 1 when the Enable PTP Timestamp Offload Feature is selected." "0: PTP Offload feature is not selected,1: PTP Offload feature is selected" newline bitfld.long 0x4 11. "OSTEN,One-Step Timestamping Enable This bit is set to 1 when the Enable One-Step Timestamp Feature is selected" "0: One-Step Timestamping feature is not selected,1: One-Step Timestamping feature is selected" newline hexmask.long.byte 0x4 6.--10. 1. "TXFIFOSIZE,MTL Transmit FIFO Size This field contains the configured value of MTL Tx FIFO in bytes expressed as Log to base 2 minus 7 that is Log2(TXFIFO_SIZE) -7:" newline bitfld.long 0x4 5. "SPRAM,Single Port RAM Enable This bit is set to 1 when the Use single port RAM Feature is selected." "0: Single Port RAM feature is not selected,1: Single Port RAM feature is selected" newline hexmask.long.byte 0x4 0.--4. 1. "RXFIFOSIZE,MTL Receive FIFO Size This field contains the configured value of MTL Rx FIFO in bytes expressed as Log to base 2 minus 7 that is Log2(RXFIFO_SIZE) -7:" line.long 0x8 "MAC_HW_Feature2,This register indicates the presence of third set of the optional features or functions of the DWC_ether_qos. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks." bitfld.long 0x8 31. "Reserved_31,Reserved." "0,1" newline bitfld.long 0x8 28.--30. "AUXSNAPNUM,Number of Auxiliary Snapshot Inputs This field indicates the number of auxiliary snapshot inputs:" "0: No auxiliary input,1: 1 auxiliary input,2: 2 auxiliary input,3: 3 auxiliary input,4: 4 auxiliary input,?,?,?" newline bitfld.long 0x8 27. "Reserved_27,Reserved." "0,1" newline bitfld.long 0x8 24.--26. "PPSOUTNUM,Number of PPS Outputs This field indicates the number of PPS outputs:" "0: No PPS output,1: 1 PPS output,2: 2 PPS output,3: 3 PPS output,4: 4 PPS output,?,?,?" newline bitfld.long 0x8 22.--23. "TDCSZ,Tx DMA Descriptor Cache Size in terms of 16 bytes descriptors: 00 - Cache Not configured 01 - 4 16 bytes descriptor 10 - 8 16 bytes descriptor 11 - 16 16 bytes descriptor" "0: Cache Not configured 01,?,?,?" newline hexmask.long.byte 0x8 18.--21. 1. "TXCHCNT,Number of DMA Transmit Channels This field indicates the number of DMA Transmit channels:" newline bitfld.long 0x8 16.--17. "RDCSZ,Rx DMA Descriptor Cache Size in terms of 16 bytes descriptors: 00 - Cache Not configured 01 - 4 16 bytes descriptor 10 - 8 16 bytes descriptor 11 - 16 16 bytes descriptor" "0: Cache Not configured 01,?,?,?" newline hexmask.long.byte 0x8 12.--15. 1. "RXCHCNT,Number of DMA Receive Channels This field indicates the number of DMA Receive channels:" newline bitfld.long 0x8 10.--11. "Reserved_11_10,Reserved." "0,1,2,3" newline hexmask.long.byte 0x8 6.--9. 1. "TXQCNT,Number of MTL Transmit Queues This field indicates the number of MTL Transmit queues:" newline bitfld.long 0x8 4.--5. "Reserved_5_4,Reserved." "0,1,2,3" newline hexmask.long.byte 0x8 0.--3. 1. "RXQCNT,Number of MTL Receive Queues This field indicates the number of MTL Receive queues:" line.long 0xC "MAC_HW_Feature3,This register indicates the presence of fourth set the optional features or functions of the DWC_ether_qos. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks." bitfld.long 0xC 30.--31. "Reserved_31_30,Reserved." "0,1,2,3" newline bitfld.long 0xC 28.--29. "ASP,Automotive Safety Package Following are the encoding for the different Safety features" "0: No Safety features selected,1: Only 'ECC protection for external memory'..,2: All the Automotive Safety features are selected..,3: All the Automotive Safety features are selected.." newline bitfld.long 0xC 27. "TBSSEL,Time Based Scheduling Enable This bit is set to 1 when the Time Based Scheduling feature is selected" "0: Time Based Scheduling Enable feature is not..,1: Time Based Scheduling Enable feature is selected" newline bitfld.long 0xC 26. "FPESEL,Frame Preemption Enable This bit is set to 1 when the Enable Frame preemption feature is selected." "0: Frame Preemption Enable feature is not selected,1: Frame Preemption Enable feature is selected" newline hexmask.long.byte 0xC 22.--25. 1. "Reserved_25_22,Reserved." newline bitfld.long 0xC 20.--21. "ESTWID,Width of the Time Interval field in the Gate Control List This field indicates the width of the Configured Time Interval Field" "0: Width not configured,1: 16,2: 20,3: 24" newline bitfld.long 0xC 17.--19. "ESTDEP,Depth of the Gate Control List This field indicates the depth of Gate Control list expressed as Log2(DWC_EQOS_EST_DEP)-5" "0: No Depth configured,1: 64,2: 128,3: 256,4: 512,5: 1024,?,?" newline bitfld.long 0xC 16. "ESTSEL,Enhancements to Scheduled Traffic Enable This bit is set to 1 when the Enable Enhancements to Scheduling Traffic feature is selected" "0: Enable Enhancements to Scheduling Traffic..,1: Enable Enhancements to Scheduling Traffic.." newline bitfld.long 0xC 15. "Reserved_15,Reserved." "0,1" newline bitfld.long 0xC 13.--14. "FRPES,Flexible Receive Parser Table Entries size This field indicates the Max Number of Parser Entries supported by Flexible Receive Parser" "0: 64 Entries,1: 128 Entries,2: 256 Entries,?" newline bitfld.long 0xC 11.--12. "FRPBS,Flexible Receive Parser Buffer size This field indicates the supported Max Number of bytes of the packet data to be Parsed by Flexible Receive Parser" "0: 64 Bytes,1: 128 Bytes,2: 256 Bytes,?" newline bitfld.long 0xC 10. "FRPSEL,Flexible Receive Parser Selected This bit is set to 1 when the Enable Flexible Programmable Receive Parser option is selected" "0: Flexible Receive Parser feature is not selected,1: Flexible Receive Parser feature is selected" newline bitfld.long 0xC 9. "PDUPSEL,Broadcast/Multicast Packet Duplication This bit is set to 1 when the Broadcast/Multicast Packet Duplication feature is selected" "0: Broadcast/Multicast Packet Duplication feature..,1: Broadcast/Multicast Packet Duplication feature.." newline bitfld.long 0xC 6.--8. "Reserved_7_6,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 5. "DVLAN,Double VLAN Tag Processing Selected This bit is set to 1 when the Enable Double VLAN Processing Feature is selected" "0: Double VLAN option is not selected,1: Double VLAN option is selected" newline bitfld.long 0xC 4. "CBTISEL,Queue/Channel based VLAN tag insertion on Tx Enable This bit is set to 1 when the Enable Queue/Channel based VLAN tag insertion on Tx Feature is selected" "0: Enable Queue/Channel based VLAN tag insertion on..,1: Enable Queue/Channel based VLAN tag insertion on.." newline bitfld.long 0xC 3. "Reserved_3,Reserved." "0,1" newline bitfld.long 0xC 0.--2. "NRVF,Number of Extended VLAN Tag Filters Enabled This field indicates the Number of Extended VLAN Tag Filters selected:" "0: No Extended Rx VLAN Filters,1: 4 Extended Rx VLAN Filters,2: 8 Extended Rx VLAN Filters,3: 16 Extended Rx VLAN Filters,4: 24 Extended Rx VLAN Filters,5: 32 Extended Rx VLAN Filters,?,?" group.long 0x140++0x3 line.long 0x0 "MAC_DPP_FSM_Interrupt_Status,This register contains the status of Automotive Safety related Data Path Parity Errors. Interface Timeout Errors. FSM State Parity Errors and FSM State Timeout Errors. All the non-Reserved bits are cleared on read." rbitfld.long 0x0 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 28. "Reserved_DCPES,Reserved." "0,1" newline bitfld.long 0x0 27. "MRWCPES,MTL RWC data path Parity checker Error Status This filed when set indicates that parity error is detected on the MTL RWC data interface (or at PC12 as shown in Recieve data path parity protection diagram)" "0: MTL RWC data path Parity checker Error Status..,1: MTL RWC data path Parity checker Error Status.." newline bitfld.long 0x0 26. "MTFCPES,MAC TFC data path Parity checker Error Status This filed when set indicates that parity error is detected on the MAC TFC data interface (or at PC11 as shown in Transmit data path parity protection diagram)" "0: MAC TFC data path Parity checker Error Status..,1: MAC TFC data path Parity checker Error Status.." newline bitfld.long 0x0 25. "MTBUPES,MAC TBU data path Parity checker Error Status This filed when set indicates that parity error is detected on the MAC TBU data interface (or at PC10 as shown in Transmit data path parity protection diagram)" "0: MAC TBU data path Parity checker Error Status..,1: MAC TBU data path Parity checker Error Status.." newline bitfld.long 0x0 24. "FSMPES,FSM State Parity Error Status This field when set indicates one of the FSMs State registers has a parity error detected" "0: FSM State Parity Error Status not detected,1: FSM State Parity Error Status detected" newline hexmask.long.byte 0x0 18.--23. 1. "Reserved_23_18,Reserved." newline rbitfld.long 0x0 17. "Reserved_SLVTES,Reserved." "0,1" newline bitfld.long 0x0 16. "MSTTES,Master Read/Write Timeout Error Status This field when set indicates that an Application/CSR Timeout has occurred on the master (AXI/AHB/ARI/ATI) interface" "0: Master Read/Write Timeout Error Status not..,1: Master Read/Write Timeout Error Status detected" newline rbitfld.long 0x0 15. "Reserved_RVCTES,Reserved." "0,1" newline rbitfld.long 0x0 14. "Reserved_R125ES,Reserved." "0,1" newline rbitfld.long 0x0 13. "Reserved_T125ES,Reserved." "0,1" newline bitfld.long 0x0 12. "PTES,PTP FSM Timeout Error Status This field when set indicates that one of the PTP FSM Timeout has occurred" "0: PTP FSM Timeout Error Status not detected,1: PTP FSM Timeout Error Status detected" newline bitfld.long 0x0 11. "ATES,APP FSM Timeout Error Status This field when set indicates that one of the APP FSM Timeout has occurred" "0: APP FSM Timeout Error Status not detected,1: APP FSM Timeout Error Status detected" newline rbitfld.long 0x0 10. "Reserved_CTES,Reserved." "0,1" newline bitfld.long 0x0 9. "RTES,Rx FSM Timeout Error Status This field when set indicates that one of the Rx FSM Timeout has occurred" "0: Rx FSM Timeout Error Status not detected,1: Rx FSM Timeout Error Status detected" newline bitfld.long 0x0 8. "TTES,Tx FSM Timeout Error Status This field when set indicates that one of the Tx FSM Timeout has occurred" "0: Tx FSM Timeout Error Status not detected,1: Tx FSM Timeout Error Status detected" newline rbitfld.long 0x0 7. "Reserved_ASRPES,Reserved." "0,1" newline rbitfld.long 0x0 6. "Reserved_CWPES,Reserved." "0,1" newline bitfld.long 0x0 5. "ARPES,Application Receive interface data path Parity Error Status This bit when set indicates that a parity error is detected at the following checkers based on the system configuration: - In MTL configuration (DWC_EQOS_SYS=1) parity checker (PC6 as.." "0: Application Receive interface data path Parity..,1: Application Receive interface data path Parity.." newline bitfld.long 0x0 4. "MTSPES,MTL TX Status data path Parity checker Error Status This filed when set indicates that parity error is detected on the MTL TX Status data on ati interface (or at PC5 as shown in Transmit data path parity protection diagram)" "0: MTL TX Status data path Parity checker Error..,1: MTL TX Status data path Parity checker Error.." newline bitfld.long 0x0 3. "MPES,MTL data path Parity checker Error Status This bit when set indicates that a parity error is detected at the MTL transmit write controller parity checker (or at PC4 as shown in Transmit data path parity protection diagram)" "0: MTL data path Parity checker Error Status not..,1: MTL data path Parity checker Error Status detected" newline bitfld.long 0x0 2. "RDPES,Read Descriptor Parity checker Error Status This bit when set indicates that a parity error is detected at the DMA Read descriptor parity checker (or at PC3 as shown in Transmit data path parity protection diagram)" "0: Read Descriptor Parity checker Error Status not..,1: Read Descriptor Parity checker Error Status.." newline rbitfld.long 0x0 1. "Reserved_TPES,Reserved." "0,1" newline rbitfld.long 0x0 0. "Reserved_ATPES,Reserved." "0,1" group.long 0x148++0xB line.long 0x0 "MAC_FSM_Control,This register is used to control the FSM State parity and timeout error injection in Debug mode." rbitfld.long 0x0 31. "Reserved_RVCLGRNML,Reserved." "0,1" newline rbitfld.long 0x0 30. "Reserved_R125LGRNML,Reserved." "0,1" newline rbitfld.long 0x0 29. "Reserved_T125LGRNML,Reserved." "0,1" newline bitfld.long 0x0 28. "PLGRNML,PTP Large/Normal Mode Select This field when set indicates that large mode tic generation is used for PTP domain else normal mode tic generation is used" "0: normal mode tic generation is used for PTP domain,1: large mode tic generation is used for PTP domain" newline bitfld.long 0x0 27. "ALGRNML,APP Large/Normal Mode Select This field when set indicates that large mode tic generation is used for APP domain else normal mode tic generation is used" "0: normal mode tic generation is used for APP domain,1: large mode tic generation is used for APP domain" newline rbitfld.long 0x0 26. "Reserved_CLGRNML,Reserved." "0,1" newline bitfld.long 0x0 25. "RLGRNML,Rx Large/Normal Mode Select This field when set indicates that large mode tic generation is used for Rx domain else normal mode tic generation is used" "0: normal mode tic generation is used for Rx domain,1: large mode tic generation is used for Rx domain" newline bitfld.long 0x0 24. "TLGRNML,Tx Large/Normal Mode Select This field when set indicates that large mode tic generation is used for Tx domain else normal mode tic generation is used" "0: normal mode tic generation is used for Tx domain,1: large mode tic generation is used for Tx domain" newline rbitfld.long 0x0 23. "Reserved_RVCPEIN,Reserved." "0,1" newline rbitfld.long 0x0 22. "Reserved_R125PEIN,Reserved." "0,1" newline rbitfld.long 0x0 21. "Reserved_T125PEIN,Reserved." "0,1" newline bitfld.long 0x0 20. "PPEIN,PTP FSM Parity Error Injection This field when set indicates that Error Injection for PTP FSM Parity is enabled" "0: PTP FSM Parity Error Injection is disabled,1: PTP FSM Parity Error Injection is enabled" newline bitfld.long 0x0 19. "APEIN,APP FSM Parity Error Injection This field when set indicates that Error Injection for APP FSM Parity is enabled" "0: APP FSM Parity Error Injection is disabled,1: APP FSM Parity Error Injection is enabled" newline rbitfld.long 0x0 18. "Reserved_CPEIN,Reserved." "0,1" newline bitfld.long 0x0 17. "RPEIN,Rx FSM Parity Error Injection This field when set indicates that Error Injection for RX FSM Parity is enabled" "0: Rx FSM Parity Error Injection is disabled,1: Rx FSM Parity Error Injection is enabled" newline bitfld.long 0x0 16. "TPEIN,Tx FSM Parity Error Injection This field when set indicates that Error Injection for TX FSM Parity is enabled" "0: Tx FSM Parity Error Injection is disabled,1: Tx FSM Parity Error Injection is enabled" newline rbitfld.long 0x0 15. "Reserved_RVCTEIN,Reserved." "0,1" newline rbitfld.long 0x0 14. "Reserved_R125TEIN,Reserved." "0,1" newline rbitfld.long 0x0 13. "Reserved_T125TEIN,Reserved." "0,1" newline bitfld.long 0x0 12. "PTEIN,PTP FSM Timeout Error Injection This field when set indicates that Error Injection for PTP FSM timeout is enabled" "0: PTP FSM Timeout Error Injection is disabled,1: PTP FSM Timeout Error Injection is enabled" newline bitfld.long 0x0 11. "ATEIN,APP FSM Timeout Error Injection This field when set indicates that Error Injection for APP FSM timeout is enabled" "0: APP FSM Timeout Error Injection is disabled,1: APP FSM Timeout Error Injection is enabled" newline rbitfld.long 0x0 10. "Reserved_CTEIN,Reserved." "0,1" newline bitfld.long 0x0 9. "RTEIN,Rx FSM Timeout Error Injection This field when set indicates that Error Injection for RX FSM timeout is enabled" "0: Rx FSM Timeout Error Injection is disabled,1: Rx FSM Timeout Error Injection is enabled" newline bitfld.long 0x0 8. "TTEIN,Tx FSM Timeout Error Injection This field when set indicates that Error Injection for TX FSM timeout is enabled" "0: Tx FSM Timeout Error Injection is disabled,1: Tx FSM Timeout Error Injection is enabled" newline hexmask.long.byte 0x0 2.--7. 1. "Reserved_7_2,Reserved." newline bitfld.long 0x0 1. "PRTYEN,This bit when set indicates that the FSM parity feature is enabled." "0: FSM Parity feature is disabled,1: FSM Parity feature is enabled" newline bitfld.long 0x0 0. "TMOUTEN,This bit when set indicates that the FSM timeout feature is enabled." "0: FSM timeout feature is disabled,1: FSM timeout feature is enabled" line.long 0x4 "MAC_FSM_ACT_Timer,This register is used to select the FSM and Interface Timeout values." hexmask.long.byte 0x4 24.--31. 1. "Reserved_31_24,Reserved." newline hexmask.long.byte 0x4 20.--23. 1. "LTMRMD,Large Mode Timeout Value This field provides the mode value to be used for large mode FSM and other interface time outs" newline hexmask.long.byte 0x4 16.--19. 1. "NTMRMD,Normal Mode Timeout Value This field provides the value to be used for normal mode FSM and other interface time outs" newline hexmask.long.byte 0x4 10.--15. 1. "Reserved_15_10,Reserved." newline hexmask.long.word 0x4 0.--9. 1. "TMR,CSR Clocks for 1us Tic This field indicates the number of CSR clocks required to generate 1us tic." line.long 0x8 "SCS_REG1,NXP Reserved Register" hexmask.long 0x8 0.--31. 1. "MAC_SCS1,NXP Reserved All the bits must be set to '0'" group.long 0x200++0x7 line.long 0x0 "MAC_MDIO_Address,The MDIO Address register controls the management cycles to external PHY through a management interface." hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_28,Reserved." newline bitfld.long 0x0 27. "PSE,Preamble Suppression Enable When this bit is set the SMA suppresses the 32-bit preamble and transmits MDIO frames with only 1 preamble bit" "0: Preamble Suppression disabled,1: Preamble Suppression enabled" newline bitfld.long 0x0 26. "BTB,Back to Back transactions When this bit is set and the NTC has value greater than 0 then the MAC informs the completion of a read or write command at the end of frame transfer (before the trailing clocks are transmitted)" "0: Back to Back transactions disabled,1: Back to Back transactions enabled" newline hexmask.long.byte 0x0 21.--25. 1. "PA,Physical Layer Address This field indicates which Clause 22 PHY devices (out of 32 devices) the MAC is accessing" newline hexmask.long.byte 0x0 16.--20. 1. "RDA,Register/Device Address These bits select the PHY register in selected Clause 22 PHY device" newline rbitfld.long 0x0 15. "Reserved_15,Reserved." "0,1" newline bitfld.long 0x0 12.--14. "NTC,Number of Trailing Clocks This field controls the number of trailing clock cycles generated on gmii_mdc_o (MDC) after the end of transmission of MDIO frame" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "CR,CSR Clock Range The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design: - 0000: CSR clock = 60-100 MHz; MDC clock = CSR clock/42 - 0001: CSR clock = 100-150 MHz; MDC clock = CSR.." newline rbitfld.long 0x0 5.--7. "Reserved_7_5,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "SKAP,Skip Address Packet When this bit is set the SMA does not send the address packets before read write or post-read increment address packets" "0: Skip Address Packet is disabled,1: Skip Address Packet is enabled" newline bitfld.long 0x0 3. "GOC_1,GMII Operation Command 1 This bit is higher bit of the operation command to the PHY or RevMII GOC_1 and GOC_O is encoded as follows: - 00: Reserved - 01: Write - 10: Post Read Increment Address for Clause 45 PHY - 11: Read When Clause 22 PHY or.." "0: Reserved,1: Write" newline bitfld.long 0x0 2. "GOC_0,GMII Operation Command 0 This is the lower bit of the operation command to the PHY or RevMII" "0: GMII Operation Command 0 is disabled,1: GMII Operation Command 0 is enabled" newline bitfld.long 0x0 1. "C45E,Clause 45 PHY Enable When this bit is set Clause 45 capable PHY is connected to MDIO" "0: Clause 45 PHY is disabled,1: Clause 45 PHY is enabled" newline bitfld.long 0x0 0. "GB,GMII Busy The application sets this bit to instruct the SMA to initiate a Read or Write access to the MDIO slave" "0: GMII Busy is disabled,1: GMII Busy is enabled" line.long 0x4 "MAC_MDIO_Data,The MDIO Data register stores the Write data to be written to the PHY register located at the address specified in MAC_MDIO_Address. This register also stores the Read data from the PHY register located at the address specified by MDIO.." hexmask.long.word 0x4 16.--31. 1. "RA,Register Address This field is valid only when C45E is set" newline hexmask.long.word 0x4 0.--15. 1. "GD,GMII Data This field contains the 16-bit data value read from the PHY or RevMII after a Management Read operation or the 16-bit data value to be written to the PHY or RevMII before a Management Write operation" group.long 0x210++0x3 line.long 0x0 "MAC_ARP_Address,The ARP Address register contains the IPv4 Destination Address of the MAC." hexmask.long 0x0 0.--31. 1. "ARPPA,ARP Protocol Address This field contains the IPv4 Destination Address of the MAC" group.long 0x230++0xB line.long 0x0 "MAC_CSR_SW_Ctrl,This register contains software programmable controls for changing the CSR access response and status bits clearing." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_31_9,Reserved." newline bitfld.long 0x0 8. "SEEN,Slave Error Response Enable When this bit is set the MAC responds with Slave Error for accesses to reserved registers in CSR space" "0: Slave Error Response is disabled,1: Slave Error Response is enabled" newline hexmask.long.byte 0x0 1.--7. 1. "Reserved_7_1,Reserved." newline bitfld.long 0x0 0. "RCWE,Register Clear on Write 1 Enable When this bit is set the access mode of some register fields changes to Clear on Write 1 the application needs to set that respective bit to 1 to clear it" "0: Register Clear on Write 1 is disabled,1: Register Clear on Write 1 is enabled" line.long 0x4 "MAC_FPE_CTRL_STS,This register controls the operation of Frame Preemption." hexmask.long.word 0x4 20.--31. 1. "Reserved_31_20,Reserved." newline bitfld.long 0x4 19. "TRSP,Transmitted Respond Frame Set when a Respond mPacket is transmitted (triggered by setting SRSP field)" "0: Not transmitted Respond Frame,1: transmitted Respond Frame" newline bitfld.long 0x4 18. "TVER,Transmitted Verify Frame Set when a Verify mPacket is transmitted (triggered by setting SVER field)" "0: Not transmitted Verify Frame,1: transmitted Verify Frame" newline bitfld.long 0x4 17. "RRSP,Received Respond Frame Set when a Respond mPacket is received" "0: Not received Respond Frame,1: Received Respond Frame" newline bitfld.long 0x4 16. "RVER,Received Verify Frame Set when a Verify mPacket is received" "0: Not received Verify Frame,1: Received Verify Frame" newline hexmask.long.word 0x4 4.--15. 1. "Reserved_15_4,Reserved." newline bitfld.long 0x4 3. "S1_SET_0,NXP Reserved Must be set to '0'" "0,1" newline bitfld.long 0x4 2. "SRSP,Send Respond mPacket When set indicates hardware to send a Respond mPacket" "0: Send Respond mPacket is disabled,1: Send Respond mPacket is enabled" newline bitfld.long 0x4 1. "SVER,Send Verify mPacket When set indicates hardware to send a verify mPacket" "0: Send Verify mPacket is disabled,1: Send Verify mPacket is enabled" newline bitfld.long 0x4 0. "EFPE,Enable Tx Frame Preemption When set Frame Preemption Tx functionality is enabled." "0: Tx Frame Preemption is disabled,1: Tx Frame Preemption is enabled" line.long 0x8 "MAC_Ext_Cfg1,This register contains Split mode control field and offset field for Split Header feature." hexmask.long.byte 0x8 25.--31. 1. "Reserved_31_25,Reserved." newline bitfld.long 0x8 24. "SAVE,Split AV Enable - When this bit is set to 1 and the received packet is an AV Type packet the header is split at SAVO bytes from the beginning of Length/Type field of the packet for L2 Split" "0,1" newline rbitfld.long 0x8 23. "Reserved_23,Reserved." "0,1" newline hexmask.long.byte 0x8 16.--22. 1. "SAVO,Split AV Offset When SAVE bit is set to 1 and the received packet is an AV Type packet these bits indicate the value of the offset from the beginning of Length/Type field at which header should be split when appropriate SPLM is selected" newline hexmask.long.byte 0x8 10.--15. 1. "Reserved_15_10,Reserved." newline bitfld.long 0x8 8.--9. "SPLM,Split Mode These bits indicate the mode of splitting the incoming Rx packets. They are" "0: Split at L3/L4 header,1: Split at L2 header with an offset. Always Split..,2: Combination mode: Split similar to SPLM=00 for..,?" newline rbitfld.long 0x8 7. "Reserved_7,Reserved." "0,1" newline hexmask.long.byte 0x8 0.--6. 1. "SPLOFST,Split Offset These bits indicate the value of offset from the beginning of Length/Type field at which header split should take place when the appropriate SPLM is selected" rgroup.long 0x240++0x3 line.long 0x0 "MAC_Presn_Time_ns,This register contains the 32-bit binary rollover equivalent time of the PTP System Time in ns Exists when DWC_EQOS_FLEXI_PPS_OUT_EN is configured" hexmask.long 0x0 0.--31. 1. "MPTN,MAC 1722 Presentation Time in ns These bits indicate the value of the 32-bit binary rollover equivalent time of the PTP System Time in ns" group.long 0x244++0x3 line.long 0x0 "MAC_Presn_Time_Updt,This field holds the 32-bit value of MAC 1722 Presentation Time in ns. that should be added to the Current Presentation Time Counter value. Init happens when TSINIT is set. and update happens when the TSUPDT bit is set (TSINIT and.." hexmask.long 0x0 0.--31. 1. "MPTU,MAC 1722 Presentation Time Update This field holds the init value or the update value for the presentation time" group.long 0x300++0x17 line.long 0x0 "MAC_Address0_High,The MAC Address0 High register holds the upper 16 bits of the first 6-byte MAC address of the station. The first DA byte that is received on the (G)MII interface corresponds to the LS byte (Bits [7:0]) of the MAC Address Low register." rbitfld.long 0x0 31. "AE,Address Enable This bit is always set to 1." "0: INVALID : This bit must be always set to 1,1: This bit is always set to 1" newline hexmask.long.word 0x0 19.--30. 1. "Reserved_30_y,Reserved." newline bitfld.long 0x0 16.--18. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address0 content is routed" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--15. 1. "ADDRHI,MAC Address0[47:32] This field contains the upper 16 bits [47:32] of the first 6-byte MAC address" line.long 0x4 "MAC_Address0_Low,The MAC Address0 Low register holds the lower 32 bits of the 6-byte first MAC address of the station." hexmask.long 0x4 0.--31. 1. "ADDRLO,MAC Address0[31:0] This field contains the lower 32 bits of the first 6-byte MAC address" line.long 0x8 "MAC_Address1_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x8 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled" newline bitfld.long 0x8 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address" newline hexmask.long.byte 0x8 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" newline hexmask.long.byte 0x8 19.--23. 1. "Reserved_23_y,Reserved." newline bitfld.long 0x8 16.--18. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x8 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0xC "MAC_Address1_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0xC 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address" line.long 0x10 "MAC_Address2_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x10 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled" newline bitfld.long 0x10 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address" newline hexmask.long.byte 0x10 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" newline hexmask.long.byte 0x10 19.--23. 1. "Reserved_23_y,Reserved." newline bitfld.long 0x10 16.--18. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x10 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0x14 "MAC_Address2_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0x14 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address" group.long 0x700++0x3 line.long 0x0 "MMC_Control,This register establishes the operating mode of MMC." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_31_9,Reserved." newline bitfld.long 0x0 8. "UCDBC,Update MMC Counters for Dropped Broadcast Packets Note: The CNTRST bit has a higher priority than the CNTPRST bit" "0: Update MMC Counters for Dropped Broadcast..,1: Update MMC Counters for Dropped Broadcast.." newline rbitfld.long 0x0 6.--7. "Reserved_7_6,Reserved." "0,1,2,3" newline bitfld.long 0x0 5. "CNTPRSTLVL,Full-Half Preset When this bit is low and the CNTPRST bit is set all MMC counters get preset to almost-half value" "0: Full-Half Preset is disabled,1: Full-Half Preset is enabled" newline bitfld.long 0x0 4. "CNTPRST,Counters Preset When this bit is set all counters are initialized or preset to almost full or almost half according to the CNTPRSTLVL bit" "0: Counters Preset is disabled,1: Counters Preset is enabled" newline bitfld.long 0x0 3. "CNTFREEZ,MMC Counter Freeze When this bit is set it freezes all MMC counters to their current value" "0: MMC Counter Freeze is disabled,1: MMC Counter Freeze is enabled" newline bitfld.long 0x0 2. "RSTONRD,Reset on Read When this bit is set the MMC counters are reset to zero after Read (self-clearing after reset)" "0: Reset on Read is disabled,1: Reset on Read is enabled" newline bitfld.long 0x0 1. "CNTSTOPRO,Counter Stop Rollover When this bit is set the counter does not roll over to zero after reaching the maximum value" "0: Counter Stop Rollover is disabled,1: Counter Stop Rollover is enabled" newline bitfld.long 0x0 0. "CNTRST,Counters Reset When this bit is set all counters are reset" "0: Counters are not reset,1: All counters are reset" rgroup.long 0x704++0x7 line.long 0x0 "MMC_Rx_Interrupt,This register maintains the interrupts generated from all Receive statistics counters. The MMC Receive Interrupt register maintains the interrupts that are generated when the following occur: - Receive statistic counters reach half of.." hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_28,Reserved." newline bitfld.long 0x0 27. "Reserved_RXLPITRCIS,Reserved." "0,1" newline bitfld.long 0x0 26. "Reserved_RXLPIUSCIS,Reserved." "0,1" newline bitfld.long 0x0 25. "RXCTRLPIS,MMC Receive Control Packet Counter Interrupt Status This bit is set when the rxctrlpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Control Packet Counter Interrupt..,1: MMC Receive Control Packet Counter Interrupt.." newline bitfld.long 0x0 24. "RXRCVERRPIS,MMC Receive Error Packet Counter Interrupt Status This bit is set when the rxrcverror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Error Packet Counter Interrupt..,1: MMC Receive Error Packet Counter Interrupt.." newline bitfld.long 0x0 23. "RXWDOGPIS,MMC Receive Watchdog Error Packet Counter Interrupt Status This bit is set when the rxwatchdog error counter reaches half of the maximum value or the maximum value" "0: MMC Receive Watchdog Error Packet Counter..,1: MMC Receive Watchdog Error Packet Counter.." newline bitfld.long 0x0 22. "RXVLANGBPIS,MMC Receive VLAN Good Bad Packet Counter Interrupt Status This bit is set when the rxvlanpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive VLAN Good Bad Packet Counter..,1: MMC Receive VLAN Good Bad Packet Counter.." newline bitfld.long 0x0 21. "RXFOVPIS,MMC Receive FIFO Overflow Packet Counter Interrupt Status This bit is set when the rxfifooverflow counter reaches half of the maximum value or the maximum value" "0: MMC Receive FIFO Overflow Packet Counter..,1: MMC Receive FIFO Overflow Packet Counter.." newline bitfld.long 0x0 20. "RXPAUSPIS,MMC Receive Pause Packet Counter Interrupt Status This bit is set when the rxpausepackets counter reaches half of the maximum value or the maximum value" "0: MMC Receive Pause Packet Counter Interrupt..,1: MMC Receive Pause Packet Counter Interrupt.." newline bitfld.long 0x0 19. "RXORANGEPIS,MMC Receive Out Of Range Error Packet Counter Interrupt Status" "0: MMC Receive Out Of Range Error Packet Counter..,1: MMC Receive Out Of Range Error Packet Counter.." newline bitfld.long 0x0 18. "RXLENERPIS,MMC Receive Length Error Packet Counter Interrupt Status This bit is set when the rxlengtherror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Length Error Packet Counter..,1: MMC Receive Length Error Packet Counter.." newline bitfld.long 0x0 17. "RXUCGPIS,MMC Receive Unicast Good Packet Counter Interrupt Status This bit is set when the rxunicastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Unicast Good Packet Counter..,1: MMC Receive Unicast Good Packet Counter.." newline bitfld.long 0x0 16. "RX1024TMAXOCTGBPIS,MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 1024 to Maximum Octet Good Bad..,1: MMC Receive 1024 to Maximum Octet Good Bad.." newline bitfld.long 0x0 15. "RX512T1023OCTGBPIS,MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 512 to 1023 Octet Good Bad Packet..,1: MMC Receive 512 to 1023 Octet Good Bad Packet.." newline bitfld.long 0x0 14. "RX256T511OCTGBPIS,MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 256 to 511 Octet Good Bad Packet..,1: MMC Receive 256 to 511 Octet Good Bad Packet.." newline bitfld.long 0x0 13. "RX128T255OCTGBPIS,MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 128 to 255 Octet Good Bad Packet..,1: MMC Receive 128 to 255 Octet Good Bad Packet.." newline bitfld.long 0x0 12. "RX65T127OCTGBPIS,MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 65 to 127 Octet Good Bad Packet..,1: MMC Receive 65 to 127 Octet Good Bad Packet.." newline bitfld.long 0x0 11. "RX64OCTGBPIS,MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx64octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 64 Octet Good Bad Packet Counter..,1: MMC Receive 64 Octet Good Bad Packet Counter.." newline bitfld.long 0x0 10. "RXOSIZEGPIS,MMC Receive Oversize Good Packet Counter Interrupt Status This bit is set when the rxoversize_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Oversize Good Packet Counter..,1: MMC Receive Oversize Good Packet Counter.." newline bitfld.long 0x0 9. "RXUSIZEGPIS,MMC Receive Undersize Good Packet Counter Interrupt Status This bit is set when the rxundersize_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Undersize Good Packet Counter..,1: MMC Receive Undersize Good Packet Counter.." newline bitfld.long 0x0 8. "RXJABERPIS,MMC Receive Jabber Error Packet Counter Interrupt Status This bit is set when the rxjabbererror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Jabber Error Packet Counter..,1: MMC Receive Jabber Error Packet Counter.." newline bitfld.long 0x0 7. "RXRUNTPIS,MMC Receive Runt Packet Counter Interrupt Status This bit is set when the rxrunterror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Runt Packet Counter Interrupt Status..,1: MMC Receive Runt Packet Counter Interrupt Status.." newline bitfld.long 0x0 6. "RXALGNERPIS,MMC Receive Alignment Error Packet Counter Interrupt Status This bit is set when the rxalignmenterror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Alignment Error Packet Counter..,1: MMC Receive Alignment Error Packet Counter.." newline bitfld.long 0x0 5. "RXCRCERPIS,MMC Receive CRC Error Packet Counter Interrupt Status This bit is set when the rxcrcerror counter reaches half of the maximum value or the maximum value" "0: MMC Receive CRC Error Packet Counter Interrupt..,1: MMC Receive CRC Error Packet Counter Interrupt.." newline bitfld.long 0x0 4. "RXMCGPIS,MMC Receive Multicast Good Packet Counter Interrupt Status This bit is set when the rxmulticastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Multicast Good Packet Counter..,1: MMC Receive Multicast Good Packet Counter.." newline bitfld.long 0x0 3. "RXBCGPIS,MMC Receive Broadcast Good Packet Counter Interrupt Status This bit is set when the rxbroadcastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Broadcast Good Packet Counter..,1: MMC Receive Broadcast Good Packet Counter.." newline bitfld.long 0x0 2. "RXGOCTIS,MMC Receive Good Octet Counter Interrupt Status This bit is set when the rxoctetcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Octet Counter Interrupt Status..,1: MMC Receive Good Octet Counter Interrupt Status.." newline bitfld.long 0x0 1. "RXGBOCTIS,MMC Receive Good Bad Octet Counter Interrupt Status This bit is set when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Bad Octet Counter Interrupt..,1: MMC Receive Good Bad Octet Counter Interrupt.." newline bitfld.long 0x0 0. "RXGBPKTIS,MMC Receive Good Bad Packet Counter Interrupt Status This bit is set when the rxpacketcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Bad Packet Counter Interrupt..,1: MMC Receive Good Bad Packet Counter Interrupt.." line.long 0x4 "MMC_Tx_Interrupt,This register maintains the interrupts generated from all Transmit statistics counters. The MMC Transmit Interrupt register maintains the interrupts generated when transmit statistic counters reach half their maximum values (0x8000_0000.." hexmask.long.byte 0x4 28.--31. 1. "Reserved_31_28,Reserved." newline bitfld.long 0x4 27. "Reserved_TXLPITRCIS,Reserved." "0,1" newline bitfld.long 0x4 26. "Reserved_TXLPIUSCIS,Reserved." "0,1" newline bitfld.long 0x4 25. "TXOSIZEGPIS,MMC Transmit Oversize Good Packet Counter Interrupt Status This bit is set when the txoversize_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Oversize Good Packet Counter..,1: MMC Transmit Oversize Good Packet Counter.." newline bitfld.long 0x4 24. "TXVLANGPIS,MMC Transmit VLAN Good Packet Counter Interrupt Status This bit is set when the txvlanpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit VLAN Good Packet Counter Interrupt..,1: MMC Transmit VLAN Good Packet Counter Interrupt.." newline bitfld.long 0x4 23. "TXPAUSPIS,MMC Transmit Pause Packet Counter Interrupt Status This bit is set when the txpausepacketserror counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Pause Packet Counter Interrupt..,1: MMC Transmit Pause Packet Counter Interrupt.." newline bitfld.long 0x4 22. "TXEXDEFPIS,MMC Transmit Excessive Deferral Packet Counter Interrupt Status This bit is set when the txexcessdef counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Excessive Deferral Packet Counter..,1: MMC Transmit Excessive Deferral Packet Counter.." newline bitfld.long 0x4 21. "TXGPKTIS,MMC Transmit Good Packet Counter Interrupt Status This bit is set when the txpacketcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Packet Counter Interrupt..,1: MMC Transmit Good Packet Counter Interrupt.." newline bitfld.long 0x4 20. "TXGOCTIS,MMC Transmit Good Octet Counter Interrupt Status This bit is set when the txoctetcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Octet Counter Interrupt Status..,1: MMC Transmit Good Octet Counter Interrupt Status.." newline bitfld.long 0x4 19. "TXCARERPIS,MMC Transmit Carrier Error Packet Counter Interrupt Status This bit is set when the txcarriererror counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Carrier Error Packet Counter..,1: MMC Transmit Carrier Error Packet Counter.." newline bitfld.long 0x4 18. "TXEXCOLPIS,MMC Transmit Excessive Collision Packet Counter Interrupt Status This bit is set when the txexesscol counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Excessive Collision Packet Counter..,1: MMC Transmit Excessive Collision Packet Counter.." newline bitfld.long 0x4 17. "TXLATCOLPIS,MMC Transmit Late Collision Packet Counter Interrupt Status This bit is set when the txlatecol counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Late Collision Packet Counter..,1: MMC Transmit Late Collision Packet Counter.." newline bitfld.long 0x4 16. "TXDEFPIS,MMC Transmit Deferred Packet Counter Interrupt Status This bit is set when the txdeferred counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Deferred Packet Counter Interrupt..,1: MMC Transmit Deferred Packet Counter Interrupt.." newline bitfld.long 0x4 15. "TXMCOLGPIS,MMC Transmit Multiple Collision Good Packet Counter Interrupt Status This bit is set when the txmulticol_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multiple Collision Good Packet..,1: MMC Transmit Multiple Collision Good Packet.." newline bitfld.long 0x4 14. "TXSCOLGPIS,MMC Transmit Single Collision Good Packet Counter Interrupt Status This bit is set when the txsinglecol_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Single Collision Good Packet..,1: MMC Transmit Single Collision Good Packet.." newline bitfld.long 0x4 13. "TXUFLOWERPIS,MMC Transmit Underflow Error Packet Counter Interrupt Status This bit is set when the txunderflowerror counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Underflow Error Packet Counter..,1: MMC Transmit Underflow Error Packet Counter.." newline bitfld.long 0x4 12. "TXBCGBPIS,MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status This bit is set when the txbroadcastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Broadcast Good Bad Packet Counter..,1: MMC Transmit Broadcast Good Bad Packet Counter.." newline bitfld.long 0x4 11. "TXMCGBPIS,MMC Transmit Multicast Good Bad Packet Counter Interrupt Status The bit is set when the txmulticastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multicast Good Bad Packet Counter..,1: MMC Transmit Multicast Good Bad Packet Counter.." newline bitfld.long 0x4 10. "TXUCGBPIS,MMC Transmit Unicast Good Bad Packet Counter Interrupt Status This bit is set when the txunicastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Unicast Good Bad Packet Counter..,1: MMC Transmit Unicast Good Bad Packet Counter.." newline bitfld.long 0x4 9. "TX1024TMAXOCTGBPIS,MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 1024 to Maximum Octet Good Bad..,1: MMC Transmit 1024 to Maximum Octet Good Bad.." newline bitfld.long 0x4 8. "TX512T1023OCTGBPIS,MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 512 to 1023 Octet Good Bad Packet..,1: MMC Transmit 512 to 1023 Octet Good Bad Packet.." newline bitfld.long 0x4 7. "TX256T511OCTGBPIS,MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 256 to 511 Octet Good Bad Packet..,1: MMC Transmit 256 to 511 Octet Good Bad Packet.." newline bitfld.long 0x4 6. "TX128T255OCTGBPIS,MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 128 to 255 Octet Good Bad Packet..,1: MMC Transmit 128 to 255 Octet Good Bad Packet.." newline bitfld.long 0x4 5. "TX65T127OCTGBPIS,MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx65to127octets_gb counter reaches half the maximum value and also when it reaches the maximum value" "0: MMC Transmit 65 to 127 Octet Good Bad Packet..,1: MMC Transmit 65 to 127 Octet Good Bad Packet.." newline bitfld.long 0x4 4. "TX64OCTGBPIS,MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx64octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 64 Octet Good Bad Packet Counter..,1: MMC Transmit 64 Octet Good Bad Packet Counter.." newline bitfld.long 0x4 3. "TXMCGPIS,MMC Transmit Multicast Good Packet Counter Interrupt Status This bit is set when the txmulticastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multicast Good Packet Counter..,1: MMC Transmit Multicast Good Packet Counter.." newline bitfld.long 0x4 2. "TXBCGPIS,MMC Transmit Broadcast Good Packet Counter Interrupt Status This bit is set when the txbroadcastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Broadcast Good Packet Counter..,1: MMC Transmit Broadcast Good Packet Counter.." newline bitfld.long 0x4 1. "TXGBPKTIS,MMC Transmit Good Bad Packet Counter Interrupt Status This bit is set when the txpacketcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Bad Packet Counter Interrupt..,1: MMC Transmit Good Bad Packet Counter Interrupt.." newline bitfld.long 0x4 0. "TXGBOCTIS,MMC Transmit Good Bad Octet Counter Interrupt Status This bit is set when the txoctetcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Bad Octet Counter Interrupt..,1: MMC Transmit Good Bad Octet Counter Interrupt.." group.long 0x70C++0x7 line.long 0x0 "MMC_Rx_Interrupt_Mask,This register maintains the masks for interrupts generated from all Receive statistics counters. The MMC Receive Interrupt Mask register maintains the masks for the interrupts generated when receive statistic counters reach half of.." hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_28,Reserved." newline rbitfld.long 0x0 27. "Reserved_RXLPITRCIM,Reserved." "0,1" newline rbitfld.long 0x0 26. "Reserved_RXLPIUSCIM,Reserved." "0,1" newline bitfld.long 0x0 25. "RXCTRLPIM,MMC Receive Control Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxctrlpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Control Packet Counter Interrupt..,1: MMC Receive Control Packet Counter Interrupt.." newline bitfld.long 0x0 24. "RXRCVERRPIM,MMC Receive Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Error Packet Counter Interrupt Mask..,1: MMC Receive Error Packet Counter Interrupt Mask.." newline bitfld.long 0x0 23. "RXWDOGPIM,MMC Receive Watchdog Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value" "0: MMC Receive Watchdog Error Packet Counter..,1: MMC Receive Watchdog Error Packet Counter.." newline bitfld.long 0x0 22. "RXVLANGBPIM,MMC Receive VLAN Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxvlanpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive VLAN Good Bad Packet Counter..,1: MMC Receive VLAN Good Bad Packet Counter.." newline bitfld.long 0x0 21. "RXFOVPIM,MMC Receive FIFO Overflow Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value" "0: MMC Receive FIFO Overflow Packet Counter..,1: MMC Receive FIFO Overflow Packet Counter.." newline bitfld.long 0x0 20. "RXPAUSPIM,MMC Receive Pause Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxpausepackets counter reaches half of the maximum value or the maximum value" "0: MMC Receive Pause Packet Counter Interrupt Mask..,1: MMC Receive Pause Packet Counter Interrupt Mask.." newline bitfld.long 0x0 19. "RXORANGEPIM,MMC Receive Out Of Range Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the maximum value" "0: MMC Receive Out Of Range Error Packet Counter..,1: MMC Receive Out Of Range Error Packet Counter.." newline bitfld.long 0x0 18. "RXLENERPIM,MMC Receive Length Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Length Error Packet Counter..,1: MMC Receive Length Error Packet Counter.." newline bitfld.long 0x0 17. "RXUCGPIM,MMC Receive Unicast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxunicastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Unicast Good Packet Counter..,1: MMC Receive Unicast Good Packet Counter.." newline bitfld.long 0x0 16. "RX1024TMAXOCTGBPIM,MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask" "0: MMC Receive 1024 to Maximum Octet Good Bad..,1: MMC Receive 1024 to Maximum Octet Good Bad.." newline bitfld.long 0x0 15. "RX512T1023OCTGBPIM,MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 512 to 1023 Octet Good Bad Packet..,1: MMC Receive 512 to 1023 Octet Good Bad Packet.." newline bitfld.long 0x0 14. "RX256T511OCTGBPIM,MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 256 to 511 Octet Good Bad Packet..,1: MMC Receive 256 to 511 Octet Good Bad Packet.." newline bitfld.long 0x0 13. "RX128T255OCTGBPIM,MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 128 to 255 Octet Good Bad Packet..,1: MMC Receive 128 to 255 Octet Good Bad Packet.." newline bitfld.long 0x0 12. "RX65T127OCTGBPIM,MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 65 to 127 Octet Good Bad Packet..,1: MMC Receive 65 to 127 Octet Good Bad Packet.." newline bitfld.long 0x0 11. "RX64OCTGBPIM,MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 64 Octet Good Bad Packet Counter..,1: MMC Receive 64 Octet Good Bad Packet Counter.." newline bitfld.long 0x0 10. "RXOSIZEGPIM,MMC Receive Oversize Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Oversize Good Packet Counter..,1: MMC Receive Oversize Good Packet Counter.." newline bitfld.long 0x0 9. "RXUSIZEGPIM,MMC Receive Undersize Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Undersize Good Packet Counter..,1: MMC Receive Undersize Good Packet Counter.." newline bitfld.long 0x0 8. "RXJABERPIM,MMC Receive Jabber Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Jabber Error Packet Counter..,1: MMC Receive Jabber Error Packet Counter.." newline bitfld.long 0x0 7. "RXRUNTPIM,MMC Receive Runt Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxrunterror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Runt Packet Counter Interrupt Mask..,1: MMC Receive Runt Packet Counter Interrupt Mask.." newline bitfld.long 0x0 6. "RXALGNERPIM,MMC Receive Alignment Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxalignmenterror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Alignment Error Packet Counter..,1: MMC Receive Alignment Error Packet Counter.." newline bitfld.long 0x0 5. "RXCRCERPIM,MMC Receive CRC Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value" "0: MMC Receive CRC Error Packet Counter Interrupt..,1: MMC Receive CRC Error Packet Counter Interrupt.." newline bitfld.long 0x0 4. "RXMCGPIM,MMC Receive Multicast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxmulticastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Multicast Good Packet Counter..,1: MMC Receive Multicast Good Packet Counter.." newline bitfld.long 0x0 3. "RXBCGPIM,MMC Receive Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxbroadcastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Broadcast Good Packet Counter..,1: MMC Receive Broadcast Good Packet Counter.." newline bitfld.long 0x0 2. "RXGOCTIM,MMC Receive Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoctetcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Octet Counter Interrupt Mask is..,1: MMC Receive Good Octet Counter Interrupt Mask is.." newline bitfld.long 0x0 1. "RXGBOCTIM,MMC Receive Good Bad Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Bad Octet Counter Interrupt..,1: MMC Receive Good Bad Octet Counter Interrupt.." newline bitfld.long 0x0 0. "RXGBPKTIM,MMC Receive Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxpacketcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Bad Packet Counter Interrupt..,1: MMC Receive Good Bad Packet Counter Interrupt.." line.long 0x4 "MMC_Tx_Interrupt_Mask,This register maintains the masks for interrupts generated from all Transmit statistics counters. The MMC Transmit Interrupt Mask register maintains the masks for the interrupts generated when the transmit statistic counters reach.." hexmask.long.byte 0x4 28.--31. 1. "Reserved_31_28,Reserved." newline rbitfld.long 0x4 27. "Reserved_TXLPITRCIM,Reserved." "0,1" newline rbitfld.long 0x4 26. "Reserved_TXLPIUSCIM,Reserved." "0,1" newline bitfld.long 0x4 25. "TXOSIZEGPIM,MMC Transmit Oversize Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Oversize Good Packet Counter..,1: MMC Transmit Oversize Good Packet Counter.." newline bitfld.long 0x4 24. "TXVLANGPIM,MMC Transmit VLAN Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txvlanpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit VLAN Good Packet Counter Interrupt..,1: MMC Transmit VLAN Good Packet Counter Interrupt.." newline bitfld.long 0x4 23. "TXPAUSPIM,MMC Transmit Pause Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txpausepackets counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Pause Packet Counter Interrupt Mask..,1: MMC Transmit Pause Packet Counter Interrupt Mask.." newline bitfld.long 0x4 22. "TXEXDEFPIM,MMC Transmit Excessive Deferral Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Excessive Deferral Packet Counter..,1: MMC Transmit Excessive Deferral Packet Counter.." newline bitfld.long 0x4 21. "TXGPKTIM,MMC Transmit Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txpacketcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Packet Counter Interrupt Mask..,1: MMC Transmit Good Packet Counter Interrupt Mask.." newline bitfld.long 0x4 20. "TXGOCTIM,MMC Transmit Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the txoctetcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Octet Counter Interrupt Mask..,1: MMC Transmit Good Octet Counter Interrupt Mask.." newline bitfld.long 0x4 19. "TXCARERPIM,MMC Transmit Carrier Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txcarriererror counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Carrier Error Packet Counter..,1: MMC Transmit Carrier Error Packet Counter.." newline bitfld.long 0x4 18. "TXEXCOLPIM,MMC Transmit Excessive Collision Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Excessive Collision Packet Counter..,1: MMC Transmit Excessive Collision Packet Counter.." newline bitfld.long 0x4 17. "TXLATCOLPIM,MMC Transmit Late Collision Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Late Collision Packet Counter..,1: MMC Transmit Late Collision Packet Counter.." newline bitfld.long 0x4 16. "TXDEFPIM,MMC Transmit Deferred Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txdeferred counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Deferred Packet Counter Interrupt..,1: MMC Transmit Deferred Packet Counter Interrupt.." newline bitfld.long 0x4 15. "TXMCOLGPIM,MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multiple Collision Good Packet..,1: MMC Transmit Multiple Collision Good Packet.." newline bitfld.long 0x4 14. "TXSCOLGPIM,MMC Transmit Single Collision Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Single Collision Good Packet..,1: MMC Transmit Single Collision Good Packet.." newline bitfld.long 0x4 13. "TXUFLOWERPIM,MMC Transmit Underflow Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txunderflowerror counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Underflow Error Packet Counter..,1: MMC Transmit Underflow Error Packet Counter.." newline bitfld.long 0x4 12. "TXBCGBPIM,MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txbroadcastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Broadcast Good Bad Packet Counter..,1: MMC Transmit Broadcast Good Bad Packet Counter.." newline bitfld.long 0x4 11. "TXMCGBPIM,MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multicast Good Bad Packet Counter..,1: MMC Transmit Multicast Good Bad Packet Counter.." newline bitfld.long 0x4 10. "TXUCGBPIM,MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txunicastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Unicast Good Bad Packet Counter..,1: MMC Transmit Unicast Good Bad Packet Counter.." newline bitfld.long 0x4 9. "TX1024TMAXOCTGBPIM,MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 1024 to Maximum Octet Good Bad..,1: MMC Transmit 1024 to Maximum Octet Good Bad.." newline bitfld.long 0x4 8. "TX512T1023OCTGBPIM,MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 512 to 1023 Octet Good Bad Packet..,1: MMC Transmit 512 to 1023 Octet Good Bad Packet.." newline bitfld.long 0x4 7. "TX256T511OCTGBPIM,MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 256 to 511 Octet Good Bad Packet..,1: MMC Transmit 256 to 511 Octet Good Bad Packet.." newline bitfld.long 0x4 6. "TX128T255OCTGBPIM,MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 128 to 255 Octet Good Bad Packet..,1: MMC Transmit 128 to 255 Octet Good Bad Packet.." newline bitfld.long 0x4 5. "TX65T127OCTGBPIM,MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 65 to 127 Octet Good Bad Packet..,1: MMC Transmit 65 to 127 Octet Good Bad Packet.." newline bitfld.long 0x4 4. "TX64OCTGBPIM,MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 64 Octet Good Bad Packet Counter..,1: MMC Transmit 64 Octet Good Bad Packet Counter.." newline bitfld.long 0x4 3. "TXMCGPIM,MMC Transmit Multicast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multicast Good Packet Counter..,1: MMC Transmit Multicast Good Packet Counter.." newline bitfld.long 0x4 2. "TXBCGPIM,MMC Transmit Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txbroadcastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Broadcast Good Packet Counter..,1: MMC Transmit Broadcast Good Packet Counter.." newline bitfld.long 0x4 1. "TXGBPKTIM,MMC Transmit Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txpacketcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Bad Packet Counter Interrupt..,1: MMC Transmit Good Bad Packet Counter Interrupt.." newline bitfld.long 0x4 0. "TXGBOCTIM,MMC Transmit Good Bad Octet Counter Interrupt Mask Setting this bit masks the interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Bad Octet Counter Interrupt..,1: MMC Transmit Good Bad Octet Counter Interrupt.." rgroup.long 0x714++0x67 line.long 0x0 "Tx_Octet_Count_Good_Bad,This register provides the number of bytes transmitted by the DWC_ether_qos. exclusive of preamble and retried bytes. in good and bad packets." hexmask.long 0x0 0.--31. 1. "TXOCTGB,Tx Octet Count Good Bad This field indicates the number of bytes transmitted exclusive of preamble and retried bytes in good and bad packets" line.long 0x4 "Tx_Packet_Count_Good_Bad,This register provides the number of good and bad packets transmitted by DWC_ether_qos. exclusive of retried packets." hexmask.long 0x4 0.--31. 1. "TXPKTGB,Tx Packet Count Good Bad This field indicates the number of good and bad packets transmitted exclusive of retried packets" line.long 0x8 "Tx_Broadcast_Packets_Good,This register provides the number of good broadcast packets transmitted by DWC_ether_qos." hexmask.long 0x8 0.--31. 1. "TXBCASTG,Tx Broadcast Packets Good This field indicates the number of good broadcast packets transmitted." line.long 0xC "Tx_Multicast_Packets_Good,This register provides the number of good multicast packets transmitted by DWC_ether_qos." hexmask.long 0xC 0.--31. 1. "TXMCASTG,Tx Multicast Packets Good This field indicates the number of good multicast packets transmitted." line.long 0x10 "Tx_64Octets_Packets_Good_Bad,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length 64 bytes. exclusive of preamble and retried packets." hexmask.long 0x10 0.--31. 1. "TX64OCTGB,Tx 64Octets Packets Good_Bad This field indicates the number of good and bad packets transmitted with length 64 bytes exclusive of preamble and retried packets" line.long 0x14 "Tx_65To127Octets_Packets_Good_Bad,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length between 65 and 127 (inclusive) bytes. exclusive of preamble and retried packets." hexmask.long 0x14 0.--31. 1. "TX65_127OCTGB,Tx 65To127Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 65 and 127 (inclusive) bytes exclusive of preamble and retried packets" line.long 0x18 "Tx_128To255Octets_Packets_Good_Bad,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length between 128 to 255 (inclusive) bytes. exclusive of preamble and retried packets." hexmask.long 0x18 0.--31. 1. "TX128_255OCTGB,Tx 128To255Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 128 and 255 (inclusive) bytes exclusive of preamble and retried packets" line.long 0x1C "Tx_256To511Octets_Packets_Good_Bad,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length between 256 to 511 (inclusive) bytes. exclusive of preamble and retried packets." hexmask.long 0x1C 0.--31. 1. "TX256_511OCTGB,Tx 256To511Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 256 and 511 (inclusive) bytes exclusive of preamble and retried packets" line.long 0x20 "Tx_512To1023Octets_Packets_Good_Bad,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length 512 to 1023 (inclusive) bytes. exclusive of preamble and retried packets." hexmask.long 0x20 0.--31. 1. "TX512_1023OCTGB,Tx 512To1023Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 512 and 1023 (inclusive) bytes exclusive of preamble and retried packets" line.long 0x24 "Tx_1024ToMaxOctets_Packets_Good_Bad,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length 1024 to maxsize (inclusive) bytes. exclusive of preamble and retried packets." hexmask.long 0x24 0.--31. 1. "TX1024_MAXOCTGB,Tx 1024ToMaxOctets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 1024 and maxsize (inclusive) bytes exclusive of preamble and retried packets" line.long 0x28 "Tx_Unicast_Packets_Good_Bad,This register provides the number of good and bad unicast packets transmitted by DWC_ether_qos." hexmask.long 0x28 0.--31. 1. "TXUCASTGB,Tx Unicast Packets Good Bad This field indicates the number of good and bad unicast packets transmitted" line.long 0x2C "Tx_Multicast_Packets_Good_Bad,This register provides the number of good and bad multicast packets transmitted by DWC_ether_qos." hexmask.long 0x2C 0.--31. 1. "TXMCASTGB,Tx Multicast Packets Good Bad This field indicates the number of good and bad multicast packets transmitted" line.long 0x30 "Tx_Broadcast_Packets_Good_Bad,This register provides the number of good and bad broadcast packets transmitted by DWC_ether_qos." hexmask.long 0x30 0.--31. 1. "TXBCASTGB,Tx Broadcast Packets Good Bad This field indicates the number of good and bad broadcast packets transmitted" line.long 0x34 "Tx_Underflow_Error_Packets,This register provides the number of packets aborted by DWC_ether_qos because of packets underflow error." hexmask.long 0x34 0.--31. 1. "TXUNDRFLW,Tx Underflow Error Packets This field indicates the number of packets aborted because of packets underflow error" line.long 0x38 "Tx_Single_Collision_Good_Packets,This register provides the number of successfully transmitted packets by DWC_ether_qos after a single collision in the half-duplex mode." hexmask.long 0x38 0.--31. 1. "TXSNGLCOLG,Tx Single Collision Good Packets This field indicates the number of successfully transmitted packets after a single collision in the half-duplex mode" line.long 0x3C "Tx_Multiple_Collision_Good_Packets,This register provides the number of successfully transmitted packets by DWC_ether_qos after multiple collisions in the half-duplex mode." hexmask.long 0x3C 0.--31. 1. "TXMULTCOLG,Tx Multiple Collision Good Packets This field indicates the number of successfully transmitted packets after multiple collisions in the half-duplex mode" line.long 0x40 "Tx_Deferred_Packets,This register provides the number of successfully transmitted by DWC_ether_qos after a deferral in the half-duplex mode." hexmask.long 0x40 0.--31. 1. "TXDEFRD,Tx Deferred Packets This field indicates the number of successfully transmitted after a deferral in the half-duplex mode" line.long 0x44 "Tx_Late_Collision_Packets,This register provides the number of packets aborted by DWC_ether_qos because of late collision error." hexmask.long 0x44 0.--31. 1. "TXLATECOL,Tx Late Collision Packets This field indicates the number of packets aborted because of late collision error" line.long 0x48 "Tx_Excessive_Collision_Packets,This register provides the number of packets aborted by DWC_ether_qos because of excessive (16) collision errors." hexmask.long 0x48 0.--31. 1. "TXEXSCOL,Tx Excessive Collision Packets This field indicates the number of packets aborted because of excessive (16) collision errors" line.long 0x4C "Tx_Carrier_Error_Packets,This register provides the number of packets aborted by DWC_ether_qos because of carrier sense error (no carrier or loss of carrier)." hexmask.long 0x4C 0.--31. 1. "TXCARR,Tx Carrier Error Packets This field indicates the number of packets aborted because of carrier sense error (no carrier or loss of carrier)" line.long 0x50 "Tx_Octet_Count_Good,This register provides the number of bytes transmitted by DWC_ether_qos. exclusive of preamble. only in good packets." hexmask.long 0x50 0.--31. 1. "TXOCTG,Tx Octet Count Good This field indicates the number of bytes transmitted exclusive of preamble only in good packets" line.long 0x54 "Tx_Packet_Count_Good,This register provides the number of good packets transmitted by DWC_ether_qos." hexmask.long 0x54 0.--31. 1. "TXPKTG,Tx Packet Count Good This field indicates the number of good packets transmitted." line.long 0x58 "Tx_Excessive_Deferral_Error,This register provides the number of packets aborted by DWC_ether_qos because of excessive deferral error (deferred for more than two max-sized packet times)." hexmask.long 0x58 0.--31. 1. "TXEXSDEF,Tx Excessive Deferral Error This field indicates the number of packets aborted because of excessive deferral error (deferred for more than two max-sized packet times)" line.long 0x5C "Tx_Pause_Packets,This register provides the number of good Pause packets transmitted by DWC_ether_qos." hexmask.long 0x5C 0.--31. 1. "TXPAUSE,Tx Pause Packets This field indicates the number of good Pause packets transmitted." line.long 0x60 "Tx_VLAN_Packets_Good,This register provides the number of good VLAN packets transmitted by DWC_ether_qos." hexmask.long 0x60 0.--31. 1. "TXVLANG,Tx VLAN Packets Good This field provides the number of good VLAN packets transmitted." line.long 0x64 "Tx_OSize_Packets_Good,This register provides the number of packets transmitted by DWC_ether_qos without errors and with length greater than the maxsize (1.518 or 1.522 bytes for VLAN tagged packets; 2000 bytes if enabled in S2KP bit of the.." hexmask.long 0x64 0.--31. 1. "TXOSIZG,Tx OSize Packets Good This field indicates the number of packets transmitted without errors and with length greater than the maxsize (1 518 or 1 522 bytes for VLAN tagged packets; 2000 bytes if enabled in S2KP bit of the MAC_Configuration register)" rgroup.long 0x780++0x67 line.long 0x0 "Rx_Packets_Count_Good_Bad,This register provides the number of good and bad packets received by DWC_ether_qos." hexmask.long 0x0 0.--31. 1. "RXPKTGB,Rx Packets Count Good Bad This field indicates the number of good and bad packets received." line.long 0x4 "Rx_Octet_Count_Good_Bad,This register provides the number of bytes received by DWC_ther_qos. exclusive of preamble. in good and bad packets." hexmask.long 0x4 0.--31. 1. "RXOCTGB,Rx Octet Count Good Bad This field indicates the number of bytes received exclusive of preamble in good and bad packets" line.long 0x8 "Rx_Octet_Count_Good,This register provides the number of bytes received by DWC_ether_qos. exclusive of preamble. only in good packets." hexmask.long 0x8 0.--31. 1. "RXOCTG,Rx Octet Count Good This field indicates the number of bytes received exclusive of preamble only in good packets" line.long 0xC "Rx_Broadcast_Packets_Good,This register provides the number of good broadcast packets received by DWC_ether_qos." hexmask.long 0xC 0.--31. 1. "RXBCASTG,Rx Broadcast Packets Good This field indicates the number of good broadcast packets received." line.long 0x10 "Rx_Multicast_Packets_Good,This register provides the number of good multicast packets received by DWC_ether_qos." hexmask.long 0x10 0.--31. 1. "RXMCASTG,Rx Multicast Packets Good This field indicates the number of good multicast packets received." line.long 0x14 "Rx_CRC_Error_Packets,This register provides the number of packets received by DWC_ether_qos with CRC error." hexmask.long 0x14 0.--31. 1. "RXCRCERR,Rx CRC Error Packets This field indicates the number of packets received with CRC error." line.long 0x18 "Rx_Alignment_Error_Packets,This register provides the number of packets received by DWC_ether_qos with alignment (dribble) error. It is valid only in 10/100 mode." hexmask.long 0x18 0.--31. 1. "RXALGNERR,Rx Alignment Error Packets This field indicates the number of packets received with alignment (dribble) error" line.long 0x1C "Rx_Runt_Error_Packets,This register provides the number of packets received by DWC_ether_qos with runt (length less than 64 bytes and CRC error) error." hexmask.long 0x1C 0.--31. 1. "RXRUNTERR,Rx Runt Error Packets This field indicates the number of packets received with runt (length less than 64 bytes and CRC error) error" line.long 0x20 "Rx_Jabber_Error_Packets,This register provides the number of giant packets received by DWC_ether_qos with length (including CRC) greater than 1.518 bytes (1.522 bytes for VLAN tagged) and with CRC error. If Jumbo Packet mode is enabled. packets of length.." hexmask.long 0x20 0.--31. 1. "RXJABERR,Rx Jabber Error Packets This field indicates the number of giant packets received with length (including CRC) greater than 1 518 bytes (1 522 bytes for VLAN tagged) and with CRC error" line.long 0x24 "Rx_Undersize_Packets_Good,This register provides the number of packets received by DWC_ether_qos with length less than 64 bytes. without any errors." hexmask.long 0x24 0.--31. 1. "RXUNDERSZG,Rx Undersize Packets Good This field indicates the number of packets received with length less than 64 bytes without any errors" line.long 0x28 "Rx_Oversize_Packets_Good,This register provides the number of packets received by DWC_ether_qos without errors. with length greater than the maxsize (1.518 bytes or 1.522 bytes for VLAN tagged packets; 2000 bytes if enabled in the S2KP bit of the.." hexmask.long 0x28 0.--31. 1. "RXOVERSZG,Rx Oversize Packets Good This field indicates the number of packets received without errors with length greater than the maxsize (1 518 bytes or 1 522 bytes for VLAN tagged packets; 2000 bytes if enabled in the S2KP bit of the.." line.long 0x2C "Rx_64Octets_Packets_Good_Bad,This register provides the number of good and bad packets received by DWC_ether_qos with length 64 bytes. exclusive of the preamble." hexmask.long 0x2C 0.--31. 1. "RX64OCTGB,Rx 64 Octets Packets Good Bad This field indicates the number of good and bad packets received with length 64 bytes exclusive of the preamble" line.long 0x30 "Rx_65To127Octets_Packets_Good_Bad,This register provides the number of good and bad packets received by DWC_ether_qos with length between 65 and 127 (inclusive) bytes. exclusive of the preamble." hexmask.long 0x30 0.--31. 1. "RX65_127OCTGB,Rx 65-127 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 65 and 127 (inclusive) bytes exclusive of the preamble" line.long 0x34 "Rx_128To255Octets_Packets_Good_Bad,This register provides the number of good and bad packets received by DWC_ether_qos with length between 128 and 255 (inclusive) bytes. exclusive of the preamble." hexmask.long 0x34 0.--31. 1. "RX128_255OCTGB,Rx 128-255 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 128 and 255 (inclusive) bytes exclusive of the preamble" line.long 0x38 "Rx_256To511Octets_Packets_Good_Bad,This register provides the number of good and bad packets received by DWC_ether_qos with length between 256 and 511 (inclusive) bytes. exclusive of the preamble." hexmask.long 0x38 0.--31. 1. "RX256_511OCTGB,Rx 256-511 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 256 and 511 (inclusive) bytes exclusive of the preamble" line.long 0x3C "Rx_512To1023Octets_Packets_Good_Bad,This register provides the number of good and bad packets received by DWC_ether_qos with length between 512 and 1023 (inclusive) bytes. exclusive of the preamble." hexmask.long 0x3C 0.--31. 1. "RX512_1023OCTGB,RX 512-1023 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 512 and 1023 (inclusive) bytes exclusive of the preamble" line.long 0x40 "Rx_1024ToMaxOctets_Packets_Good_Bad,This register provides the number of good and bad packets received by DWC_ether_qos with length between 1024 and maxsize (inclusive) bytes. exclusive of the preamble." hexmask.long 0x40 0.--31. 1. "RX1024_MAXOCTGB,Rx 1024-Max Octets Good Bad This field indicates the number of good and bad packets received with length between 1024 and maxsize (inclusive) bytes exclusive of the preamble" line.long 0x44 "Rx_Unicast_Packets_Good,This register provides the number of good unicast packets received by DWC_ether_qos." hexmask.long 0x44 0.--31. 1. "RXUCASTG,Rx Unicast Packets Good This field indicates the number of good unicast packets received." line.long 0x48 "Rx_Length_Error_Packets,This register provides the number of packets received by DWC_ether_qos with length error (Length Type field not equal to packet size). for all packets with valid length field." hexmask.long 0x48 0.--31. 1. "RXLENERR,Rx Length Error Packets This field indicates the number of packets received with length error (Length Type field not equal to packet size) for all packets with valid length field" line.long 0x4C "Rx_Out_Of_Range_Type_Packets,This register provides the number of packets received by DWC_ether_qos with length field not equal to the valid packet size (greater than 1.500 but less than 1.536)." hexmask.long 0x4C 0.--31. 1. "RXOUTOFRNG,Rx Out of Range Type Packet This field indicates the number of packets received with length field not equal to the valid packet size (greater than 1 500 but less than 1 536)" line.long 0x50 "Rx_Pause_Packets,This register provides the number of good and valid Pause packets received by DWC_ether_qos." hexmask.long 0x50 0.--31. 1. "RXPAUSEPKT,Rx Pause Packets This field indicates the number of good and valid Pause packets received." line.long 0x54 "Rx_FIFO_Overflow_Packets,This register provides the number of missed received packets because of FIFO overflow in DWC_ether_qos." hexmask.long 0x54 0.--31. 1. "RXFIFOOVFL,Rx FIFO Overflow Packets This field indicates the number of missed received packets because of FIFO overflow" line.long 0x58 "Rx_VLAN_Packets_Good_Bad,This register provides the number of good and bad VLAN packets received by DWC_ether_qos." hexmask.long 0x58 0.--31. 1. "RXVLANPKTGB,Rx VLAN Packets Good Bad This field indicates the number of good and bad VLAN packets received." line.long 0x5C "Rx_Watchdog_Error_Packets,This register provides the number of packets received by DWC_ether_qos with error because of watchdog timeout error (packets with a data load larger than 2.048 bytes (when JE and WD bits are reset in MAC_Configuration register)..." hexmask.long 0x5C 0.--31. 1. "RXWDGERR,Rx Watchdog Error Packets This field indicates the number of packets received with error because of watchdog timeout error (packets with a data load larger than 2 048 bytes (when JE and WD bits are reset in MAC_Configuration register) 10 240.." line.long 0x60 "Rx_Receive_Error_Packets,This register provides the number of packets received by DWC_ether_qos with Receive error or Packet Extension error on the GMII or MII interface." hexmask.long 0x60 0.--31. 1. "RXRCVERR,Rx Receive Error Packets This field indicates the number of packets received with Receive error or Packet Extension error on the GMII or MII interface" line.long 0x64 "Rx_Control_Packets_Good,This register provides the number of good control packets received by DWC_ether_qos." hexmask.long 0x64 0.--31. 1. "RXCTRLG,Rx Control Packets Good This field indicates the number of good control packets received." rgroup.long 0x8A0++0x3 line.long 0x0 "MMC_FPE_Tx_Interrupt,This register maintains the interrupts generated from all FPE related Transmit statistics counters. The MMC FPE Transmit Interrupt register maintains the interrupts generated when transmit statistic counters reach half their maximum.." hexmask.long 0x0 2.--31. 1. "Reserved_31_2,Reserved." newline bitfld.long 0x0 1. "HRCIS,MMC Tx Hold Request Counter Interrupt Status This bit is set when the Tx_Hold_Req_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Tx Hold Request Counter Interrupt Status not..,1: MMC Tx Hold Request Counter Interrupt Status.." newline bitfld.long 0x0 0. "FCIS,MMC Tx FPE Fragment Counter Interrupt status This bit is set when the Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Tx FPE Fragment Counter Interrupt status not..,1: MMC Tx FPE Fragment Counter Interrupt status.." group.long 0x8A4++0x3 line.long 0x0 "MMC_FPE_Tx_Interrupt_Mask,This register maintains the masks for interrupts generated from all FPE related Transmit statistics counters. The MMC Receive Interrupt Mask register maintains the masks for the interrupts generated when FPE related receive.." hexmask.long 0x0 2.--31. 1. "Reserved_31_2,Reserved." newline bitfld.long 0x0 1. "HRCIM,MMC Transmit Hold Request Counter Interrupt Mask Setting this bit masks the interrupt when the Tx_Hold_Req_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Hold Request Counter Interrupt Mask..,1: MMC Transmit Hold Request Counter Interrupt Mask.." newline bitfld.long 0x0 0. "FCIM,MMC Transmit Fragment Counter Interrupt Mask Setting this bit masks the interrupt when the Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Fragment Counter Interrupt Mask is..,1: MMC Transmit Fragment Counter Interrupt Mask is.." rgroup.long 0x8A8++0x7 line.long 0x0 "MMC_Tx_FPE_Fragment_Cntr,This register provides the number of additional mPackets transmitted due to preemption." hexmask.long 0x0 0.--31. 1. "TXFFC,Tx FPE Fragment counter This field indicates the number of additional mPackets that has been transmitted due to preemption Exists when any one of the RX/TX MMC counters are enabled during FPE Enabled configuration" line.long 0x4 "MMC_Tx_Hold_Req_Cntr,This register provides the count of number of times a hold request is given to MAC" hexmask.long 0x4 0.--31. 1. "TXHRC,Tx Hold Request Counter This field indicates count of number of a hold request is given to MAC" rgroup.long 0x8C0++0x3 line.long 0x0 "MMC_FPE_Rx_Interrupt,This register maintains the interrupts generated from all FPE related Receive statistics counters. The MMC FPE Receive Interrupt register maintains the interrupts generated when transmit statistic counters reach half their maximum.." hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved." newline bitfld.long 0x0 3. "FCIS,MMC Rx FPE Fragment Counter Interrupt Status This bit is set when the Rx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx FPE Fragment Counter Interrupt Status not..,1: MMC Rx FPE Fragment Counter Interrupt Status.." newline bitfld.long 0x0 2. "PAOCIS,MMC Rx Packet Assembly OK Counter Interrupt Status This bit is set when the Rx_Packet_Assemble_Ok_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet Assembly OK Counter Interrupt..,1: MMC Rx Packet Assembly OK Counter Interrupt.." newline bitfld.long 0x0 1. "PSECIS,MMC Rx Packet SMD Error Counter Interrupt Status This bit is set when the Rx_Packet_SMD_Err_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet SMD Error Counter Interrupt Status..,1: MMC Rx Packet SMD Error Counter Interrupt Status.." newline bitfld.long 0x0 0. "PAECIS,MMC Rx Packet Assembly Error Counter Interrupt Status This bit is set when the Rx_Packet_Assemble_Err_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet Assembly Error Counter Interrupt..,1: MMC Rx Packet Assembly Error Counter Interrupt.." group.long 0x8C4++0x3 line.long 0x0 "MMC_FPE_Rx_Interrupt_Mask,This register maintains the masks for interrupts generated from all FPE related Receive statistics counters. The MMC Receive Interrupt Mask register maintains the masks for the interrupts generated when FPE related receive.." hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved." newline bitfld.long 0x0 3. "FCIM,MMC Rx FPE Fragment Counter Interrupt Mask Setting this bit masks the interrupt when the Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx FPE Fragment Counter Interrupt Mask is..,1: MMC Rx FPE Fragment Counter Interrupt Mask is.." newline bitfld.long 0x0 2. "PAOCIM,MMC Rx Packet Assembly OK Counter Interrupt Mask Setting this bit masks the interrupt when the Rx_Packet_Assemble_Ok_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet Assembly OK Counter Interrupt Mask..,1: MMC Rx Packet Assembly OK Counter Interrupt Mask.." newline bitfld.long 0x0 1. "PSECIM,MMC Rx Packet SMD Error Counter Interrupt Mask Setting this bit masks the interrupt when the R Rx_Packet_SMD_Err_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet SMD Error Counter Interrupt Mask..,1: MMC Rx Packet SMD Error Counter Interrupt Mask.." newline bitfld.long 0x0 0. "PAECIM,MMC Rx Packet Assembly Error Counter Interrupt Mask Setting this bit masks the interrupt when the R Rx_Packet_Assemble_Err_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet Assembly Error Counter Interrupt..,1: MMC Rx Packet Assembly Error Counter Interrupt.." rgroup.long 0x8C8++0xF line.long 0x0 "MMC_Rx_Packet_Assembly_Err_Cntr,This register provides the number of MAC frames with reassembly errors on the Receiver. due to mismatch in the Fragment Count value." hexmask.long 0x0 0.--31. 1. "PAEC,Rx Packet Assembly Error Counter This field indicates the number of MAC frames with reassembly errors on the Receiver due to mismatch in the Fragment Count value" line.long 0x4 "MMC_Rx_Packet_SMD_Err_Cntr,This register provides the number of received MAC frames rejected due to unknown SMD value and MAC frame fragments rejected due to arriving with an SMD-C when there was no preceding preempted frame." hexmask.long 0x4 0.--31. 1. "PSEC,Rx Packet SMD Error Counter This field indicates the number of MAC frames rejected due to unknown SMD value and MAC frame fragments rejected due to arriving with an SMD-C when there was no preceding preempted frame" line.long 0x8 "MMC_Rx_Packet_Assembly_OK_Cntr,This register provides the number of MAC frames that were successfully reassembled and delivered to MAC." hexmask.long 0x8 0.--31. 1. "PAOC,Rx Packet Assembly OK Counter This field indicates the number of MAC frames that were successfully reassembled and delivered to MAC" line.long 0xC "MMC_Rx_FPE_Fragment_Cntr,This register provides the number of additional mPackets received due to preemption." hexmask.long 0xC 0.--31. 1. "FFC,Rx FPE Fragment Counter This field indicates the number of additional mPackets received due to preemption Exists when at least one of the RX/TX MMC counters are enabled during FPE Enabled configuration" group.long 0x900++0x7 line.long 0x0 "MAC_L3_L4_Control0,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4." rbitfld.long 0x0 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "DMCHEN0,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled" newline rbitfld.long 0x0 26.--27. "Reserved_27_y,Reserved." "0,1,2,3" newline bitfld.long 0x0 24.--25. "DMCHN0,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3" newline rbitfld.long 0x0 22.--23. "Reserved_23_22,Reserved." "0,1,2,3" newline bitfld.long 0x0 21. "L4DPIM0,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is disabled,1: Layer 4 Destination Port Inverse Match is enabled" newline bitfld.long 0x0 20. "L4DPM0,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled" newline bitfld.long 0x0 19. "L4SPIM0,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled" newline bitfld.long 0x0 18. "L4SPM0,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled" newline rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1" newline bitfld.long 0x0 16. "L4PEN0,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled" newline hexmask.long.byte 0x0 11.--15. 1. "L3HDBM0,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" newline hexmask.long.byte 0x0 6.--10. 1. "L3HSBM0,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" newline bitfld.long 0x0 5. "L3DAIM0,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled" newline bitfld.long 0x0 4. "L3DAM0,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled" newline bitfld.long 0x0 3. "L3SAIM0,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled" newline bitfld.long 0x0 2. "L3SAM0,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled" newline rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1" newline bitfld.long 0x0 0. "L3PEN0,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled" line.long 0x4 "MAC_Layer4_Address0,The MAC_Layer4_Address(#i). MAC_L3_L4_Control(#i). MAC_Layer3_Addr0_Reg(#i). MAC_Layer3_Addr1_Reg(#i). MAC_Layer3_Addr2_Reg(#i) and MAC_Layer3_Addr3_Reg(#i) registers are reserved (RO with default value) if Enable Layer 3 and Layer 4.." hexmask.long.word 0x4 16.--31. 1. "L4DP0,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets" newline hexmask.long.word 0x4 0.--15. 1. "L4SP0,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets" group.long 0x910++0xF line.long 0x0 "MAC_Layer3_Addr0_Reg0,For IPv4 packets. the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x0 0.--31. 1. "L3A00,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets" line.long 0x4 "MAC_Layer3_Addr1_Reg0,For IPv4 packets. the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x4 0.--31. 1. "L3A10,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets" line.long 0x8 "MAC_Layer3_Addr2_Reg0,The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field." hexmask.long 0x8 0.--31. 1. "L3A20,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets" line.long 0xC "MAC_Layer3_Addr3_Reg0,The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field." hexmask.long 0xC 0.--31. 1. "L3A30,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets" group.long 0x930++0x7 line.long 0x0 "MAC_L3_L4_Control1,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4." rbitfld.long 0x0 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "DMCHEN1,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled" newline rbitfld.long 0x0 26.--27. "Reserved_27_y,Reserved." "0,1,2,3" newline bitfld.long 0x0 24.--25. "DMCHN1,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3" newline rbitfld.long 0x0 22.--23. "Reserved_23_22,Reserved." "0,1,2,3" newline bitfld.long 0x0 21. "L4DPIM1,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is disabled,1: Layer 4 Destination Port Inverse Match is enabled" newline bitfld.long 0x0 20. "L4DPM1,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled" newline bitfld.long 0x0 19. "L4SPIM1,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled" newline bitfld.long 0x0 18. "L4SPM1,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled" newline rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1" newline bitfld.long 0x0 16. "L4PEN1,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled" newline hexmask.long.byte 0x0 11.--15. 1. "L3HDBM1,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" newline hexmask.long.byte 0x0 6.--10. 1. "L3HSBM1,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" newline bitfld.long 0x0 5. "L3DAIM1,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled" newline bitfld.long 0x0 4. "L3DAM1,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled" newline bitfld.long 0x0 3. "L3SAIM1,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled" newline bitfld.long 0x0 2. "L3SAM1,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled" newline rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1" newline bitfld.long 0x0 0. "L3PEN1,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled" line.long 0x4 "MAC_Layer4_Address1,The MAC_Layer4_Address(#i). MAC_L3_L4_Control(#i). MAC_Layer3_Addr0_Reg(#i). MAC_Layer3_Addr1_Reg(#i). MAC_Layer3_Addr2_Reg(#i) and MAC_Layer3_Addr3_Reg(#i) registers are reserved (RO with default value) if Enable Layer 3 and Layer 4.." hexmask.long.word 0x4 16.--31. 1. "L4DP1,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets" newline hexmask.long.word 0x4 0.--15. 1. "L4SP1,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets" group.long 0x940++0xF line.long 0x0 "MAC_Layer3_Addr0_Reg1,For IPv4 packets. the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x0 0.--31. 1. "L3A01,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets" line.long 0x4 "MAC_Layer3_Addr1_Reg1,For IPv4 packets. the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x4 0.--31. 1. "L3A11,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets" line.long 0x8 "MAC_Layer3_Addr2_Reg1,The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field." hexmask.long 0x8 0.--31. 1. "L3A21,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets" line.long 0xC "MAC_Layer3_Addr3_Reg1,The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field." hexmask.long 0xC 0.--31. 1. "L3A31,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets" group.long 0x960++0x7 line.long 0x0 "MAC_L3_L4_Control2,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4." rbitfld.long 0x0 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "DMCHEN2,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled" newline rbitfld.long 0x0 26.--27. "Reserved_27_y,Reserved." "0,1,2,3" newline bitfld.long 0x0 24.--25. "DMCHN2,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3" newline rbitfld.long 0x0 22.--23. "Reserved_23_22,Reserved." "0,1,2,3" newline bitfld.long 0x0 21. "L4DPIM2,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is disabled,1: Layer 4 Destination Port Inverse Match is enabled" newline bitfld.long 0x0 20. "L4DPM2,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled" newline bitfld.long 0x0 19. "L4SPIM2,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled" newline bitfld.long 0x0 18. "L4SPM2,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled" newline rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1" newline bitfld.long 0x0 16. "L4PEN2,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled" newline hexmask.long.byte 0x0 11.--15. 1. "L3HDBM2,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" newline hexmask.long.byte 0x0 6.--10. 1. "L3HSBM2,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" newline bitfld.long 0x0 5. "L3DAIM2,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled" newline bitfld.long 0x0 4. "L3DAM2,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled" newline bitfld.long 0x0 3. "L3SAIM2,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled" newline bitfld.long 0x0 2. "L3SAM2,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled" newline rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1" newline bitfld.long 0x0 0. "L3PEN2,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled" line.long 0x4 "MAC_Layer4_Address2,The MAC_Layer4_Address(#i). MAC_L3_L4_Control(#i). MAC_Layer3_Addr0_Reg(#i). MAC_Layer3_Addr1_Reg(#i). MAC_Layer3_Addr2_Reg(#i) and MAC_Layer3_Addr3_Reg(#i) registers are reserved (RO with default value) if Enable Layer 3 and Layer 4.." hexmask.long.word 0x4 16.--31. 1. "L4DP2,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets" newline hexmask.long.word 0x4 0.--15. 1. "L4SP2,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets" group.long 0x970++0xF line.long 0x0 "MAC_Layer3_Addr0_Reg2,For IPv4 packets. the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x0 0.--31. 1. "L3A02,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets" line.long 0x4 "MAC_Layer3_Addr1_Reg2,For IPv4 packets. the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x4 0.--31. 1. "L3A12,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets" line.long 0x8 "MAC_Layer3_Addr2_Reg2,The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field." hexmask.long 0x8 0.--31. 1. "L3A22,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets" line.long 0xC "MAC_Layer3_Addr3_Reg2,The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field." hexmask.long 0xC 0.--31. 1. "L3A32,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets" group.long 0x990++0x7 line.long 0x0 "MAC_L3_L4_Control3,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4." rbitfld.long 0x0 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "DMCHEN3,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled" newline rbitfld.long 0x0 26.--27. "Reserved_27_y,Reserved." "0,1,2,3" newline bitfld.long 0x0 24.--25. "DMCHN3,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3" newline rbitfld.long 0x0 22.--23. "Reserved_23_22,Reserved." "0,1,2,3" newline bitfld.long 0x0 21. "L4DPIM3,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is disabled,1: Layer 4 Destination Port Inverse Match is enabled" newline bitfld.long 0x0 20. "L4DPM3,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled" newline bitfld.long 0x0 19. "L4SPIM3,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled" newline bitfld.long 0x0 18. "L4SPM3,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled" newline rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1" newline bitfld.long 0x0 16. "L4PEN3,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled" newline hexmask.long.byte 0x0 11.--15. 1. "L3HDBM3,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" newline hexmask.long.byte 0x0 6.--10. 1. "L3HSBM3,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" newline bitfld.long 0x0 5. "L3DAIM3,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled" newline bitfld.long 0x0 4. "L3DAM3,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled" newline bitfld.long 0x0 3. "L3SAIM3,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled" newline bitfld.long 0x0 2. "L3SAM3,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled" newline rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1" newline bitfld.long 0x0 0. "L3PEN3,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled" line.long 0x4 "MAC_Layer4_Address3,The MAC_Layer4_Address(#i). MAC_L3_L4_Control(#i). MAC_Layer3_Addr0_Reg(#i). MAC_Layer3_Addr1_Reg(#i). MAC_Layer3_Addr2_Reg(#i) and MAC_Layer3_Addr3_Reg(#i) registers are reserved (RO with default value) if Enable Layer 3 and Layer 4.." hexmask.long.word 0x4 16.--31. 1. "L4DP3,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets" newline hexmask.long.word 0x4 0.--15. 1. "L4SP3,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets" group.long 0x9A0++0xF line.long 0x0 "MAC_Layer3_Addr0_Reg3,For IPv4 packets. the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x0 0.--31. 1. "L3A03,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets" line.long 0x4 "MAC_Layer3_Addr1_Reg3,For IPv4 packets. the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x4 0.--31. 1. "L3A13,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets" line.long 0x8 "MAC_Layer3_Addr2_Reg3,The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field." hexmask.long 0x8 0.--31. 1. "L3A23,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets" line.long 0xC "MAC_Layer3_Addr3_Reg3,The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field." hexmask.long 0xC 0.--31. 1. "L3A33,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets" group.long 0x9C0++0x7 line.long 0x0 "MAC_L3_L4_Control4,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4." rbitfld.long 0x0 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "DMCHEN4,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled" newline rbitfld.long 0x0 26.--27. "Reserved_27_y,Reserved." "0,1,2,3" newline bitfld.long 0x0 24.--25. "DMCHN4,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3" newline rbitfld.long 0x0 22.--23. "Reserved_23_22,Reserved." "0,1,2,3" newline bitfld.long 0x0 21. "L4DPIM4,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is disabled,1: Layer 4 Destination Port Inverse Match is enabled" newline bitfld.long 0x0 20. "L4DPM4,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled" newline bitfld.long 0x0 19. "L4SPIM4,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled" newline bitfld.long 0x0 18. "L4SPM4,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled" newline rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1" newline bitfld.long 0x0 16. "L4PEN4,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled" newline hexmask.long.byte 0x0 11.--15. 1. "L3HDBM4,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" newline hexmask.long.byte 0x0 6.--10. 1. "L3HSBM4,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" newline bitfld.long 0x0 5. "L3DAIM4,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled" newline bitfld.long 0x0 4. "L3DAM4,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled" newline bitfld.long 0x0 3. "L3SAIM4,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled" newline bitfld.long 0x0 2. "L3SAM4,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled" newline rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1" newline bitfld.long 0x0 0. "L3PEN4,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled" line.long 0x4 "MAC_Layer4_Address4,The MAC_Layer4_Address(#i). MAC_L3_L4_Control(#i). MAC_Layer3_Addr0_Reg(#i). MAC_Layer3_Addr1_Reg(#i). MAC_Layer3_Addr2_Reg(#i) and MAC_Layer3_Addr3_Reg(#i) registers are reserved (RO with default value) if Enable Layer 3 and Layer 4.." hexmask.long.word 0x4 16.--31. 1. "L4DP4,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets" newline hexmask.long.word 0x4 0.--15. 1. "L4SP4,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets" group.long 0x9D0++0xF line.long 0x0 "MAC_Layer3_Addr0_Reg4,For IPv4 packets. the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x0 0.--31. 1. "L3A04,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets" line.long 0x4 "MAC_Layer3_Addr1_Reg4,For IPv4 packets. the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x4 0.--31. 1. "L3A14,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets" line.long 0x8 "MAC_Layer3_Addr2_Reg4,The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field." hexmask.long 0x8 0.--31. 1. "L3A24,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets" line.long 0xC "MAC_Layer3_Addr3_Reg4,The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field." hexmask.long 0xC 0.--31. 1. "L3A34,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets" group.long 0x9F0++0x7 line.long 0x0 "MAC_L3_L4_Control5,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4." rbitfld.long 0x0 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "DMCHEN5,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled" newline rbitfld.long 0x0 26.--27. "Reserved_27_y,Reserved." "0,1,2,3" newline bitfld.long 0x0 24.--25. "DMCHN5,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3" newline rbitfld.long 0x0 22.--23. "Reserved_23_22,Reserved." "0,1,2,3" newline bitfld.long 0x0 21. "L4DPIM5,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is disabled,1: Layer 4 Destination Port Inverse Match is enabled" newline bitfld.long 0x0 20. "L4DPM5,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled" newline bitfld.long 0x0 19. "L4SPIM5,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled" newline bitfld.long 0x0 18. "L4SPM5,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled" newline rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1" newline bitfld.long 0x0 16. "L4PEN5,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled" newline hexmask.long.byte 0x0 11.--15. 1. "L3HDBM5,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" newline hexmask.long.byte 0x0 6.--10. 1. "L3HSBM5,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" newline bitfld.long 0x0 5. "L3DAIM5,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled" newline bitfld.long 0x0 4. "L3DAM5,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled" newline bitfld.long 0x0 3. "L3SAIM5,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled" newline bitfld.long 0x0 2. "L3SAM5,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled" newline rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1" newline bitfld.long 0x0 0. "L3PEN5,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled" line.long 0x4 "MAC_Layer4_Address5,The MAC_Layer4_Address(#i). MAC_L3_L4_Control(#i). MAC_Layer3_Addr0_Reg(#i). MAC_Layer3_Addr1_Reg(#i). MAC_Layer3_Addr2_Reg(#i) and MAC_Layer3_Addr3_Reg(#i) registers are reserved (RO with default value) if Enable Layer 3 and Layer 4.." hexmask.long.word 0x4 16.--31. 1. "L4DP5,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets" newline hexmask.long.word 0x4 0.--15. 1. "L4SP5,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets" group.long 0xA00++0xF line.long 0x0 "MAC_Layer3_Addr0_Reg5,For IPv4 packets. the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x0 0.--31. 1. "L3A05,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets" line.long 0x4 "MAC_Layer3_Addr1_Reg5,For IPv4 packets. the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x4 0.--31. 1. "L3A15,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets" line.long 0x8 "MAC_Layer3_Addr2_Reg5,The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field." hexmask.long 0x8 0.--31. 1. "L3A25,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets" line.long 0xC "MAC_Layer3_Addr3_Reg5,The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field." hexmask.long 0xC 0.--31. 1. "L3A35,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets" group.long 0xA20++0x7 line.long 0x0 "MAC_L3_L4_Control6,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4." rbitfld.long 0x0 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "DMCHEN6,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled" newline rbitfld.long 0x0 26.--27. "Reserved_27_y,Reserved." "0,1,2,3" newline bitfld.long 0x0 24.--25. "DMCHN6,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3" newline rbitfld.long 0x0 22.--23. "Reserved_23_22,Reserved." "0,1,2,3" newline bitfld.long 0x0 21. "L4DPIM6,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is disabled,1: Layer 4 Destination Port Inverse Match is enabled" newline bitfld.long 0x0 20. "L4DPM6,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled" newline bitfld.long 0x0 19. "L4SPIM6,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled" newline bitfld.long 0x0 18. "L4SPM6,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled" newline rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1" newline bitfld.long 0x0 16. "L4PEN6,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled" newline hexmask.long.byte 0x0 11.--15. 1. "L3HDBM6,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" newline hexmask.long.byte 0x0 6.--10. 1. "L3HSBM6,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" newline bitfld.long 0x0 5. "L3DAIM6,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled" newline bitfld.long 0x0 4. "L3DAM6,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled" newline bitfld.long 0x0 3. "L3SAIM6,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled" newline bitfld.long 0x0 2. "L3SAM6,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled" newline rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1" newline bitfld.long 0x0 0. "L3PEN6,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled" line.long 0x4 "MAC_Layer4_Address6,The MAC_Layer4_Address(#i). MAC_L3_L4_Control(#i). MAC_Layer3_Addr0_Reg(#i). MAC_Layer3_Addr1_Reg(#i). MAC_Layer3_Addr2_Reg(#i) and MAC_Layer3_Addr3_Reg(#i) registers are reserved (RO with default value) if Enable Layer 3 and Layer 4.." hexmask.long.word 0x4 16.--31. 1. "L4DP6,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets" newline hexmask.long.word 0x4 0.--15. 1. "L4SP6,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets" group.long 0xA30++0xF line.long 0x0 "MAC_Layer3_Addr0_Reg6,For IPv4 packets. the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x0 0.--31. 1. "L3A06,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets" line.long 0x4 "MAC_Layer3_Addr1_Reg6,For IPv4 packets. the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x4 0.--31. 1. "L3A16,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets" line.long 0x8 "MAC_Layer3_Addr2_Reg6,The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field." hexmask.long 0x8 0.--31. 1. "L3A26,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets" line.long 0xC "MAC_Layer3_Addr3_Reg6,The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field." hexmask.long 0xC 0.--31. 1. "L3A36,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets" group.long 0xA50++0x7 line.long 0x0 "MAC_L3_L4_Control7,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4." rbitfld.long 0x0 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "DMCHEN7,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled" newline rbitfld.long 0x0 26.--27. "Reserved_27_y,Reserved." "0,1,2,3" newline bitfld.long 0x0 24.--25. "DMCHN7,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3" newline rbitfld.long 0x0 22.--23. "Reserved_23_22,Reserved." "0,1,2,3" newline bitfld.long 0x0 21. "L4DPIM7,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is disabled,1: Layer 4 Destination Port Inverse Match is enabled" newline bitfld.long 0x0 20. "L4DPM7,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled" newline bitfld.long 0x0 19. "L4SPIM7,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled" newline bitfld.long 0x0 18. "L4SPM7,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled" newline rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1" newline bitfld.long 0x0 16. "L4PEN7,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled" newline hexmask.long.byte 0x0 11.--15. 1. "L3HDBM7,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" newline hexmask.long.byte 0x0 6.--10. 1. "L3HSBM7,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" newline bitfld.long 0x0 5. "L3DAIM7,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled" newline bitfld.long 0x0 4. "L3DAM7,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled" newline bitfld.long 0x0 3. "L3SAIM7,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled" newline bitfld.long 0x0 2. "L3SAM7,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled" newline rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1" newline bitfld.long 0x0 0. "L3PEN7,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled" line.long 0x4 "MAC_Layer4_Address7,The MAC_Layer4_Address(#i). MAC_L3_L4_Control(#i). MAC_Layer3_Addr0_Reg(#i). MAC_Layer3_Addr1_Reg(#i). MAC_Layer3_Addr2_Reg(#i) and MAC_Layer3_Addr3_Reg(#i) registers are reserved (RO with default value) if Enable Layer 3 and Layer 4.." hexmask.long.word 0x4 16.--31. 1. "L4DP7,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets" newline hexmask.long.word 0x4 0.--15. 1. "L4SP7,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets" group.long 0xA60++0x17 line.long 0x0 "MAC_Layer3_Addr0_Reg7,For IPv4 packets. the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x0 0.--31. 1. "L3A07,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets" line.long 0x4 "MAC_Layer3_Addr1_Reg7,For IPv4 packets. the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x4 0.--31. 1. "L3A17,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets" line.long 0x8 "MAC_Layer3_Addr2_Reg7,The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field." hexmask.long 0x8 0.--31. 1. "L3A27,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets" line.long 0xC "MAC_Layer3_Addr3_Reg7,The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field." hexmask.long 0xC 0.--31. 1. "L3A37,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets" line.long 0x10 "MAC_Indir_Access_Ctrl,This register provides the Indirect Access control and status for MAC__ registers." hexmask.long.word 0x10 20.--31. 1. "Reserved_31_20,Reserved." newline hexmask.long.byte 0x10 16.--19. 1. "MSEL,Mode Select This field is used in indirect access of MAC__" newline hexmask.long.byte 0x10 8.--15. 1. "AOFF,Address Offset This field is used in indirect access of MAC__" newline rbitfld.long 0x10 6.--7. "Reserved_7_6,Reserved." "0,1,2,3" newline bitfld.long 0x10 5. "AUTO,Auto increment - 1: AOFF is incremented by 1" "?,1: AOFF is incremented by 1" newline rbitfld.long 0x10 2.--4. "Reserved_4_2,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 1. "COM,Command type This bit indicates the register access type" "0: Write operation,1: Read operation" newline bitfld.long 0x10 0. "OB,Operation Busy" "0,1" line.long 0x14 "MAC_Indir_Access_Data,This register holds the read/write data for Indirect Access of MAC_ registers." hexmask.long 0x14 0.--31. 1. "DATA,This field contains data to read/write for Indirect address access associated with MAC_Indir_Access_Ctrl register" group.long 0xA74++0x3 line.long 0x0 "MAC_TMRQ_Regs0,This register contains the type. associated queue number and paket type (Pre emption/EXpress) related to Type based RXQ mapping." hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved." newline bitfld.long 0x0 20. "PFEX,Preemption or Express Packet This bit indicates if it is a preemption packet or express packet." "0,1" newline rbitfld.long 0x0 19. "Reserved_19,Reserved." "0,1" newline bitfld.long 0x0 16.--18. "TMRQ,Type Match Rx Queue Number Indicates the receive queue number to which the packet needs to be forwarded on detecting a type match" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--15. 1. "TYP,Type field Value Indicates the type value of packet that needs to be compared with received Ethernet packet" group.long 0xA74++0x3 line.long 0x0 "MAC_TMRQ_Regs1,This register contains the type. associated queue number and paket type (Pre emption/EXpress) related to Type based RXQ mapping." hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved." newline bitfld.long 0x0 20. "PFEX,Preemption or Express Packet This bit indicates if it is a preemption packet or express packet." "0,1" newline rbitfld.long 0x0 19. "Reserved_19,Reserved." "0,1" newline bitfld.long 0x0 16.--18. "TMRQ,Type Match Rx Queue Number Indicates the receive queue number to which the packet needs to be forwarded on detecting a type match" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--15. 1. "TYP,Type field Value Indicates the type value of packet that needs to be compared with received Ethernet packet" group.long 0xA74++0x3 line.long 0x0 "MAC_TMRQ_Regs2,This register contains the type. associated queue number and paket type (Pre emption/EXpress) related to Type based RXQ mapping." hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved." newline bitfld.long 0x0 20. "PFEX,Preemption or Express Packet This bit indicates if it is a preemption packet or express packet." "0,1" newline rbitfld.long 0x0 19. "Reserved_19,Reserved." "0,1" newline bitfld.long 0x0 16.--18. "TMRQ,Type Match Rx Queue Number Indicates the receive queue number to which the packet needs to be forwarded on detecting a type match" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--15. 1. "TYP,Type field Value Indicates the type value of packet that needs to be compared with received Ethernet packet" group.long 0xA74++0x3 line.long 0x0 "MAC_TMRQ_Regs3,This register contains the type. associated queue number and paket type (Pre emption/EXpress) related to Type based RXQ mapping." hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved." newline bitfld.long 0x0 20. "PFEX,Preemption or Express Packet This bit indicates if it is a preemption packet or express packet." "0,1" newline rbitfld.long 0x0 19. "Reserved_19,Reserved." "0,1" newline bitfld.long 0x0 16.--18. "TMRQ,Type Match Rx Queue Number Indicates the receive queue number to which the packet needs to be forwarded on detecting a type match" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--15. 1. "TYP,Type field Value Indicates the type value of packet that needs to be compared with received Ethernet packet" group.long 0xA74++0x3 line.long 0x0 "MAC_TMRQ_Regs4,This register contains the type. associated queue number and paket type (Pre emption/EXpress) related to Type based RXQ mapping." hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved." newline bitfld.long 0x0 20. "PFEX,Preemption or Express Packet This bit indicates if it is a preemption packet or express packet." "0,1" newline rbitfld.long 0x0 19. "Reserved_19,Reserved." "0,1" newline bitfld.long 0x0 16.--18. "TMRQ,Type Match Rx Queue Number Indicates the receive queue number to which the packet needs to be forwarded on detecting a type match" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--15. 1. "TYP,Type field Value Indicates the type value of packet that needs to be compared with received Ethernet packet" group.long 0xA74++0x3 line.long 0x0 "MAC_TMRQ_Regs5,This register contains the type. associated queue number and paket type (Pre emption/EXpress) related to Type based RXQ mapping." hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved." newline bitfld.long 0x0 20. "PFEX,Preemption or Express Packet This bit indicates if it is a preemption packet or express packet." "0,1" newline rbitfld.long 0x0 19. "Reserved_19,Reserved." "0,1" newline bitfld.long 0x0 16.--18. "TMRQ,Type Match Rx Queue Number Indicates the receive queue number to which the packet needs to be forwarded on detecting a type match" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--15. 1. "TYP,Type field Value Indicates the type value of packet that needs to be compared with received Ethernet packet" group.long 0xA74++0x3 line.long 0x0 "MAC_TMRQ_Regs6,This register contains the type. associated queue number and paket type (Pre emption/EXpress) related to Type based RXQ mapping." hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved." newline bitfld.long 0x0 20. "PFEX,Preemption or Express Packet This bit indicates if it is a preemption packet or express packet." "0,1" newline rbitfld.long 0x0 19. "Reserved_19,Reserved." "0,1" newline bitfld.long 0x0 16.--18. "TMRQ,Type Match Rx Queue Number Indicates the receive queue number to which the packet needs to be forwarded on detecting a type match" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--15. 1. "TYP,Type field Value Indicates the type value of packet that needs to be compared with received Ethernet packet" group.long 0xA74++0x3 line.long 0x0 "MAC_TMRQ_Regs7,This register contains the type. associated queue number and paket type (Pre emption/EXpress) related to Type based RXQ mapping." hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved." newline bitfld.long 0x0 20. "PFEX,Preemption or Express Packet This bit indicates if it is a preemption packet or express packet." "0,1" newline rbitfld.long 0x0 19. "Reserved_19,Reserved." "0,1" newline bitfld.long 0x0 16.--18. "TMRQ,Type Match Rx Queue Number Indicates the receive queue number to which the packet needs to be forwarded on detecting a type match" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--15. 1. "TYP,Type field Value Indicates the type value of packet that needs to be compared with received Ethernet packet" group.long 0xB00++0x7 line.long 0x0 "MAC_Timestamp_Control,This register controls the operation of the System Time generator and processing of PTP packets for timestamping in the Receiver." rbitfld.long 0x0 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "AV8021ASMEN,AV 802" "0: AV 802.1AS Mode is disabled,1: AV 802.1AS Mode is enabled" newline rbitfld.long 0x0 25.--27. "Reserved_27_25,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24. "TXTSSTSM,Transmit Timestamp Status Mode When this bit is set the MAC overwrites the earlier transmit timestamp status even if it is not read by the software" "0: Transmit Timestamp Status Mode is disabled,1: Transmit Timestamp Status Mode is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ESTI,External System Time Input When this bit is set the MAC uses the external 64-bit reference System Time input for the following: - To take the timestamp provided as status - To insert the timestamp in transmit PTP packets when One-step Timestamp or.." "0: External System Time Input is disabled,1: External System Time Input is enabled" newline rbitfld.long 0x0 19. "Reserved_CSC,Reserved." "0,1" newline bitfld.long 0x0 18. "TSENMACADDR,Enable MAC Address for PTP Packet Filtering When this bit is set the DA MAC address (that matches any MAC Address register) is used to filter the PTP packets when PTP is directly sent over Ethernet" "0: MAC Address for PTP Packet Filtering is disabled,1: MAC Address for PTP Packet Filtering is enabled" newline bitfld.long 0x0 16.--17. "SNAPTYPSEL,Select PTP packets for Taking Snapshots These bits along with Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken" "0,1,2,3" newline bitfld.long 0x0 15. "TSMSTRENA,Enable Snapshot for Messages Relevant to Master When this bit is set the snapshot is taken only for the messages that are relevant to the master node" "0: Snapshot for Messages Relevant to Master is..,1: Snapshot for Messages Relevant to Master is.." newline bitfld.long 0x0 14. "TSEVNTENA,Enable Timestamp Snapshot for Event Messages When this bit is set the timestamp snapshot is taken only for event messages (SYNC Delay_Req Pdelay_Req or Pdelay_Resp)" "0: Timestamp Snapshot for Event Messages is disabled,1: Timestamp Snapshot for Event Messages is enabled" newline bitfld.long 0x0 13. "TSIPV4ENA,Enable Processing of PTP Packets Sent over IPv4-UDP When this bit is set the MAC receiver processes the PTP packets encapsulated in IPv4-UDP packets" "0: Processing of PTP Packets Sent over IPv4-UDP is..,1: Processing of PTP Packets Sent over IPv4-UDP is.." newline bitfld.long 0x0 12. "TSIPV6ENA,Enable Processing of PTP Packets Sent over IPv6-UDP When this bit is set the MAC receiver processes the PTP packets encapsulated in IPv6-UDP packets" "0: Processing of PTP Packets Sent over IPv6-UDP is..,1: Processing of PTP Packets Sent over IPv6-UDP is.." newline bitfld.long 0x0 11. "TSIPENA,Enable Processing of PTP over Ethernet Packets When this bit is set the MAC receiver processes the PTP packets encapsulated directly in the Ethernet packets" "0: Processing of PTP over Ethernet Packets is..,1: Processing of PTP over Ethernet Packets is enabled" newline bitfld.long 0x0 10. "TSVER2ENA,Enable PTP Packet Processing for Version 2 Format When this bit is set the IEEE 1588 version 2 format is used to process the PTP packets" "0: PTP Packet Processing for Version 2 Format is..,1: PTP Packet Processing for Version 2 Format is.." newline bitfld.long 0x0 9. "TSCTRLSSR,Timestamp Digital or Binary Rollover Control When this bit is set the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is 1 nanosecond accuracy) and increments the timestamp (High) seconds" "0: Timestamp Digital or Binary Rollover Control is..,1: Timestamp Digital or Binary Rollover Control is.." newline bitfld.long 0x0 8. "TSENALL,Enable Timestamp for All Packets When this bit is set the timestamp snapshot is enabled for all packets received by the MAC" "0: Timestamp for All Packets disabled,1: Timestamp for All Packets enabled" newline rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1" newline bitfld.long 0x0 6. "PTGE,Presentation Time Generation Enable When this bit is set the Presentation Time generation is enabled" "0: Presentation Time Generation is disabled,1: Presentation Time Generation is enabled" newline bitfld.long 0x0 5. "TSADDREG,Update Addend Register When this bit is set the content of the Timestamp Addend register is updated in the PTP block for fine correction" "0: Addend Register is not updated,1: Addend Register is updated" newline rbitfld.long 0x0 4. "Reserved_TSTRIG,Reserved." "0,1" newline bitfld.long 0x0 3. "TSUPDT,Update Timestamp When this bit is set the system time is updated (added or subtracted) with the value specified in MAC_System_Time_Seconds_Update and MAC_System_Time_Nanoseconds_Update registers" "0: Timestamp is not updated,1: Timestamp is updated" newline bitfld.long 0x0 2. "TSINIT,Initialize Timestamp When this bit is set the system time is initialized (overwritten) with the value specified in the MAC_System_Time_Seconds_Update and MAC_System_Time_Nanoseconds_Update registers" "0: Timestamp is not initialized,1: Timestamp is initialized" newline bitfld.long 0x0 1. "TSCFUPDT,Fine or Coarse Timestamp Update When this bit is set the Fine method is used to update system timestamp" "0: Coarse method is used to update system timestamp,1: Fine method is used to update system timestamp" newline bitfld.long 0x0 0. "TSENA,Enable Timestamp When this bit is set the timestamp is added for Transmit and Receive packets" "0: Timestamp is disabled,1: Timestamp is enabled" line.long 0x4 "MAC_Sub_Second_Increment,This register specifies the value to be added to the internal system time register every cycle of clk_ptp_ref_i clock." hexmask.long.byte 0x4 24.--31. 1. "Reserved_31_24,Reserved." newline hexmask.long.byte 0x4 16.--23. 1. "SSINC,Sub-second Increment Value The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register" newline hexmask.long.byte 0x4 8.--15. 1. "SNSINC,Sub-nanosecond Increment Value This field contains the sub-nanosecond increment value represented in nanoseconds multiplied by 2^8" newline hexmask.long.byte 0x4 0.--7. 1. "Reserved_7_0,Reserved." rgroup.long 0xB08++0x7 line.long 0x0 "MAC_System_Time_Seconds,The System Time Seconds register. along with System Time Nanoseconds register. indicates the current value of the system time maintained by the MAC. Though it is updated on a continuous basis. there is some delay from the actual.." hexmask.long 0x0 0.--31. 1. "TSS,Timestamp Second The value in this field indicates the current value in seconds of the System Time maintained by the MAC" line.long 0x4 "MAC_System_Time_Nanoseconds,The System Time Nanoseconds register. along with System Time Seconds register. indicates the current value of the system time maintained by the MAC." bitfld.long 0x4 31. "Reserved_31,Reserved." "0,1" newline hexmask.long 0x4 0.--30. 1. "TSSS,Timestamp Sub Seconds The value in this field has the sub-second representation of time with an accuracy of 0" group.long 0xB10++0xF line.long 0x0 "MAC_System_Time_Seconds_Update,The System Time Seconds Update register. along with the System Time Nanoseconds Update register. initializes or updates the system time maintained by the MAC. You must write both registers before setting the TSINIT or.." hexmask.long 0x0 0.--31. 1. "TSS,Timestamp Seconds The value in this field is the seconds part of the update" line.long 0x4 "MAC_System_Time_Nanoseconds_Update,MAC System Time Nanoseconds Update register." bitfld.long 0x4 31. "ADDSUB,Add or Subtract Time When this bit is set the time value is subtracted with the contents of the update register" "0: Add time,1: Subtract time" newline hexmask.long 0x4 0.--30. 1. "TSSS,Timestamp Sub Seconds The value in this field is the sub-seconds part of the update" line.long 0x8 "MAC_Timestamp_Addend,Timestamp Addend register. This register value is used only when the system time is configured for Fine Update mode (TSCFUPDT bit in the MAC_Timestamp_Control register). The content of this register is added to a 32-bit accumulator.." hexmask.long 0x8 0.--31. 1. "TSAR,Timestamp Addend Register This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization" line.long 0xC "MAC_System_Time_Higher_Word_Seconds,System Time - Higher Word Seconds register." hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved." newline hexmask.long.word 0xC 0.--15. 1. "TSHWR,Timestamp Higher Word Register This field contains the most-significant 16-bits of timestamp seconds value" rgroup.long 0xB20++0x3 line.long 0x0 "MAC_Timestamp_Status,Timestamp Status register. All bits except Bits[27:25] gets cleared when the application reads this register." bitfld.long 0x0 30.--31. "Reserved_31_30,Reserved." "0,1,2,3" newline hexmask.long.byte 0x0 25.--29. 1. "Reserved_ATSNS,Reserved." newline bitfld.long 0x0 24. "Reserved_ATSSTM,Reserved." "0,1" newline hexmask.long.byte 0x0 20.--23. 1. "Reserved_23_20,Reserved." newline hexmask.long.byte 0x0 16.--19. 1. "Reserved_ATSSTN,Reserved." newline bitfld.long 0x0 15. "TXTSSIS,Tx Timestamp Status Interrupt Status In non-EQOS_CORE configurations when drop transmit status is enabled in MTL this bit is set when the captured transmit timestamp is updated in the MAC_Tx_Timestamp_Status_Nanoseconds and.." "0: Tx Timestamp Status Interrupt status not detected,1: Tx Timestamp Status Interrupt status detected" newline hexmask.long.byte 0x0 10.--14. 1. "Reserved_14_10,Reserved." newline bitfld.long 0x0 9. "TSTRGTERR3,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS3_Target_Time_Seconds and MAC_PPS3_Target_Time_Nanoseconds registers elapses" "0: Timestamp Target Time Error status not detected,1: Timestamp Target Time Error status detected" newline bitfld.long 0x0 8. "TSTARGT3,Timestamp Target Time Reached for Target Time PPS3 When this bit is set and MCGREN3 of MAC_PPS_Control register is reset it indicates that the value of system time is greater than or equal to the value specified in the.." "0: Timestamp Target Time Reached for Target Time..,1: Timestamp Target Time Reached for Target Time.." newline bitfld.long 0x0 7. "TSTRGTERR2,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS2_Target_Time_Seconds and MAC_PPS2_Target_Time_Nanoseconds registers elapses" "0: Timestamp Target Time Error status not detected,1: Timestamp Target Time Error status detected" newline bitfld.long 0x0 6. "TSTARGT2,Timestamp Target Time Reached for Target Time PPS2 When this bit is set and MCGREN2 of MAC_PPS_Control register is reset it indicates that the value of system time is greater than or equal to the value specified in the.." "0: Timestamp Target Time Reached for Target Time..,1: Timestamp Target Time Reached for Target Time.." newline bitfld.long 0x0 5. "TSTRGTERR1,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS1_Target_Time_Seconds and MAC_PPS1_Target_Time_Nanoseconds registers elapses" "0: Timestamp Target Time Error status not detected,1: Timestamp Target Time Error status detected" newline bitfld.long 0x0 4. "TSTARGT1,Timestamp Target Time Reached for Target Time PPS1 When this bit is set and MCGREN1 of MAC_PPS_Control register is reset it indicates that the value of system time is greater than or equal to the value specified in the.." "0: Timestamp Target Time Reached for Target Time..,1: Timestamp Target Time Reached for Target Time.." newline bitfld.long 0x0 3. "TSTRGTERR0,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS0_Target_Time_Seconds and MAC_PPS0_Target_Time_Nanoseconds registers elapses" "0: Timestamp Target Time Error status not detected,1: Timestamp Target Time Error status detected" newline bitfld.long 0x0 2. "Reserved_AUXTSTRIG,Reserved." "0,1" newline bitfld.long 0x0 1. "TSTARGT0,Timestamp Target Time Reached When this bit is set and MCGREN0 of MAC_PPS_Control register is reset it indicates that the value of system time is greater than or equal to the value specified in the MAC_PPS0_Target_Time_Seconds and.." "0: Timestamp Target Time Reached status not detected,1: Timestamp Target Time Reached status detected" newline bitfld.long 0x0 0. "TSSOVF,Timestamp Seconds Overflow When this bit is set it indicates that the seconds value of the timestamp (when supporting version 2 format) has overflowed beyond 32'hFFFF_FFFF" "0: Timestamp Seconds Overflow status not detected,1: Timestamp Seconds Overflow status detected" rgroup.long 0xB30++0x7 line.long 0x0 "MAC_Tx_Timestamp_Status_Nanoseconds,This register contains the nanosecond part of timestamp captured for Transmit packets when Tx status is disabled. The MAC_Tx_Timestamp_Status_Nanoseconds register. along with MAC_Tx_Timestamp_Status_Seconds. gives the.." bitfld.long 0x0 31. "TXTSSMIS,Transmit Timestamp Status Missed When this bit is set it indicates one of the following: - The timestamp of the current packet is ignored if TXTSSTSM bit of the MAC_Timestamp_Control register is reset - The timestamp of the previous packet is.." "0: Transmit Timestamp Status Missed status not..,1: Transmit Timestamp Status Missed status detected" newline hexmask.long 0x0 0.--30. 1. "TXTSSLO,Transmit Timestamp Status Low This field contains the 31 bits of the Nanoseconds field of the Transmit packet's captured timestamp" line.long 0x4 "MAC_Tx_Timestamp_Status_Seconds,The register contains the higher 32 bits of the timestamp (in seconds) captured when a PTP packet is transmitted." hexmask.long 0x4 0.--31. 1. "TXTSSHI,Transmit Timestamp Status High This field contains the lower 32 bits of the Seconds field of Transmit packet's captured timestamp" group.long 0xB50++0x17 line.long 0x0 "MAC_Timestamp_Ingress_Asym_Corr,The MAC Timestamp Ingress Asymmetry Correction register contains the Ingress Asymmetry Correction value to be used while updating correction field in PDelay_Resp PTP messages." hexmask.long 0x0 0.--31. 1. "OSTIAC,One-Step Timestamp Ingress Asymmetry Correction This field contains the ingress path asymmetry value to be added to correctionField of Pdelay_Resp PTP packet" line.long 0x4 "MAC_Timestamp_Egress_Asym_Corr,The MAC Timestamp Egress Asymmetry Correction register contains the Egress Asymmetry Correction value to be used while updating the correction field in PDelay_Req PTP messages." hexmask.long 0x4 0.--31. 1. "OSTEAC,One-Step Timestamp Egress Asymmetry Correction This field contains the egress path asymmetry value to be subtracted from correctionField of Pdelay_Resp PTP packet" line.long 0x8 "MAC_Timestamp_Ingress_Corr_Nanosecond,This register contains the correction value in nanoseconds to be used with the captured timestamp value in the ingress path." hexmask.long 0x8 0.--31. 1. "TSIC,Timestamp Ingress Correction This field contains the ingress path correction value as defined by the Ingress Correction expression" line.long 0xC "MAC_Timestamp_Egress_Corr_Nanosecond,This register contains the correction value in nanoseconds to be used with the captured timestamp value in the egress path." hexmask.long 0xC 0.--31. 1. "TSEC,Timestamp Egress Correction This field contains the nanoseconds part of the egress path correction value as defined by the Egress Correction expression" line.long 0x10 "MAC_Timestamp_Ingress_Corr_Subnanosec,This register contains the sub-nanosecond part of the correction value to be used with the captured timestamp value. for ingress direction." hexmask.long.word 0x10 16.--31. 1. "Reserved_31_16,Reserved." newline hexmask.long.byte 0x10 8.--15. 1. "TSICSNS,Timestamp Ingress Correction sub-nanoseconds This field contains the sub-nanoseconds part of the ingress path correction value as defined by the 'Ingress Correction' expression" newline hexmask.long.byte 0x10 0.--7. 1. "Reserved_7_0,Reserved." line.long 0x14 "MAC_Timestamp_Egress_Corr_Subnanosec,This register contains the sub-nanosecond part of the correction value to be used with the captured timestamp value. for egress direction." hexmask.long.word 0x14 16.--31. 1. "Reserved_31_16,Reserved." newline hexmask.long.byte 0x14 8.--15. 1. "TSECSNS,Timestamp Egress Correction sub-nanoseconds This field contains the sub-nanoseconds part of the egress path correction value as defined by the 'Egress Correction' expression" newline hexmask.long.byte 0x14 0.--7. 1. "Reserved_7_0,Reserved." rgroup.long 0xB68++0x7 line.long 0x0 "MAC_Timestamp_Ingress_Latency,This register holds the Ingress MAC latency." hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_28,Reserved." newline hexmask.long.word 0x0 16.--27. 1. "ITLNS,Ingress Timestamp Latency in sub-nanoseconds This register holds the average latency in sub-nanoseconds between the input ports (phy_rxd_i) of MAC and the actual point (GMII/MII) where the ingress timestamp is taken" newline hexmask.long.byte 0x0 8.--15. 1. "ITLSNS,Ingress Timestamp Latency in nanoseconds This register holds the average latency in nanoseconds between the input ports (phy_rxd_i) of MAC and the actual point (GMII/MII) where the ingress timestamp is taken" newline hexmask.long.byte 0x0 0.--7. 1. "Reserved_7_0,Reserved." line.long 0x4 "MAC_Timestamp_Egress_Latency,This register holds the Egress MAC latency." hexmask.long.byte 0x4 28.--31. 1. "Reserved_31_28,Reserved." newline hexmask.long.word 0x4 16.--27. 1. "ETLNS,Egress Timestamp Latency in nanoseconds This register holds the average latency in nanoseconds between the actual point (GMII/MII) where the egress timestamp is taken and the output ports (phy_txd_o) of the MAC" newline hexmask.long.byte 0x4 8.--15. 1. "ETLSNS,Egress Timestamp Latency in sub-nanoseconds This register holds the average latency in sub-nanoseconds between the actual point (GMII/MII) where the egress timestamp is taken and the output ports (phy_txd_o) of the MAC" newline hexmask.long.byte 0x4 0.--7. 1. "Reserved_7_0,Reserved." group.long 0xB70++0x3 line.long 0x0 "MAC_PPS_Control,PPS Control register. Bits[30:24] of this register are valid only when four Flexible PPS outputs are selected. Bits[22:16] are valid only when three or more Flexible PPS outputs are selected. Bits[14:8] are valid only when two or more.." bitfld.long 0x0 31. "MCGREN3,MCGR Mode Enable for PPS3 Output This field enables the 3rd PPS instance to operate in PPS or MCGR mode" "0,1" newline bitfld.long 0x0 29.--30. "TRGTMODSEL3,Target Time Register Mode for PPS3 Output This field indicates the Target Time registers (MAC_PPS3_Target_Time_Seconds and MAC_PPS3_Target_Time_Nanoseconds) mode for PPS3 output signal" "0: Target Time registers are programmed only for..,1: Enables MCGR Interrupt whose status bit is..,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.." newline bitfld.long 0x0 28. "TIMESEL,Time Select When this bit is set 64 bit PTP time is used to capture time at MCGR trigger[0] input When this bit is reset presentation time is used to capture time at trigger input maintaining backward compatibility" "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "PPSCMD3,Flexible PPS3 Output Control This field controls the flexible PPS3 output (ptp_pps_o[3]) signal" newline bitfld.long 0x0 23. "MCGREN2,MCGR Mode Enable for PPS2 Output This field enables the 2nd PPS instance to operate in PPS or MCGR mode" "0: 2nd PPS instance is disabled to operate in PPS..,1: 2nd PPS instance is enabled to operate in PPS or.." newline bitfld.long 0x0 21.--22. "TRGTMODSEL2,Target Time Register Mode for PPS2 Output This field indicates the Target Time registers (MAC_PPS2_Target_Time_Seconds and MAC_PPS2_Target_Time_Nanoseconds) mode for PPS2 output signal" "0: Target Time registers are programmed only for..,1: Enables MCGR Interrupt whose status bit is..,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.." newline rbitfld.long 0x0 20. "Reserved_20,Reserved." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "PPSCMD2,Flexible PPS2 Output Control This field controls the flexible PPS2 output (ptp_pps_o[2]) signal" newline bitfld.long 0x0 15. "MCGREN1,MCGR Mode Enable for PPS1 Output This field enables the 1st PPS instance to operate in PPS or MCGR mode" "0: 1st PPS instance is disabled to operate in PPS..,1: 1st PPS instance is enabled to operate in PPS or.." newline bitfld.long 0x0 13.--14. "TRGTMODSEL1,Target Time Register Mode for PPS1 Output This field indicates the Target Time registers (MAC_PPS1_Target_Time_Seconds and MAC_PPS1_Target_Time_Nanoseconds) mode for PPS1 output signal" "0: Target Time registers are programmed only for..,1: Enables MCGR Interrupt whose status bit is..,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.." newline rbitfld.long 0x0 12. "Reserved_12,Reserved." "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "PPSCMD1,Flexible PPS1 Output Control This field controls the flexible PPS1 output (ptp_pps_o[1]) signal" newline bitfld.long 0x0 7. "MCGREN0,MCGR Mode Enable for PPS0 Output This field enables the 0th PPS instance to operate in PPS or MCGR mode" "0: 0th PPS instance is enabled to operate in PPS mode,1: 0th PPS instance is enabled to operate in MCGR.." newline bitfld.long 0x0 5.--6. "TRGTMODSEL0,Target Time Register Mode for PPS0 Output This field indicates the Target Time registers (MAC_PPS0_Target_Time_Seconds and MAC_PPS0_Target_Time_Nanoseconds) mode for PPS0 output signal:" "0: Target Time registers are programmed only for..,1: Enables MCGR Interrupt whose status bit is..,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.." newline bitfld.long 0x0 4. "PPSEN0,Flexible PPS Output Mode Enable When this bit is - 1: Bits[3:0] function as PPSCMD" "0: Flexible PPS Output Mode is disabled,1: Bits[3:0] function as PPSCMD" newline hexmask.long.byte 0x0 0.--3. 1. "PPSCTRL_PPSCMD,PPS Output Frequency Control This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal" group.long 0xB80++0x3F line.long 0x0 "MAC_PPS0_Target_Time_Seconds,The PPS Target Time Seconds register. along with PPS Target Time Nanoseconds register. is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these registers." hexmask.long 0x0 0.--31. 1. "TSTRH0,PPS Target Time Seconds Register This field stores the time in seconds" line.long 0x4 "MAC_PPS0_Target_Time_Nanoseconds,PPS0 Target Time Nanoseconds register." bitfld.long 0x4 31. "TRGTBUSY0,PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the MAC_PPS_Control register is programmed to 010 or 011" "0: PPS Target Time Register Busy status is not..,1: PPS Target Time Register Busy is detected" newline hexmask.long 0x4 0.--30. 1. "TTSL0,Target Time Low for PPS Register This register stores the time in (signed) nanoseconds" line.long 0x8 "MAC_PPS0_Interval,The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0x8 0.--31. 1. "PPSINT0,PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output" line.long 0xC "MAC_PPS0_Width,The PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0xC 0.--31. 1. "PPSWIDTH0,PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output" line.long 0x10 "MAC_PPS1_Target_Time_Seconds,The PPS Target Time Seconds register. along with PPS Target Time Nanoseconds register. is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these registers." hexmask.long 0x10 0.--31. 1. "TSTRH1,PPS Target Time Seconds Register This field stores the time in seconds" line.long 0x14 "MAC_PPS1_Target_Time_Nanoseconds,PPS0 Target Time Nanoseconds register." bitfld.long 0x14 31. "TRGTBUSY1,PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the MAC_PPS_Control register is programmed to 010 or 011" "0: PPS Target Time Register Busy status is not..,1: PPS Target Time Register Busy is detected" newline hexmask.long 0x14 0.--30. 1. "TTSL1,Target Time Low for PPS Register This register stores the time in (signed) nanoseconds" line.long 0x18 "MAC_PPS1_Interval,The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0x18 0.--31. 1. "PPSINT1,PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output" line.long 0x1C "MAC_PPS1_Width,The PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0x1C 0.--31. 1. "PPSWIDTH1,PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output" line.long 0x20 "MAC_PPS2_Target_Time_Seconds,The PPS Target Time Seconds register. along with PPS Target Time Nanoseconds register. is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these registers." hexmask.long 0x20 0.--31. 1. "TSTRH2,PPS Target Time Seconds Register This field stores the time in seconds" line.long 0x24 "MAC_PPS2_Target_Time_Nanoseconds,PPS0 Target Time Nanoseconds register." bitfld.long 0x24 31. "TRGTBUSY2,PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the MAC_PPS_Control register is programmed to 010 or 011" "0: PPS Target Time Register Busy status is not..,1: PPS Target Time Register Busy is detected" newline hexmask.long 0x24 0.--30. 1. "TTSL2,Target Time Low for PPS Register This register stores the time in (signed) nanoseconds" line.long 0x28 "MAC_PPS2_Interval,The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0x28 0.--31. 1. "PPSINT2,PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output" line.long 0x2C "MAC_PPS2_Width,The PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0x2C 0.--31. 1. "PPSWIDTH2,PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output" line.long 0x30 "MAC_PPS3_Target_Time_Seconds,The PPS Target Time Seconds register. along with PPS Target Time Nanoseconds register. is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these registers." hexmask.long 0x30 0.--31. 1. "TSTRH3,PPS Target Time Seconds Register This field stores the time in seconds" line.long 0x34 "MAC_PPS3_Target_Time_Nanoseconds,PPS0 Target Time Nanoseconds register." bitfld.long 0x34 31. "TRGTBUSY3,PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the MAC_PPS_Control register is programmed to 010 or 011" "0: PPS Target Time Register Busy status is not..,1: PPS Target Time Register Busy is detected" newline hexmask.long 0x34 0.--30. 1. "TTSL3,Target Time Low for PPS Register This register stores the time in (signed) nanoseconds" line.long 0x38 "MAC_PPS3_Interval,The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0x38 0.--31. 1. "PPSINT3,PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output" line.long 0x3C "MAC_PPS3_Width,The PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0x3C 0.--31. 1. "PPSWIDTH3,PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output" group.long 0xC00++0x3 line.long 0x0 "MTL_Operation_Mode,The Operation Mode register establishes the Transmit and Receive operating modes and commands." hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved." newline bitfld.long 0x0 15. "FRPE,Flexible Rx parser Enable - 1: Enables Programmable Rx Parser - 0: Disables Programmable Rx Parser When the Rx parser is disabled when parsing is in progress the Rx parser is disabled only after the current packet parsing complete" "0: Disables Programmable Rx Parser When the Rx..,1: Enables Programmable Rx Parser" newline bitfld.long 0x0 14. "RXPED,RxParser Software Error/Incomplete Parsing Packet Drop Enable when this bit is set to 0 packets encountering software programming errors (NPE/NVE/frame offset overflow errors) or incomplete parsing are forwarded to application with the.." "0: Flexible Rx parser packet drop in case software..,1: Flexible Rx parser packet drop in case software.." newline hexmask.long.byte 0x0 10.--13. 1. "Reserved_13_10,Reserved." newline bitfld.long 0x0 9. "CNTCLR,Counters Reset When this bit is set all counters are reset" "0: Counters are not reset,1: All counters are reset" newline bitfld.long 0x0 8. "CNTPRST,Counters Preset When this bit is set - MTL_TxQ[0-7]_Underflow register is initialized/preset to 12'h7F0" "0: Counters Preset is disabled,1: Counters Preset is enabled" newline rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1" newline bitfld.long 0x0 5.--6. "SCHALG,Tx Scheduling Algorithm This field indicates the algorithm for Tx scheduling:" "0: WRR algorithm,1: WFQ algorithm when DCB feature is..,2: DWRR algorithm when DCB feature is..,3: Strict priority algorithm" newline rbitfld.long 0x0 3.--4. "Reserved_4_3,Reserved." "0,1,2,3" newline bitfld.long 0x0 2. "RAA,Receive Arbitration Algorithm This field is used to select the arbitration algorithm for the Rx side" "0: Strict priority (SP),1: Weighted Strict Priority (WSP)" newline bitfld.long 0x0 1. "DTXSTS,Drop Transmit Status - 1: Tx packet status received from the MAC is dropped in the MTL - 0: Tx packet status received from the MAC is forwarded to the application" "0: Tx packet status received from the MAC is..,1: Tx packet status received from the MAC is.." newline rbitfld.long 0x0 0. "Reserved_0,Reserved." "0,1" group.long 0xC08++0xB line.long 0x0 "MTL_DBG_CTL,The FIFO Debug Access Control and Status register controls the operation mode of FIFO debug access." hexmask.long.word 0x0 19.--31. 1. "Reserved_31_19,Reserved." newline bitfld.long 0x0 18. "EIEC,ECC Inject Error Control for Tx Rx TSO and DCACHE memories When EIEE or EIAEE bit of this register is set following are the errors inserted based on the value encoded in this field" "0: Insert 1 bit error,1: insert 2 bit errors" newline bitfld.long 0x0 17. "EIAEE,ECC Inject Address Error for Tx Rx TSO and DCACHE memories - 1: Enables the ECC address error injection feature - 0: Disables the ECC address error injection feature" "0: Disables the ECC address error injection feature,1: Enables the ECC address error injection feature" newline bitfld.long 0x0 16. "EIEE,ECC Inject Error Enable for Tx Rx TSO and DCACHE memories - 1: Enables the ECC error injection feature - 0: Disables the ECC error injection feature" "0: Disables the ECC error injection feature,1: Enables the ECC error injection feature" newline bitfld.long 0x0 15. "STSIE,Transmit Status Available Interrupt Status Enable When this bit is set an interrupt is generated when Transmit status is available in slave mode" "0: Transmit Packet Available Interrupt Status is..,1: Transmit Packet Available Interrupt Status is.." newline bitfld.long 0x0 14. "PKTIE,Receive Packet Available Interrupt Status Enable When this bit is set an interrupt is generated when EOP of received packet is written to the Rx FIFO" "0: Receive Packet Available Interrupt Status is..,1: Receive Packet Available Interrupt Status is.." newline bitfld.long 0x0 12.--13. "FIFOSEL,FIFO Selected for Access This field indicates the FIFO selected for debug access." "0: Tx FIFO,1: Tx Status FIFO (only read access when SLVMOD is..,2: TSO FIFO (cannot be accessed when SLVMOD is set),3: Rx FIFO" newline bitfld.long 0x0 11. "FIFOWREN,FIFO Write Enable When this bit is set it enables the Write operation on selected FIFO when FIFO Debug Access is enabled" "0: FIFO Write is disabled,1: FIFO Write is enabled" newline bitfld.long 0x0 10. "FIFORDEN,FIFO Read Enable When this bit is set it enables the Read operation on selected FIFO when FIFO Debug Access is enabled" "0: FIFO Read is disabled,1: FIFO Read is enabled" newline bitfld.long 0x0 9. "RSTSEL,Reset Pointers of Selected FIFO When this bit is set the pointers of the currently-selected FIFO are reset when FIFO Debug Access is enabled" "0: Reset Pointers of Selected FIFO is disabled,1: Reset Pointers of Selected FIFO is enabled" newline bitfld.long 0x0 8. "RSTALL,Reset All Pointers When this bit is set the pointers of all FIFOs are reset when FIFO Debug Access is enabled" "0: Reset All Pointers is disabled,1: Reset All Pointers is enabled" newline rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1" newline bitfld.long 0x0 5.--6. "PKTSTATE,Encoded Packet State This field is used to write the control information to the Tx FIFO or Rx FIFO" "0: Packet Data,1: Control Word/Normal Status,2: SOP Data/Last Status,3: EOP Data/EOP" newline rbitfld.long 0x0 4. "Reserved_4,Reserved." "0,1" newline bitfld.long 0x0 2.--3. "BYTEEN,Byte Enables This field indicates the number of data bytes valid in the data register during Write operation" "0: Byte 0 valid,1: Byte 0 and Byte 1 are valid,2: Byte 0 Byte 1 and Byte 2 are valid,3: All four bytes are valid" newline bitfld.long 0x0 1. "DBGMOD,Debug Mode Access to FIFO - 1: Indicates that the current access to the FIFO is read write and debug access" "0: Debug Mode Access to FIFO is disabled,1: Indicates that the current access to the FIFO is.." newline bitfld.long 0x0 0. "FDBGEN,FIFO Debug Access Enable - 1: Indicates that the debug mode access to the FIFO is enabled" "0: FIFO Debug Access is disabled,1: Indicates that the debug mode access to the FIFO.." line.long 0x4 "MTL_DBG_STS,The FIFO Debug Status register contains the status of FIFO debug access." hexmask.long.tbyte 0x4 15.--31. 1. "LOCR,Remaining Locations in the FIFO - Slave Access Mode: This field indicates the space available in the selected FIFO" newline hexmask.long.byte 0x4 10.--14. 1. "Reserved_14_10,Reserved." newline bitfld.long 0x4 9. "STSI,Transmit Status Available Interrupt Status When set this bit indicates that the Slave mode Tx packet is transmitted and the status is available in Tx Status FIFO" "0: Transmit Status Available Interrupt Status not..,1: Transmit Status Available Interrupt Status.." newline bitfld.long 0x4 8. "PKTI,Receive Packet Available Interrupt Status When set this bit indicates that MAC layer has written the EOP of received packet to the Rx FIFO" "0: Receive Packet Available Interrupt Status not..,1: Receive Packet Available Interrupt Status detected" newline rbitfld.long 0x4 5.--7. "Reserved_7_5,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 3.--4. "BYTEEN,Byte Enables This field indicates the number of data bytes valid in the data register during Read operation" "0: Byte 0 valid,1: Byte 0 and Byte 1 are valid,2: Byte 0 Byte 1 and Byte 2 are valid,3: All four bytes are valid" newline rbitfld.long 0x4 1.--2. "PKTSTATE,Encoded Packet State This field is used to get the control or status information of the selected FIFO" "0: Packet Data,1: Control Word/Normal Status,2: SOP Data/Last Status,3: EOP Data/EOP" newline rbitfld.long 0x4 0. "FIFOBUSY,FIFO Busy When set this bit indicates that a FIFO operation is in progress in the MAC and content of the following fields is not valid: - All other fields of this register - All fields of the MTL_FIFO_Debug_Data register" "0: FIFO Busy not detected,1: FIFO Busy detected" line.long 0x8 "MTL_FIFO_Debug_Data,The FIFO Debug Data register contains the data to be written to or read from the FIFOs." hexmask.long 0x8 0.--31. 1. "FDBGDATA,FIFO Debug Data During debug or slave access write operation this field contains the data to be written to the Tx FIFO Rx FIFO or TSO FIFO" rgroup.long 0xC20++0x3 line.long 0x0 "MTL_Interrupt_Status,The software driver (application) reads this register during interrupt service routine or polling to determine the interrupt status of MTL queues and the MAC." hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved." newline bitfld.long 0x0 23. "MTLPIS,MTL Rx Parser Interrupt Status This bit indicates that there is an interrupt from Rx Parser Block" "0: MTL Rx Parser Interrupt status not detected,1: MTL Rx Parser Interrupt status detected" newline hexmask.long.byte 0x0 19.--22. 1. "Reserved_22_19,Reserved." newline bitfld.long 0x0 18. "ESTIS,EST (TAS- 802" "0: EST (TAS- 802.1Qbv) Interrupt status not detected,1: EST (TAS- 802.1Qbv) Interrupt status detected" newline bitfld.long 0x0 17. "DBGIS,Debug Interrupt status This bit indicates an interrupt event during the slave access" "0: Debug Interrupt status not detected,1: Debug Interrupt status detected" newline bitfld.long 0x0 16. "Reserved_MACIS,Reserved." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "Reserved_15_8,Reserved." newline bitfld.long 0x0 7. "Reserved_Q7IS,Reserved." "0,1" newline bitfld.long 0x0 6. "Reserved_Q6IS,Reserved." "0,1" newline bitfld.long 0x0 5. "Reserved_Q5IS,Reserved." "0,1" newline bitfld.long 0x0 4. "Reserved_Q4IS,Reserved." "0,1" newline bitfld.long 0x0 3. "Reserved_Q3IS,Reserved." "0,1" newline bitfld.long 0x0 2. "Q2IS,Queue 2 Interrupt status This bit indicates that there is an interrupt from Queue 2" "0: Queue 2 Interrupt status not detected,1: Queue 2 Interrupt status detected" newline bitfld.long 0x0 1. "Q1IS,Queue 1 Interrupt status This bit indicates that there is an interrupt from Queue 1" "0: Queue 1 Interrupt status not detected,1: Queue 1 Interrupt status detected" newline bitfld.long 0x0 0. "Q0IS,Queue 0 Interrupt status This bit indicates that there is an interrupt from Queue 0" "0: Queue 0 Interrupt status not detected,1: Queue 0 Interrupt status detected" group.long 0xC30++0x3 line.long 0x0 "MTL_RxQ_DMA_Map0,The Receive Queue and DMA Channel Mapping 0 register is reserved in EQOS-CORE and EQOS-MTL configurations." rbitfld.long 0x0 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 28. "Reserved_Q3DDMACH,Reserved." "0,1" newline rbitfld.long 0x0 26.--27. "Reserved_27_y,Reserved." "0,1,2,3" newline rbitfld.long 0x0 24.--25. "Reserved_Q3MDMACH,Reserved." "0,1,2,3" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "Q2DDMACH,Queue 2 Enabled for DA-based DMA Channel Selection When set this bit indicates that the packets received in Queue 2 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4.." "0: Queue 2 disabled for DA-based DMA Channel..,1: Queue 2 enabled for DA-based DMA Channel Selection" newline rbitfld.long 0x0 18.--19. "Reserved_19_y,Reserved." "0,1,2,3" newline bitfld.long 0x0 16.--17. "Q2MDMACH,Queue 2 Mapped to DMA Channel This field controls the routing of the received packet in Queue 2 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: DMA Channel 5 -.." "0: DMA Channel 0,1: DMA Channel 1,?,?" newline rbitfld.long 0x0 13.--15. "Reserved_15_13,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12. "Q1DDMACH,Queue 1 Enabled for DA-based DMA Channel Selection When set this bit indicates that the packets received in Queue 1 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4.." "0: Queue 1 disabled for DA-based DMA Channel..,1: Queue 1 enabled for DA-based DMA Channel Selection" newline rbitfld.long 0x0 10.--11. "Reserved_11_y,Reserved." "0,1,2,3" newline bitfld.long 0x0 8.--9. "Q1MDMACH,Queue 1 Mapped to DMA Channel This field controls the routing of the received packet in Queue 1 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: DMA Channel 5 -.." "0: DMA Channel 0,1: DMA Channel 1,?,?" newline rbitfld.long 0x0 5.--7. "Reserved_7_5,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "Q0DDMACH,Queue 0 Enabled for DA-based DMA Channel Selection When set this bit indicates that the packets received in Queue 0 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4.." "0: Queue 0 disabled for DA-based DMA Channel..,1: Queue 0 enabled for DA-based DMA Channel Selection" newline rbitfld.long 0x0 2.--3. "Reserved_3_y,Reserved." "0,1,2,3" newline bitfld.long 0x0 0.--1. "Q0MDMACH,Queue 0 Mapped to DMA Channel This field controls the routing of the packet received in Queue 0 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: DMA Channel 5 -.." "0: DMA Channel 0,1: DMA Channel 1,?,?" group.long 0xC40++0x3 line.long 0x0 "MTL_TBS_CTRL,This register controls the operation of Time Based Scheduling." hexmask.long.tbyte 0x0 8.--31. 1. "LEOS,Launch Expiry Offset The value in units of 256 nanoseconds that has to be added to the Launch time to compute the Launch Expiry time" newline rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1" newline bitfld.long 0x0 4.--6. "LEGOS,Launch Expiry GSN Offset The number GSN slots that has to be added to the Launch GSN to compute the Launch Expiry time" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 2.--3. "Reserved_3_2,Reserved." "0,1,2,3" newline bitfld.long 0x0 1. "LEOV,Launch Expiry Offset Valid When set indicates the LEOS field is valid" "0: LEOS field is invalid,1: LEOS field is valid" newline bitfld.long 0x0 0. "ESTM,EST offset Mode When this bit is set the Launch Time value used in Time Based Scheduling is interpreted as an EST offset value and is added to the Base Time Register (BTR) of the current list" "0: EST offset Mode is disabled,1: EST offset Mode is enabled" group.long 0xC50++0xB line.long 0x0 "MTL_EST_Control,This register controls the operation of Enhancements to Scheduled Transmission (IEEE802.1Qbv)." hexmask.long.byte 0x0 24.--31. 1. "PTOV,PTP Time Offset Value The value of PTP Clock period multiplied by 6 in nanoseconds" newline hexmask.long.word 0x0 12.--23. 1. "CTOV,Current Time Offset Value Provides a 12 bit time offset value in nano second that is added to the current time to compensate for all the implementation pipeline delays such as the CDC sync delay buffering delays data path delays and so on" newline rbitfld.long 0x0 11. "Reserved_11,Reserved." "0,1" newline bitfld.long 0x0 8.--10. "TILS,Time Interval Left Shift Amount This field provides the left shift amount for the programmed Time Interval values used in the Gate Control Lists" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "LCSE,Loop Count to report Scheduling Error Programmable number of GCL list iterations before reporting an HLBS error defined in EST_Status register" "0: 4 iterations,1: 8 iterations,2: 16 iterations,3: 32 iterations" newline bitfld.long 0x0 5. "DFBS,Drop Frames causing Scheduling Error When set frames reported to cause HOL Blocking due to not getting scheduled (HLBS field of EST_Status register) after 4 8 16 32 (based on LCSE field of this register) GCL iterations are dropped" "0: Do not Drop Frames causing Scheduling Error,1: Drop Frames causing Scheduling Error" newline bitfld.long 0x0 4. "DDBF,Do not Drop frames during Frame Size Error When set frames are not be dropped during Head-of-Line blocking due to Frame Size Error (HLBF field of EST_Status register)" "0: Drop frames during Frame Size Error,1: Do not Drop frames during Frame Size Error" newline bitfld.long 0x0 3. "QHLBF,Quick Assertion of HLBF Error When set Time Window for Head-of-Line blocking due to Frame Size Error is 1 to 2 loop count of GCL list" "0: Disable Quick assertion of HLBF error,1: Quick Assertion of HLBF Error" newline rbitfld.long 0x0 2. "Reserved_2,Reserved." "0,1" newline bitfld.long 0x0 1. "SSWL,Switch to S/W owned list When set indicates that the software has programmed that list that it currently owns (SWOL) and the hardware should switch to the new list based on the new BTR" "0: Switch to S/W owned list is disabled,1: Switch to S/W owned list is enabled" newline bitfld.long 0x0 0. "EEST,Enable EST When reset the gate control list processing is halted and all gates are assumed to be in Open state" "0: EST is disabled,1: EST is enabled" line.long 0x4 "MTL_EST_Ext_Control,This register indicates the number of Overhead bytes for EST related scheduling." hexmask.long 0x4 6.--31. 1. "Reserved_31_6,Reserved." newline hexmask.long.byte 0x4 0.--5. 1. "OVHD,Overhead Bytes Value This field indicates the fixed overhead for every packet to account for EST Scheduler Delay IPG or EIPG and Preamble bytes" line.long 0x8 "MTL_EST_Status,This register provides Status related to Enhancements to Scheduled Transmission (IEEE802.1Qbv)." hexmask.long.word 0x8 20.--31. 1. "Reserved_31_20,Reserved." newline hexmask.long.byte 0x8 16.--19. 1. "CGSN,Current GCL Slot Number Indicates the slot number of the GCL list" newline hexmask.long.byte 0x8 8.--15. 1. "BTRL,BTR Error Loop Count Provides the minimum count (N) for which the equation Current Time =< New BTR + (N * New Cycle Time) becomes true" newline rbitfld.long 0x8 7. "SWOL,S/W owned list When '0' indicates Gate control list number '0' is owned by software and when '1' indicates the Gate Control list '1' is owned by the software" "0: Gate control list number '0' is owned by software,1: Gate control list number '1' is owned by software" newline rbitfld.long 0x8 5.--6. "Reserved_6_5,Reserved." "0,1,2,3" newline bitfld.long 0x8 4. "CGCE,Constant Gate Control Error This error occurs when the list length (LLR) is 1 and the Cycle Time (CTR) is less than or equal to the programmed Time Interval (TI) value after the optional Left Shifting" "0: Constant Gate Control Error not detected,1: Constant Gate Control Error detected" newline rbitfld.long 0x8 3. "HLBS,Head-Of-Line Blocking due to Scheduling Set when the frame is not able to win arbitration and get scheduled even after 4 iterations of the GCL" "0: Head-Of-Line Blocking due to Scheduling not..,1: Head-Of-Line Blocking due to Scheduling detected" newline rbitfld.long 0x8 2. "HLBF,Head-Of-Line Blocking due to Frame Size Set when HOL Blocking is noticed on one or more Queues as a result of none of the Time Intervals of gate open in the GCL being greater than or equal to the duration needed for frame size (or frame fragment.." "0: Head-Of-Line Blocking due to Frame Size not..,1: Head-Of-Line Blocking due to Frame Size detected" newline bitfld.long 0x8 1. "BTRE,BTR Error When '1' indicates a programming error in the BTR of SWOL where the programmed value is less than current time" "0: BTR Error not detected,1: BTR Error detected" newline bitfld.long 0x8 0. "SWLC,Switch to S/W owned list Complete When '1' indicates the hardware has successfully switched to the SWOL and the SWOL bit has been updated to that effect" "0: Switch to S/W owned list Complete not detected,1: Switch to S/W owned list Complete detected" group.long 0xC60++0x7 line.long 0x0 "MTL_EST_Sch_Error,This register provides the One Hot encoded Queue Numbers that are having the Scheduling related error (timeout)." hexmask.long 0x0 3.--31. 1. "Reserved_31_x,Reserved." newline bitfld.long 0x0 0.--2. "SEQN,Schedule Error Queue Number The One Hot Encoded Queue Numbers that have experienced error/timeout described in HLBS field of status register" "0,1,2,3,4,5,6,7" line.long 0x4 "MTL_EST_Frm_Size_Error,This register provides the One Hot encoded Queue Numbers that are having the Frame Size related error." hexmask.long 0x4 3.--31. 1. "Reserved_31_x,Reserved." newline bitfld.long 0x4 0.--2. "FEQN,Frame Size Error Queue Number The One Hot Encoded Queue Numbers that have experienced error described in HLBF field of status register" "0,1,2,3,4,5,6,7" rgroup.long 0xC68++0x3 line.long 0x0 "MTL_EST_Frm_Size_Capture,This register captures the Frame Size and Queue Number of the first occurrence of the Frame Size related error. Up on clearing it captures the data of immediate next occurrence of a similar error." hexmask.long.word 0x0 18.--31. 1. "Reserved_31_x,Reserved." newline bitfld.long 0x0 16.--17. "HBFQ,Queue Number of HLBF Captures the binary value of the of the first Queue (number) experiencing HLBF error (see HLBF field of status register)" "0,1,2,3" newline bitfld.long 0x0 15. "Reserved_15,Reserved." "0,1" newline hexmask.long.word 0x0 0.--14. 1. "HBFS,Frame Size of HLBF Captures the Frame Size of the dropped frame related to queue number indicated in HBFQ field of this register" group.long 0xC70++0x3 line.long 0x0 "MTL_EST_Intr_Enable,This register implements the Interrupt Enable bits for the various events that generate an interrupt. Bit positions have a 1 to 1 correlation with the status bit positions in MTL_ETS_Status register." hexmask.long 0x0 5.--31. 1. "Reserved_31_5,Reserved." newline bitfld.long 0x0 4. "CGCE,Interrupt Enable for CGCE When set generates interrupt when the Constant Gate Control Error occurs and is indicated in the status" "0: Interrupt for CGCE is disabled,1: Interrupt for CGCE is enabled" newline bitfld.long 0x0 3. "IEHS,Interrupt Enable for HLBS When set generates interrupt when the Head-of-Line Blocking due to Scheduling issue and is indicated in the status" "0: Interrupt for HLBS is disabled,1: Interrupt for HLBS is enabled" newline bitfld.long 0x0 2. "IEHF,Interrupt Enable for HLBF When set generates interrupt when the Head-of-Line Blocking due to Frame Size error occurs and is indicated in the status" "0: Interrupt for HLBF is disabled,1: Interrupt for HLBF is enabled" newline bitfld.long 0x0 1. "IEBE,Interrupt Enable for BTR Error When set generates interrupt when the BTR Error occurs and is indicated in the status" "0: Interrupt for BTR Error is disabled,1: Interrupt for BTR Error is enabled" newline bitfld.long 0x0 0. "IECC,Interrupt Enable for Switch List When set generates interrupt when the configuration change is successful and the hardware has switched to the new list" "0: Interrupt for Switch List is disabled,1: Interrupt for Switch List is enabled" group.long 0xC80++0x7 line.long 0x0 "MTL_EST_GCL_Control,This register provides the control information for reading/writing to the Gate Control lists." hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved." newline bitfld.long 0x0 23. "ESTEIEC,ECC Inject Error Control for EST Memory When ESTEIEE or ESTEIAEE bit of this register is set following are the errors inserted based on the value encoded in this field" "0: Insert 1 bit error,1: Insert 2 bit errors" newline bitfld.long 0x0 22. "ESTEIAEE,EST ECC Inject Address Error Enable When set along with EEST bit of MTL_EST_Control register enables the ECC address error injection feature" "0: EST ECC Inject Address Error is disabled,1: EST ECC Inject Address Error is enabled" newline bitfld.long 0x0 21. "ESTEIEE,EST ECC Inject Error Enable When set along with EEST bit of MTL_EST_Control register enables the ECC error injection feature" "0: EST ECC Inject Error is disabled,1: EST ECC Inject Error is enabled" newline hexmask.long.byte 0x0 16.--20. 1. "Reserved_20_y,Reserved." newline hexmask.long.byte 0x0 8.--15. 1. "ADDR,Gate Control List Address: (GCLA when GCRR is '0')" newline bitfld.long 0x0 6.--7. "Reserved_7_6,Reserved." "0,1,2,3" newline bitfld.long 0x0 5. "DBGB,Debug Mode Bank Select When set to '0' indicates R/W in debug mode should be directed to Bank 0 (GCL0 and corresponding Time related registers)" "0: R/W in debug mode should be directed to Bank 0,1: R/W in debug mode should be directed to Bank 1" newline bitfld.long 0x0 4. "DBGM,Debug Mode When set to '1' indicates R/W in debug mode where the memory bank (for GCL and Time related registers) is explicitly provided by DBGB value when set to '0' SWOL bit is used to determine which bank to use" "0: Debug Mode is disabled,1: Debug Mode is enabled" newline bitfld.long 0x0 3. "Reserved_3,Reserved." "0,1" newline bitfld.long 0x0 2. "GCRR,Gate Control Related Registers When set to '1' indicates the R/W access is for the GCL related registers (BTR CTR TER LLR) whose address is provided by GCRA" "0: Gate Control Related Registers are disabled,1: Gate Control Related Registers are enabled" newline bitfld.long 0x0 1. "R1W0,Read '1' Write '0': - 1: Read operation - 0: Write operation." "0: Write operation,1: Read operation" newline bitfld.long 0x0 0. "SRWO,Start Read/Write Op - 1: Indicates the start/progress of a Read/Write operation" "0: Start Read/Write Op disabled,1: Indicates the start/progress of a Read/Write.." line.long 0x4 "MTL_EST_GCL_Data,This register holds the read data or write data in case of reads and writes respectively." hexmask.long 0x4 0.--31. 1. "GCD,Gate Control Data The data corresponding to the address selected in the GCL_Control register" group.long 0xC90++0x7 line.long 0x0 "MTL_FPE_CTRL_STS,This register controls the operation of. and provides status for Frame Preemption (IEEE802.1Qbu/802.3br)." rbitfld.long 0x0 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 28. "HRS,Hold/Release Status - 1: Indicates a Set-and-Hold-MAC operation was last executed and the pMAC is in Hold State" "0: Indicates a Set-and-Release-MAC operation was..,1: Indicates a Set-and-Hold-MAC operation was last.." newline hexmask.long.word 0x0 16.--27. 1. "Reserved_27_16,Reserved." newline hexmask.long.byte 0x0 11.--15. 1. "Reserved_15_y,Reserved." newline bitfld.long 0x0 8.--10. "PEC,Preemption Classification When set indicates the corresponding Queue must be classified as preemptable when '0' Queue is classified as express" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 2.--7. 1. "Reserved_7_2,Reserved." newline bitfld.long 0x0 0.--1. "AFSZ,Additional Fragment Size used to indicate in units of 64 bytes the minimum number of bytes over 64 bytes required in non-final fragments of preempted frames" "0,1,2,3" line.long 0x4 "MTL_FPE_Advance,This register holds the Hold and Release Advance time." hexmask.long.word 0x4 16.--31. 1. "RADV,Release Advance The maximum time in nanoseconds that can elapse between issuing a RELEASE to the MAC and the MAC being ready to resume transmission of preemptable frames in the absence of there being any express frames available for transmission" newline hexmask.long.word 0x4 0.--15. 1. "HADV,Hold Advance The maximum time in nanoseconds that can elapse between issuing a HOLD to the MAC and the MAC ceasing to transmit any preemptable frame that is in the process of transmission or any preemptable frames that are queued for transmission" group.long 0xCA0++0x7 line.long 0x0 "MTL_RXP_Control_Status,The MTL_RXP_Control_Status register establishes the operating mode of Rx Parser and provides some status." rbitfld.long 0x0 31. "RXPI,RX Parser in Idle state This status bit is set to 1 when the Rx parser is in Idle State and waiting for a new packet for processing" "0: RX Parser not in Idle state,1: RX Parser in Idle state" newline bitfld.long 0x0 30. "ELIRS,Enable Last Instruction in RX Status When this bit is set RDES2[31:16] indicates the index of the last instruction excecuted in Rx Parse when set to 0 indicates MAC filter status" "0,1" newline hexmask.long.byte 0x0 22.--29. 1. "Reserved_29_x,Reserved." newline hexmask.long.byte 0x0 16.--21. 1. "NPE,Number of parsable entries in the Instruction table This control indicates the number of parsable entries in the Instruction Memory" newline hexmask.long.word 0x0 6.--15. 1. "Reserved_15_x,Reserved." newline hexmask.long.byte 0x0 0.--5. 1. "NVE,Number of valid entry address/index in the Instruction table This control indicates the number of valid entries address/index in the Instruction Memory (i" line.long 0x4 "MTL_RXP_Interrupt_Control_Status,The MTL_RXP_Interrupt_Control_Status registers provides enable control for the interrupts and provides interrupt status." hexmask.long.word 0x4 20.--31. 1. "Reserved_31_20,Reserved." newline bitfld.long 0x4 19. "PDRFIE,Packet Drop due to RF Interrupt Enable When this bit is set the PDRFIS interrupt is enabled" "0: Packet Drop due to RF Interrupt is disabled,1: Packet Drop due to RF Interrupt is enabled" newline bitfld.long 0x4 18. "FOOVIE,Frame Offset Overflow Interrupt Enable When this bit is set the FOOVIS interrupt is enabled" "0: Frame Offset Overflow Interrupt is disabled,1: Frame Offset Overflow Interrupt is enabled" newline bitfld.long 0x4 17. "NPEOVIE,Number of Parsable Entries Overflow Interrupt Enable When this bit is set the NPEOVIS interrupt is enabled" "0: Number of Parsable Entries Overflow Interrupt is..,1: Number of Parsable Entries Overflow Interrupt is.." newline bitfld.long 0x4 16. "NVEOVIE,Number of Valid Entries Overflow Interrupt Enable When this bit is set the NVEOVIS interrupt is enabled" "0: Number of Valid Entries Overflow Interrupt is..,1: Number of Valid Entries Overflow Interrupt is.." newline hexmask.long.word 0x4 4.--15. 1. "Reserved_15_4,Reserved." newline bitfld.long 0x4 3. "PDRFIS,Packet Dropped due to RF Interrupt Status If the Rx Parser result says to drop the packet by setting RF=1 in the instruction memory then this bit is set to 1" "0: Packet Dropped due to RF Interrupt Status not..,1: Packet Dropped due to RF Interrupt Status detected" newline bitfld.long 0x4 2. "FOOVIS,Frame Offset Overflow Interrupt Status While parsing if the Instruction table entry's 'Frame Offset' found to be more than EOF offset then then this bit is set" "0: Frame Offset Overflow Interrupt Status not..,1: Frame Offset Overflow Interrupt Status detected" newline bitfld.long 0x4 1. "NPEOVIS,Number of Parsable Entries Overflow Interrupt Status While parsing a packet if the number of parsed entries found to be more than NPE[] (Number of Parseable Entries in MTL_RXP_Control register) then this bit is set to 1" "0: Number of Parsable Entries Overflow Interrupt..,1: Number of Parsable Entries Overflow Interrupt.." newline bitfld.long 0x4 0. "NVEOVIS,Number of Valid Entry Address/Index Overflow Interrupt Status While parsing if the Instruction address found to be more than NVE (Number of Valid Entry Address/index in MTL_RXP_Control register) then this bit is set to 1" "0: Number of Valid Entries Overflow Interrupt..,1: Number of Valid Entries Overflow Interrupt.." rgroup.long 0xCA8++0x7 line.long 0x0 "MTL_RXP_Drop_Cnt,The MTL_RXP_Drop_Cnt register provides the drop count of Rx Parser initiated drops." bitfld.long 0x0 31. "RXPDCOVF,Rx Parser Drop Counter Overflow Bit When set this bit indicates that the MTL_RXP_Drop_cnt (RXPDC) Counter field crossed the maximum limit" "0: Rx Parser Drop count overflow not occurred,1: Rx Parser Drop count overflow occurred" newline hexmask.long 0x0 0.--30. 1. "RXPDC,Rx Parser Drop count This 31-bit counter is implemented when a Rx Parser Drops a packet due to RF =1" line.long 0x4 "MTL_RXP_Error_Cnt,The MTL_RXP_Error_Cnt register provides the Rx Parser related error occurrence count." bitfld.long 0x4 31. "RXPECOVF,Rx Parser Error Counter Overflow Bit When set this bit indicates that the MTL_RXP_Error_cnt (RXPEC) Counter field crossed the maximum limit" "0: Rx Parser Error count overflow not occurred,1: Rx Parser Error count overflow occurred" newline hexmask.long 0x4 0.--30. 1. "RXPEC,Rx Parser Error count This 31-bit counter is implemented whenr a Rx Parser encounters following Error scenarios - Entry address >= NVE[] - Number Parsed Entries >= NPE[] - Entry address > EOF data entry address The counter is cleared when the.." group.long 0xCB0++0x3 line.long 0x0 "MTL_RXP_Indirect_Acc_Control_Status,The MTL_RXP_Indirect_Acc_Control_Status register provides the Indirect Access control and status for Rx Parser memory." bitfld.long 0x0 31. "STARTBUSY,FRP Instruction Table Access Busy - Set to 1 by the software indicates to start the Read/Write operation from/to the Rx Parser Memory" "0: hardware not busy,1: hardware is busy (Read/Write operation from/to.." newline hexmask.long.byte 0x0 23.--30. 1. "Reserved_30_23,Reserved." newline bitfld.long 0x0 22. "RXPEIEC,ECC Inject Error Control for Rx Parser Memory When RXPEIEE or RXPEIAEE bit of this register is set following are the errors inserted based on the value encoded in this field: - 1: Insert 1 bit error" "0: Insert 1 bit error,1: Insert 1 bit error" newline bitfld.long 0x0 21. "RXPEIAEE,ECC Inject Address Error Enable for Rx Parser Memory - 1: Enables the ECC address error injection feature" "0: ECC Inject Address Error for Rx Parser Memory is..,1: Enables the ECC address error injection feature" newline bitfld.long 0x0 20. "RXPEIEE,ECC Inject Error Enable for Rx Parser Memory - 1: Enables the ECC error injection feature" "0: ECC Inject Error for Rx Parser Memory is disabled,1: Enables the ECC error injection feature" newline rbitfld.long 0x0 17.--19. "Reserved_19_17,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "WRRDN,Read Write Control - 1: Indicates the write operation to the Rx Parser Memory" "0: Read operation to the Rx Parser Memory,1: Indicates the write operation to the Rx Parser.." newline hexmask.long.byte 0x0 8.--15. 1. "Reserved_15_x,Reserved." newline hexmask.long.byte 0x0 0.--7. 1. "ADDR,FRP Instruction Table Offset Address This field indicates the ADDR of the 32-bit entry in Rx parser instruction table" rgroup.long 0xCB4++0x7 line.long 0x0 "MTL_RXP_Indirect_Acc_Data,The MTL_RXP_Indirect_Acc_Data registers holds the data associated to Indirect Access to Rx Parser memory." hexmask.long 0x0 0.--31. 1. "DATA,FRP Instruction Table Write/Read Data Software should write this register before issuing any write command" line.long 0x4 "MTL_RXP_Bypass_Cnt,The MTL_RXP_Bypass_Cnt register provides the bypass count of Rx Parser." bitfld.long 0x4 31. "RXPBCOF,Rx Parser bypass Counter Overflow Bit When set this bit indicates that the MTL_RXP_Bypass_cnt (RXPBC) Counter field crossed the maximum limit" "0: Rx Parser Bypass count overflow not occurred,1: Rx Parser Bypass count overflow occurred" newline hexmask.long 0x4 0.--30. 1. "RXPBC,Rx Parser Bypass count This 31-bit counter is implemented when a Rx Parser bypass a packet due to AF=1 and RF =1" group.long 0xCC0++0x3 line.long 0x0 "MTL_ECC_Control,The MTL_ECC_Control register establishes the operating mode of ECC related to MTL memories." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_31_9,Reserved." newline bitfld.long 0x0 8. "MEEAO,MTL ECC Error Address Status Over-ride - 1: The EUEAS/ECEAS field of MTL_ECC_Err_Addr_Status register holds the last valid address where the error is detected" "0: MTL ECC Error Address Status Over-ride is disabled,1: The EUEAS/ECEAS field of MTL_ECC_Err_Addr_Status.." newline rbitfld.long 0x0 6.--7. "Reserved_7_6,Reserved." "0,1,2,3" newline rbitfld.long 0x0 5. "Reserved_DSCEE,Reserved." "0,1" newline rbitfld.long 0x0 4. "Reserved_TSOEE,Reserved." "0,1" newline bitfld.long 0x0 3. "MRXPEE,MTL Rx Parser ECC Enable - 1: Enables the ECC feature for Rx Parser memory - 0: Disables the ECC feature for Rx Parser memory" "0: Disables the ECC feature for Rx Parser memory,1: Enables the ECC feature for Rx Parser memory" newline bitfld.long 0x0 2. "MESTEE,MTL EST ECC Enable - 1: Enables the ECC feature for EST memory - 0: Disables the ECC feature for EST memory" "0: Disables the ECC feature for EST memory,1: Enables the ECC feature for EST memory" newline bitfld.long 0x0 1. "MRXEE,MTL Rx FIFO ECC Enable - 1: Enables the ECC feature for MTL Rx FIFO memory" "0: MTL Rx FIFO ECC is disabled,1: Enables the ECC feature for MTL Rx FIFO memory" newline bitfld.long 0x0 0. "MTXEE,MTL Tx FIFO ECC Enable - 1: Enables the ECC feature for MTL Tx FIFO memory - 0: Disables the ECC feature for MTL Tx FIFO memory" "0: Disables the ECC feature for MTL Tx FIFO memory,1: Enables the ECC feature for MTL Tx FIFO memory" rgroup.long 0xCC4++0x3 line.long 0x0 "MTL_Safety_Interrupt_Status,The MTL_Safety_Interrupt_Status registers provides Safety interrupt status." bitfld.long 0x0 31. "Reserved_MCSIS,Reserved." "0: MAC Safety Uncorrectable Interrupt Status not..,1: MAC Safety Uncorrectable Interrupt Status detected" newline hexmask.long 0x0 2.--30. 1. "Reserved_30_2,Reserved." newline bitfld.long 0x0 1. "MEUIS,MTL ECC Uncorrectable error Interrupt Status This bit indicates that an uncorrectable error interrupt event in the MTL ECC safety feature" "0: MTL ECC Uncorrectable error Interrupt Status not..,1: MTL ECC Uncorrectable error Interrupt Status.." newline bitfld.long 0x0 0. "MECIS,MTL ECC Correctable error Interrupt Status This bit indicates that a correctable error interrupt event in the MTL ECC safety feature" "0: MTL ECC Correctable error Interrupt Status not..,1: MTL ECC Correctable error Interrupt Status.." group.long 0xCC8++0xB line.long 0x0 "MTL_ECC_Interrupt_Enable,The MTL_ECC_Interrupt_Enable register provides enable bits for the ECC interrupts." hexmask.long.tbyte 0x0 13.--31. 1. "Reserved_31_13,Reserved." newline bitfld.long 0x0 12. "RPCEIE,Rx Parser memory Correctable Error Interrupt Enable When set generates an interrupt when an uncorrectable error is detected at the Rx Parser memory interface" "0: Rx Parser memory Correctable Error Interrupt is..,1: Rx Parser memory Correctable Error Interrupt is.." newline rbitfld.long 0x0 9.--11. "Reserved_11_9,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8. "ECEIE,EST memory Correctable Error Interrupt Enable When set generates an interrupt when a correctable error is detected at the MTL EST memory interface" "0: EST memory Correctable Error Interrupt is disabled,1: EST memory Correctable Error Interrupt is enabled" newline rbitfld.long 0x0 5.--7. "Reserved_7_5,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "RXCEIE,Rx memory Correctable Error Interrupt Enable When set generates an interrupt when a correctable error is detected at the MTL Rx memory interface" "0: Rx memory Correctable Error Interrupt is disabled,1: Rx memory Correctable Error Interrupt is enabled" newline rbitfld.long 0x0 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "TXCEIE,Tx memory Correctable Error Interrupt Enable When set generates an interrupt when a correctable error is detected at the MTL Tx memory interface" "0: Tx memory Correctable Error Interrupt is disabled,1: Tx memory Correctable Error Interrupt is enabled" line.long 0x4 "MTL_ECC_Interrupt_Status,The MTL_ECC_Interrupt_Status register provides MTL ECC Interrupt Status." hexmask.long.tbyte 0x4 15.--31. 1. "Reserved_31_15,Reserved." newline bitfld.long 0x4 14. "RPUES,Rx Parser memory Uncorrectable Error Status When set indicates that an uncorrectable error is detected at Rx Parser memory interface" "0: Rx Parser memory Uncorrectable Error Status not..,1: Rx Parser memory Uncorrectable Error Status.." newline bitfld.long 0x4 13. "RPAMS,MTL Rx Parser memory Address Mismatch Status This bit when set indicates that address mismatch is found for address bus of Rx Parser memory" "0: MTL Rx Parser memory Address Mismatch Status not..,1: MTL Rx Parser memory Address Mismatch Status.." newline bitfld.long 0x4 12. "RPCES,MTL Rx Parser memory Correctable Error Status This bit when set indicates that correctable error is detected at RX Parser memory interface" "0: MTL Rx Parser memory Correctable Error Status..,1: MTL Rx Parser memory Correctable Error Status.." newline rbitfld.long 0x4 11. "Reserved_11,Reserved." "0,1" newline bitfld.long 0x4 10. "EUES,MTL EST memory Uncorrectable Error Status When set indicates that an uncorrectable error is detected at MTL EST memory interface" "0: MTL EST memory Uncorrectable Error Status not..,1: MTL EST memory Uncorrectable Error Status detected" newline bitfld.long 0x4 9. "EAMS,MTL EST memory Address Mismatch Status This bit when set indicates that address mismatch is found for address bus of MTL EST memory" "0: MTL EST memory Address Mismatch Status not..,1: MTL EST memory Address Mismatch Status detected" newline bitfld.long 0x4 8. "ECES,MTL EST memory Correctable Error Status This bit when set indicates that correctable error is detected at the MTL EST memory" "0: MTL EST memory Correctable Error Status not..,1: MTL EST memory Correctable Error Status detected" newline rbitfld.long 0x4 7. "Reserved_7,Reserved." "0,1" newline bitfld.long 0x4 6. "RXUES,MTL Rx memory Uncorrectable Error Status When set indicates that an uncorrectable error is detected at the MTL Rx memory interface" "0: MTL Rx memory Uncorrectable Error Status not..,1: MTL Rx memory Uncorrectable Error Status detected" newline bitfld.long 0x4 5. "RXAMS,MTL Rx memory Address Mismatch Status This bit when set indicates that address mismatch is found for address bus of the MTL Rx memory" "0: MTL Rx memory Address Mismatch Status not detected,1: MTL Rx memory Address Mismatch Status detected" newline bitfld.long 0x4 4. "RXCES,MTL Rx memory Correctable Error Status This bit when set indicates that correctable error is detected at the MTL Rx memory" "0: MTL Rx memory correctable Error Status not..,1: MTL Rx memory correctable Error Status detected" newline rbitfld.long 0x4 3. "Reserved_3,Reserved." "0,1" newline bitfld.long 0x4 2. "TXUES,MTL Tx memory Uncorrectable Error Status When set indicates that an uncorrectable error is detected at the MTL TX memory interface" "0: MTL Tx memory Uncorrectable Error Status not..,1: MTL Tx memory Uncorrectable Error Status detected" newline bitfld.long 0x4 1. "TXAMS,MTL Tx memory Address Mismatch Status This bit when set indicates that address mismatch is found for address bus of the MTL Tx memory" "0: MTL Tx memory Address Mismatch Status not detected,1: MTL Tx memory Address Mismatch Status detected" newline bitfld.long 0x4 0. "TXCES,MTL Tx memory Correctable Error Status This bit when set indicates that a correctable error is detected at the MTL Tx memory" "0: MTL Tx memory Correctable Error Status not..,1: MTL Tx memory Correctable Error Status detected" line.long 0x8 "MTL_ECC_Err_Sts_Rctl,The MTL_ECC_Err_Sts_Rctl register establishes the control for ECC Error status capture." hexmask.long 0x8 6.--31. 1. "Reserved_31_6,Reserved." newline bitfld.long 0x8 5. "CUES,Clear Uncorrectable Error Status When this bit is set along with EESRE bit of this register based on the EMS field of this register the respective memory's uncorrectable error address and uncorrectable error count values are cleared upon reading" "0: Clear Uncorrectable Error Status not detected,1: Clear Uncorrectable Error Status detected" newline bitfld.long 0x8 4. "CCES,Clear Correctable Error Status When this bit is set along with EESRE bit of this register based on the EMS field of this register the respective memory's correctable error address and correctable error count values are cleared upon reading" "0: Clear Correctable Error Status not detected,1: Clear Correctable Error Status detected" newline bitfld.long 0x8 1.--3. "EMS,MTL ECC Memory Selection When EESRE bit of this register is set this field indicates which memory's error status value to be read" "0: MTL Tx memory,1: MTL Rx memory,2: MTL EST memory,3: MTL Rx Parser memory,4: DMA TSO memory,5: DMA DCACHE memory,?,?" newline bitfld.long 0x8 0. "EESRE,MTL ECC Error Status Read Enable When this bit is set based on the EMS field of this register the respective memory's error status values are captured as described: - The correctable and uncorrectable error count values are captured into.." "0: MTL ECC Error Status Read is disabled,1: MTL ECC Error Status Read is enabled" rgroup.long 0xCD4++0x7 line.long 0x0 "MTL_ECC_Err_Addr_Status,The MTL_ECC_Err_Addr_Status register provides the memory addresses for the correctable and uncorrectable errors." hexmask.long.word 0x0 16.--31. 1. "EUEAS,MTL ECC Uncorrectable Error Address Status Based on the EMS field of MTL_ECC_Err_Sts_Rctl register this field holds the respective memory's address locations for which an uncorrectable error or address mismatch is detected" newline hexmask.long.word 0x0 0.--15. 1. "ECEAS,MTL ECC Correctable Error Address Status Based on the EMS field of MTL_ECC_Err_Sts_Rctl register this field holds the respective memory's address locations for which a correctable error is detected" line.long 0x4 "MTL_ECC_Err_Cntr_Status,The MTL_ECC_Err_Cntr_Status register provides ECC Error count for Correctable and uncorrectable errors." hexmask.long.word 0x4 20.--31. 1. "Reserved_31_20,Reserved." newline hexmask.long.byte 0x4 16.--19. 1. "EUECS,MTL ECC Uncorrectable Error Counter Status Based on the EMS field of MTL_ECC_Err_Cntr_Rctl register this field holds the respective memory's uncorrectable error count value" newline hexmask.long.byte 0x4 8.--15. 1. "Reserved_15_8,Reserved." newline hexmask.long.byte 0x4 0.--7. 1. "ECECS,MTL ECC Correctable Error Counter Status Based on the EMS field of MTL_ECC_Err_Cntr_Rctl register this field holds the respective memory's correctable error count value" group.long 0xCE0++0x7 line.long 0x0 "MTL_DPP_Control,The MTL_DPP_Control establishes the operating mode of Data Parity protection and error injection." hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved." newline rbitfld.long 0x0 16. "Reserved_IPEDC,Reserved." "0,1" newline bitfld.long 0x0 15. "IPEMRWC,no description available" "0: Insert Parity error in MTL RWC data parity..,1: Insert Parity error in MTL RWC data parity.." newline bitfld.long 0x0 14. "IPEMTFC,Insert Parity error in MAC TFC data parity checker When set to 1 parity/data bit of first valid input parity/data of the MAC TFC data parity checker (or at PC11 as shown in Transmit Data path parity protection diagram) is flipped" "0: Insert Parity error in MAC TFC data parity..,1: Insert Parity error in MAC TFC data parity.." newline bitfld.long 0x0 13. "IPEMTBU,Insert Parity error in MTL RWC data parity checker When set to 1 parity/data bit of first valid input parity/data of the MTL RWC data parity checker (or at PC12 as shown in Recieve data path parity protection diagram) is flipped" "0: Insert Parity error in MAC TBU data parity..,1: Insert Parity error in MAC TBU data parity.." newline rbitfld.long 0x0 12. "Reserved_IPEASR,Reserved." "0,1" newline rbitfld.long 0x0 11. "Reserved_IPEMSW,Reserved." "0,1" newline rbitfld.long 0x0 10. "Reserved_IPEASW,Reserved." "0,1" newline bitfld.long 0x0 9. "IPERID,Insert Parity Error in RX Interface Data parity checker When set to 1 parity/data bit of first valid input parity/data of the RX Interface Data parity checker is (or at PC6 as shown in Receive data path parity protection diagram) flipped" "0: Insert Parity Error in Rx Interface Data parity..,1: Insert Parity Error in Rx Interface Data parity.." newline bitfld.long 0x0 8. "IPEMTS,Insert Parity Error in MTL Tx Status FIFO parity checker When set to 1 parity/data bit of first valid input parity/data of the MTL Tx Status FIFO parity checker (or at PC5 as shown in Transmit data path parity protection diagram) is flipped" "0: Insert Parity Error in MTL TX Status FIFO parity..,1: Insert Parity Error in MTL TX Status FIFO parity.." newline bitfld.long 0x0 7. "IPEMTF,Insert Parity Error in MTL Tx FIFO write data parity checker When set to 1 parity/data bit of first valid input parity/data of the MTL Tx FIFO write data parity checker (or at PC4 as shown in Transmit data path parity protection diagram) is flipped" "0: Insert Parity Error in MTL Tx FIFO write data..,1: Insert Parity Error in MTL Tx FIFO write data.." newline bitfld.long 0x0 6. "IPETRD,Insert Parity Error in DMA Tx/Rx Descriptor parity checker When set to 1 parity/data bit of first valid input parity/data of the DMA Tx/Rx Descriptor parity checker (or at PC3 as shown in Transmit data path parity protection diagram) is flipped" "0: Insert Parity Error in DMA Tx/Rx Descriptor..,1: Insert Parity Error in DMA Tx/Rx Descriptor.." newline rbitfld.long 0x0 5. "Reserved_IPETH,Reserved." "0,1" newline rbitfld.long 0x0 4. "Reserved_IPETID,Reserved." "0,1" newline rbitfld.long 0x0 3. "Reserved_3,Reserved." "0,1" newline rbitfld.long 0x0 2. "Reserved_EPSI,Reserved." "0,1" newline rbitfld.long 0x0 1. "OPE,Odd Parity Enable When set to 1 enables odd parity protection on all the external interfaces and when set to 0 enables even parity protection on all the external interfaces" "0: Odd Parity is disabled,1: Odd Parity is enabled" newline bitfld.long 0x0 0. "EDPP,Enable Data path Parity Protection When set to 1 enables the parity protection for EQOS datapath by generating and checking the parity on EQOS datapath" "0: Data path Parity Protection is disabled,1: Data path Parity Protection is enabled" line.long 0x4 "MTL_DPP_ECC_EIC,The MTL_DPP_ECC_EIC establishes the operating mode of ECC/DPP error injection." hexmask.long.word 0x4 17.--31. 1. "Reserved_31_17,Reserved." newline bitfld.long 0x4 16. "EIM,Error Injection Mode When it set to 0 indicate error injection on data; When it set to 1 indicate error injection on ECC/Parity bits(need to check the address error injection mode is disabled)" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "Reserved_15_8,Reserved." newline hexmask.long.byte 0x4 0.--7. 1. "BLEI,Bit Location of error injection This field indicates the bit location of DPP/ECC error injection determination of error in Parity/ECC bits or Data (being protected) depends on the Error Injection Mode(EIM field)" group.long 0xD00++0x3 line.long 0x0 "MTL_TxQ0_Operation_Mode,The Queue 0 Transmit Operation Mode register establishes the Transmit queue operating modes and commands." hexmask.long.word 0x0 22.--31. 1. "Reserved_31_y,Reserved." newline hexmask.long.byte 0x0 16.--21. 1. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes" newline hexmask.long.word 0x0 7.--15. 1. "Reserved_15_7,Reserved." newline bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue" "0: 32,1: 64,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512" newline bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0" "0: Not enabled,1: Enable in AV mode (Reserved in non-AV),2: Enabled,?" newline bitfld.long 0x0 1. "TSF,Transmit Store and Forward When this bit is set the transmission starts when a full packet resides in the MTL Tx queue" "0: Transmit Store and Forward is disabled,1: Transmit Store and Forward is enabled" newline bitfld.long 0x0 0. "FTQ,Flush Transmit Queue When this bit is set the Tx queue controller logic is reset to its default values" "0: Flush Transmit Queue is disabled,1: Flush Transmit Queue is enabled" rgroup.long 0xD04++0x7 line.long 0x0 "MTL_TxQ0_Underflow,The Queue 0 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow and packets missed because of Receive queue packet flush" hexmask.long.tbyte 0x0 12.--31. 1. "Reserved_31_12,Reserved." newline bitfld.long 0x0 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows that is it has crossed the maximum count" "0: Overflow not detected for Underflow Packet Counter,1: Overflow detected for Underflow Packet Counter" newline hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow" line.long 0x4 "MTL_TxQ0_Debug,The Queue 0 Transmit Debug register gives the debug status of various blocks related to the Transmit queue." hexmask.long.word 0x4 23.--31. 1. "Reserved_31_23,Reserved." newline bitfld.long 0x4 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 19. "Reserved_19,Reserved." "0,1" newline bitfld.long 0x4 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4 6.--15. 1. "Reserved_15_6,Reserved." newline bitfld.long 0x4 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high this bit indicates that the MTL Tx Status FIFO is full" "0: MTL Tx Status FIFO Full status is not detected,1: MTL Tx Status FIFO Full status is detected" newline bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high it indicates that the MTL Tx Queue is not empty and some data is left for transmission" "0: MTL Tx Queue Not Empty status is not detected,1: MTL Tx Queue Not Empty status is detected" newline bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status When high this bit indicates that the MTL Tx Queue Write Controller is active and it is transferring the data to the Tx Queue" "0: MTL Tx Queue Write Controller status is not..,1: MTL Tx Queue Write Controller status is detected" newline bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller:" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.." newline bitfld.long 0x4 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "0: Transmit Queue in Pause status is not detected,1: Transmit Queue in Pause status is detected" rgroup.long 0xD14++0x3 line.long 0x0 "MTL_TxQ0_ETS_Status,The Queue 0 ETS Status register provides the average traffic transmitted in Queue 0." hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved." newline hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot This field contains the average transmitted bits per slot" group.long 0xD18++0x3 line.long 0x0 "MTL_TxQ0_Quantum_Weight,The Queue 0 Quantum or Weights register contains the quantum value for Deficit Weighted Round Robin (DWRR). weights for the Weighted Round Robin (WRR). and Weighted Fair Queuing (WFQ) for Queue 0." hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved." newline hexmask.long.tbyte 0x0 0.--20. 1. "ISCQW,Quantum or Weights When the DCB operation is enabled with DWRR algorithm for Queue 0 traffic this field contains the quantum value in bytes to be added to credit during every queue scanning cycle" group.long 0xD2C++0x7 line.long 0x0 "MTL_Q0_Interrupt_Control_Status,This register contains the interrupt enable and status bits for the queue 0 interrupts." hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved." newline bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set the Receive Queue Overflow interrupt is enabled" "0: Receive Queue Overflow Interrupt is disabled,1: Receive Queue Overflow Interrupt is enabled" newline hexmask.long.byte 0x0 17.--23. 1. "Reserved_23_17,Reserved." newline bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet" "0: Receive Queue Overflow Interrupt Status not..,1: Receive Queue Overflow Interrupt Status detected" newline hexmask.long.byte 0x0 10.--15. 1. "Reserved_15_10,Reserved." newline bitfld.long 0x0 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated" "0: Average Bits Per Slot Interrupt is disabled,1: Average Bits Per Slot Interrupt is enabled" newline bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set the Transmit Queue Underflow interrupt is enabled" "0: Transmit Queue Underflow Interrupt Status is..,1: Transmit Queue Underflow Interrupt Status is.." newline hexmask.long.byte 0x0 2.--7. 1. "Reserved_7_2,Reserved." newline bitfld.long 0x0 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set this bit indicates that the MAC has updated the ABS value" "0: Average Bits Per Slot Interrupt Status not..,1: Average Bits Per Slot Interrupt Status detected" newline bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet" "0: Transmit Queue Underflow Interrupt Status not..,1: Transmit Queue Underflow Interrupt Status detected" line.long 0x4 "MTL_RxQ0_Operation_Mode,The Queue 0 Receive Operation Mode register establishes the Receive queue operating modes and command. The RFA and RFD fields are not backward compatible with the RFA and RFD fields of 4.00a release" hexmask.long.byte 0x4 26.--31. 1. "Reserved_31_y,Reserved." newline hexmask.long.byte 0x4 20.--25. 1. "RQS,Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes" newline rbitfld.long 0x4 19. "Reserved_19_y,Reserved." "0,1" newline hexmask.long.byte 0x4 14.--18. 1. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation: - 0: Full minus 1 KB that is FULL 1 KB - 1: Full.." newline rbitfld.long 0x4 13. "Reserved_13_y,Reserved." "0,1" newline hexmask.long.byte 0x4 8.--12. 1. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field see RFD" newline bitfld.long 0x4 7. "EHFC,Enable Hardware Flow Control When this bit is set the flow control signal operation based on the fill-level of Rx queue is enabled" "0: Hardware Flow Control is disabled,1: Hardware Flow Control is enabled" newline bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine" "0: Dropping of TCP/IP Checksum Error Packets is..,1: Dropping of TCP/IP Checksum Error Packets is.." newline bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward When this bit is set the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it ignoring the RTC field of this register" "0: Receive Queue Store and Forward is disabled,1: Receive Queue Store and Forward is enabled" newline bitfld.long 0x4 4. "FEP,Forward Error Packets When this bit is reset the Rx queue drops packets with error status (CRC error GMII_ER watchdog timeout or overflow)" "0: Forward Error Packets is disabled,1: Forward Error Packets is enabled" newline bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets When this bit is set the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes) including pad-bytes and CRC" "0: Forward Undersized Good Packets is disabled,1: Forward Undersized Good Packets is enabled" newline rbitfld.long 0x4 2. "Reserved_2,Reserved." "0,1" newline bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold" "0: 64,1: 32,2: 96,3: 128" rgroup.long 0xD34++0x7 line.long 0x0 "MTL_RxQ0_Missed_Packet_Overflow_Cnt,The Queue 0 Missed Packet and Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow." hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_28,Reserved." newline bitfld.long 0x0 27. "MISCNTOVF,Missed Packet Counter Overflow Bit When set this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit" "0: Missed Packet Counter overflow not detected,1: Missed Packet Counter overflow detected" newline hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue" newline hexmask.long.byte 0x0 12.--15. 1. "Reserved_15_12,Reserved." newline bitfld.long 0x0 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit" "0: Overflow Counter overflow not detected,1: Overflow Counter overflow detected" newline hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow" line.long 0x4 "MTL_RxQ0_Debug,The Queue 0 Receive Debug register gives the debug status of various blocks related to the Receive queue." bitfld.long 0x4 30.--31. "Reserved_31_30,Reserved." "0,1,2,3" newline hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue" newline hexmask.long.word 0x4 6.--15. 1. "Reserved_15_6,Reserved." newline bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue:" "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full" newline bitfld.long 0x4 3. "Reserved_3,Reserved." "0,1" newline bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller:" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status" newline bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high this bit indicates that the MTL Rx queue Write controller is active and it is transferring a received packet to the Rx Queue" "0: MTL Rx Queue Write Controller Active Status not..,1: MTL Rx Queue Write Controller Active Status.." group.long 0xD3C++0x7 line.long 0x0 "MTL_RxQ0_Control,The Queue Receive Control register controls the receive arbitration and passing of received packets to the application." hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved." newline bitfld.long 0x0 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue" "0: Receive Queue Packet Arbitration is disabled,1: Receive Queue Packet Arbitration is enabled" newline bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0" "0,1,2,3,4,5,6,7" line.long 0x4 "MTL_TxQ1_Operation_Mode,The Queue 1 Transmit Operation Mode register establishes the Transmit queue operating modes and commands." hexmask.long.word 0x4 22.--31. 1. "Reserved_31_y,Reserved." newline hexmask.long.byte 0x4 16.--21. 1. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes" newline hexmask.long.word 0x4 7.--15. 1. "Reserved_15_7,Reserved." newline bitfld.long 0x4 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue" "0: 32,1: 64,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512" newline bitfld.long 0x4 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0" "0: Not enabled,1: Enable in AV mode (Reserved in non-AV),2: Enabled,?" newline bitfld.long 0x4 1. "TSF,Transmit Store and Forward When this bit is set the transmission starts when a full packet resides in the MTL Tx queue" "0: Transmit Store and Forward is disabled,1: Transmit Store and Forward is enabled" newline bitfld.long 0x4 0. "FTQ,Flush Transmit Queue When this bit is set the Tx queue controller logic is reset to its default values" "0: Flush Transmit Queue is disabled,1: Flush Transmit Queue is enabled" rgroup.long 0xD44++0x7 line.long 0x0 "MTL_TxQ1_Underflow,The Queue 1 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow and packets missed because of Receive queue packet flush" hexmask.long.tbyte 0x0 12.--31. 1. "Reserved_31_12,Reserved." newline bitfld.long 0x0 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows that is it has crossed the maximum count" "0: Overflow not detected for Underflow Packet Counter,1: Overflow detected for Underflow Packet Counter" newline hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow" line.long 0x4 "MTL_TxQ1_Debug,The Queue 1 Transmit Debug register gives the debug status of various blocks related to the Transmit queue." hexmask.long.word 0x4 23.--31. 1. "Reserved_31_23,Reserved." newline bitfld.long 0x4 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 19. "Reserved_19,Reserved." "0,1" newline bitfld.long 0x4 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4 6.--15. 1. "Reserved_15_6,Reserved." newline bitfld.long 0x4 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high this bit indicates that the MTL Tx Status FIFO is full" "0: MTL Tx Status FIFO Full status is not detected,1: MTL Tx Status FIFO Full status is detected" newline bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high it indicates that the MTL Tx Queue is not empty and some data is left for transmission" "0: MTL Tx Queue Not Empty status is not detected,1: MTL Tx Queue Not Empty status is detected" newline bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status When high this bit indicates that the MTL Tx Queue Write Controller is active and it is transferring the data to the Tx Queue" "0: MTL Tx Queue Write Controller status is not..,1: MTL Tx Queue Write Controller status is detected" newline bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller:" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.." newline bitfld.long 0x4 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "0: Transmit Queue in Pause status is not detected,1: Transmit Queue in Pause status is detected" group.long 0xD50++0x3 line.long 0x0 "MTL_TxQ1_ETS_Control,The Queue ETS Control register controls the enhanced transmission selection operation." hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved." newline bitfld.long 0x0 4.--6. "SLC,Slot Count If the credit-based shaper algorithm is enabled the software can program the number of slots (of duration programmed in DMA_CH(#i)_Slot_Interval register) over which the average transmitted bits per slot provided in the.." "0: 1 slot,1: 2 slots,2: 4 slots,3: 8 slots,4: 16 slots,?,?,?" newline bitfld.long 0x0 3. "CC,Credit Control When this bit is set the accumulated credit parameter in the credit-based shaper algorithm logic is not reset to zero when there is positive credit and no packet to transmit in Channel 1" "0: Credit Control is disabled,1: Credit Control is enabled" newline bitfld.long 0x0 2. "AVALG,AV Algorithm When Queue 1 is programmed for AV this field configures the scheduling algorithm for this queue: This bit when set indicates credit based shaper algorithm (CBS) is selected for Queue 1 traffic" "0: CBS Algorithm is disabled,1: CBS Algorithm is enabled" newline rbitfld.long 0x0 0.--1. "Reserved_1_0,Reserved." "0,1,2,3" rgroup.long 0xD54++0x3 line.long 0x0 "MTL_TxQ1_ETS_Status,The Queue 1 ETS Status register provides the average traffic transmitted in Queue 1." hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved." newline hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot This field contains the average transmitted bits per slot" group.long 0xD58++0xF line.long 0x0 "MTL_TxQ1_Quantum_Weight,The Queue 1 idleSlopeCredit. Quantum or Weights register provides the average traffic transmitted in Queue 1." hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved." newline hexmask.long.tbyte 0x0 0.--20. 1. "ISCQW,idleSlopeCredit Quantum or Weights - idleSlopeCredit When AV feature is enabled this field contains the idleSlopeCredit value required for the credit-based shaper algorithm for Queue 1" line.long 0x4 "MTL_TxQ1_SendSlopeCredit,The sendSlopeCredit register contains the sendSlope credit value required for the credit-based shaper algorithm for the Queue." hexmask.long.tbyte 0x4 14.--31. 1. "Reserved_31_14,Reserved." newline hexmask.long.word 0x4 0.--13. 1. "SSC,sendSlopeCredit Value When AV operation is enabled this field contains the sendSlopeCredit value required for credit-based shaper algorithm for Queue 1" line.long 0x8 "MTL_TxQ1_HiCredit,The hiCredit register contains the hiCredit value required for the credit-based shaper algorithm for the Queue." rbitfld.long 0x8 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long 0x8 0.--28. 1. "HC,hiCredit Value When the AV feature is enabled this field contains the hiCredit value required for the credit-based shaper algorithm" line.long 0xC "MTL_TxQ1_LoCredit,The loCredit register contains the loCredit value required for the credit-based shaper algorithm for the Queue." rbitfld.long 0xC 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long 0xC 0.--28. 1. "LC,loCredit Value When AV operation is enabled this field contains the loCredit value required for the credit-based shaper algorithm" group.long 0xD6C++0x7 line.long 0x0 "MTL_Q1_Interrupt_Control_Status,This register contains the interrupt enable and status bits for the queue 1 interrupts." hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved." newline bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set the Receive Queue Overflow interrupt is enabled" "0: Receive Queue Overflow Interrupt is disabled,1: Receive Queue Overflow Interrupt is enabled" newline hexmask.long.byte 0x0 17.--23. 1. "Reserved_23_17,Reserved." newline bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet" "0: Receive Queue Overflow Interrupt Status not..,1: Receive Queue Overflow Interrupt Status detected" newline hexmask.long.byte 0x0 10.--15. 1. "Reserved_15_10,Reserved." newline bitfld.long 0x0 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated" "0: Average Bits Per Slot Interrupt is disabled,1: Average Bits Per Slot Interrupt is enabled" newline bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set the Transmit Queue Underflow interrupt is enabled" "0: Transmit Queue Underflow Interrupt Status is..,1: Transmit Queue Underflow Interrupt Status is.." newline hexmask.long.byte 0x0 2.--7. 1. "Reserved_7_2,Reserved." newline bitfld.long 0x0 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set this bit indicates that the MAC has updated the ABS value" "0: Average Bits Per Slot Interrupt Status not..,1: Average Bits Per Slot Interrupt Status detected" newline bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet" "0: Transmit Queue Underflow Interrupt Status not..,1: Transmit Queue Underflow Interrupt Status detected" line.long 0x4 "MTL_RxQ1_Operation_Mode,The Queue 1 Receive Operation Mode register establishes the Receive queue operating modes and command. The RFA and RFD fields are not backward compatible with the RFA and RFD fields of 4.00a release" hexmask.long.byte 0x4 26.--31. 1. "Reserved_31_y,Reserved." newline hexmask.long.byte 0x4 20.--25. 1. "RQS,Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes" newline rbitfld.long 0x4 19. "Reserved_19_y,Reserved." "0,1" newline hexmask.long.byte 0x4 14.--18. 1. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation: - 0: Full minus 1 KB that is FULL 1 KB - 1: Full.." newline rbitfld.long 0x4 13. "Reserved_13_y,Reserved." "0,1" newline hexmask.long.byte 0x4 8.--12. 1. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field see RFD" newline bitfld.long 0x4 7. "EHFC,Enable Hardware Flow Control When this bit is set the flow control signal operation based on the fill-level of Rx queue is enabled" "0: Hardware Flow Control is disabled,1: Hardware Flow Control is enabled" newline bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine" "0: Dropping of TCP/IP Checksum Error Packets is..,1: Dropping of TCP/IP Checksum Error Packets is.." newline bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward When this bit is set the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it ignoring the RTC field of this register" "0: Receive Queue Store and Forward is disabled,1: Receive Queue Store and Forward is enabled" newline bitfld.long 0x4 4. "FEP,Forward Error Packets When this bit is reset the Rx queue drops packets with error status (CRC error GMII_ER watchdog timeout or overflow)" "0: Forward Error Packets is disabled,1: Forward Error Packets is enabled" newline bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets When this bit is set the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes) including pad-bytes and CRC" "0: Forward Undersized Good Packets is disabled,1: Forward Undersized Good Packets is enabled" newline rbitfld.long 0x4 2. "Reserved_2,Reserved." "0,1" newline bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold" "0: 64,1: 32,2: 96,3: 128" rgroup.long 0xD74++0x7 line.long 0x0 "MTL_RxQ1_Missed_Packet_Overflow_Cnt,The Queue 1 Missed Packet and Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow." hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_28,Reserved." newline bitfld.long 0x0 27. "MISCNTOVF,Missed Packet Counter Overflow Bit When set this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit" "0: Missed Packet Counter overflow not detected,1: Missed Packet Counter overflow detected" newline hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue" newline hexmask.long.byte 0x0 12.--15. 1. "Reserved_15_12,Reserved." newline bitfld.long 0x0 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit" "0: Overflow Counter overflow not detected,1: Overflow Counter overflow detected" newline hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow" line.long 0x4 "MTL_RxQ1_Debug,The Queue 1 Receive Debug register gives the debug status of various blocks related to the Receive queue." bitfld.long 0x4 30.--31. "Reserved_31_30,Reserved." "0,1,2,3" newline hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue" newline hexmask.long.word 0x4 6.--15. 1. "Reserved_15_6,Reserved." newline bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue:" "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full" newline bitfld.long 0x4 3. "Reserved_3,Reserved." "0,1" newline bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller:" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status" newline bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high this bit indicates that the MTL Rx queue Write controller is active and it is transferring a received packet to the Rx Queue" "0: MTL Rx Queue Write Controller Active Status not..,1: MTL Rx Queue Write Controller Active Status.." group.long 0xD7C++0x7 line.long 0x0 "MTL_RxQ1_Control,The Queue Receive Control register controls the receive arbitration and passing of received packets to the application." hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved." newline bitfld.long 0x0 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue" "0: Receive Queue Packet Arbitration is disabled,1: Receive Queue Packet Arbitration is enabled" newline bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0" "0,1,2,3,4,5,6,7" line.long 0x4 "MTL_TxQ2_Operation_Mode,The Queue 2 Transmit Operation Mode register establishes the Transmit queue operating modes and commands." hexmask.long.word 0x4 22.--31. 1. "Reserved_31_y,Reserved." newline hexmask.long.byte 0x4 16.--21. 1. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes" newline hexmask.long.word 0x4 7.--15. 1. "Reserved_15_7,Reserved." newline bitfld.long 0x4 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue" "0: 32,1: 64,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512" newline bitfld.long 0x4 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0" "0: Not enabled,1: Enable in AV mode (Reserved in non-AV),2: Enabled,?" newline bitfld.long 0x4 1. "TSF,Transmit Store and Forward When this bit is set the transmission starts when a full packet resides in the MTL Tx queue" "0: Transmit Store and Forward is disabled,1: Transmit Store and Forward is enabled" newline bitfld.long 0x4 0. "FTQ,Flush Transmit Queue When this bit is set the Tx queue controller logic is reset to its default values" "0: Flush Transmit Queue is disabled,1: Flush Transmit Queue is enabled" rgroup.long 0xD84++0x7 line.long 0x0 "MTL_TxQ2_Underflow,The Queue 2 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow and packets missed because of Receive queue packet flush" hexmask.long.tbyte 0x0 12.--31. 1. "Reserved_31_12,Reserved." newline bitfld.long 0x0 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows that is it has crossed the maximum count" "0: Overflow not detected for Underflow Packet Counter,1: Overflow detected for Underflow Packet Counter" newline hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow" line.long 0x4 "MTL_TxQ2_Debug,The Queue 2 Transmit Debug register gives the debug status of various blocks related to the Transmit queue." hexmask.long.word 0x4 23.--31. 1. "Reserved_31_23,Reserved." newline bitfld.long 0x4 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 19. "Reserved_19,Reserved." "0,1" newline bitfld.long 0x4 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4 6.--15. 1. "Reserved_15_6,Reserved." newline bitfld.long 0x4 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high this bit indicates that the MTL Tx Status FIFO is full" "0: MTL Tx Status FIFO Full status is not detected,1: MTL Tx Status FIFO Full status is detected" newline bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high it indicates that the MTL Tx Queue is not empty and some data is left for transmission" "0: MTL Tx Queue Not Empty status is not detected,1: MTL Tx Queue Not Empty status is detected" newline bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status When high this bit indicates that the MTL Tx Queue Write Controller is active and it is transferring the data to the Tx Queue" "0: MTL Tx Queue Write Controller status is not..,1: MTL Tx Queue Write Controller status is detected" newline bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller:" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.." newline bitfld.long 0x4 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "0: Transmit Queue in Pause status is not detected,1: Transmit Queue in Pause status is detected" group.long 0xD90++0x3 line.long 0x0 "MTL_TxQ2_ETS_Control,The Queue ETS Control register controls the enhanced transmission selection operation." hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved." newline bitfld.long 0x0 4.--6. "SLC,Slot Count If the credit-based shaper algorithm is enabled the software can program the number of slots (of duration programmed in DMA_CH(#i)_Slot_Interval register) over which the average transmitted bits per slot provided in the.." "0: 1 slot,1: 2 slots,2: 4 slots,3: 8 slots,4: 16 slots,?,?,?" newline bitfld.long 0x0 3. "CC,Credit Control When this bit is set the accumulated credit parameter in the credit-based shaper algorithm logic is not reset to zero when there is positive credit and no packet to transmit in Channel 1" "0: Credit Control is disabled,1: Credit Control is enabled" newline bitfld.long 0x0 2. "AVALG,AV Algorithm When Queue 1 is programmed for AV this field configures the scheduling algorithm for this queue: This bit when set indicates credit based shaper algorithm (CBS) is selected for Queue 1 traffic" "0: CBS Algorithm is disabled,1: CBS Algorithm is enabled" newline rbitfld.long 0x0 0.--1. "Reserved_1_0,Reserved." "0,1,2,3" rgroup.long 0xD94++0x3 line.long 0x0 "MTL_TxQ2_ETS_Status,The Queue 2 ETS Status register provides the average traffic transmitted in Queue 2." hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved." newline hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot This field contains the average transmitted bits per slot" group.long 0xD98++0xF line.long 0x0 "MTL_TxQ2_Quantum_Weight,The Queue 2 idleSlopeCredit. Quantum or Weights register provides the average traffic transmitted in Queue 2." hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved." newline hexmask.long.tbyte 0x0 0.--20. 1. "ISCQW,idleSlopeCredit Quantum or Weights - idleSlopeCredit When AV feature is enabled this field contains the idleSlopeCredit value required for the credit-based shaper algorithm for Queue 1" line.long 0x4 "MTL_TxQ2_SendSlopeCredit,The sendSlopeCredit register contains the sendSlope credit value required for the credit-based shaper algorithm for the Queue." hexmask.long.tbyte 0x4 14.--31. 1. "Reserved_31_14,Reserved." newline hexmask.long.word 0x4 0.--13. 1. "SSC,sendSlopeCredit Value When AV operation is enabled this field contains the sendSlopeCredit value required for credit-based shaper algorithm for Queue 1" line.long 0x8 "MTL_TxQ2_HiCredit,The hiCredit register contains the hiCredit value required for the credit-based shaper algorithm for the Queue." rbitfld.long 0x8 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long 0x8 0.--28. 1. "HC,hiCredit Value When the AV feature is enabled this field contains the hiCredit value required for the credit-based shaper algorithm" line.long 0xC "MTL_TxQ2_LoCredit,The loCredit register contains the loCredit value required for the credit-based shaper algorithm for the Queue." rbitfld.long 0xC 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long 0xC 0.--28. 1. "LC,loCredit Value When AV operation is enabled this field contains the loCredit value required for the credit-based shaper algorithm" group.long 0xDAC++0x7 line.long 0x0 "MTL_Q2_Interrupt_Control_Status,This register contains the interrupt enable and status bits for the queue 2 interrupts." hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved." newline bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set the Receive Queue Overflow interrupt is enabled" "0: Receive Queue Overflow Interrupt is disabled,1: Receive Queue Overflow Interrupt is enabled" newline hexmask.long.byte 0x0 17.--23. 1. "Reserved_23_17,Reserved." newline bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet" "0: Receive Queue Overflow Interrupt Status not..,1: Receive Queue Overflow Interrupt Status detected" newline hexmask.long.byte 0x0 10.--15. 1. "Reserved_15_10,Reserved." newline bitfld.long 0x0 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated" "0: Average Bits Per Slot Interrupt is disabled,1: Average Bits Per Slot Interrupt is enabled" newline bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set the Transmit Queue Underflow interrupt is enabled" "0: Transmit Queue Underflow Interrupt Status is..,1: Transmit Queue Underflow Interrupt Status is.." newline hexmask.long.byte 0x0 2.--7. 1. "Reserved_7_2,Reserved." newline bitfld.long 0x0 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set this bit indicates that the MAC has updated the ABS value" "0: Average Bits Per Slot Interrupt Status not..,1: Average Bits Per Slot Interrupt Status detected" newline bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet" "0: Transmit Queue Underflow Interrupt Status not..,1: Transmit Queue Underflow Interrupt Status detected" line.long 0x4 "MTL_RxQ2_Operation_Mode,The Queue 2 Receive Operation Mode register establishes the Receive queue operating modes and command. The RFA and RFD fields are not backward compatible with the RFA and RFD fields of 4.00a release" hexmask.long.byte 0x4 26.--31. 1. "Reserved_31_y,Reserved." newline hexmask.long.byte 0x4 20.--25. 1. "RQS,Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes" newline rbitfld.long 0x4 19. "Reserved_19_y,Reserved." "0,1" newline hexmask.long.byte 0x4 14.--18. 1. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation: - 0: Full minus 1 KB that is FULL 1 KB - 1: Full.." newline rbitfld.long 0x4 13. "Reserved_13_y,Reserved." "0,1" newline hexmask.long.byte 0x4 8.--12. 1. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field see RFD" newline bitfld.long 0x4 7. "EHFC,Enable Hardware Flow Control When this bit is set the flow control signal operation based on the fill-level of Rx queue is enabled" "0: Hardware Flow Control is disabled,1: Hardware Flow Control is enabled" newline bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine" "0: Dropping of TCP/IP Checksum Error Packets is..,1: Dropping of TCP/IP Checksum Error Packets is.." newline bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward When this bit is set the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it ignoring the RTC field of this register" "0: Receive Queue Store and Forward is disabled,1: Receive Queue Store and Forward is enabled" newline bitfld.long 0x4 4. "FEP,Forward Error Packets When this bit is reset the Rx queue drops packets with error status (CRC error GMII_ER watchdog timeout or overflow)" "0: Forward Error Packets is disabled,1: Forward Error Packets is enabled" newline bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets When this bit is set the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes) including pad-bytes and CRC" "0: Forward Undersized Good Packets is disabled,1: Forward Undersized Good Packets is enabled" newline rbitfld.long 0x4 2. "Reserved_2,Reserved." "0,1" newline bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold" "0: 64,1: 32,2: 96,3: 128" rgroup.long 0xDB4++0x7 line.long 0x0 "MTL_RxQ2_Missed_Packet_Overflow_Cnt,The Queue 2 Missed Packet and Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow." hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_28,Reserved." newline bitfld.long 0x0 27. "MISCNTOVF,Missed Packet Counter Overflow Bit When set this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit" "0: Missed Packet Counter overflow not detected,1: Missed Packet Counter overflow detected" newline hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue" newline hexmask.long.byte 0x0 12.--15. 1. "Reserved_15_12,Reserved." newline bitfld.long 0x0 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit" "0: Overflow Counter overflow not detected,1: Overflow Counter overflow detected" newline hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow" line.long 0x4 "MTL_RxQ2_Debug,The Queue 2 Receive Debug register gives the debug status of various blocks related to the Receive queue." bitfld.long 0x4 30.--31. "Reserved_31_30,Reserved." "0,1,2,3" newline hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue" newline hexmask.long.word 0x4 6.--15. 1. "Reserved_15_6,Reserved." newline bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue:" "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full" newline bitfld.long 0x4 3. "Reserved_3,Reserved." "0,1" newline bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller:" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status" newline bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high this bit indicates that the MTL Rx queue Write controller is active and it is transferring a received packet to the Rx Queue" "0: MTL Rx Queue Write Controller Active Status not..,1: MTL Rx Queue Write Controller Active Status.." group.long 0xDBC++0x3 line.long 0x0 "MTL_RxQ2_Control,The Queue Receive Control register controls the receive arbitration and passing of received packets to the application." hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved." newline bitfld.long 0x0 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue" "0: Receive Queue Packet Arbitration is disabled,1: Receive Queue Packet Arbitration is enabled" newline bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0" "0,1,2,3,4,5,6,7" group.long 0x1000++0x7 line.long 0x0 "DMA_Mode,The Bus Mode register establishes the bus operating modes for the DMA." hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved." newline rbitfld.long 0x0 22.--23. "Reserved_RNDF,Reserved." "0,1,2,3" newline rbitfld.long 0x0 20.--21. "Reserved_TNDF,Reserved." "0,1,2,3" newline rbitfld.long 0x0 19. "Reserved_DCHE,Reserved." "0,1" newline rbitfld.long 0x0 18. "Reserved_18,Reserved." "0,1" newline bitfld.long 0x0 16.--17. "INTM,Interrupt Mode This field defines the interrupt mode of DWC_ether_qos" "0: See above description,1: See above description,2: See above description,?" newline rbitfld.long 0x0 15. "Reserved_15,Reserved." "0,1" newline bitfld.long 0x0 12.--14. "PR,Priority Ratio These bits control the priority ratio in weighted round-robin arbitration between the Rx DMA and Tx DMA" "0: The priority ratio is 1:1,1: The priority ratio is 2:1,2: The priority ratio is 3:1,3: The priority ratio is 4:1,4: The priority ratio is 5:1,5: The priority ratio is 6:1,6: The priority ratio is 7:1,7: The priority ratio is 8:1" newline bitfld.long 0x0 11. "TXPR,Transmit Priority When set this bit indicates that the Tx DMA has higher priority than the Rx DMA during arbitration for the system-side bus or Descriptor reads from DCACHE memory when DWC_EQOS_DCEXT is enabled" "0: Transmit Priority is disabled,1: Transmit Priority is enabled" newline rbitfld.long 0x0 10. "Reserved_SCSW,Reserved." "0,1" newline bitfld.long 0x0 9. "ARBC,ARBC is NXP Reserved This field must be set to '0'" "0: NXP reserved field disabled,1: NXP reserved field enabled up on NXP request" newline rbitfld.long 0x0 8. "Reserved_DSPW,Reserved." "0,1" newline rbitfld.long 0x0 5.--7. "Reserved_7_5,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--4. "TAA,Transmit Arbitration Algorithm This field is used to select the arbitration algorithm for the Transmit side when multiple Tx DMAs are selected" "0: Fixed priority (Channel 0 has the lowest..,1: Weighted Strict Priority (WSP),2: Weighted Round-Robin (WRR),?,?,?,?,?" newline bitfld.long 0x0 1. "DA,DMA Tx or Rx Arbitration Scheme This bit specifies the arbitration scheme between the Transmit and Receive paths of all channels: - 0: Weighted Round-Robin with Rx:Tx or Tx:Rx The priority between the paths is according to the priority specified in.." "0: Weighted Round-Robin with Rx:Tx or Tx:Rx The..,1: Fixed Priority" newline bitfld.long 0x0 0. "SWR,Software Reset When this bit is set the MAC and the DMA controller reset the logic and all internal registers of the DMA MTL and MAC" "0: Software Reset is disabled,1: Software Reset is enabled" line.long 0x4 "DMA_SysBus_Mode,The System Bus mode register controls the behavior of the AHB or AXI master. It mainly controls burst splitting and number of outstanding requests." rbitfld.long 0x4 31. "Reserved_EN_LPI,Reserved." "0,1" newline rbitfld.long 0x4 30. "Reserved_LPI_XIT_PKT,Reserved." "0,1" newline rbitfld.long 0x4 27.--29. "Reserved_29_y,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 24.--26. "Reserved_WR_OSR_LMT,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 19.--23. 1. "Reserved_23_y,Reserved." newline rbitfld.long 0x4 16.--18. "Reserved_RD_OSR_LMT,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 15. "RB,Rebuild INCRx Burst When this bit is set high and the AHB master gets SPLIT RETRY or Early Burst Termination (EBT) response the AHB master interface rebuilds the pending beats of any initiated burst transfer with INCRx and SINGLE transfers" "0: Rebuild INCRx Burst is disabled,1: Rebuild INCRx Burst is enabled" newline bitfld.long 0x4 14. "MB,Mixed Burst When this bit is high and the FB bit is low the AHB master performs undefined bursts transfers (INCR) for burst length of 16 or more" "0: Mixed Burst is disabled,1: Mixed Burst is enabled" newline rbitfld.long 0x4 13. "Reserved_ONEKBBE,Reserved." "0,1" newline bitfld.long 0x4 12. "AAL,Address-Aligned Beats When this bit is set to 1 the EQOS-AXI or EQOS-AHB master performs address-aligned burst transfers on Read and Write channels" "0: Address-Aligned Beats is disabled,1: Address-Aligned Beats is enabled" newline rbitfld.long 0x4 11. "Reserved_EAME,Reserved." "0,1" newline rbitfld.long 0x4 10. "Reserved_AALE,Reserved." "0,1" newline rbitfld.long 0x4 8.--9. "Reserved_9_8,Reserved." "0,1,2,3" newline rbitfld.long 0x4 7. "Reserved_BLEN256,Reserved." "0,1" newline rbitfld.long 0x4 6. "Reserved_BLEN128,Reserved." "0,1" newline rbitfld.long 0x4 5. "Reserved_BLEN64,Reserved." "0,1" newline rbitfld.long 0x4 4. "Reserved_BLEN32,Reserved." "0,1" newline rbitfld.long 0x4 3. "Reserved_BLEN16,Reserved." "0,1" newline rbitfld.long 0x4 2. "Reserved_BLEN8,Reserved." "0,1" newline rbitfld.long 0x4 1. "Reserved_BLEN4,Reserved." "0,1" newline bitfld.long 0x4 0. "FB,Fixed Burst Length - 1: AHB master initiates burst transfers of specified length (INCRx or SINGLE)" "0: Fixed Burst Length is disabled,1: AHB master initiates burst transfers of.." rgroup.long 0x1008++0x7 line.long 0x0 "DMA_Interrupt_Status,The application reads this Interrupt Status register during interrupt service routine or polling to determine the interrupt status of DMA channels. MTL queues. and the MAC." hexmask.long.word 0x0 18.--31. 1. "Reserved_31_18,Reserved." newline bitfld.long 0x0 17. "MACIS,MAC Interrupt Status This bit indicates an interrupt event in the MAC" "0: MAC Interrupt Status not detected,1: MAC Interrupt Status detected" newline bitfld.long 0x0 16. "MTLIS,MTL Interrupt Status This bit indicates an interrupt event in the MTL" "0: MTL Interrupt Status not detected,1: MTL Interrupt Status detected" newline hexmask.long.byte 0x0 8.--15. 1. "Reserved_15_8,Reserved." newline bitfld.long 0x0 7. "Reserved_DC7IS,Reserved." "0,1" newline bitfld.long 0x0 6. "Reserved_DC6IS,Reserved." "0,1" newline bitfld.long 0x0 5. "Reserved_DC5IS,Reserved." "0,1" newline bitfld.long 0x0 4. "Reserved_DC4IS,Reserved." "0,1" newline bitfld.long 0x0 3. "Reserved_DC3IS,Reserved." "0,1" newline bitfld.long 0x0 2. "DC2IS,DMA Channel 2 Interrupt Status This bit indicates an interrupt event in DMA Channel 2" "0: DMA Channel 2 Interrupt Status not detected,1: DMA Channel 2 Interrupt Status detected" newline bitfld.long 0x0 1. "DC1IS,DMA Channel 1 Interrupt Status This bit indicates an interrupt event in DMA Channel 1" "0: DMA Channel 1 Interrupt Status not detected,1: DMA Channel 1 Interrupt Status detected" newline bitfld.long 0x0 0. "DC0IS,DMA Channel 0 Interrupt Status This bit indicates an interrupt event in DMA Channel 0" "0: DMA Channel 0 Interrupt Status not detected,1: DMA Channel 0 Interrupt Status detected" line.long 0x4 "DMA_Debug_Status0,The Debug Status 0 register gives the Receive and Transmit process status for DMA Channel 0-Channel 2 for debugging purpose." hexmask.long.byte 0x4 28.--31. 1. "TPS2,DMA Channel 2 Transmit Process State This field indicates the Tx DMA FSM state for Channel 2" newline hexmask.long.byte 0x4 24.--27. 1. "RPS2,DMA Channel 2 Receive Process State This field indicates the Rx DMA FSM state for Channel 2" newline hexmask.long.byte 0x4 20.--23. 1. "TPS1,DMA Channel 1 Transmit Process State This field indicates the Tx DMA FSM state for Channel 1" newline hexmask.long.byte 0x4 16.--19. 1. "RPS1,DMA Channel 1 Receive Process State This field indicates the Rx DMA FSM state for Channel 1" newline hexmask.long.byte 0x4 12.--15. 1. "TPS0,DMA Channel 0 Transmit Process State This field indicates the Tx DMA FSM state for Channel 0" newline hexmask.long.byte 0x4 8.--11. 1. "RPS0,DMA Channel 0 Receive Process State This field indicates the Rx DMA FSM state for Channel 0" newline hexmask.long.byte 0x4 2.--7. 1. "Reserved_7_2,Reserved." newline bitfld.long 0x4 1. "Reserved_AXRHSTS,Reserved." "0,1" newline bitfld.long 0x4 0. "AXWHSTS,AHB Master Status When high this bit indicates that the AHB master FSMs are in the non-idle state." "0: AXI Master Write Channel or AHB Master Status..,1: AXI Master Write Channel or AHB Master Status.." group.long 0x1050++0xF line.long 0x0 "DMA_TBS_CTRL0,This register is used to control the TBS attributes." hexmask.long.tbyte 0x0 8.--31. 1. "FTOS,Fetch Time Offset The value in units of 256 nanoseconds that has to be deducted from the Launch time to compute the Fetch Time" newline rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1" newline bitfld.long 0x0 4.--6. "FGOS,Fetch GSN Offset The number GSN slots that must be deducted from the Launch GSN to compute the Fetch GSN" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "FTOV,Fetch Time Offset Valid When set indicates the FTOS field is valid" "0: Fetch Time Offset is invalid,1: Fetch Time Offset is valid" line.long 0x4 "DMA_TBS_CTRL1,This register is used to control the TBS attributes." hexmask.long.tbyte 0x4 8.--31. 1. "FTOS,Fetch Time Offset The value in units of 256 nanoseconds that has to be deducted from the Launch time to compute the Fetch Time" newline rbitfld.long 0x4 7. "Reserved_7,Reserved." "0,1" newline bitfld.long 0x4 4.--6. "FGOS,Fetch GSN Offset The number GSN slots that must be deducted from the Launch GSN to compute the Fetch GSN" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "FTOV,Fetch Time Offset Valid When set indicates the FTOS field is valid" "0: Fetch Time Offset is invalid,1: Fetch Time Offset is valid" line.long 0x8 "DMA_TBS_CTRL2,This register is used to control the TBS attributes." hexmask.long.tbyte 0x8 8.--31. 1. "FTOS,Fetch Time Offset The value in units of 256 nanoseconds that has to be deducted from the Launch time to compute the Fetch Time" newline rbitfld.long 0x8 7. "Reserved_7,Reserved." "0,1" newline bitfld.long 0x8 4.--6. "FGOS,Fetch GSN Offset The number GSN slots that must be deducted from the Launch GSN to compute the Fetch GSN" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "FTOV,Fetch Time Offset Valid When set indicates the FTOS field is valid" "0: Fetch Time Offset is invalid,1: Fetch Time Offset is valid" line.long 0xC "DMA_TBS_CTRL3,This register is used to control the TBS attributes." hexmask.long.tbyte 0xC 8.--31. 1. "FTOS,Fetch Time Offset The value in units of 256 nanoseconds that has to be deducted from the Launch time to compute the Fetch Time" newline rbitfld.long 0xC 7. "Reserved_7,Reserved." "0,1" newline bitfld.long 0xC 4.--6. "FGOS,Fetch GSN Offset The number GSN slots that must be deducted from the Launch GSN to compute the Fetch GSN" "0,1,2,3,4,5,6,7" newline rbitfld.long 0xC 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "FTOV,Fetch Time Offset Valid When set indicates the FTOS field is valid" "0: Fetch Time Offset is invalid,1: Fetch Time Offset is valid" rgroup.long 0x1080++0x3 line.long 0x0 "DMA_Safety_Interrupt_Status,This register indicates summary (whether error occured in DMA/MTL/MAC and correctable/uncorrectable) of the Automotive Safety related error interrupts." bitfld.long 0x0 31. "MCSIS,MAC Safety Uncorrectable Interrupt Status Indicates a uncorrectable Safety related Interrupt is set in the MAC module" "0: MAC Safety Uncorrectable Interrupt Status not..,1: MAC Safety Uncorrectable Interrupt Status detected" newline bitfld.long 0x0 30. "Reserved_30,Reserved." "0,1" newline bitfld.long 0x0 29. "MSUIS,MTL Safety Uncorrectable error Interrupt Status This bit indicates an uncorrectable error interrupt event in MTL" "0: MTL Safety Uncorrectable error Interrupt Status..,1: MTL Safety Uncorrectable error Interrupt Status.." newline bitfld.long 0x0 28. "MSCIS,MTL Safety Correctable error Interrupt Status This bit indicates a correctable error interrupt event in MTL" "0: MTL Safety Correctable error Interrupt Status..,1: MTL Safety Correctable error Interrupt Status.." newline hexmask.long 0x0 2.--27. 1. "Reserved_27_2,Reserved." newline bitfld.long 0x0 1. "DEUIS,DMA ECC Uncorrectable error Interrupt Status This bit indicates an interrupt event in the DMA ECC safety feature" "0: DMA ECC Uncorrectable error Interrupt Status not..,1: DMA ECC Uncorrectable error Interrupt Status.." newline bitfld.long 0x0 0. "DECIS,DMA ECC Correctable error Interrupt Status This bit indicates an interrupt event in the DMA ECC safety feature" "0: DMA ECC Correctable error Interrupt Status not..,1: DMA ECC Correctable error Interrupt Status.." group.long 0x1100++0xB line.long 0x0 "DMA_CH0_Control,The DMA Channeli Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode." hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved." newline bitfld.long 0x0 24. "SPH,Split Headers When this bit is set the DMA splits the header and payload in the Receive path" "0: Split Headers feature is disabled,1: Split Headers feature is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length This bit specifies the Word Dword or Lword number (depending on the 32-bit 64-bit or 128-bit bus) to skip between two unchained descriptors" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1" newline bitfld.long 0x0 16. "PBLx8,8xPBL mode When this bit is set the PBL value programmed in Bits[21:16] in DMA_CH(#i)_Tx_Control and Bits[21:16] in DMA_CH(#i)_Rx_Control is multiplied by eight times" "0: 8xPBL mode is disabled,1: 8xPBL mode is enabled" newline rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3" newline hexmask.long.word 0x0 0.--13. 1. "Reserved_MSS,Reserved." line.long 0x4 "DMA_CH0_Tx_Control,The DMA Channeli Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights." rbitfld.long 0x4 31. "Reserved_31,Reserved." "0,1" newline bitfld.long 0x4 29.--30. "TFSEL,TBS Fetch Select Select bits for one of the four DMA_TBS_CTRL register fields (FTOS FGSN FTOV) for the channel Values: - 2'b00: DMA_TBS_CTRL0 - 2'b01: DMA_TBS_CTRL1 - 2'b10: DMA_TBS_CTRL2 - 2'b11: DMA_TBS_CTRL3 (Reserved if DWC_EQOS_NUM_DMA_TX_CH=3)" "0: DMA_TBS_CTRL0,1: DMA_TBS_CTRL1,2: DMA_TBS_CTRL2,3: DMA_TBS_CTRL3" newline bitfld.long 0x4 28. "EDSE,Enhanced Descriptor Enable When this bit is set the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors" "0: Enhanced Descriptor is disabled,1: Enhanced Descriptor is enabled" newline hexmask.long.byte 0x4 24.--27. 1. "Reserved_TQOS,Reserved." newline rbitfld.long 0x4 23. "Reserved_23,Reserved." "0,1" newline bitfld.long 0x4 22. "ETIC,Early Transmit Interrupt Control When this bit is set Early Transmit Interrupt (ETI) status is set after completion of transfer of data from buffers of a transmit descriptor in which IOC bit (TDES2[31]) is set" "0: Early Transmit Interrupt is disabled,1: Early Transmit Interrupt is enabled" newline hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" newline rbitfld.long 0x4 15. "Reserved_IPBL,Reserved." "0,1" newline rbitfld.long 0x4 13.--14. "Reserved_TSE_MODE,Reserved." "0,1,2,3" newline rbitfld.long 0x4 12. "Reserved_TSE,Reserved." "0,1" newline hexmask.long.byte 0x4 5.--11. 1. "Reserved_11_5,Reserved." newline bitfld.long 0x4 4. "OSF,Operate on Second Packet When this bit is set it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained" "0: Operate on Second Packet disabled,1: Operate on Second Packet enabled" newline bitfld.long 0x4 1.--3. "TCW,Transmit Channel Weight This field indicates the weight assigned to the corresponding Transmit channel" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "ST,Start or Stop Transmission Command When this bit is set transmission is placed in the Running state" "0: Stop Transmission Command,1: Start Transmission Command" line.long 0x8 "DMA_CH0_Rx_Control,The DMA Channeli Receive Control register controls the Rx features such as PBL. buffer size. and extended status." bitfld.long 0x8 31. "RPF,Rx Packet Flush" "0: Rx Packet Flush is disabled,1: Rx Packet Flush is enabled" newline rbitfld.long 0x8 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 24.--27. 1. "Reserved_RQOS,Reserved." newline rbitfld.long 0x8 23. "Reserved_23,Reserved." "0,1" newline bitfld.long 0x8 22. "ERIC,Early Receive Interrupt Control When this bit is set Early Receive Interrupt (ERI) status is set after the completion of every burst transfer of data from the Rx DMA to the buffer" "0: Early Receive Interrupt is disabled,1: Early Receive Interrupt is enabled" newline hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" newline rbitfld.long 0x8 15. "Reserved_15,Reserved." "0,1" newline hexmask.long.word 0x8 4.--14. 1. "RBSZ_13_y,Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0" newline rbitfld.long 0x8 1.--3. "RBSZ_x_0,Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "SR,Start or Stop Receive When this bit is set the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets" "0: Stop Receive,1: Start Receive" group.long 0x1114++0x3 line.long 0x0 "DMA_CH0_TxDesc_List_Address,The Channeli Tx Descriptor List Address register points the DMA to the start of Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Word. Dword. or Lword-aligned.." hexmask.long 0x0 3.--31. 1. "TDESLA,Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list" newline rbitfld.long 0x0 0.--2. "Reserved_LSb,Reserved." "0,1,2,3,4,5,6,7" group.long 0x111C++0x7 line.long 0x0 "DMA_CH0_RxDesc_List_Address,The Channeli Rx Descriptor List Address register points the DMA to the start of Receive descriptor list. This register points to the start of the Receive Descriptor List. The descriptor lists reside in the physical memory.." hexmask.long 0x0 3.--31. 1. "RDESLA,Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list" newline rbitfld.long 0x0 0.--2. "Reserved_LSb,Reserved." "0,1,2,3,4,5,6,7" line.long 0x4 "DMA_CH0_TxDesc_Tail_Pointer,The Channeli Tx Descriptor Tail Pointer register points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x4 3.--31. 1. "TDTP,Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring" newline rbitfld.long 0x4 0.--2. "Reserved_LSb,Reserved." "0,1,2,3,4,5,6,7" group.long 0x1128++0x17 line.long 0x0 "DMA_CH0_RxDesc_Tail_Pointer,The Channeli Rx Descriptor Tail Pointer Points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x0 3.--31. 1. "RDTP,Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring" newline rbitfld.long 0x0 0.--2. "Reserved_LSb,Reserved." "0,1,2,3,4,5,6,7" line.long 0x4 "DMA_CH0_TxDesc_Ring_Length,The Tx Descriptor Ring Length register contains the length of the Transmit descriptor ring." hexmask.long.tbyte 0x4 10.--31. 1. "Reserved_31_10,Reserved." newline hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring" line.long 0x8 "DMA_CH0_Rx_Control2,The Channeli Receive Control register controls the Rx features such as Rx Descriptor Ring Length and Alternate Rx Buffer Size." hexmask.long.byte 0x8 24.--31. 1. "Reserved_31_24,Reserved." newline hexmask.long.byte 0x8 17.--23. 1. "ARBS,Alternate Receive Buffer Size Indicates size in bytes for Buffer 1 when ARBS is programmed to a non-zero value (when split header feature is not enabled)" newline hexmask.long.byte 0x8 10.--16. 1. "Reserved_x_10,Reserved." newline hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring" line.long 0xC "DMA_CH0_Interrupt_Enable,The Channeli Interrupt Enable register enables the interrupts reported by the Status register." hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved." newline bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable When this bit is set the normal interrupt summary is enabled" "0: Normal Interrupt Summary is disabled,1: Normal Interrupt Summary is enabled" newline bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable When this bit is set the abnormal interrupt summary is enabled" "0: Abnormal Interrupt Summary is disabled,1: Abnormal Interrupt Summary is enabled" newline bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable When this bit is set along with the AIE bit the Descriptor error interrupt is enabled" "0: Context Descriptor Error is disabled,1: Context Descriptor Error is enabled" newline bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable When this bit is set along with the AIE bit the Fatal Bus error interrupt is enabled" "0: Fatal Bus Error is disabled,1: Fatal Bus Error is enabled" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt Enable When this bit is set along with the NIE bit the Early Receive interrupt is enabled" "0: Early Receive Interrupt is disabled,1: Early Receive Interrupt is enabled" newline bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt Enable When this bit is set along with the AIE bit the Early Transmit interrupt is enabled" "0: Early Transmit Interrupt is disabled,1: Early Transmit Interrupt is enabled" newline bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout Enable When this bit is set along with the AIE bit the Receive Watchdog Timeout interrupt is enabled" "0: Receive Watchdog Timeout is disabled,1: Receive Watchdog Timeout is enabled" newline bitfld.long 0xC 8. "RSE,Receive Stopped Enable When this bit is set along with the AIE bit the Receive Stopped Interrupt is enabled" "0: Receive Stopped is disabled,1: Receive Stopped is enabled" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable When this bit is set along with the AIE bit the Receive Buffer Unavailable interrupt is enabled" "0: Receive Buffer Unavailable is disabled,1: Receive Buffer Unavailable is enabled" newline bitfld.long 0xC 6. "RIE,Receive Interrupt Enable When this bit is set along with the NIE bit the Receive Interrupt is enabled" "0: Receive Interrupt is disabled,1: Receive Interrupt is enabled" newline rbitfld.long 0xC 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit the Transmit Buffer Unavailable interrupt is enabled" "0: Transmit Buffer Unavailable is disabled,1: Transmit Buffer Unavailable is enabled" newline bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable When this bit is set along with the AIE bit the Transmission Stopped interrupt is enabled" "0: Transmit Stopped is disabled,1: Transmit Stopped is enabled" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable When this bit is set along with the NIE bit the Transmit Interrupt is enabled" "0: Transmit Interrupt is disabled,1: Transmit Interrupt is enabled" line.long 0x10 "DMA_CH0_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. When this register is written with a non-zero value. it enables the watchdog timer for the RI bit of.." hexmask.long.word 0x10 18.--31. 1. "Reserved_31_18,Reserved." newline bitfld.long 0x10 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field" "0,1,2,3" newline hexmask.long.byte 0x10 8.--15. 1. "Reserved_15_8,Reserved." newline hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles multiplied by factor indicated in RWTU field for which the watchdog timer is set" line.long 0x14 "DMA_CH0_Slot_Function_Control_Status,The Slot Function Control and Status register contains the control bits for slot function and the status for Transmit path." hexmask.long.word 0x14 20.--31. 1. "Reserved_31_20,Reserved." newline hexmask.long.byte 0x14 16.--19. 1. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA" newline hexmask.long.word 0x14 4.--15. 1. "SIV,Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets" newline rbitfld.long 0x14 2.--3. "Reserved_3_2,Reserved." "0,1,2,3" newline bitfld.long 0x14 1. "ASC,Advance Slot Check When set this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot.." "0: Advance Slot Check is disabled,1: Advance Slot Check is enabled" newline bitfld.long 0x14 0. "ESC,Enable Slot Comparison When set this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field" "0: Slot Comparison is disabled,1: Slot Comparison is enabled" rgroup.long 0x1144++0x3 line.long 0x0 "DMA_CH0_Current_App_TxDesc,The Channeli Current Application Transmit Descriptor register points to the current Transmit descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation" rgroup.long 0x114C++0x3 line.long 0x0 "DMA_CH0_Current_App_RxDesc,The Channeli Current Application Receive Descriptor register points to the current Receive descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation" rgroup.long 0x1154++0x3 line.long 0x0 "DMA_CH0_Current_App_TxBuffer,The Channeli Current Application Transmit Buffer Address register points to the current Tx buffer address read by the DMA." hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation" rgroup.long 0x115C++0x3 line.long 0x0 "DMA_CH0_Current_App_RxBuffer,The Channel 0 Current Application Receive Buffer Address register points to the current Rx buffer address read by the DMA." hexmask.long 0x0 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation" group.long 0x1160++0x3 line.long 0x0 "DMA_CH0_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA. Note: The number of DMA_CH(#i)_Status register in the configuration is the higher of number of Rx.." hexmask.long.word 0x0 22.--31. 1. "Reserved_31_22,Reserved." newline rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer.." "0: Transmit Interrupt,1: Normal Interrupt Summary status detected" newline bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer.." "0: Abnormal Interrupt Summary status not detected,1: Transmit Process Stopped" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates.." "0: Context Descriptor Error status not detected,1: Context Descriptor Error status detected" newline bitfld.long 0x0 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field)" "0: Fatal Bus Error status not detected,1: Fatal Bus Error status detected" newline bitfld.long 0x0 11. "ERI,Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory" "0: Early Receive Interrupt status not detected,1: Early Receive Interrupt status detected" newline bitfld.long 0x0 10. "ETI,Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory" "0: Early Transmit Interrupt status not detected,1: Early Transmit Interrupt status detected" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received" "0: Receive Watchdog Timeout status not detected,1: Receive Watchdog Timeout status detected" newline bitfld.long 0x0 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state" "0: Receive Process Stopped status not detected,1: Receive Process Stopped status detected" newline bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list and the DMA cannot acquire it" "0: Receive Buffer Unavailable status not detected,1: Receive Buffer Unavailable status detected" newline bitfld.long 0x0 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete" "0: Receive Interrupt status not detected,1: Receive Interrupt status detected" newline rbitfld.long 0x0 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list and the DMA cannot acquire it" "0: Transmit Buffer Unavailable status not detected,1: Transmit Buffer Unavailable status detected" newline bitfld.long 0x0 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped" "0: Transmit Process Stopped status not detected,1: Transmit Process Stopped status detected" newline bitfld.long 0x0 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete" "0: Transmit Interrupt status not detected,1: Transmit Interrupt status detected" rgroup.long 0x1164++0xB line.long 0x0 "DMA_CH0_Miss_Frame_Cnt,This register has the number of packet counter that got dropped by the DMA either due to Bus Error or due to programming RPF field in DMA_CH{i}_Rx_Control register." hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved." newline bitfld.long 0x0 15. "MFCO,Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further" "0: Miss Frame Counter overflow not occurred,1: Miss Frame Counter overflow occurred" newline hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved." newline hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programing RPF field in DMA_CH{i}_Rx_Control register" line.long 0x4 "DMA_CH0_RXP_Accept_Cnt,The DMA_CH(#i)_RXP_Accept_Cnt registers provides the count of the number of frames accepted by Rx Parser." bitfld.long 0x4 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit When set this bit indicates that the RXPAC Counter field crossed the maximum limit" "0: Rx Parser Accept Counter overflow not occurred,1: Rx Parser Accept Counter overflow occurred" newline hexmask.long 0x4 0.--30. 1. "RXPAC,Rx Parser Accept Counter This 31-bit counter is implemented when a Rx Parser Accept a packet due to AF =1" line.long 0x8 "DMA_CH0_RX_ERI_Cnt,The DMA_CH(#i)_RX_ERI_Cnt registers provides the count of the number of times ERI was asserted." hexmask.long.tbyte 0x8 12.--31. 1. "Reserved_31_12,Reserved." newline hexmask.long.word 0x8 0.--11. 1. "ECNT,ERI Counter When ERIC bit of DMA_CH(#i)_RX_Control register is set this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer" group.long 0x1180++0xB line.long 0x0 "DMA_CH1_Control,The DMA Channeli Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode." hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved." newline bitfld.long 0x0 24. "SPH,Split Headers When this bit is set the DMA splits the header and payload in the Receive path" "0: Split Headers feature is disabled,1: Split Headers feature is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length This bit specifies the Word Dword or Lword number (depending on the 32-bit 64-bit or 128-bit bus) to skip between two unchained descriptors" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1" newline bitfld.long 0x0 16. "PBLx8,8xPBL mode When this bit is set the PBL value programmed in Bits[21:16] in DMA_CH(#i)_Tx_Control and Bits[21:16] in DMA_CH(#i)_Rx_Control is multiplied by eight times" "0: 8xPBL mode is disabled,1: 8xPBL mode is enabled" newline rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3" newline hexmask.long.word 0x0 0.--13. 1. "Reserved_MSS,Reserved." line.long 0x4 "DMA_CH1_Tx_Control,The DMA Channeli Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights." rbitfld.long 0x4 31. "Reserved_31,Reserved." "0,1" newline bitfld.long 0x4 29.--30. "TFSEL,TBS Fetch Select Select bits for one of the four DMA_TBS_CTRL register fields (FTOS FGSN FTOV) for the channel Values: - 2'b00: DMA_TBS_CTRL0 - 2'b01: DMA_TBS_CTRL1 - 2'b10: DMA_TBS_CTRL2 - 2'b11: DMA_TBS_CTRL3 (Reserved if DWC_EQOS_NUM_DMA_TX_CH=3)" "0: DMA_TBS_CTRL0,1: DMA_TBS_CTRL1,2: DMA_TBS_CTRL2,3: DMA_TBS_CTRL3" newline bitfld.long 0x4 28. "EDSE,Enhanced Descriptor Enable When this bit is set the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors" "0: Enhanced Descriptor is disabled,1: Enhanced Descriptor is enabled" newline hexmask.long.byte 0x4 24.--27. 1. "Reserved_TQOS,Reserved." newline rbitfld.long 0x4 23. "Reserved_23,Reserved." "0,1" newline bitfld.long 0x4 22. "ETIC,Early Transmit Interrupt Control When this bit is set Early Transmit Interrupt (ETI) status is set after completion of transfer of data from buffers of a transmit descriptor in which IOC bit (TDES2[31]) is set" "0: Early Transmit Interrupt is disabled,1: Early Transmit Interrupt is enabled" newline hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" newline rbitfld.long 0x4 15. "Reserved_IPBL,Reserved." "0,1" newline rbitfld.long 0x4 13.--14. "Reserved_TSE_MODE,Reserved." "0,1,2,3" newline rbitfld.long 0x4 12. "Reserved_TSE,Reserved." "0,1" newline hexmask.long.byte 0x4 5.--11. 1. "Reserved_11_5,Reserved." newline bitfld.long 0x4 4. "OSF,Operate on Second Packet When this bit is set it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained" "0: Operate on Second Packet disabled,1: Operate on Second Packet enabled" newline bitfld.long 0x4 1.--3. "TCW,Transmit Channel Weight This field indicates the weight assigned to the corresponding Transmit channel" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "ST,Start or Stop Transmission Command When this bit is set transmission is placed in the Running state" "0: Stop Transmission Command,1: Start Transmission Command" line.long 0x8 "DMA_CH1_Rx_Control,The DMA Channeli Receive Control register controls the Rx features such as PBL. buffer size. and extended status." bitfld.long 0x8 31. "RPF,Rx Packet Flush" "0: Rx Packet Flush is disabled,1: Rx Packet Flush is enabled" newline rbitfld.long 0x8 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 24.--27. 1. "Reserved_RQOS,Reserved." newline rbitfld.long 0x8 23. "Reserved_23,Reserved." "0,1" newline bitfld.long 0x8 22. "ERIC,Early Receive Interrupt Control When this bit is set Early Receive Interrupt (ERI) status is set after the completion of every burst transfer of data from the Rx DMA to the buffer" "0: Early Receive Interrupt is disabled,1: Early Receive Interrupt is enabled" newline hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" newline rbitfld.long 0x8 15. "Reserved_15,Reserved." "0,1" newline hexmask.long.word 0x8 4.--14. 1. "RBSZ_13_y,Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0" newline rbitfld.long 0x8 1.--3. "RBSZ_x_0,Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "SR,Start or Stop Receive When this bit is set the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets" "0: Stop Receive,1: Start Receive" group.long 0x1194++0x3 line.long 0x0 "DMA_CH1_TxDesc_List_Address,The Channeli Tx Descriptor List Address register points the DMA to the start of Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Word. Dword. or Lword-aligned.." hexmask.long 0x0 3.--31. 1. "TDESLA,Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list" newline rbitfld.long 0x0 0.--2. "Reserved_LSb,Reserved." "0,1,2,3,4,5,6,7" group.long 0x119C++0x7 line.long 0x0 "DMA_CH1_RxDesc_List_Address,The Channeli Rx Descriptor List Address register points the DMA to the start of Receive descriptor list. This register points to the start of the Receive Descriptor List. The descriptor lists reside in the physical memory.." hexmask.long 0x0 3.--31. 1. "RDESLA,Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list" newline rbitfld.long 0x0 0.--2. "Reserved_LSb,Reserved." "0,1,2,3,4,5,6,7" line.long 0x4 "DMA_CH1_TxDesc_Tail_Pointer,The Channeli Tx Descriptor Tail Pointer register points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x4 3.--31. 1. "TDTP,Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring" newline rbitfld.long 0x4 0.--2. "Reserved_LSb,Reserved." "0,1,2,3,4,5,6,7" group.long 0x11A8++0x17 line.long 0x0 "DMA_CH1_RxDesc_Tail_Pointer,The Channeli Rx Descriptor Tail Pointer Points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x0 3.--31. 1. "RDTP,Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring" newline rbitfld.long 0x0 0.--2. "Reserved_LSb,Reserved." "0,1,2,3,4,5,6,7" line.long 0x4 "DMA_CH1_TxDesc_Ring_Length,The Tx Descriptor Ring Length register contains the length of the Transmit descriptor ring." hexmask.long.tbyte 0x4 10.--31. 1. "Reserved_31_10,Reserved." newline hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring Length" line.long 0x8 "DMA_CH1_Rx_Control2,The Channeli Receive Control register controls the Rx features such as Rx Descriptor Ring Length and Alternate Rx Buffer Size." hexmask.long.byte 0x8 24.--31. 1. "Reserved_31_24,Reserved." newline hexmask.long.byte 0x8 17.--23. 1. "ARBS,Alternate Receive Buffer Size Indicates size in bytes for Buffer 1 when ARBS is programmed to a non-zero value (when split header feature is not enabled)" newline hexmask.long.byte 0x8 10.--16. 1. "Reserved_x_10,Reserved." newline hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring" line.long 0xC "DMA_CH1_Interrupt_Enable,The Channeli Interrupt Enable register enables the interrupts reported by the Status register." hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved." newline bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable When this bit is set the normal interrupt summary is enabled" "0: Normal Interrupt Summary is disabled,1: Normal Interrupt Summary is enabled" newline bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable When this bit is set the abnormal interrupt summary is enabled" "0: Abnormal Interrupt Summary is disabled,1: Abnormal Interrupt Summary is enabled" newline bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable When this bit is set along with the AIE bit the Descriptor error interrupt is enabled" "0: Context Descriptor Error is disabled,1: Context Descriptor Error is enabled" newline bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable When this bit is set along with the AIE bit the Fatal Bus error interrupt is enabled" "0: Fatal Bus Error is disabled,1: Fatal Bus Error is enabled" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt Enable When this bit is set along with the NIE bit the Early Receive interrupt is enabled" "0: Early Receive Interrupt is disabled,1: Early Receive Interrupt is enabled" newline bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt Enable When this bit is set along with the AIE bit the Early Transmit interrupt is enabled" "0: Early Transmit Interrupt is disabled,1: Early Transmit Interrupt is enabled" newline bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout Enable When this bit is set along with the AIE bit the Receive Watchdog Timeout interrupt is enabled" "0: Receive Watchdog Timeout is disabled,1: Receive Watchdog Timeout is enabled" newline bitfld.long 0xC 8. "RSE,Receive Stopped Enable When this bit is set along with the AIE bit the Receive Stopped Interrupt is enabled" "0: Receive Stopped is disabled,1: Receive Stopped is enabled" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable When this bit is set along with the AIE bit the Receive Buffer Unavailable interrupt is enabled" "0: Receive Buffer Unavailable is disabled,1: Receive Buffer Unavailable is enabled" newline bitfld.long 0xC 6. "RIE,Receive Interrupt Enable When this bit is set along with the NIE bit the Receive Interrupt is enabled" "0: Receive Interrupt is disabled,1: Receive Interrupt is enabled" newline rbitfld.long 0xC 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit the Transmit Buffer Unavailable interrupt is enabled" "0: Transmit Buffer Unavailable is disabled,1: Transmit Buffer Unavailable is enabled" newline bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable When this bit is set along with the AIE bit the Transmission Stopped interrupt is enabled" "0: Transmit Stopped is disabled,1: Transmit Stopped is enabled" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable When this bit is set along with the NIE bit the Transmit Interrupt is enabled" "0: Transmit Interrupt is disabled,1: Transmit Interrupt is enabled" line.long 0x10 "DMA_CH1_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. When this register is written with a non-zero value. it enables the watchdog timer for the RI bit of.." hexmask.long.word 0x10 18.--31. 1. "Reserved_31_18,Reserved." newline bitfld.long 0x10 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field" "0,1,2,3" newline hexmask.long.byte 0x10 8.--15. 1. "Reserved_15_8,Reserved." newline hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles multiplied by factor indicated in RWTU field for which the watchdog timer is set" line.long 0x14 "DMA_CH1_Slot_Function_Control_Status,The Slot Function Control and Status register contains the control bits for slot function and the status for Transmit path." hexmask.long.word 0x14 20.--31. 1. "Reserved_31_20,Reserved." newline hexmask.long.byte 0x14 16.--19. 1. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA" newline hexmask.long.word 0x14 4.--15. 1. "SIV,Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets" newline rbitfld.long 0x14 2.--3. "Reserved_3_2,Reserved." "0,1,2,3" newline bitfld.long 0x14 1. "ASC,Advance Slot Check When set this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot.." "0: Advance Slot Check is disabled,1: Advance Slot Check is enabled" newline bitfld.long 0x14 0. "ESC,Enable Slot Comparison When set this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field" "0: Slot Comparison is disabled,1: Slot Comparison is enabled" rgroup.long 0x11C4++0x3 line.long 0x0 "DMA_CH1_Current_App_TxDesc,The Channeli Current Application Transmit Descriptor register points to the current Transmit descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation" rgroup.long 0x11CC++0x3 line.long 0x0 "DMA_CH1_Current_App_RxDesc,The Channeli Current Application Receive Descriptor register points to the current Receive descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation" rgroup.long 0x11D4++0x3 line.long 0x0 "DMA_CH1_Current_App_TxBuffer,The Channeli Current Application Transmit Buffer Address register points to the current Tx buffer address read by the DMA." hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation" rgroup.long 0x11DC++0x3 line.long 0x0 "DMA_CH1_Current_App_RxBuffer,The Channel 0 Current Application Receive Buffer Address register points to the current Rx buffer address read by the DMA." hexmask.long 0x0 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation" group.long 0x11E0++0x3 line.long 0x0 "DMA_CH1_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA. Note: The number of DMA_CH(#i)_Status register in the configuration is the higher of number of Rx.." hexmask.long.word 0x0 22.--31. 1. "Reserved_31_22,Reserved." newline rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer.." "0: Transmit Interrupt,1: Normal Interrupt Summary status detected" newline bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer.." "0: Abnormal Interrupt Summary status not detected,1: Transmit Process Stopped" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates.." "0: Context Descriptor Error status not detected,1: Context Descriptor Error status detected" newline bitfld.long 0x0 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field)" "0: Fatal Bus Error status not detected,1: Fatal Bus Error status detected" newline bitfld.long 0x0 11. "ERI,Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory" "0: Early Receive Interrupt status not detected,1: Early Receive Interrupt status detected" newline bitfld.long 0x0 10. "ETI,Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory" "0: Early Transmit Interrupt status not detected,1: Early Transmit Interrupt status detected" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received" "0: Receive Watchdog Timeout status not detected,1: Receive Watchdog Timeout status detected" newline bitfld.long 0x0 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state" "0: Receive Process Stopped status not detected,1: Receive Process Stopped status detected" newline bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list and the DMA cannot acquire it" "0: Receive Buffer Unavailable status not detected,1: Receive Buffer Unavailable status detected" newline bitfld.long 0x0 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete" "0: Receive Interrupt status not detected,1: Receive Interrupt status detected" newline rbitfld.long 0x0 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list and the DMA cannot acquire it" "0: Transmit Buffer Unavailable status not detected,1: Transmit Buffer Unavailable status detected" newline bitfld.long 0x0 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped" "0: Transmit Process Stopped status not detected,1: Transmit Process Stopped status detected" newline bitfld.long 0x0 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete" "0: Transmit Interrupt status not detected,1: Transmit Interrupt status detected" rgroup.long 0x11E4++0xB line.long 0x0 "DMA_CH1_Miss_Frame_Cnt,This register has the number of packet counter that got dropped by the DMA either due to Bus Error or due to programming RPF field in DMA_CH{i}_Rx_Control register." hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved." newline bitfld.long 0x0 15. "MFCO,Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further" "0: Miss Frame Counter overflow not occurred,1: Miss Frame Counter overflow occurred" newline hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved." newline hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programing RPF field in DMA_CH{i}_Rx_Control register" line.long 0x4 "DMA_CH1_RXP_Accept_Cnt,The DMA_CH(#i)_RXP_Accept_Cnt registers provides the count of the number of frames accepted by Rx Parser." bitfld.long 0x4 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit When set this bit indicates that the RXPAC Counter field crossed the maximum limit" "0: Rx Parser Accept Counter overflow not occurred,1: Rx Parser Accept Counter overflow occurred" newline hexmask.long 0x4 0.--30. 1. "RXPAC,Rx Parser Accept Counter This 31-bit counter is implemented when a Rx Parser Accept a packet due to AF =1" line.long 0x8 "DMA_CH1_RX_ERI_Cnt,The DMA_CH(#i)_RX_ERI_Cnt registers provides the count of the number of times ERI was asserted." hexmask.long.tbyte 0x8 12.--31. 1. "Reserved_31_12,Reserved." newline hexmask.long.word 0x8 0.--11. 1. "ECNT,ERI Counter When ERIC bit of DMA_CH(#i)_RX_Control register is set this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer" group.long 0x1200++0xB line.long 0x0 "DMA_CH2_Control,The DMA Channeli Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode." hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved." newline bitfld.long 0x0 24. "SPH,Split Headers When this bit is set the DMA splits the header and payload in the Receive path" "0: Split Headers feature is disabled,1: Split Headers feature is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length This bit specifies the Word Dword or Lword number (depending on the 32-bit 64-bit or 128-bit bus) to skip between two unchained descriptors" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1" newline bitfld.long 0x0 16. "PBLx8,8xPBL mode When this bit is set the PBL value programmed in Bits[21:16] in DMA_CH(#i)_Tx_Control and Bits[21:16] in DMA_CH(#i)_Rx_Control is multiplied by eight times" "0: 8xPBL mode is disabled,1: 8xPBL mode is enabled" newline rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3" newline hexmask.long.word 0x0 0.--13. 1. "Reserved_MSS,Reserved." line.long 0x4 "DMA_CH2_Tx_Control,The DMA Channeli Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights." rbitfld.long 0x4 31. "Reserved_31,Reserved." "0,1" newline bitfld.long 0x4 29.--30. "TFSEL,TBS Fetch Select Select bits for one of the four DMA_TBS_CTRL register fields (FTOS FGSN FTOV) for the channel Values: - 2'b00: DMA_TBS_CTRL0 - 2'b01: DMA_TBS_CTRL1 - 2'b10: DMA_TBS_CTRL2 - 2'b11: DMA_TBS_CTRL3 (Reserved if DWC_EQOS_NUM_DMA_TX_CH=3)" "0: DMA_TBS_CTRL0,1: DMA_TBS_CTRL1,2: DMA_TBS_CTRL2,3: DMA_TBS_CTRL3" newline bitfld.long 0x4 28. "EDSE,Enhanced Descriptor Enable When this bit is set the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors" "0: Enhanced Descriptor is disabled,1: Enhanced Descriptor is enabled" newline hexmask.long.byte 0x4 24.--27. 1. "Reserved_TQOS,Reserved." newline rbitfld.long 0x4 23. "Reserved_23,Reserved." "0,1" newline bitfld.long 0x4 22. "ETIC,Early Transmit Interrupt Control When this bit is set Early Transmit Interrupt (ETI) status is set after completion of transfer of data from buffers of a transmit descriptor in which IOC bit (TDES2[31]) is set" "0: Early Transmit Interrupt is disabled,1: Early Transmit Interrupt is enabled" newline hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" newline rbitfld.long 0x4 15. "Reserved_IPBL,Reserved." "0,1" newline rbitfld.long 0x4 13.--14. "Reserved_TSE_MODE,Reserved." "0,1,2,3" newline rbitfld.long 0x4 12. "Reserved_TSE,Reserved." "0,1" newline hexmask.long.byte 0x4 5.--11. 1. "Reserved_11_5,Reserved." newline bitfld.long 0x4 4. "OSF,Operate on Second Packet When this bit is set it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained" "0: Operate on Second Packet disabled,1: Operate on Second Packet enabled" newline bitfld.long 0x4 1.--3. "TCW,Transmit Channel Weight This field indicates the weight assigned to the corresponding Transmit channel" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "ST,Start or Stop Transmission Command When this bit is set transmission is placed in the Running state" "0: Stop Transmission Command,1: Start Transmission Command" line.long 0x8 "DMA_CH2_Rx_Control,The DMA Channeli Receive Control register controls the Rx features such as PBL. buffer size. and extended status." bitfld.long 0x8 31. "RPF,Rx Packet Flush" "0: Rx Packet Flush is disabled,1: Rx Packet Flush is enabled" newline rbitfld.long 0x8 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 24.--27. 1. "Reserved_RQOS,Reserved." newline rbitfld.long 0x8 23. "Reserved_23,Reserved." "0,1" newline bitfld.long 0x8 22. "ERIC,Early Receive Interrupt Control When this bit is set Early Receive Interrupt (ERI) status is set after the completion of every burst transfer of data from the Rx DMA to the buffer" "0: Early Receive Interrupt is disabled,1: Early Receive Interrupt is enabled" newline hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" newline rbitfld.long 0x8 15. "Reserved_15,Reserved." "0,1" newline hexmask.long.word 0x8 4.--14. 1. "RBSZ_13_y,Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0" newline rbitfld.long 0x8 1.--3. "RBSZ_x_0,Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "SR,Start or Stop Receive When this bit is set the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets" "0: Stop Receive,1: Start Receive" group.long 0x1214++0x3 line.long 0x0 "DMA_CH2_TxDesc_List_Address,The Channeli Tx Descriptor List Address register points the DMA to the start of Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Word. Dword. or Lword-aligned.." hexmask.long 0x0 3.--31. 1. "TDESLA,Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list" newline rbitfld.long 0x0 0.--2. "Reserved_LSb,Reserved." "0,1,2,3,4,5,6,7" group.long 0x121C++0x7 line.long 0x0 "DMA_CH2_RxDesc_List_Address,The Channeli Rx Descriptor List Address register points the DMA to the start of Receive descriptor list. This register points to the start of the Receive Descriptor List. The descriptor lists reside in the physical memory.." hexmask.long 0x0 3.--31. 1. "RDESLA,Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list" newline rbitfld.long 0x0 0.--2. "Reserved_LSb,Reserved." "0,1,2,3,4,5,6,7" line.long 0x4 "DMA_CH2_TxDesc_Tail_Pointer,The Channeli Tx Descriptor Tail Pointer register points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x4 3.--31. 1. "TDTP,Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring" newline rbitfld.long 0x4 0.--2. "Reserved_LSb,Reserved." "0,1,2,3,4,5,6,7" group.long 0x1228++0x17 line.long 0x0 "DMA_CH2_RxDesc_Tail_Pointer,The Channeli Rx Descriptor Tail Pointer Points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x0 3.--31. 1. "RDTP,Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring" newline rbitfld.long 0x0 0.--2. "Reserved_LSb,Reserved." "0,1,2,3,4,5,6,7" line.long 0x4 "DMA_CH2_TxDesc_Ring_Length,The Tx Descriptor Ring Length register contains the length of the Transmit descriptor ring." hexmask.long.tbyte 0x4 10.--31. 1. "Reserved_31_10,Reserved." newline hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring Length" line.long 0x8 "DMA_CH2_Rx_Control2,The Channeli Receive Control register controls the Rx features such as Rx Descriptor Ring Length and Alternate Rx Buffer Size." hexmask.long.byte 0x8 24.--31. 1. "Reserved_31_24,Reserved." newline hexmask.long.byte 0x8 17.--23. 1. "ARBS,Alternate Receive Buffer Size Indicates size in bytes for Buffer 1 when ARBS is programmed to a non-zero value (when split header feature is not enabled)" newline hexmask.long.byte 0x8 10.--16. 1. "Reserved_x_10,Reserved." newline hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring" line.long 0xC "DMA_CH2_Interrupt_Enable,The Channeli Interrupt Enable register enables the interrupts reported by the Status register." hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved." newline bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable When this bit is set the normal interrupt summary is enabled" "0: Normal Interrupt Summary is disabled,1: Normal Interrupt Summary is enabled" newline bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable When this bit is set the abnormal interrupt summary is enabled" "0: Abnormal Interrupt Summary is disabled,1: Abnormal Interrupt Summary is enabled" newline bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable When this bit is set along with the AIE bit the Descriptor error interrupt is enabled" "0: Context Descriptor Error is disabled,1: Context Descriptor Error is enabled" newline bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable When this bit is set along with the AIE bit the Fatal Bus error interrupt is enabled" "0: Fatal Bus Error is disabled,1: Fatal Bus Error is enabled" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt Enable When this bit is set along with the NIE bit the Early Receive interrupt is enabled" "0: Early Receive Interrupt is disabled,1: Early Receive Interrupt is enabled" newline bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt Enable When this bit is set along with the AIE bit the Early Transmit interrupt is enabled" "0: Early Transmit Interrupt is disabled,1: Early Transmit Interrupt is enabled" newline bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout Enable When this bit is set along with the AIE bit the Receive Watchdog Timeout interrupt is enabled" "0: Receive Watchdog Timeout is disabled,1: Receive Watchdog Timeout is enabled" newline bitfld.long 0xC 8. "RSE,Receive Stopped Enable When this bit is set along with the AIE bit the Receive Stopped Interrupt is enabled" "0: Receive Stopped is disabled,1: Receive Stopped is enabled" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable When this bit is set along with the AIE bit the Receive Buffer Unavailable interrupt is enabled" "0: Receive Buffer Unavailable is disabled,1: Receive Buffer Unavailable is enabled" newline bitfld.long 0xC 6. "RIE,Receive Interrupt Enable When this bit is set along with the NIE bit the Receive Interrupt is enabled" "0: Receive Interrupt is disabled,1: Receive Interrupt is enabled" newline rbitfld.long 0xC 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit the Transmit Buffer Unavailable interrupt is enabled" "0: Transmit Buffer Unavailable is disabled,1: Transmit Buffer Unavailable is enabled" newline bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable When this bit is set along with the AIE bit the Transmission Stopped interrupt is enabled" "0: Transmit Stopped is disabled,1: Transmit Stopped is enabled" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable When this bit is set along with the NIE bit the Transmit Interrupt is enabled" "0: Transmit Interrupt is disabled,1: Transmit Interrupt is enabled" line.long 0x10 "DMA_CH2_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. When this register is written with a non-zero value. it enables the watchdog timer for the RI bit of.." hexmask.long.word 0x10 18.--31. 1. "Reserved_31_18,Reserved." newline bitfld.long 0x10 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field" "0,1,2,3" newline hexmask.long.byte 0x10 8.--15. 1. "Reserved_15_8,Reserved." newline hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles multiplied by factor indicated in RWTU field for which the watchdog timer is set" line.long 0x14 "DMA_CH2_Slot_Function_Control_Status,The Slot Function Control and Status register contains the control bits for slot function and the status for Transmit path." hexmask.long.word 0x14 20.--31. 1. "Reserved_31_20,Reserved." newline hexmask.long.byte 0x14 16.--19. 1. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA" newline hexmask.long.word 0x14 4.--15. 1. "SIV,Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets" newline rbitfld.long 0x14 2.--3. "Reserved_3_2,Reserved." "0,1,2,3" newline bitfld.long 0x14 1. "ASC,Advance Slot Check When set this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot.." "0: Advance Slot Check is disabled,1: Advance Slot Check is enabled" newline bitfld.long 0x14 0. "ESC,Enable Slot Comparison When set this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field" "0: Slot Comparison is disabled,1: Slot Comparison is enabled" rgroup.long 0x1244++0x3 line.long 0x0 "DMA_CH2_Current_App_TxDesc,The Channeli Current Application Transmit Descriptor register points to the current Transmit descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation" rgroup.long 0x124C++0x3 line.long 0x0 "DMA_CH2_Current_App_RxDesc,The Channeli Current Application Receive Descriptor register points to the current Receive descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation" rgroup.long 0x1254++0x3 line.long 0x0 "DMA_CH2_Current_App_TxBuffer,The Channeli Current Application Transmit Buffer Address register points to the current Tx buffer address read by the DMA." hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation" rgroup.long 0x125C++0x3 line.long 0x0 "DMA_CH2_Current_App_RxBuffer,The Channel 0 Current Application Receive Buffer Address register points to the current Rx buffer address read by the DMA." hexmask.long 0x0 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation" group.long 0x1260++0x3 line.long 0x0 "DMA_CH2_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA. Note: The number of DMA_CH(#i)_Status register in the configuration is the higher of number of Rx.." hexmask.long.word 0x0 22.--31. 1. "Reserved_31_22,Reserved." newline rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer.." "0: Transmit Interrupt,1: Normal Interrupt Summary status detected" newline bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer.." "0: Abnormal Interrupt Summary status not detected,1: Transmit Process Stopped" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates.." "0: Context Descriptor Error status not detected,1: Context Descriptor Error status detected" newline bitfld.long 0x0 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field)" "0: Fatal Bus Error status not detected,1: Fatal Bus Error status detected" newline bitfld.long 0x0 11. "ERI,Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory" "0: Early Receive Interrupt status not detected,1: Early Receive Interrupt status detected" newline bitfld.long 0x0 10. "ETI,Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory" "0: Early Transmit Interrupt status not detected,1: Early Transmit Interrupt status detected" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received" "0: Receive Watchdog Timeout status not detected,1: Receive Watchdog Timeout status detected" newline bitfld.long 0x0 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state" "0: Receive Process Stopped status not detected,1: Receive Process Stopped status detected" newline bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list and the DMA cannot acquire it" "0: Receive Buffer Unavailable status not detected,1: Receive Buffer Unavailable status detected" newline bitfld.long 0x0 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete" "0: Receive Interrupt status not detected,1: Receive Interrupt status detected" newline rbitfld.long 0x0 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list and the DMA cannot acquire it" "0: Transmit Buffer Unavailable status not detected,1: Transmit Buffer Unavailable status detected" newline bitfld.long 0x0 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped" "0: Transmit Process Stopped status not detected,1: Transmit Process Stopped status detected" newline bitfld.long 0x0 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete" "0: Transmit Interrupt status not detected,1: Transmit Interrupt status detected" rgroup.long 0x1264++0xB line.long 0x0 "DMA_CH2_Miss_Frame_Cnt,This register has the number of packet counter that got dropped by the DMA either due to Bus Error or due to programming RPF field in DMA_CH{i}_Rx_Control register." hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved." newline bitfld.long 0x0 15. "MFCO,Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further" "0: Miss Frame Counter overflow not occurred,1: Miss Frame Counter overflow occurred" newline hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved." newline hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programing RPF field in DMA_CH{i}_Rx_Control register" line.long 0x4 "DMA_CH2_RXP_Accept_Cnt,The DMA_CH(#i)_RXP_Accept_Cnt registers provides the count of the number of frames accepted by Rx Parser." bitfld.long 0x4 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit When set this bit indicates that the RXPAC Counter field crossed the maximum limit" "0: Rx Parser Accept Counter overflow not occurred,1: Rx Parser Accept Counter overflow occurred" newline hexmask.long 0x4 0.--30. 1. "RXPAC,Rx Parser Accept Counter This 31-bit counter is implemented when a Rx Parser Accept a packet due to AF =1" line.long 0x8 "DMA_CH2_RX_ERI_Cnt,The DMA_CH(#i)_RX_ERI_Cnt registers provides the count of the number of times ERI was asserted." hexmask.long.tbyte 0x8 12.--31. 1. "Reserved_31_12,Reserved." newline hexmask.long.word 0x8 0.--11. 1. "ECNT,ERI Counter When ERIC bit of DMA_CH(#i)_RX_Control register is set this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer" tree.end tree "GMAC_1" base ad:0x40488000 group.long 0x0++0x2F line.long 0x0 "MAC_Configuration,The MAC Configuration Register establishes the operating mode of the MAC." bitfld.long 0x0 31. "ARPEN,ARP Offload Enable When this bit is set the MAC can recognize an incoming ARP request packet and schedules the ARP packet for transmission" "0: ARP Offload is disabled,1: ARP Offload is enabled" newline bitfld.long 0x0 28.--30. "SARC,Source Address Insertion or Replacement Control This field controls the source address insertion or replacement for all transmitted packets" "0: mti_sa_ctrl_i and ati_sa_ctrl_i input signals..,?,2: Contents of MAC Addr-0 inserted in SA field,3: Contents of MAC Addr-0 replaces SA field,?,?,6: Contents of MAC Addr-1 inserted in SA field,7: Contents of MAC Addr-1 replaces SA field" newline bitfld.long 0x0 27. "IPC,Checksum Offload When set this bit enables the IPv4 header checksum checking and IPv4 or IPv6 TCP UDP or ICMP payload checksum checking" "0: IP header/payload checksum checking is disabled,1: IP header/payload checksum checking is enabled" newline bitfld.long 0x0 24.--26. "IPG,Inter-Packet Gap These bits control the minimum IPG between packets during transmission" "0: 96 bit times IPG,1: 88 bit times IPG,2: 80 bit times IPG,3: 72 bit times IPG,4: 64 bit times IPG,5: 56 bit times IPG,6: 48 bit times IPG,7: 40 bit times IPG" newline bitfld.long 0x0 23. "GPSLCE,Giant Packet Size Limit Control Enable When this bit is set the MAC considers the value in GPSL field in MAC_Ext_Configuration register to declare a received packet as Giant packet" "0: Giant Packet Size Limit Control is disabled,1: Giant Packet Size Limit Control is enabled" newline bitfld.long 0x0 22. "S2KP,IEEE 802" "0: Support upto 2K packet is disabled,1: Support upto 2K packet is Enabled" newline bitfld.long 0x0 21. "CST,CRC stripping for Type packets When this bit is set the last four bytes (FCS) of all packets of Ether type (type field greater than 1 536) are stripped and dropped before forwarding the packet to the application" "0: CRC stripping for Type packets is disabled,1: CRC stripping for Type packets is enabled" newline bitfld.long 0x0 20. "ACS,Automatic Pad or CRC Stripping When this bit is set the MAC strips the Pad or FCS field on the incoming packets only if the value of the length field is less than 1 536 bytes" "0: Automatic Pad or CRC Stripping is disabled,1: Automatic Pad or CRC Stripping is enabled" newline bitfld.long 0x0 19. "WD,Watchdog Disable When this bit is set the MAC disables the watchdog timer on the receiver" "0: Watchdog is enabled,1: Watchdog is disabled" newline bitfld.long 0x0 18. "BE,Packet Burst Enable When this bit is set the MAC allows packet bursting during transmission in the GMII half-duplex mode" "0: Packet Burst is disabled,1: Packet Burst is enabled" newline bitfld.long 0x0 17. "JD,Jabber Disable When this bit is set the MAC disables the jabber timer on the transmitter" "0: Jabber is enabled,1: Jabber is disabled" newline bitfld.long 0x0 16. "JE,Jumbo Packet Enable When this bit is set the MAC allows jumbo packets of 9 018 bytes (9 022 bytes for VLAN tagged packets) without reporting a giant packet error in the Rx packet status" "0: Jumbo packet is disabled,1: Jumbo packet is enabled" newline bitfld.long 0x0 15. "PS,Port Select This bit selects the Ethernet line speed" "0: For 1000 or 2500 Mbps operations,1: For 10 or 100 Mbps operations" newline bitfld.long 0x0 14. "FES,Speed This bit selects the speed mode. The mac_speed_o[0] signal reflects the value of this bit." "0: 10 Mbps when PS bit is 1 and 1 Gbps when PS bit..,1: 100 Mbps when PS bit is 1 and 2.5 Gbps when PS.." newline bitfld.long 0x0 13. "DM,Duplex Mode When this bit is set the MAC operates in the full-duplex mode in which it can transmit and receive simultaneously" "0: Half-duplex mode,1: Full-duplex mode" newline bitfld.long 0x0 12. "LM,Loopback Mode When this bit is set the MAC operates in the loopback mode at GMII or MII" "0: Loopback is disabled,1: Loopback is enabled" newline bitfld.long 0x0 11. "ECRSFD,Enable Carrier Sense Before Transmission in Full-Duplex Mode When this bit is set the MAC transmitter checks the CRS signal before packet transmission in the full-duplex mode" "0: ECRSFD is disabled,1: ECRSFD is enabled" newline bitfld.long 0x0 10. "DO,Disable Receive Own When this bit is set the MAC disables the reception of packets when the gmii_txen_o is asserted in the half-duplex mode" "0: Enable Receive Own,1: Disable Receive Own" newline bitfld.long 0x0 9. "DCRS,Disable Carrier Sense During Transmission When this bit is set the MAC transmitter ignores the (G)MII CRS signal during packet transmission in the half-duplex mode" "0: Enable Carrier Sense During Transmission,1: Disable Carrier Sense During Transmission" newline bitfld.long 0x0 8. "DR,Disable Retry When this bit is set the MAC attempts only one transmission" "0: Enable Retry,1: Disable Retry" newline rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1" newline bitfld.long 0x0 5.--6. "BL,Back-Off Limit The back-off limit determines the random integer number (r) of slot time delays (4 096 bit times for 1000/2500 Mbps; 512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after.." "0: k = min(n 10),1: k = min(n 8),2: k = min(n 4),3: k = min(n 1)" newline bitfld.long 0x0 4. "DC,Deferral Check When this bit is set the deferral check function is enabled in the MAC" "0: Deferral check function is disabled,1: Deferral check function is enabled" newline bitfld.long 0x0 2.--3. "PRELEN,Preamble Length for Transmit packets These bits control the number of preamble bytes that are added to the beginning of every Tx packet" "0: 7 bytes of preamble,1: 5 bytes of preamble,2: 3 bytes of preamble,?" newline bitfld.long 0x0 1. "TE,Transmitter Enable When this bit is set the Tx state machine of the MAC is enabled for transmission on the GMII or MII interface" "0: Transmitter is disabled,1: Transmitter is enabled" newline bitfld.long 0x0 0. "RE,Receiver Enable When this bit is set the Rx state machine of the MAC is enabled for receiving packets from the GMII or MII interface" "0: Receiver is disabled,1: Receiver is enabled" line.long 0x4 "MAC_Ext_Configuration,The MAC Extended Configuration Register establishes the operating mode of the MAC." rbitfld.long 0x4 31. "Reserved_FHE,Reserved." "0,1" newline bitfld.long 0x4 30. "APDIM,ARP Packet Drop if IP Address Mismatch When this bit is set Packet for which Target Protocol Address does not match IPv4 address is dropped in the MTL layer" "0: mux select to drop the arp packet if target..,1: mux select to drop the arp packet if target.." newline hexmask.long.byte 0x4 25.--29. 1. "EIPG,Extended Inter-Packet Gap The value in this field is applicable when the EIPGEN bit is set" newline bitfld.long 0x4 24. "EIPGEN,Extended Inter-Packet Gap Enable When this bit is set the MAC interprets EIPG field and IPG field in MAC_Configuration register together as minimum IPG greater than 96 bit times in steps of 8 bit times" "0: Extended Inter-Packet Gap is disabled,1: Extended Inter-Packet Gap is enabled" newline rbitfld.long 0x4 23. "Reserved_23,Reserved." "0,1" newline bitfld.long 0x4 20.--22. "HDSMS,Maximum Size for Splitting the Header Data These bits indicate the maximum header size allowed for splitting the header data in the received packet" "0: Maximum Size for Splitting the Header Data is 64..,1: Maximum Size for Splitting the Header Data is..,2: Maximum Size for Splitting the Header Data is..,3: Maximum Size for Splitting the Header Data is..,4: Maximum Size for Splitting the Header Data is..,?,?,?" newline bitfld.long 0x4 19. "PDC,Packet Duplication Control When this bit is set the received packet with Multicast/Broadcast Destination address is routed to multiple Receive DMA Channels" "0: Packet Duplication Control is disabled,1: Packet Duplication Control is enabled" newline bitfld.long 0x4 18. "USP,Unicast Slow Protocol Packet Detect When this bit is set the MAC detects the Slow Protocol packets with unicast address of the station specified in the MAC_Address0_High and MAC_Address0_Low registers" "0: Unicast Slow Protocol Packet Detection is disabled,1: Unicast Slow Protocol Packet Detection is enabled" newline bitfld.long 0x4 17. "SPEN,Slow Protocol Detection Enable When this bit is set MAC processes the Slow Protocol packets (Ether Type 0x8809) and provides the Slow Protocol Sub-Type and Code fields in Rx status" "0: Slow Protocol Detection is disabled,1: Slow Protocol Detection is enabled" newline bitfld.long 0x4 16. "DCRCC,Disable CRC Checking for Received Packets When this bit is set the MAC receiver does not check the CRC field in the received packets" "0: CRC Checking is enabled,1: CRC Checking is disabled" newline rbitfld.long 0x4 14.--15. "Reserved_15_14,Reserved." "0,1,2,3" newline hexmask.long.word 0x4 0.--13. 1. "GPSL,Giant Packet Size Limit If the received packet size is greater than the value programmed in this field in units of bytes the MAC declares the received packet as Giant packet" line.long 0x8 "MAC_Packet_Filter,The MAC Packet Filter register contains the filter controls for receiving packets. Some of the controls from this register go to the address check block of the MAC which performs the first level of address filtering. The second level of.." bitfld.long 0x8 31. "RA,Receive All When this bit is set the MAC Receiver module passes all received packets to the application irrespective of whether they pass the address filter or not" "0: Receive All is disabled,1: Receive All is enabled" newline hexmask.long.word 0x8 22.--30. 1. "Reserved_30_22,Reserved." newline bitfld.long 0x8 21. "DNTU,Drop Non-TCP/UDP over IP Packets When this bit is set the MAC drops the non-TCP or UDP over IP packets" "0: Forward Non-TCP/UDP over IP Packets,1: Drop Non-TCP/UDP over IP Packets" newline bitfld.long 0x8 20. "IPFE,Layer 3 and Layer 4 Filter Enable When this bit is set the MAC drops packets that do not match the enabled Layer 3 and Layer 4 filters" "0: Layer 3 and Layer 4 Filters are disabled,1: Layer 3 and Layer 4 Filters are enabled" newline rbitfld.long 0x8 17.--19. "Reserved_19_17,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 16. "VTFE,VLAN Tag Filter Enable When this bit is set the MAC drops the VLAN tagged packets that do not match the VLAN Tag" "0: VLAN Tag Filter is disabled,1: VLAN Tag Filter is enabled" newline hexmask.long.byte 0x8 11.--15. 1. "Reserved_15_11,Reserved." newline bitfld.long 0x8 10. "HPF,Hash or Perfect Filter When this bit is set the address filter passes a packet if it matches either the perfect filtering or hash filtering as set by the HMC or HUC bit" "0: Hash or Perfect Filter is disabled,1: Hash or Perfect Filter is enabled" newline bitfld.long 0x8 9. "SAF,Source Address Filter Enable When this bit is set the MAC compares the SA field of the received packets with the values programmed in the enabled SA registers" "0: SA Filtering is disabled,1: SA Filtering is enabled" newline bitfld.long 0x8 8. "SAIF,SA Inverse Filtering When this bit is set the Address Check block operates in the inverse filtering mode for SA address comparison" "0: SA Inverse Filtering is disabled,1: SA Inverse Filtering is enabled" newline bitfld.long 0x8 6.--7. "PCF,Pass Control Packets These bits control the forwarding of all control packets (including unicast and multicast Pause packets)" "0: MAC filters all control packets from reaching..,1: MAC forwards all control packets except Pause..,2: MAC forwards all control packets to the..,3: MAC forwards the control packets that pass the.." newline bitfld.long 0x8 5. "DBF,Disable Broadcast Packets When this bit is set the AFM module blocks all the incoming broadcast packets" "0: Enable Broadcast Packets,1: Disable Broadcast Packets" newline bitfld.long 0x8 4. "PM,Pass All Multicast When this bit is set it indicates that all the received packets with a multicast destination address (first bit in the destination address field is '1') are passed" "0: Pass All Multicast is disabled,1: Pass All Multicast is enabled" newline bitfld.long 0x8 3. "DAIF,DA Inverse Filtering When this bit is set the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast packets" "0: DA Inverse Filtering is disabled,1: DA Inverse Filtering is enabled" newline bitfld.long 0x8 2. "HMC,Hash Multicast When this bit is set the MAC performs the destination address filtering of received multicast packets according to the hash table" "0: Hash Multicast is disabled,1: Hash Multicast is enabled" newline bitfld.long 0x8 1. "HUC,Hash Unicast When this bit is set the MAC performs the destination address filtering of unicast packets according to the hash table" "0: Hash Unicast is disabled,1: Hash Unicast is enabled" newline bitfld.long 0x8 0. "PR,Promiscuous Mode When this bit is set the Address Filtering module passes all incoming packets irrespective of the destination or source address" "0: Promiscuous Mode is disabled,1: Promiscuous Mode is enabled" line.long 0xC "MAC_Watchdog_Timeout,The Watchdog Timeout register controls the watchdog timeout for received packets." hexmask.long.tbyte 0xC 9.--31. 1. "Reserved_31_9,Reserved." newline bitfld.long 0xC 8. "PWE,Programmable Watchdog Enable When this bit is set and the WD bit of the MAC_Configuration register is reset the WTO field is used as watchdog timeout for a received packet" "0: Programmable Watchdog is disabled,1: Programmable Watchdog is enabled" newline hexmask.long.byte 0xC 4.--7. 1. "Reserved_7_4,Reserved." newline hexmask.long.byte 0xC 0.--3. 1. "WTO,Watchdog Timeout When the PWE bit is set and the WD bit of the MAC_Configuration register is reset this field is used as watchdog timeout for a received packet" line.long 0x10 "MAC_Hash_Table_Reg0,The Hash Table Register 0 contains the first 32 bits of the hash table. when the width of the hash table is 128 or 256 bits. You can specify the width of the hash table by using the Hash Table Size option in coreConsultant. In this.." hexmask.long 0x10 0.--31. 1. "HT31T0,MAC Hash Table First 32 Bits This field contains the first 32 Bits [31:0] of the Hash table." line.long 0x14 "MAC_Hash_Table_Reg1,The Hash Table Register 1 contains the second 32 bits of the hash table. You can specify the width of the hash table by using the Hash Table Size option in coreConsultant. The Hash table is used for group address filtering. For hash.." hexmask.long 0x14 0.--31. 1. "HT63T32,MAC Hash Table Second 32 Bits This field contains the second 32 Bits [63:32] of the Hash table." line.long 0x18 "MAC_Hash_Table_Reg2,The Hash Table Register 2 contains the third 32 bits of the hash table. You can specify the width of the hash table by using the Hash Table Size option in coreConsultant. The Hash table is used for group address filtering. For hash.." hexmask.long 0x18 0.--31. 1. "HT95T64,MAC Hash Table Third 32 Bits This field contains the third 32 Bits [95:64] of the Hash table." line.long 0x1C "MAC_Hash_Table_Reg3,The Hash Table Register 3 contains the fourth 32 bits of the hash table. You can specify the width of the hash table by using the Hash Table Size option in coreConsultant. The Hash table is used for group address filtering. For hash.." hexmask.long 0x1C 0.--31. 1. "HT127T96,MAC Hash Table Fourth 32 Bits This field contains the fourth 32 Bits [127:96] of the Hash table." line.long 0x20 "MAC_Hash_Table_Reg4,The Hash Table Register 4 contains the fifth 32 bits of the hash table. You can specify the width of the hash table by using the Hash Table Size option in coreConsultant. The Hash table is used for group address filtering. For hash.." hexmask.long 0x20 0.--31. 1. "HT159T128,MAC Hash Table Fifth 32 Bits This field contains the fifth 32 Bits [159:128] of the Hash table." line.long 0x24 "MAC_Hash_Table_Reg5,The Hash Table Register 5 contains the sixth 32 bits of the hash table. You can specify the width of the hash table by using the Hash Table Size option in coreConsultant. The Hash table is used for group address filtering. For hash.." hexmask.long 0x24 0.--31. 1. "HT191T160,MAC Hash Table Sixth 32 Bits This field contains the sixth 32 Bits [191:160] of the Hash table." line.long 0x28 "MAC_Hash_Table_Reg6,The Hash Table Register 6 contains the seventh 32 bits of the hash table. You can specify the width of the hash table by using the Hash Table Size option in coreConsultant. The Hash table is used for group address filtering. For hash.." hexmask.long 0x28 0.--31. 1. "HT223T192,MAC Hash Table Seventh 32 Bits This field contains the seventh 32 Bits [223:192] of the Hash table." line.long 0x2C "MAC_Hash_Table_Reg7,The Hash Table Register 7 contains the eighth 32 bits of the hash table. You can specify the width of the hash table by using the Hash Table Size option in coreConsultant. The Hash table is used for group address filtering. For hash.." hexmask.long 0x2C 0.--31. 1. "HT255T224,MAC Hash Table Eighth 32 Bits This field contains the eighth 32 Bits [255:224] of the Hash table." group.long 0x50++0x7 line.long 0x0 "MAC_VLAN_Tag_Ctrl,This register is the redefined format of the MAC VLAN Tag Register. It is used for indirect addressing. It contains the address offset. command type and Busy Bit for CSR access of the Per VLAN Tag registers." bitfld.long 0x0 31. "EIVLRXS,Enable Inner VLAN Tag in Rx Status When this bit is set the MAC provides the inner VLAN Tag in the Rx status" "0: Inner VLAN Tag in Rx status is disabled,1: Inner VLAN Tag in Rx status is enabled" newline rbitfld.long 0x0 30. "Reserved_30,Reserved." "0,1" newline bitfld.long 0x0 28.--29. "EIVLS,Enable Inner VLAN Tag Stripping on Receive This field indicates the stripping operation on inner VLAN Tag in received packet" "0: Do not strip,1: Strip if VLAN filter passes,2: Strip if VLAN filter fails,3: Always strip" newline bitfld.long 0x0 27. "ERIVLT,Enable Inner VLAN Tag Comparison When this bit VTHM bit and the EDVLP field are set the MAC receiver enables VLAN Hash filtering operation on the inner VLAN Tag (if present)" "0: Inner VLAN tag is disabled,1: Inner VLAN tag is enabled" newline bitfld.long 0x0 26. "EDVLP,Enable Double VLAN Processing When this bit is set the MAC enables processing of up to two VLAN Tags on Tx and Rx (if present)" "0: Double VLAN Processing is disabled,1: Double VLAN Processing is enabled" newline bitfld.long 0x0 25. "VTHM,VLAN Tag Hash Table Match Enable When this bit is set the most significant four bits of CRC of VLAN Tag are used to index the content of the MAC_VLAN_Hash_Table register" "0: VLAN Tag Hash Table Match is disabled,1: VLAN Tag Hash Table Match is enabled" newline bitfld.long 0x0 24. "EVLRXS,Enable VLAN Tag in Rx status When this bit is set MAC provides the outer VLAN Tag in the Rx status" "0: VLAN Tag in Rx status is disabled,1: VLAN Tag in Rx status is enabled" newline rbitfld.long 0x0 23. "Reserved_23,Reserved." "0,1" newline bitfld.long 0x0 21.--22. "EVLS,Enable VLAN Tag Stripping on Receive This field indicates the stripping operation on the outer VLAN Tag in received packet" "0: Do not strip,1: Strip if VLAN filter passes,2: Strip if VLAN filter fails,3: Always strip" newline bitfld.long 0x0 20. "DOVLTC,Disable VLAN Type Check for VLAN Hash Filtering When this bit is set the MAC VLAN Hash Filter does not check whether the VLAN Tag specified by the ERIVLT bit is of type S-VLAN or C-VLAN" "0: VLAN Type Check is enabled,1: VLAN Type Check is disabled" newline bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match for VLAN Hash Filtering When this bit is set the MAC receiver enables VLAN Hash filtering or matching for S-VLAN (Type = 0x88A8) packets" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "ESVL,Enable S-VLAN When this bit is set the MAC transmitter and receiver consider the S-VLAN packets (Type = 0x88A8) as valid VLAN tagged packets" "0: S-VLAN is disabled,1: S-VLAN is enabled" newline bitfld.long 0x0 17. "VTIM,VLAN Tag Inverse Match Enable When this bit is set this bit enables the VLAN Tag inverse matching" "0: VLAN Tag Inverse Match is disabled,1: VLAN Tag Inverse Match is enabled" newline bitfld.long 0x0 16. "ETV,Enable 12-Bit VLAN Tag Comparison for VLAN Hash Filtering When this bit is set a 12-bit VLAN identifier is used for VLAN Hash filtering instead of the complete 16-bit VLAN tag" "0: 12-Bit VLAN Tag Comparison is disabled,1: 12-Bit VLAN Tag Comparison is enabled" newline hexmask.long.word 0x0 7.--15. 1. "Reserved_15_y,Reserved." newline hexmask.long.byte 0x0 2.--6. 1. "OFS,Offset This field holds the address offset of the MAC VLAN Tag Filter Register which the application is trying to access" newline bitfld.long 0x0 1. "CT,Command Type This bit indicates if the current register access is a read or a write" "0: Write operation,1: Read operation" newline bitfld.long 0x0 0. "OB,Operation Busy This bit is set along with a read or write command for initiating the indirect access to per VLAN Tag Filter register" "0: Operation Busy is disabled,1: Operation Busy is enabled" line.long 0x4 "MAC_VLAN_Tag_Data,This register holds the read/write data for Indirect Access of the Per VLAN Tag registers. During the read access. this field contains valid read data only after the OB bit is reset. During the write access. this field should be valid.." hexmask.long.byte 0x4 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x4 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x4 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x4 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x4 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x4 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x4 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x4 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x4 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter0,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter1,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter10,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter11,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter12,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter13,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter14,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter15,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter16,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter17,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter18,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter19,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter2,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter20,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter21,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter22,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter23,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter24,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter25,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter26,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter27,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter28,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter29,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter3,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter30,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter31,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter4,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter5,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter6,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter7,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x3 line.long 0x0 "MAC_VLAN_Tag_Filter8,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" group.long 0x54++0x7 line.long 0x0 "MAC_VLAN_Tag_Filter9,This register contains VLAN Tag filter {i} control information." hexmask.long.byte 0x0 27.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x0 25.--26. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1,2,3" newline bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled" newline bitfld.long 0x0 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled" newline bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled" newline bitfld.long 0x0 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison" newline bitfld.long 0x0 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled" newline hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison" line.long 0x4 "MAC_VLAN_Hash_Table,When VTHM bit of the MAC_VLAN_Tag register is set. the 16-bit VLAN Hash Table register is used for group address filtering based on the VLAN tag. For hash filtering. the content of the 16-bit VLAN tag or 12-bit VLAN ID (based on the.." hexmask.long.word 0x4 16.--31. 1. "Reserved_31_16,Reserved." newline hexmask.long.word 0x4 0.--15. 1. "VLHT,VLAN Hash Table This field contains the 16-bit VLAN Hash Table." group.long 0x60++0x3 line.long 0x0 "MAC_VLAN_Incl,The VLAN Tag Inclusion or Replacement register contains the VLAN tag for insertion or replacement in the Transmit packets. It also contains the VLAN tag insertion controls." rbitfld.long 0x0 31. "BUSY,Busy This bit indicates the status of the read/write operation of indirect access to the queue/channel specific VLAN inclusion register" "0: Busy status not detected,1: Busy status detected" newline bitfld.long 0x0 30. "RDWR,Read write control This bit controls the read or write operation for indirectly accessing the queue/channel specific VLAN Inclusion register" "0: Read operation of indirect access,1: Write operation of indirect access" newline hexmask.long.byte 0x0 26.--29. 1. "Reserved_29_y,Reserved." newline bitfld.long 0x0 24.--25. "ADDR,Address This field selects one of the queue/channel specific VLAN Inclusion register for read/write access" "0,1,2,3" newline rbitfld.long 0x0 22.--23. "Reserved_23_22,Reserved." "0,1,2,3" newline bitfld.long 0x0 21. "CBTI,Channel based tag insertion When this bit is set outer VLAN tag is inserted for every packets transmitted by the MAC" "0: Channel based tag insertion is disabled,1: Channel based tag insertion is enabled" newline bitfld.long 0x0 20. "VLTI,VLAN Tag Input When this bit is set it indicates that the VLAN tag to be inserted or replaced in Tx packet should be taken from: - The Tx descriptor" "0: VLAN Tag Input is disabled,1: VLAN Tag Input is enabled" newline bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN When this bit is set S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted packets" "0: C-VLAN type (0x8100) is inserted or replaced,1: S-VLAN type (0x88A8) is inserted or replaced" newline bitfld.long 0x0 18. "VLP,VLAN Priority Control When this bit is set the control bits[17:16] are used for VLAN deletion insertion or replacement" "0: VLAN Priority Control is disabled,1: VLAN Priority Control is enabled" newline bitfld.long 0x0 16.--17. "VLC,VLAN Tag Control in Transmit Packets - 2'b00: No VLAN tag deletion insertion or replacement - 2'b01: VLAN tag deletion The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16) of all transmitted packets with VLAN tags" "0: No VLAN tag deletion,1: VLAN tag deletion The MAC removes the VLAN type,2: VLAN tag insertion,3: VLAN tag replacement" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted or replaced" group.long 0x60++0x3 line.long 0x0 "MAC_VLAN_Incl0,The Tx Queue {i} VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from Tx Queue {i}. It also contains the VLAN tag insertion controls." hexmask.long.word 0x0 20.--31. 1. "Reserved_31_20,Reserved." newline bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN When this bit is set S-VLAN type (0x88A8) is inserted in the 13th and 14th bytes of transmitted packets" "0: C-VLAN type (0x8100) is inserted,1: S-VLAN type (0x88A8) is inserted" newline rbitfld.long 0x0 16.--18. "Reserved_18_16,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted" group.long 0x60++0x3 line.long 0x0 "MAC_VLAN_Incl1,The Tx Queue {i} VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from Tx Queue {i}. It also contains the VLAN tag insertion controls." hexmask.long.word 0x0 20.--31. 1. "Reserved_31_20,Reserved." newline bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN When this bit is set S-VLAN type (0x88A8) is inserted in the 13th and 14th bytes of transmitted packets" "0: C-VLAN type (0x8100) is inserted,1: S-VLAN type (0x88A8) is inserted" newline rbitfld.long 0x0 16.--18. "Reserved_18_16,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted" group.long 0x60++0x3 line.long 0x0 "MAC_VLAN_Incl2,The Tx Queue {i} VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from Tx Queue {i}. It also contains the VLAN tag insertion controls." hexmask.long.word 0x0 20.--31. 1. "Reserved_31_20,Reserved." newline bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN When this bit is set S-VLAN type (0x88A8) is inserted in the 13th and 14th bytes of transmitted packets" "0: C-VLAN type (0x8100) is inserted,1: S-VLAN type (0x88A8) is inserted" newline rbitfld.long 0x0 16.--18. "Reserved_18_16,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted" group.long 0x60++0x3 line.long 0x0 "MAC_VLAN_Incl3,The Tx Queue {i} VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from Tx Queue {i}. It also contains the VLAN tag insertion controls." hexmask.long.word 0x0 20.--31. 1. "Reserved_31_20,Reserved." newline bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN When this bit is set S-VLAN type (0x88A8) is inserted in the 13th and 14th bytes of transmitted packets" "0: C-VLAN type (0x8100) is inserted,1: S-VLAN type (0x88A8) is inserted" newline rbitfld.long 0x0 16.--18. "Reserved_18_16,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted" group.long 0x60++0x3 line.long 0x0 "MAC_VLAN_Incl4,The Tx Queue {i} VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from Tx Queue {i}. It also contains the VLAN tag insertion controls." hexmask.long.word 0x0 20.--31. 1. "Reserved_31_20,Reserved." newline bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN When this bit is set S-VLAN type (0x88A8) is inserted in the 13th and 14th bytes of transmitted packets" "0: C-VLAN type (0x8100) is inserted,1: S-VLAN type (0x88A8) is inserted" newline rbitfld.long 0x0 16.--18. "Reserved_18_16,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted" group.long 0x60++0x3 line.long 0x0 "MAC_VLAN_Incl5,The Tx Queue {i} VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from Tx Queue {i}. It also contains the VLAN tag insertion controls." hexmask.long.word 0x0 20.--31. 1. "Reserved_31_20,Reserved." newline bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN When this bit is set S-VLAN type (0x88A8) is inserted in the 13th and 14th bytes of transmitted packets" "0: C-VLAN type (0x8100) is inserted,1: S-VLAN type (0x88A8) is inserted" newline rbitfld.long 0x0 16.--18. "Reserved_18_16,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted" group.long 0x60++0x3 line.long 0x0 "MAC_VLAN_Incl6,The Tx Queue {i} VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from Tx Queue {i}. It also contains the VLAN tag insertion controls." hexmask.long.word 0x0 20.--31. 1. "Reserved_31_20,Reserved." newline bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN When this bit is set S-VLAN type (0x88A8) is inserted in the 13th and 14th bytes of transmitted packets" "0: C-VLAN type (0x8100) is inserted,1: S-VLAN type (0x88A8) is inserted" newline rbitfld.long 0x0 16.--18. "Reserved_18_16,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted" group.long 0x60++0x7 line.long 0x0 "MAC_VLAN_Incl7,The Tx Queue {i} VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from Tx Queue {i}. It also contains the VLAN tag insertion controls." hexmask.long.word 0x0 20.--31. 1. "Reserved_31_20,Reserved." newline bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN When this bit is set S-VLAN type (0x88A8) is inserted in the 13th and 14th bytes of transmitted packets" "0: C-VLAN type (0x8100) is inserted,1: S-VLAN type (0x88A8) is inserted" newline rbitfld.long 0x0 16.--18. "Reserved_18_16,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted" line.long 0x4 "MAC_Inner_VLAN_Incl,The Inner VLAN Tag Inclusion or Replacement register contains the inner VLAN tag to be inserted or replaced in the Transmit packet. It also contains the inner VLAN tag insertion controls." hexmask.long.word 0x4 21.--31. 1. "Reserved_31_21,Reserved." newline bitfld.long 0x4 20. "VLTI,VLAN Tag Input When this bit is set it indicates that the VLAN tag to be inserted or replaced in Tx packet should be taken from: - The Tx descriptor" "0: VLAN Tag Input is disabled,1: VLAN Tag Input is enabled" newline bitfld.long 0x4 19. "CSVL,C-VLAN or S-VLAN When this bit is set S-VLAN type (0x88A8) is inserted or replaced in the 17th and 18th bytes of transmitted packets" "0: C-VLAN type (0x8100) is inserted,1: S-VLAN type (0x88A8) is inserted" newline bitfld.long 0x4 18. "VLP,VLAN Priority Control When this bit is set the VLC field is used for VLAN deletion insertion or replacement" "0: VLAN Priority Control is disabled,1: VLAN Priority Control is enabled" newline bitfld.long 0x4 16.--17. "VLC,VLAN Tag Control in Transmit Packets - 2'b00: No VLAN tag deletion insertion or replacement - 2'b01: VLAN tag deletion The MAC removes the VLAN type (bytes 17 and 18) and VLAN tag (bytes 19 and 20) of all transmitted packets with VLAN tags" "0: No VLAN tag deletion,1: VLAN tag deletion The MAC removes the VLAN type,2: VLAN tag insertion,3: VLAN tag replacement" newline hexmask.long.word 0x4 0.--15. 1. "VLT,VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted or replaced" group.long 0x70++0xB line.long 0x0 "MAC_Q0_Tx_Flow_Ctrl,The Flow Control register controls the generation and reception of the Control (Pause Command) packets by the Flow control module of the MAC. A Write to a register with the Busy bit set to 1 triggers the Flow Control block to generate.." hexmask.long.word 0x0 16.--31. 1. "PT,Pause Time This field holds the value to be used in the Pause Time field in the Tx control packet" newline hexmask.long.byte 0x0 8.--15. 1. "Reserved_15_8,Reserved." newline bitfld.long 0x0 7. "DZPQ,Disable Zero-Quanta Pause When this bit is set it disables the automatic generation of the zero-quanta Pause packets on de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i or.." "0: Zero-Quanta Pause packet generation is enabled,1: Zero-Quanta Pause packet generation is disabled" newline bitfld.long 0x0 4.--6. "PLT,Pause Low Threshold This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause packet" "0: Pause Time minus 4 Slot Times (PT -4 slot times),1: Pause Time minus 28 Slot Times (PT -28 slot times),2: Pause Time minus 36 Slot Times (PT -36 slot times),3: Pause Time minus 144 Slot Times (PT -144 slot..,4: Pause Time minus 256 Slot Times (PT -256 slot..,5: Pause Time minus 512 Slot Times (PT -512 slot..,?,?" newline rbitfld.long 0x0 2.--3. "Reserved_3_2,Reserved." "0,1,2,3" newline bitfld.long 0x0 1. "TFE,Transmit Flow Control Enable Full-Duplex Mode: In the full-duplex mode when this bit is set the MAC enables the flow control operation to Tx Pause packets" "0: Transmit Flow Control is disabled,1: Transmit Flow Control is enabled" newline bitfld.long 0x0 0. "FCB_BPA,Flow Control Busy or Backpressure Activate This bit initiates a Pause packet in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set" "0: Flow Control Busy or Backpressure Activate is..,1: Flow Control Busy or Backpressure Activate is.." line.long 0x4 "MAC_Q1_Tx_Flow_Ctrl,This register controls the generation of PFC Control packets of priorities mapped as per the PSRQi field in the MAC_RxQ_Ctrl2/MAC_RxQ_Ctrl3 registers." hexmask.long.word 0x4 16.--31. 1. "PT,Pause Time This field holds the value to be used in the Pause Time field in the Tx control packet" newline hexmask.long.byte 0x4 8.--15. 1. "Reserved_15_8,Reserved." newline bitfld.long 0x4 7. "DZPQ,Disable Zero-Quanta Pause When this bit is set it disables the automatic generation of the zero-quanta Pause packets on de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i or.." "0: Zero-Quanta Pause packet generation is enabled,1: Zero-Quanta Pause packet generation is disabled" newline bitfld.long 0x4 4.--6. "PLT,Pause Low Threshold This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause packet" "0: Pause Time minus 4 Slot Times (PT -4 slot times),1: Pause Time minus 28 Slot Times (PT -28 slot times),2: Pause Time minus 36 Slot Times (PT -36 slot times),3: Pause Time minus 144 Slot Times (PT -144 slot..,4: Pause Time minus 256 Slot Times (PT -256 slot..,5: Pause Time minus 512 Slot Times (PT -512 slot..,?,?" newline rbitfld.long 0x4 2.--3. "Reserved_3_2,Reserved." "0,1,2,3" newline bitfld.long 0x4 1. "TFE,Transmit Flow Control Enable When this bit is set in full-duplex mode the MAC enables the flow control operation to Tx pause packets" "0: Transmit Flow Control is disabled,1: Transmit Flow Control is enabled" newline bitfld.long 0x4 0. "FCB_BPA,Flow Control Busy This bit initiates a PFC packet if the TFE bit is set" "0: Flow Control Busy or Backpressure Activate is..,1: Flow Control Busy or Backpressure Activate is.." line.long 0x8 "MAC_Q2_Tx_Flow_Ctrl,This register controls the generation of PFC Control packets of priorities mapped as per the PSRQi field in the MAC_RxQ_Ctrl2/MAC_RxQ_Ctrl3 registers." hexmask.long.word 0x8 16.--31. 1. "PT,Pause Time This field holds the value to be used in the Pause Time field in the Tx control packet" newline hexmask.long.byte 0x8 8.--15. 1. "Reserved_15_8,Reserved." newline bitfld.long 0x8 7. "DZPQ,Disable Zero-Quanta Pause When this bit is set it disables the automatic generation of the zero-quanta Pause packets on de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i or.." "0: Zero-Quanta Pause packet generation is enabled,1: Zero-Quanta Pause packet generation is disabled" newline bitfld.long 0x8 4.--6. "PLT,Pause Low Threshold This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause packet" "0: Pause Time minus 4 Slot Times (PT -4 slot times),1: Pause Time minus 28 Slot Times (PT -28 slot times),2: Pause Time minus 36 Slot Times (PT -36 slot times),3: Pause Time minus 144 Slot Times (PT -144 slot..,4: Pause Time minus 256 Slot Times (PT -256 slot..,5: Pause Time minus 512 Slot Times (PT -512 slot..,?,?" newline rbitfld.long 0x8 2.--3. "Reserved_3_2,Reserved." "0,1,2,3" newline bitfld.long 0x8 1. "TFE,Transmit Flow Control Enable When this bit is set in full-duplex mode the MAC enables the flow control operation to Tx pause packets" "0: Transmit Flow Control is disabled,1: Transmit Flow Control is enabled" newline bitfld.long 0x8 0. "FCB_BPA,Flow Control Busy This bit initiates a PFC packet if the TFE bit is set" "0: Flow Control Busy or Backpressure Activate is..,1: Flow Control Busy or Backpressure Activate is.." group.long 0x90++0xB line.long 0x0 "MAC_Rx_Flow_Ctrl,The Receive Flow Control register controls the pausing of MAC Transmit based on the received Pause packet." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_31_9,Reserved." newline bitfld.long 0x0 8. "PFCE,Priority Based Flow Control Enable When this bit is set it enables generation and reception of priority-based flow control (PFC) packets" "0: Priority Based Flow Control is disabled,1: Priority Based Flow Control is enabled" newline hexmask.long.byte 0x0 2.--7. 1. "Reserved_7_2,Reserved." newline bitfld.long 0x0 1. "UP,Unicast Pause Packet Detect A pause packet is processed when it has the unique multicast address specified in the IEEE 802" "0: Unicast Pause Packet Detect disabled,1: Unicast Pause Packet Detect enabled" newline bitfld.long 0x0 0. "RFE,Receive Flow Control Enable When this bit is set and the MAC is operating in full-duplex mode the MAC decodes the received Pause packet and disables its transmitter for a specified (Pause) time" "0: Receive Flow Control is disabled,1: Receive Flow Control is enabled" line.long 0x4 "MAC_RxQ_Ctrl4,The Receive Queue Control 4 register controls the routing of unicast and multicast packets that fail the Destination or Source address filter to the Rx queues." hexmask.long.word 0x4 19.--31. 1. "Reserved_31_y,Reserved." newline bitfld.long 0x4 17.--18. "VFFQ,VLAN Tag Filter Fail Packets Queue This field holds the Rx queue number to which the tagged packets failing the Destination or Source Address filter (and UFFQE/MFFQE not enabled) or failing the VLAN tag filter must be routed to" "0,1,2,3" newline bitfld.long 0x4 16. "VFFQE,VLAN Tag Filter Fail Packets Queuing Enable When this bit is set the tagged packets which fail the Destination or Source address filter or fail the VLAN tag filter are routed to the Rx Queue Number programmed in the VFFQ" "0: VLAN tag Filter Fail Packets Queuing is disabled,1: VLAN tag Filter Fail Packets Queuing is enabled" newline hexmask.long.byte 0x4 11.--15. 1. "Reserved_15_y,Reserved." newline bitfld.long 0x4 9.--10. "MFFQ,Multicast Address Filter Fail Packets Queue" "0,1,2,3" newline bitfld.long 0x4 8. "MFFQE,Multicast Address Filter Fail Packets Queuing Enable" "0: Multicast Address Filter Fail Packets Queuing is..,1: Multicast Address Filter Fail Packets Queuing is.." newline hexmask.long.byte 0x4 3.--7. 1. "Reserved_7_y,Reserved." newline bitfld.long 0x4 1.--2. "UFFQ,Unicast Address Filter Fail Packets Queue" "0,1,2,3" newline bitfld.long 0x4 0. "UFFQE,Unicast Address Filter Fail Packets Queuing Enable" "0: Unicast Address Filter Fail Packets Queuing is..,1: Unicast Address Filter Fail Packets Queuing is.." line.long 0x8 "MAC_TxQ_Prty_Map0,The Transmit Queue Priority Mapping 0 register contains the priority values assigned to Tx Queue 0 through Tx Queue 3." hexmask.long.byte 0x8 24.--31. 1. "Reserved_PSTQ3,Reserved." newline hexmask.long.byte 0x8 16.--23. 1. "PSTQ2,Priorities Selected in Transmit Queue 2 This bit is similar to the PSTQ0 bit." newline hexmask.long.byte 0x8 8.--15. 1. "PSTQ1,Priorities Selected in Transmit Queue 1 This bit is similar to the PSTQ0 bit." newline hexmask.long.byte 0x8 0.--7. 1. "PSTQ0,Priorities Selected in Transmit Queue 0 This field holds the priorities assigned to Tx Queue 0 by the software" group.long 0xA0++0xB line.long 0x0 "MAC_RxQ_Ctrl0,The Receive Queue Control 0 register controls the queue management in the MAC Receiver. Note: In multiple Rx queues configuration. all the queues are disabled by default. Enable the Rx queue by programming the corresponding field in this.." hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved." newline rbitfld.long 0x0 14.--15. "Reserved_RXQ7EN,Reserved." "0,1,2,3" newline rbitfld.long 0x0 12.--13. "Reserved_RXQ6EN,Reserved." "0,1,2,3" newline rbitfld.long 0x0 10.--11. "Reserved_RXQ5EN,Reserved." "0,1,2,3" newline rbitfld.long 0x0 8.--9. "Reserved_RXQ4EN,Reserved." "0,1,2,3" newline rbitfld.long 0x0 6.--7. "Reserved_RXQ3EN,Reserved." "0,1,2,3" newline bitfld.long 0x0 4.--5. "RXQ2EN,Receive Queue 2 Enable This field is similar to the RXQ0EN field." "0: Queue not enabled,1: Queue enabled for AV,2: Queue enabled for DCB/Generic,?" newline bitfld.long 0x0 2.--3. "RXQ1EN,Receive Queue 1 Enable This field is similar to the RXQ0EN field." "0: Queue not enabled,1: Queue enabled for AV,2: Queue enabled for DCB/Generic,?" newline bitfld.long 0x0 0.--1. "RXQ0EN,Receive Queue 0 Enable This field indicates whether Rx Queue 0 is enabled for AV or DCB." "0: Queue not enabled,1: Queue enabled for AV,2: Queue enabled for DCB/Generic,?" line.long 0x4 "MAC_RxQ_Ctrl1,The Receive Queue Control 1 register controls the routing of multicast. broadcast. AV. DCB. and untagged packets to the Rx queues." rbitfld.long 0x4 30.--31. "Reserved_31_30,Reserved." "0,1,2,3" newline bitfld.long 0x4 29. "TBRQE,Type Field Based Rx Queuing Enable When this bit is set it enables Type Field based Rx Queuing where the Type field of received packet is compared with programmed TYP field in MAC_TMRQ_Regs(#i) and if a match occurs the packet is routed to the.." "0,1" newline bitfld.long 0x4 28. "OMCBCQ,Over-riding MC-BC queue priority select - 1: Priority of MCBCQ is reduced and the received packet is first routed to PTPQ AVCPQ DCBCPQ depending on packet type" "0: overriding MCBCQ priority disabled,1: Priority of MCBCQ is reduced and the received.." newline rbitfld.long 0x4 27. "Reserved_27,Reserved." "0,1" newline bitfld.long 0x4 24.--26. "FPRQ,Frame Preemption Residue Queue This field holds the Rx queue number to which the residual preemption frames must be forwarded" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 22.--23. "TPQC,Tagged PTP over Ethernet Packets Queuing Control" "0,1,2,3" newline bitfld.long 0x4 21. "TACPQE,Tagged AV Control Packets Queuing Enable" "0: Tagged AV Control Packets Queuing is disabled,1: Tagged AV Control Packets Queuing is enabled" newline bitfld.long 0x4 20. "MCBCQEN,Multicast and Broadcast Queue Enable This bit specifies that Multicast or Broadcast packets routing to the Rx Queue is enabled and the Multicast or Broadcast packets must be routed to Rx Queue specified in MCBCQ field" "0: Multicast and Broadcast Queue is disabled,1: Multicast and Broadcast Queue is enabled" newline rbitfld.long 0x4 19. "Reserved_19,Reserved." "0,1" newline bitfld.long 0x4 16.--18. "MCBCQ,Multicast and Broadcast Queue This field specifies the Rx Queue onto which Multicast or Broadcast Packets are routed" "0: Receive Queue 0,1: Receive Queue 1,2: Receive Queue 2,3: Receive Queue 3,4: Receive Queue 4,5: Receive Queue 5,6: Receive Queue 6,7: Receive Queue 7" newline rbitfld.long 0x4 15. "Reserved_15,Reserved." "0,1" newline bitfld.long 0x4 12.--14. "UPQ,Untagged Packet Queue This field indicates the Rx Queue to which Untagged Packets are to be routed" "0: Receive Queue 0,1: Receive Queue 1,2: Receive Queue 2,3: Receive Queue 3,4: Receive Queue 4,5: Receive Queue 5,6: Receive Queue 6,7: Receive Queue 7" newline rbitfld.long 0x4 11. "Reserved_11,Reserved." "0,1" newline bitfld.long 0x4 8.--10. "DCBCPQ,DCB Control Packets Queue This field specifies the Rx queue on which the received DCB control packets are routed" "0: Receive Queue 0,1: Receive Queue 1,2: Receive Queue 2,3: Receive Queue 3,4: Receive Queue 4,5: Receive Queue 5,6: Receive Queue 6,7: Receive Queue 7" newline rbitfld.long 0x4 7. "Reserved_7,Reserved." "0,1" newline bitfld.long 0x4 4.--6. "PTPQ,PTP Packets Queue This field specifies the Rx queue on which the PTP packets sent over the Ethernet payload (not over IPv4 or IPv6) are routed" "0: Receive Queue 0,1: Receive Queue 1,2: Receive Queue 2,3: Receive Queue 3,4: Receive Queue 4,5: Receive Queue 5,6: Receive Queue 6,7: Receive Queue 7" newline rbitfld.long 0x4 3. "Reserved_3,Reserved." "0,1" newline bitfld.long 0x4 0.--2. "AVCPQ,AV Untagged Control Packets Queue This field specifies the Receive queue on which the received AV tagged and untagged control packets are routed" "0: Receive Queue 0,1: Receive Queue 1,2: Receive Queue 2,3: Receive Queue 3,4: Receive Queue 4,5: Receive Queue 5,6: Receive Queue 6,7: Receive Queue 7" line.long 0x8 "MAC_RxQ_Ctrl2,This register controls the routing of tagged packets based on the USP (user Priority) field of the received packets to the RxQueues 0 to 3." hexmask.long.byte 0x8 24.--31. 1. "Reserved_PSRQ3,Reserved." newline hexmask.long.byte 0x8 16.--23. 1. "PSRQ2,Priorities Selected in the Receive Queue 2 This field decides the priorities assigned to Rx Queue 2" newline hexmask.long.byte 0x8 8.--15. 1. "PSRQ1,Priorities Selected in the Receive Queue 1 This field decides the priorities assigned to Rx Queue 1" newline hexmask.long.byte 0x8 0.--7. 1. "PSRQ0,Priorities Selected in the Receive Queue 0 This field decides the priorities assigned to Rx Queue 0" rgroup.long 0xB0++0x3 line.long 0x0 "MAC_Interrupt_Status,The Interrupt Status register contains the status of interrupts." hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved." newline bitfld.long 0x0 20. "MFRIS,MMC FPE Receive Interrupt Status This bit is set high when an interrupt is generated in the MMC FPE Receive Interrupt Register" "0: MMC FPE Receive Interrupt status not active,1: MMC FPE Receive Interrupt status active" newline bitfld.long 0x0 19. "MFTIS,MMC FPE Transmit Interrupt Status This bit is set high when an interrupt is generated in the MMC FPE Transmit Interrupt Register" "0: MMC FPE Transmit Interrupt status not active,1: MMC FPE Transmit Interrupt status active" newline bitfld.long 0x0 18. "MDIOIS,MDIO Interrupt Status This bit indicates an interrupt event after the completion of MDIO operation" "0: MDIO Interrupt status not active,1: MDIO Interrupt status active" newline bitfld.long 0x0 17. "FPEIS,Frame Preemption Interrupt Status This bit indicates an interrupt event during the operation of Frame Preemption (Bits[19:16] of MAC_FPE_CTRL_STS register is set)" "0: Frame Preemption Interrupt status not active,1: Frame Preemption Interrupt status active" newline bitfld.long 0x0 16. "Reserved_16,Reserved." "0,1" newline bitfld.long 0x0 15. "Reserved_GPIIS,Reserved." "0,1" newline bitfld.long 0x0 14. "RXSTSIS,Receive Status Interrupt This bit indicates the status of received packets" "0: Receive Interrupt status not active,1: Receive Interrupt status active" newline bitfld.long 0x0 13. "TXSTSIS,Transmit Status Interrupt This bit indicates the status of transmitted packets" "0: Transmit Interrupt status not active,1: Transmit Interrupt status active" newline bitfld.long 0x0 12. "TSIS,Timestamp Interrupt Status If the Timestamp feature is enabled this bit is set when any of the following conditions is true: - The system time value is equal to or exceeds the value specified in the Target Time High and Low registers" "0: Timestamp Interrupt status not active,1: Timestamp Interrupt status active" newline bitfld.long 0x0 11. "Reserved_MMCRXIPIS,Reserved." "0,1" newline bitfld.long 0x0 10. "MMCTXIS,MMC Transmit Interrupt Status This bit is set high when an interrupt is generated in the MMC Transmit Interrupt Register" "0: MMC Transmit Interrupt status not active,1: MMC Transmit Interrupt status active" newline bitfld.long 0x0 9. "MMCRXIS,MMC Receive Interrupt Status This bit is set high when an interrupt is generated in the MMC Receive Interrupt Register" "0: MMC Receive Interrupt status not active,1: MMC Receive Interrupt status active" newline bitfld.long 0x0 8. "MMCIS,MMC Interrupt Status This bit is set high when Bit 11 Bit 10 or Bit 9 is set high" "0: MMC Interrupt status not active,1: MMC Interrupt status active" newline bitfld.long 0x0 6.--7. "Reserved_7_6,Reserved." "0,1,2,3" newline bitfld.long 0x0 5. "Reserved_LPIIS,Reserved." "0,1" newline bitfld.long 0x0 4. "Reserved_PMTIS,Reserved." "0,1" newline bitfld.long 0x0 3. "PHYIS,PHY Interrupt This bit is set when rising edge is detected on the phy_intr_i input" "0: PHY Interrupt not detected,1: PHY Interrupt detected" newline bitfld.long 0x0 2. "Reserved_PCSANCIS,Reserved." "0,1" newline bitfld.long 0x0 1. "Reserved_PCSLCHGIS,Reserved." "0,1" newline bitfld.long 0x0 0. "RGSMIIIS,RGMII or SMII Interrupt Status This bit is set because of any change in value of the Link Status of RGMII or SMII interface (LNKSTS bit in MAC_PHYIF_Control_Status register)" "0: RGMII or SMII Interrupt Status is not active,1: RGMII or SMII Interrupt Status is active" group.long 0xB4++0x3 line.long 0x0 "MAC_Interrupt_Enable,The Interrupt Enable register contains the masks for generating the interrupts." hexmask.long.word 0x0 19.--31. 1. "Reserved_31_19,Reserved." newline bitfld.long 0x0 18. "MDIOIE,MDIO Interrupt Enable When this bit is set it enables the assertion of the interrupt when MDIOIS field is set in the MAC_Interrupt_Status register" "0: MDIO Interrupt is disabled,1: MDIO Interrupt is enabled" newline bitfld.long 0x0 17. "FPEIE,Frame Preemption Interrupt Enable When this bit is set it enables the assertion of the interrupt when FPEIS field is set in the MAC_Interrupt_Status register" "0: Frame Preemption Interrupt is disabled,1: Frame Preemption Interrupt is enabled" newline rbitfld.long 0x0 16. "Reserved_16,Reserved." "0,1" newline rbitfld.long 0x0 15. "Reserved_15,Reserved." "0,1" newline bitfld.long 0x0 14. "RXSTSIE,Receive Status Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of RXSTSIS bit in the MAC_Interrupt_Status register" "0: Receive Status Interrupt is disabled,1: Receive Status Interrupt is enabled" newline bitfld.long 0x0 13. "TXSTSIE,Transmit Status Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of TXSTSIS bit in the MAC_Interrupt_Status register" "0: Timestamp Status Interrupt is disabled,1: Timestamp Status Interrupt is enabled" newline bitfld.long 0x0 12. "TSIE,Timestamp Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of TSIS bit in MAC_Interrupt_Status register" "0: Timestamp Interrupt is disabled,1: Timestamp Interrupt is enabled" newline hexmask.long.byte 0x0 6.--11. 1. "Reserved_11_6,Reserved." newline rbitfld.long 0x0 5. "Reserved_LPIIE,Reserved." "0,1" newline rbitfld.long 0x0 4. "Reserved_PMTIE,Reserved." "0,1" newline bitfld.long 0x0 3. "PHYIE,PHY Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of PHYIS bit in MAC_Interrupt_Status register" "0: PHY Interrupt is disabled,1: PHY Interrupt is enabled" newline rbitfld.long 0x0 2. "Reserved_PCSANCIE,Reserved." "0,1" newline rbitfld.long 0x0 1. "Reserved_PCSLCHGIE,Reserved." "0,1" newline bitfld.long 0x0 0. "RGSMIIIE,RGMII or SMII Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of RGSMIIIS bit in MAC_Interrupt_Status register" "0: RGMII or SMII Interrupt is disabled,1: RGMII or SMII Interrupt is enabled" rgroup.long 0xB8++0x3 line.long 0x0 "MAC_Rx_Tx_Status,The Receive Transmit Status register contains the Receive and Transmit Error status." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_31_9,Reserved." newline bitfld.long 0x0 8. "RWT,Receive Watchdog Timeout This bit is set when a packet with length greater than 2 048 bytes is received (10 240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the MAC_Configuration register" "0: No receive watchdog timeout,1: Receive watchdog timed out" newline bitfld.long 0x0 6.--7. "Reserved_7_6,Reserved." "0,1,2,3" newline bitfld.long 0x0 5. "EXCOL,Excessive Collisions When the DTXSTS bit is set in the MTL_Operation_Mode register this bit indicates that the transmission aborted after 16 successive collisions while attempting to transmit the current packet" "0: No collision,1: Excessive collision is sensed" newline bitfld.long 0x0 4. "LCOL,Late Collision When the DTXSTS bit is set in the MTL_Operation_Mode register this bit indicates that the packet transmission aborted because a collision occurred after the collision window (64 bytes including Preamble in MII mode; 512 bytes.." "0: No collision,1: Late collision is sensed" newline bitfld.long 0x0 3. "EXDEF,Excessive Deferral When the DTXSTS bit is set in the MTL_Operation_Mode register and the DC bit is set in the MAC_Configuration register this bit indicates that the transmission ended because of excessive deferral of over 24 288 bit times (155 680.." "0: No Excessive deferral,1: Excessive deferral" newline bitfld.long 0x0 2. "LCARR,Loss of Carrier When the DTXSTS bit is set in the MTL_Operation_Mode register this bit indicates that the loss of carrier occurred during packet transmission that is the phy_crs_i signal was inactive for one or more transmission clock periods.." "0: Carrier is present,1: Loss of carrier" newline bitfld.long 0x0 1. "NCARR,No Carrier When the DTXSTS bit is set in the MTL_Operation_Mode register this bit indicates that the carrier signal from the PHY is not present at the end of preamble transmission" "0: Carrier is present,1: No carrier" newline bitfld.long 0x0 0. "TJT,Transmit Jabber Timeout This bit indicates that the Transmit Jabber Timer expired which happens when the packet size exceeds 2 048 bytes (10 240 bytes when the Jumbo packet is enabled) and JD bit is reset in the MAC_Configuration register" "0: No Transmit Jabber Timeout,1: Transmit Jabber Timeout occurred" group.long 0xF8++0x3 line.long 0x0 "MAC_PHYIF_Control_Status,The PHY Interface Control and Status register indicates the status signals received by the SGMII. RGMII. or SMII interface (selected at reset) from the PHY. This register is optional." hexmask.long.word 0x0 22.--31. 1. "Reserved_31_22,Reserved." newline rbitfld.long 0x0 21. "Reserved_FALSCARDET,Reserved." "0,1" newline rbitfld.long 0x0 20. "Reserved_JABTO,Reserved." "0,1" newline rbitfld.long 0x0 19. "LNKSTS,Link Status This bit indicates whether the link is up (1'b1) or down (1'b0)." "0: Link down,1: Link up" newline rbitfld.long 0x0 17.--18. "LNKSPEED,Link Speed This bit indicates the current speed of the link." "0: 2.5 MHz,1: 25 MHz,2: 125 MHz,?" newline rbitfld.long 0x0 16. "LNKMOD,Link Mode This bit indicates the current mode of operation of the link." "0: Half-duplex mode,1: Full-duplex mode" newline hexmask.long.word 0x0 5.--15. 1. "Reserved_15_5,Reserved." newline rbitfld.long 0x0 4. "Reserved_SMIDRXS,Reserved." "0,1" newline rbitfld.long 0x0 3. "Reserved_3,Reserved." "0,1" newline rbitfld.long 0x0 2. "Reserved_SFTERR,Reserved." "0,1" newline bitfld.long 0x0 1. "LUD,Link Up or Down This bit indicates whether the link is up or down during transmission of configuration in the RGMII SGMII or SMII interface" "0: Link down,1: Link up" newline bitfld.long 0x0 0. "TC,Transmit Configuration in RGMII SGMII or SMII When set this bit enables the transmission of duplex mode link speed and link up or down information to the PHY in the RGMII SMII or SGMII port" "0: Disable Transmit Configuration in RGMII SGMII or..,1: Enable Transmit Configuration in RGMII SGMII or.." rgroup.long 0x110++0x7 line.long 0x0 "MAC_Version,Identifies the version of the module." hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved." newline hexmask.long.byte 0x0 8.--15. 1. "USERVER,User-defined Version (configured with coreConsultant)" newline hexmask.long.byte 0x0 0.--7. 1. "IPVER,IP version" line.long 0x4 "MAC_Debug,The Debug register provides the debug status of various MAC blocks." hexmask.long.word 0x4 19.--31. 1. "Reserved_31_19,Reserved." newline bitfld.long 0x4 17.--18. "TFCSTS,MAC Transmit Packet Controller Status This field indicates the state of the MAC Transmit Packet Controller module" "0: Idle state,1: Waiting for one of the following: Status of the..,2: Generating and transmitting a Pause control..,3: Transferring input packet for transmission" newline bitfld.long 0x4 16. "TPESTS,MAC GMII or MII Transmit Protocol Engine Status When this bit is set it indicates that the MAC GMII or MII transmit protocol engine is actively transmitting data and it is not in the Idle state" "0: MAC GMII or MII Transmit Protocol Engine Status..,1: MAC GMII or MII Transmit Protocol Engine Status.." newline hexmask.long.word 0x4 3.--15. 1. "Reserved_15_3,Reserved." newline bitfld.long 0x4 1.--2. "RFCFCSTS,MAC Receive Packet Controller FIFO Status When this bit is set this field indicates the active state of the small FIFO Read and Write controllers of the MAC Receive Packet Controller module" "0,1,2,3" newline bitfld.long 0x4 0. "RPESTS,MAC GMII or MII Receive Protocol Engine Status When this bit is set it indicates that the MAC GMII or MII receive protocol engine is actively receiving data and it is not in the Idle state" "0: MAC GMII or MII Receive Protocol Engine Status..,1: MAC GMII or MII Receive Protocol Engine Status.." rgroup.long 0x11C++0xF line.long 0x0 "MAC_HW_Feature0,This register indicates the presence of first set of the optional features or functions of the DWC_ether_qos. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks. Note:.." bitfld.long 0x0 31. "Reserved_31,Reserved." "0,1" newline bitfld.long 0x0 28.--30. "ACTPHYSEL,Active PHY Selected When you have multiple PHY interfaces in your configuration this field indicates the sampled value of phy_intf_sel_i during reset de-assertion" "0: GMII or MII,1: RGMII,2: SGMII,3: TBI,4: RMII,5: RTBI,6: SMII,7: RevMII" newline bitfld.long 0x0 27. "SAVLANINS,Source Address or VLAN Insertion Enable This bit is set to 1 when the Enable SA and VLAN Insertion on Tx option is selected" "0: Source Address or VLAN Insertion Enable option..,1: Source Address or VLAN Insertion Enable option.." newline bitfld.long 0x0 25.--26. "TSSTSSEL,Timestamp System Time Source This bit indicates the source of the Timestamp system time: This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected" "0: Internal,1: External,2: Both,?" newline bitfld.long 0x0 24. "MACADR64SEL,MAC Addresses 64-127 Selected This bit is set to 1 when the Enable Additional 64 MAC Address Registers (64-127) option is selected" "0: MAC Addresses 64-127 Select option is not selected,1: MAC Addresses 64-127 Select option is selected" newline bitfld.long 0x0 23. "MACADR32SEL,MAC Addresses 32-63 Selected This bit is set to 1 when the Enable Additional 32 MAC Address Registers (32-63) option is selected" "0: MAC Addresses 32-63 Select option is not selected,1: MAC Addresses 32-63 Select option is selected" newline hexmask.long.byte 0x0 18.--22. 1. "ADDMACADRSEL,MAC Addresses 1-31 Selected This bit is set to 1 when the non-zero value is selected for Enable Additional 1-31 MAC Address Registers option" newline bitfld.long 0x0 17. "Reserved_17,Reserved." "0,1" newline bitfld.long 0x0 16. "RXCOESEL,Receive Checksum Offload Enabled This bit is set to 1 when the Enable Receive TCP/IP Checksum Check option is selected" "0: Receive Checksum Offload Enable option is not..,1: Receive Checksum Offload Enable option is selected" newline bitfld.long 0x0 15. "Reserved_15,Reserved." "0,1" newline bitfld.long 0x0 14. "TXCOESEL,Transmit Checksum Offload Enabled This bit is set to 1 when the Enable Transmit TCP/IP Checksum Insertion option is selected" "0: Transmit Checksum Offload Enable option is not..,1: Transmit Checksum Offload Enable option is.." newline bitfld.long 0x0 13. "EEESEL,Energy Efficient Ethernet Enabled This bit is set to 1 when the Enable Energy Efficient Ethernet (EEE) option is selected" "0: Energy Efficient Ethernet Enable option is not..,1: Energy Efficient Ethernet Enable option is.." newline bitfld.long 0x0 12. "TSSEL,IEEE 1588-2008 Timestamp Enabled This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected" "0: IEEE 1588-2008 Timestamp Enable option is not..,1: IEEE 1588-2008 Timestamp Enable option is selected" newline bitfld.long 0x0 10.--11. "Reserved_11_10,Reserved." "0,1,2,3" newline bitfld.long 0x0 9. "ARPOFFSEL,ARP Offload Enabled This bit is set to 1 when the Enable IPv4 ARP Offload option is selected" "0: ARP Offload Enable option is not selected,1: ARP Offload Enable option is selected" newline bitfld.long 0x0 8. "MMCSEL,RMON Module Enable This bit is set to 1 when the Enable MAC Management Counters (MMC) option is selected" "0: RMON Module Enable option is not selected,1: RMON Module Enable option is selected" newline bitfld.long 0x0 7. "MGKSEL,PMT Magic Packet Enable This bit is set to 1 when the Enable Magic Packet Detection option is selected" "0: PMT Magic Packet Enable option is not selected,1: PMT Magic Packet Enable option is selected" newline bitfld.long 0x0 6. "RWKSEL,PMT Remote Wake-up Packet Enable This bit is set to 1 when the Enable Remote Wake-Up Packet Detection option is selected" "0: PMT Remote Wake-up Packet Enable option is not..,1: PMT Remote Wake-up Packet Enable option is.." newline bitfld.long 0x0 5. "SMASEL,SMA (MDIO) Interface This bit is set to 1 when the Enable Station Management (MDIO Interface) option is selected" "0: SMA (MDIO) Interface not selected,1: SMA (MDIO) Interface selected" newline bitfld.long 0x0 4. "VLHASH,VLAN Hash Filter Selected This bit is set to 1 when the Enable VLAN Hash Table Based Filtering option is selected" "0: VLAN Hash Filter not selected,1: VLAN Hash Filter selected" newline bitfld.long 0x0 3. "PCSSEL,PCS Registers (TBI SGMII or RTBI PHY interface) This bit is set to 1 when the TBI SGMII or RTBI PHY interface option is selected" "0: No PCS Registers (TBI SGMII or RTBI PHY interface),1: PCS Registers (TBI SGMII or RTBI PHY interface)" newline bitfld.long 0x0 2. "HDSEL,Half-duplex Support This bit is set to 1 when the half-duplex mode is selected" "0: No Half-duplex support,1: Half-duplex support" newline bitfld.long 0x0 1. "GMIISEL,1000 Mbps Support This bit is set to 1 when 1000 Mbps is selected as the Mode of Operation" "0: No 1000 Mbps support,1: 1000 Mbps support" newline bitfld.long 0x0 0. "MIISEL,10 or 100 Mbps Support This bit is set to 1 when 10/100 Mbps is selected as the Mode of Operation" "0: No 10 or 100 Mbps support,1: 10 or 100 Mbps support" line.long 0x4 "MAC_HW_Feature1,This register indicates the presence of second set of the optional features or functions of the DWC_ether_qos. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks. Note:.." bitfld.long 0x4 31. "Reserved_31,Reserved." "0,1" newline hexmask.long.byte 0x4 27.--30. 1. "L3L4FNUM,Total number of L3 or L4 Filters This field indicates the total number of L3 or L4 filters:" newline bitfld.long 0x4 26. "Reserved_26,Reserved." "0,1" newline bitfld.long 0x4 24.--25. "HASHTBLSZ,Hash Table Size This field indicates the size of the hash table:" "0: No hash table,1: 64,2: 128,3: 256" newline bitfld.long 0x4 23. "POUOST,One Step for PTP over UDP/IP Feature Enable This bit is set to 1 when the Enable One step timestamp for PTP over UDP/IP feature is selected" "0: One Step for PTP over UDP/IP Feature is not..,1: One Step for PTP over UDP/IP Feature is selected" newline bitfld.long 0x4 22. "Reserved_22,Reserved." "0,1" newline bitfld.long 0x4 21. "RAVSEL,Rx Side Only AV Feature Enable This bit is set to 1 when the Enable Audio Video Bridging option on Rx Side Only is selected" "0: Rx Side Only AV Feature is not selected,1: Rx Side Only AV Feature is selected" newline bitfld.long 0x4 20. "AVSEL,AV Feature Enable This bit is set to 1 when the Enable Audio Video Bridging option is selected." "0: AV Feature is not selected,1: AV Feature is selected" newline bitfld.long 0x4 19. "DBGMEMA,DMA Debug Registers Enable This bit is set to 1 when the Debug Mode Enable option is selected" "0: DMA Debug Registers option is not selected,1: DMA Debug Registers option is selected" newline bitfld.long 0x4 18. "TSOEN,TCP Segmentation Offload Enable This bit is set to 1 when the Enable TCP Segmentation Offloading for TCP/IP Packets option is selected" "0: TCP Segmentation Offload Feature is not selected,1: TCP Segmentation Offload Feature is selected" newline bitfld.long 0x4 17. "SPHEN,Split Header Feature Enable This bit is set to 1 when the Enable Split Header Structure option is selected" "0: Split Header Feature is not selected,1: Split Header Feature is selected" newline bitfld.long 0x4 16. "DCBEN,DCB Feature Enable This bit is set to 1 when the Enable Data Center Bridging option is selected" "0: DCB Feature is not selected,1: DCB Feature is selected" newline bitfld.long 0x4 14.--15. "ADDR64,Address Width. This field indicates the configured address width:" "0: 32,1: 40,2: 48,?" newline bitfld.long 0x4 13. "ADVTHWORD,IEEE 1588 High Word Register Enable This bit is set to 1 when the Add IEEE 1588 Higher Word Register option is selected" "0: IEEE 1588 High Word Register option is not..,1: IEEE 1588 High Word Register option is selected" newline bitfld.long 0x4 12. "PTOEN,PTP Offload Enable This bit is set to 1 when the Enable PTP Timestamp Offload Feature is selected." "0: PTP Offload feature is not selected,1: PTP Offload feature is selected" newline bitfld.long 0x4 11. "OSTEN,One-Step Timestamping Enable This bit is set to 1 when the Enable One-Step Timestamp Feature is selected" "0: One-Step Timestamping feature is not selected,1: One-Step Timestamping feature is selected" newline hexmask.long.byte 0x4 6.--10. 1. "TXFIFOSIZE,MTL Transmit FIFO Size This field contains the configured value of MTL Tx FIFO in bytes expressed as Log to base 2 minus 7 that is Log2(TXFIFO_SIZE) -7:" newline bitfld.long 0x4 5. "SPRAM,Single Port RAM Enable This bit is set to 1 when the Use single port RAM Feature is selected." "0: Single Port RAM feature is not selected,1: Single Port RAM feature is selected" newline hexmask.long.byte 0x4 0.--4. 1. "RXFIFOSIZE,MTL Receive FIFO Size This field contains the configured value of MTL Rx FIFO in bytes expressed as Log to base 2 minus 7 that is Log2(RXFIFO_SIZE) -7:" line.long 0x8 "MAC_HW_Feature2,This register indicates the presence of third set of the optional features or functions of the DWC_ether_qos. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks." bitfld.long 0x8 31. "Reserved_31,Reserved." "0,1" newline bitfld.long 0x8 28.--30. "AUXSNAPNUM,Number of Auxiliary Snapshot Inputs This field indicates the number of auxiliary snapshot inputs:" "0: No auxiliary input,1: 1 auxiliary input,2: 2 auxiliary input,3: 3 auxiliary input,4: 4 auxiliary input,?,?,?" newline bitfld.long 0x8 27. "Reserved_27,Reserved." "0,1" newline bitfld.long 0x8 24.--26. "PPSOUTNUM,Number of PPS Outputs This field indicates the number of PPS outputs:" "0: No PPS output,1: 1 PPS output,2: 2 PPS output,3: 3 PPS output,4: 4 PPS output,?,?,?" newline bitfld.long 0x8 22.--23. "TDCSZ,Tx DMA Descriptor Cache Size in terms of 16 bytes descriptors: 00 - Cache Not configured 01 - 4 16 bytes descriptor 10 - 8 16 bytes descriptor 11 - 16 16 bytes descriptor" "0: Cache Not configured 01,?,?,?" newline hexmask.long.byte 0x8 18.--21. 1. "TXCHCNT,Number of DMA Transmit Channels This field indicates the number of DMA Transmit channels:" newline bitfld.long 0x8 16.--17. "RDCSZ,Rx DMA Descriptor Cache Size in terms of 16 bytes descriptors: 00 - Cache Not configured 01 - 4 16 bytes descriptor 10 - 8 16 bytes descriptor 11 - 16 16 bytes descriptor" "0: Cache Not configured 01,?,?,?" newline hexmask.long.byte 0x8 12.--15. 1. "RXCHCNT,Number of DMA Receive Channels This field indicates the number of DMA Receive channels:" newline bitfld.long 0x8 10.--11. "Reserved_11_10,Reserved." "0,1,2,3" newline hexmask.long.byte 0x8 6.--9. 1. "TXQCNT,Number of MTL Transmit Queues This field indicates the number of MTL Transmit queues:" newline bitfld.long 0x8 4.--5. "Reserved_5_4,Reserved." "0,1,2,3" newline hexmask.long.byte 0x8 0.--3. 1. "RXQCNT,Number of MTL Receive Queues This field indicates the number of MTL Receive queues:" line.long 0xC "MAC_HW_Feature3,This register indicates the presence of fourth set the optional features or functions of the DWC_ether_qos. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks." bitfld.long 0xC 30.--31. "Reserved_31_30,Reserved." "0,1,2,3" newline bitfld.long 0xC 28.--29. "ASP,Automotive Safety Package Following are the encoding for the different Safety features" "0: No Safety features selected,1: Only 'ECC protection for external memory'..,2: All the Automotive Safety features are selected..,3: All the Automotive Safety features are selected.." newline bitfld.long 0xC 27. "TBSSEL,Time Based Scheduling Enable This bit is set to 1 when the Time Based Scheduling feature is selected" "0: Time Based Scheduling Enable feature is not..,1: Time Based Scheduling Enable feature is selected" newline bitfld.long 0xC 26. "FPESEL,Frame Preemption Enable This bit is set to 1 when the Enable Frame preemption feature is selected." "0: Frame Preemption Enable feature is not selected,1: Frame Preemption Enable feature is selected" newline hexmask.long.byte 0xC 22.--25. 1. "Reserved_25_22,Reserved." newline bitfld.long 0xC 20.--21. "ESTWID,Width of the Time Interval field in the Gate Control List This field indicates the width of the Configured Time Interval Field" "0: Width not configured,1: 16,2: 20,3: 24" newline bitfld.long 0xC 17.--19. "ESTDEP,Depth of the Gate Control List This field indicates the depth of Gate Control list expressed as Log2(DWC_EQOS_EST_DEP)-5" "0: No Depth configured,1: 64,2: 128,3: 256,4: 512,5: 1024,?,?" newline bitfld.long 0xC 16. "ESTSEL,Enhancements to Scheduled Traffic Enable This bit is set to 1 when the Enable Enhancements to Scheduling Traffic feature is selected" "0: Enable Enhancements to Scheduling Traffic..,1: Enable Enhancements to Scheduling Traffic.." newline bitfld.long 0xC 15. "Reserved_15,Reserved." "0,1" newline bitfld.long 0xC 13.--14. "FRPES,Flexible Receive Parser Table Entries size This field indicates the Max Number of Parser Entries supported by Flexible Receive Parser" "0: 64 Entries,1: 128 Entries,2: 256 Entries,?" newline bitfld.long 0xC 11.--12. "FRPBS,Flexible Receive Parser Buffer size This field indicates the supported Max Number of bytes of the packet data to be Parsed by Flexible Receive Parser" "0: 64 Bytes,1: 128 Bytes,2: 256 Bytes,?" newline bitfld.long 0xC 10. "FRPSEL,Flexible Receive Parser Selected This bit is set to 1 when the Enable Flexible Programmable Receive Parser option is selected" "0: Flexible Receive Parser feature is not selected,1: Flexible Receive Parser feature is selected" newline bitfld.long 0xC 9. "PDUPSEL,Broadcast/Multicast Packet Duplication This bit is set to 1 when the Broadcast/Multicast Packet Duplication feature is selected" "0: Broadcast/Multicast Packet Duplication feature..,1: Broadcast/Multicast Packet Duplication feature.." newline bitfld.long 0xC 6.--8. "Reserved_7_6,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 5. "DVLAN,Double VLAN Tag Processing Selected This bit is set to 1 when the Enable Double VLAN Processing Feature is selected" "0: Double VLAN option is not selected,1: Double VLAN option is selected" newline bitfld.long 0xC 4. "CBTISEL,Queue/Channel based VLAN tag insertion on Tx Enable This bit is set to 1 when the Enable Queue/Channel based VLAN tag insertion on Tx Feature is selected" "0: Enable Queue/Channel based VLAN tag insertion on..,1: Enable Queue/Channel based VLAN tag insertion on.." newline bitfld.long 0xC 3. "Reserved_3,Reserved." "0,1" newline bitfld.long 0xC 0.--2. "NRVF,Number of Extended VLAN Tag Filters Enabled This field indicates the Number of Extended VLAN Tag Filters selected:" "0: No Extended Rx VLAN Filters,1: 4 Extended Rx VLAN Filters,2: 8 Extended Rx VLAN Filters,3: 16 Extended Rx VLAN Filters,4: 24 Extended Rx VLAN Filters,5: 32 Extended Rx VLAN Filters,?,?" group.long 0x140++0x3 line.long 0x0 "MAC_DPP_FSM_Interrupt_Status,This register contains the status of Automotive Safety related Data Path Parity Errors. Interface Timeout Errors. FSM State Parity Errors and FSM State Timeout Errors. All the non-Reserved bits are cleared on read." rbitfld.long 0x0 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 28. "Reserved_DCPES,Reserved." "0,1" newline bitfld.long 0x0 27. "MRWCPES,MTL RWC data path Parity checker Error Status This filed when set indicates that parity error is detected on the MTL RWC data interface (or at PC12 as shown in Recieve data path parity protection diagram)" "0: MTL RWC data path Parity checker Error Status..,1: MTL RWC data path Parity checker Error Status.." newline bitfld.long 0x0 26. "MTFCPES,MAC TFC data path Parity checker Error Status This filed when set indicates that parity error is detected on the MAC TFC data interface (or at PC11 as shown in Transmit data path parity protection diagram)" "0: MAC TFC data path Parity checker Error Status..,1: MAC TFC data path Parity checker Error Status.." newline bitfld.long 0x0 25. "MTBUPES,MAC TBU data path Parity checker Error Status This filed when set indicates that parity error is detected on the MAC TBU data interface (or at PC10 as shown in Transmit data path parity protection diagram)" "0: MAC TBU data path Parity checker Error Status..,1: MAC TBU data path Parity checker Error Status.." newline bitfld.long 0x0 24. "FSMPES,FSM State Parity Error Status This field when set indicates one of the FSMs State registers has a parity error detected" "0: FSM State Parity Error Status not detected,1: FSM State Parity Error Status detected" newline hexmask.long.byte 0x0 18.--23. 1. "Reserved_23_18,Reserved." newline rbitfld.long 0x0 17. "Reserved_SLVTES,Reserved." "0,1" newline bitfld.long 0x0 16. "MSTTES,Master Read/Write Timeout Error Status This field when set indicates that an Application/CSR Timeout has occurred on the master (AXI/AHB/ARI/ATI) interface" "0: Master Read/Write Timeout Error Status not..,1: Master Read/Write Timeout Error Status detected" newline rbitfld.long 0x0 15. "Reserved_RVCTES,Reserved." "0,1" newline rbitfld.long 0x0 14. "Reserved_R125ES,Reserved." "0,1" newline rbitfld.long 0x0 13. "Reserved_T125ES,Reserved." "0,1" newline bitfld.long 0x0 12. "PTES,PTP FSM Timeout Error Status This field when set indicates that one of the PTP FSM Timeout has occurred" "0: PTP FSM Timeout Error Status not detected,1: PTP FSM Timeout Error Status detected" newline bitfld.long 0x0 11. "ATES,APP FSM Timeout Error Status This field when set indicates that one of the APP FSM Timeout has occurred" "0: APP FSM Timeout Error Status not detected,1: APP FSM Timeout Error Status detected" newline rbitfld.long 0x0 10. "Reserved_CTES,Reserved." "0,1" newline bitfld.long 0x0 9. "RTES,Rx FSM Timeout Error Status This field when set indicates that one of the Rx FSM Timeout has occurred" "0: Rx FSM Timeout Error Status not detected,1: Rx FSM Timeout Error Status detected" newline bitfld.long 0x0 8. "TTES,Tx FSM Timeout Error Status This field when set indicates that one of the Tx FSM Timeout has occurred" "0: Tx FSM Timeout Error Status not detected,1: Tx FSM Timeout Error Status detected" newline rbitfld.long 0x0 7. "Reserved_ASRPES,Reserved." "0,1" newline rbitfld.long 0x0 6. "Reserved_CWPES,Reserved." "0,1" newline bitfld.long 0x0 5. "ARPES,Application Receive interface data path Parity Error Status This bit when set indicates that a parity error is detected at the following checkers based on the system configuration: - In MTL configuration (DWC_EQOS_SYS=1) parity checker (PC6 as.." "0: Application Receive interface data path Parity..,1: Application Receive interface data path Parity.." newline bitfld.long 0x0 4. "MTSPES,MTL TX Status data path Parity checker Error Status This filed when set indicates that parity error is detected on the MTL TX Status data on ati interface (or at PC5 as shown in Transmit data path parity protection diagram)" "0: MTL TX Status data path Parity checker Error..,1: MTL TX Status data path Parity checker Error.." newline bitfld.long 0x0 3. "MPES,MTL data path Parity checker Error Status This bit when set indicates that a parity error is detected at the MTL transmit write controller parity checker (or at PC4 as shown in Transmit data path parity protection diagram)" "0: MTL data path Parity checker Error Status not..,1: MTL data path Parity checker Error Status detected" newline bitfld.long 0x0 2. "RDPES,Read Descriptor Parity checker Error Status This bit when set indicates that a parity error is detected at the DMA Read descriptor parity checker (or at PC3 as shown in Transmit data path parity protection diagram)" "0: Read Descriptor Parity checker Error Status not..,1: Read Descriptor Parity checker Error Status.." newline rbitfld.long 0x0 1. "Reserved_TPES,Reserved." "0,1" newline rbitfld.long 0x0 0. "Reserved_ATPES,Reserved." "0,1" group.long 0x148++0xB line.long 0x0 "MAC_FSM_Control,This register is used to control the FSM State parity and timeout error injection in Debug mode." rbitfld.long 0x0 31. "Reserved_RVCLGRNML,Reserved." "0,1" newline rbitfld.long 0x0 30. "Reserved_R125LGRNML,Reserved." "0,1" newline rbitfld.long 0x0 29. "Reserved_T125LGRNML,Reserved." "0,1" newline bitfld.long 0x0 28. "PLGRNML,PTP Large/Normal Mode Select This field when set indicates that large mode tic generation is used for PTP domain else normal mode tic generation is used" "0: normal mode tic generation is used for PTP domain,1: large mode tic generation is used for PTP domain" newline bitfld.long 0x0 27. "ALGRNML,APP Large/Normal Mode Select This field when set indicates that large mode tic generation is used for APP domain else normal mode tic generation is used" "0: normal mode tic generation is used for APP domain,1: large mode tic generation is used for APP domain" newline rbitfld.long 0x0 26. "Reserved_CLGRNML,Reserved." "0,1" newline bitfld.long 0x0 25. "RLGRNML,Rx Large/Normal Mode Select This field when set indicates that large mode tic generation is used for Rx domain else normal mode tic generation is used" "0: normal mode tic generation is used for Rx domain,1: large mode tic generation is used for Rx domain" newline bitfld.long 0x0 24. "TLGRNML,Tx Large/Normal Mode Select This field when set indicates that large mode tic generation is used for Tx domain else normal mode tic generation is used" "0: normal mode tic generation is used for Tx domain,1: large mode tic generation is used for Tx domain" newline rbitfld.long 0x0 23. "Reserved_RVCPEIN,Reserved." "0,1" newline rbitfld.long 0x0 22. "Reserved_R125PEIN,Reserved." "0,1" newline rbitfld.long 0x0 21. "Reserved_T125PEIN,Reserved." "0,1" newline bitfld.long 0x0 20. "PPEIN,PTP FSM Parity Error Injection This field when set indicates that Error Injection for PTP FSM Parity is enabled" "0: PTP FSM Parity Error Injection is disabled,1: PTP FSM Parity Error Injection is enabled" newline bitfld.long 0x0 19. "APEIN,APP FSM Parity Error Injection This field when set indicates that Error Injection for APP FSM Parity is enabled" "0: APP FSM Parity Error Injection is disabled,1: APP FSM Parity Error Injection is enabled" newline rbitfld.long 0x0 18. "Reserved_CPEIN,Reserved." "0,1" newline bitfld.long 0x0 17. "RPEIN,Rx FSM Parity Error Injection This field when set indicates that Error Injection for RX FSM Parity is enabled" "0: Rx FSM Parity Error Injection is disabled,1: Rx FSM Parity Error Injection is enabled" newline bitfld.long 0x0 16. "TPEIN,Tx FSM Parity Error Injection This field when set indicates that Error Injection for TX FSM Parity is enabled" "0: Tx FSM Parity Error Injection is disabled,1: Tx FSM Parity Error Injection is enabled" newline rbitfld.long 0x0 15. "Reserved_RVCTEIN,Reserved." "0,1" newline rbitfld.long 0x0 14. "Reserved_R125TEIN,Reserved." "0,1" newline rbitfld.long 0x0 13. "Reserved_T125TEIN,Reserved." "0,1" newline bitfld.long 0x0 12. "PTEIN,PTP FSM Timeout Error Injection This field when set indicates that Error Injection for PTP FSM timeout is enabled" "0: PTP FSM Timeout Error Injection is disabled,1: PTP FSM Timeout Error Injection is enabled" newline bitfld.long 0x0 11. "ATEIN,APP FSM Timeout Error Injection This field when set indicates that Error Injection for APP FSM timeout is enabled" "0: APP FSM Timeout Error Injection is disabled,1: APP FSM Timeout Error Injection is enabled" newline rbitfld.long 0x0 10. "Reserved_CTEIN,Reserved." "0,1" newline bitfld.long 0x0 9. "RTEIN,Rx FSM Timeout Error Injection This field when set indicates that Error Injection for RX FSM timeout is enabled" "0: Rx FSM Timeout Error Injection is disabled,1: Rx FSM Timeout Error Injection is enabled" newline bitfld.long 0x0 8. "TTEIN,Tx FSM Timeout Error Injection This field when set indicates that Error Injection for TX FSM timeout is enabled" "0: Tx FSM Timeout Error Injection is disabled,1: Tx FSM Timeout Error Injection is enabled" newline hexmask.long.byte 0x0 2.--7. 1. "Reserved_7_2,Reserved." newline bitfld.long 0x0 1. "PRTYEN,This bit when set indicates that the FSM parity feature is enabled." "0: FSM Parity feature is disabled,1: FSM Parity feature is enabled" newline bitfld.long 0x0 0. "TMOUTEN,This bit when set indicates that the FSM timeout feature is enabled." "0: FSM timeout feature is disabled,1: FSM timeout feature is enabled" line.long 0x4 "MAC_FSM_ACT_Timer,This register is used to select the FSM and Interface Timeout values." hexmask.long.byte 0x4 24.--31. 1. "Reserved_31_24,Reserved." newline hexmask.long.byte 0x4 20.--23. 1. "LTMRMD,Large Mode Timeout Value This field provides the mode value to be used for large mode FSM and other interface time outs" newline hexmask.long.byte 0x4 16.--19. 1. "NTMRMD,Normal Mode Timeout Value This field provides the value to be used for normal mode FSM and other interface time outs" newline hexmask.long.byte 0x4 10.--15. 1. "Reserved_15_10,Reserved." newline hexmask.long.word 0x4 0.--9. 1. "TMR,CSR Clocks for 1us Tic This field indicates the number of CSR clocks required to generate 1us tic." line.long 0x8 "SCS_REG1,NXP Reserved Register" hexmask.long 0x8 0.--31. 1. "MAC_SCS1,NXP Reserved All the bits must be set to '0'" group.long 0x200++0x7 line.long 0x0 "MAC_MDIO_Address,The MDIO Address register controls the management cycles to external PHY through a management interface." hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_28,Reserved." newline bitfld.long 0x0 27. "PSE,Preamble Suppression Enable When this bit is set the SMA suppresses the 32-bit preamble and transmits MDIO frames with only 1 preamble bit" "0: Preamble Suppression disabled,1: Preamble Suppression enabled" newline bitfld.long 0x0 26. "BTB,Back to Back transactions When this bit is set and the NTC has value greater than 0 then the MAC informs the completion of a read or write command at the end of frame transfer (before the trailing clocks are transmitted)" "0: Back to Back transactions disabled,1: Back to Back transactions enabled" newline hexmask.long.byte 0x0 21.--25. 1. "PA,Physical Layer Address This field indicates which Clause 22 PHY devices (out of 32 devices) the MAC is accessing" newline hexmask.long.byte 0x0 16.--20. 1. "RDA,Register/Device Address These bits select the PHY register in selected Clause 22 PHY device" newline rbitfld.long 0x0 15. "Reserved_15,Reserved." "0,1" newline bitfld.long 0x0 12.--14. "NTC,Number of Trailing Clocks This field controls the number of trailing clock cycles generated on gmii_mdc_o (MDC) after the end of transmission of MDIO frame" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "CR,CSR Clock Range The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design: - 0000: CSR clock = 60-100 MHz; MDC clock = CSR clock/42 - 0001: CSR clock = 100-150 MHz; MDC clock = CSR.." newline rbitfld.long 0x0 5.--7. "Reserved_7_5,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "SKAP,Skip Address Packet When this bit is set the SMA does not send the address packets before read write or post-read increment address packets" "0: Skip Address Packet is disabled,1: Skip Address Packet is enabled" newline bitfld.long 0x0 3. "GOC_1,GMII Operation Command 1 This bit is higher bit of the operation command to the PHY or RevMII GOC_1 and GOC_O is encoded as follows: - 00: Reserved - 01: Write - 10: Post Read Increment Address for Clause 45 PHY - 11: Read When Clause 22 PHY or.." "0: Reserved,1: Write" newline bitfld.long 0x0 2. "GOC_0,GMII Operation Command 0 This is the lower bit of the operation command to the PHY or RevMII" "0: GMII Operation Command 0 is disabled,1: GMII Operation Command 0 is enabled" newline bitfld.long 0x0 1. "C45E,Clause 45 PHY Enable When this bit is set Clause 45 capable PHY is connected to MDIO" "0: Clause 45 PHY is disabled,1: Clause 45 PHY is enabled" newline bitfld.long 0x0 0. "GB,GMII Busy The application sets this bit to instruct the SMA to initiate a Read or Write access to the MDIO slave" "0: GMII Busy is disabled,1: GMII Busy is enabled" line.long 0x4 "MAC_MDIO_Data,The MDIO Data register stores the Write data to be written to the PHY register located at the address specified in MAC_MDIO_Address. This register also stores the Read data from the PHY register located at the address specified by MDIO.." hexmask.long.word 0x4 16.--31. 1. "RA,Register Address This field is valid only when C45E is set" newline hexmask.long.word 0x4 0.--15. 1. "GD,GMII Data This field contains the 16-bit data value read from the PHY or RevMII after a Management Read operation or the 16-bit data value to be written to the PHY or RevMII before a Management Write operation" group.long 0x210++0x3 line.long 0x0 "MAC_ARP_Address,The ARP Address register contains the IPv4 Destination Address of the MAC." hexmask.long 0x0 0.--31. 1. "ARPPA,ARP Protocol Address This field contains the IPv4 Destination Address of the MAC" group.long 0x230++0xB line.long 0x0 "MAC_CSR_SW_Ctrl,This register contains software programmable controls for changing the CSR access response and status bits clearing." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_31_9,Reserved." newline bitfld.long 0x0 8. "SEEN,Slave Error Response Enable When this bit is set the MAC responds with Slave Error for accesses to reserved registers in CSR space" "0: Slave Error Response is disabled,1: Slave Error Response is enabled" newline hexmask.long.byte 0x0 1.--7. 1. "Reserved_7_1,Reserved." newline bitfld.long 0x0 0. "RCWE,Register Clear on Write 1 Enable When this bit is set the access mode of some register fields changes to Clear on Write 1 the application needs to set that respective bit to 1 to clear it" "0: Register Clear on Write 1 is disabled,1: Register Clear on Write 1 is enabled" line.long 0x4 "MAC_FPE_CTRL_STS,This register controls the operation of Frame Preemption." hexmask.long.word 0x4 20.--31. 1. "Reserved_31_20,Reserved." newline bitfld.long 0x4 19. "TRSP,Transmitted Respond Frame Set when a Respond mPacket is transmitted (triggered by setting SRSP field)" "0: Not transmitted Respond Frame,1: transmitted Respond Frame" newline bitfld.long 0x4 18. "TVER,Transmitted Verify Frame Set when a Verify mPacket is transmitted (triggered by setting SVER field)" "0: Not transmitted Verify Frame,1: transmitted Verify Frame" newline bitfld.long 0x4 17. "RRSP,Received Respond Frame Set when a Respond mPacket is received" "0: Not received Respond Frame,1: Received Respond Frame" newline bitfld.long 0x4 16. "RVER,Received Verify Frame Set when a Verify mPacket is received" "0: Not received Verify Frame,1: Received Verify Frame" newline hexmask.long.word 0x4 4.--15. 1. "Reserved_15_4,Reserved." newline bitfld.long 0x4 3. "S1_SET_0,NXP Reserved Must be set to '0'" "0,1" newline bitfld.long 0x4 2. "SRSP,Send Respond mPacket When set indicates hardware to send a Respond mPacket" "0: Send Respond mPacket is disabled,1: Send Respond mPacket is enabled" newline bitfld.long 0x4 1. "SVER,Send Verify mPacket When set indicates hardware to send a verify mPacket" "0: Send Verify mPacket is disabled,1: Send Verify mPacket is enabled" newline bitfld.long 0x4 0. "EFPE,Enable Tx Frame Preemption When set Frame Preemption Tx functionality is enabled." "0: Tx Frame Preemption is disabled,1: Tx Frame Preemption is enabled" line.long 0x8 "MAC_Ext_Cfg1,This register contains Split mode control field and offset field for Split Header feature." hexmask.long.byte 0x8 25.--31. 1. "Reserved_31_25,Reserved." newline bitfld.long 0x8 24. "SAVE,Split AV Enable - When this bit is set to 1 and the received packet is an AV Type packet the header is split at SAVO bytes from the beginning of Length/Type field of the packet for L2 Split" "0,1" newline rbitfld.long 0x8 23. "Reserved_23,Reserved." "0,1" newline hexmask.long.byte 0x8 16.--22. 1. "SAVO,Split AV Offset When SAVE bit is set to 1 and the received packet is an AV Type packet these bits indicate the value of the offset from the beginning of Length/Type field at which header should be split when appropriate SPLM is selected" newline hexmask.long.byte 0x8 10.--15. 1. "Reserved_15_10,Reserved." newline bitfld.long 0x8 8.--9. "SPLM,Split Mode These bits indicate the mode of splitting the incoming Rx packets. They are" "0: Split at L3/L4 header,1: Split at L2 header with an offset. Always Split..,2: Combination mode: Split similar to SPLM=00 for..,?" newline rbitfld.long 0x8 7. "Reserved_7,Reserved." "0,1" newline hexmask.long.byte 0x8 0.--6. 1. "SPLOFST,Split Offset These bits indicate the value of offset from the beginning of Length/Type field at which header split should take place when the appropriate SPLM is selected" rgroup.long 0x240++0x3 line.long 0x0 "MAC_Presn_Time_ns,This register contains the 32-bit binary rollover equivalent time of the PTP System Time in ns Exists when DWC_EQOS_FLEXI_PPS_OUT_EN is configured" hexmask.long 0x0 0.--31. 1. "MPTN,MAC 1722 Presentation Time in ns These bits indicate the value of the 32-bit binary rollover equivalent time of the PTP System Time in ns" group.long 0x244++0x3 line.long 0x0 "MAC_Presn_Time_Updt,This field holds the 32-bit value of MAC 1722 Presentation Time in ns. that should be added to the Current Presentation Time Counter value. Init happens when TSINIT is set. and update happens when the TSUPDT bit is set (TSINIT and.." hexmask.long 0x0 0.--31. 1. "MPTU,MAC 1722 Presentation Time Update This field holds the init value or the update value for the presentation time" group.long 0x300++0x17 line.long 0x0 "MAC_Address0_High,The MAC Address0 High register holds the upper 16 bits of the first 6-byte MAC address of the station. The first DA byte that is received on the (G)MII interface corresponds to the LS byte (Bits [7:0]) of the MAC Address Low register." rbitfld.long 0x0 31. "AE,Address Enable This bit is always set to 1." "0: INVALID : This bit must be always set to 1,1: This bit is always set to 1" newline hexmask.long.word 0x0 19.--30. 1. "Reserved_30_y,Reserved." newline bitfld.long 0x0 16.--18. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address0 content is routed" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--15. 1. "ADDRHI,MAC Address0[47:32] This field contains the upper 16 bits [47:32] of the first 6-byte MAC address" line.long 0x4 "MAC_Address0_Low,The MAC Address0 Low register holds the lower 32 bits of the 6-byte first MAC address of the station." hexmask.long 0x4 0.--31. 1. "ADDRLO,MAC Address0[31:0] This field contains the lower 32 bits of the first 6-byte MAC address" line.long 0x8 "MAC_Address1_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x8 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled" newline bitfld.long 0x8 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address" newline hexmask.long.byte 0x8 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" newline hexmask.long.byte 0x8 19.--23. 1. "Reserved_23_y,Reserved." newline bitfld.long 0x8 16.--18. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x8 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0xC "MAC_Address1_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0xC 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address" line.long 0x10 "MAC_Address2_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x10 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled" newline bitfld.long 0x10 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address" newline hexmask.long.byte 0x10 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" newline hexmask.long.byte 0x10 19.--23. 1. "Reserved_23_y,Reserved." newline bitfld.long 0x10 16.--18. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x10 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0x14 "MAC_Address2_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0x14 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address" group.long 0x700++0x3 line.long 0x0 "MMC_Control,This register establishes the operating mode of MMC." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_31_9,Reserved." newline bitfld.long 0x0 8. "UCDBC,Update MMC Counters for Dropped Broadcast Packets Note: The CNTRST bit has a higher priority than the CNTPRST bit" "0: Update MMC Counters for Dropped Broadcast..,1: Update MMC Counters for Dropped Broadcast.." newline rbitfld.long 0x0 6.--7. "Reserved_7_6,Reserved." "0,1,2,3" newline bitfld.long 0x0 5. "CNTPRSTLVL,Full-Half Preset When this bit is low and the CNTPRST bit is set all MMC counters get preset to almost-half value" "0: Full-Half Preset is disabled,1: Full-Half Preset is enabled" newline bitfld.long 0x0 4. "CNTPRST,Counters Preset When this bit is set all counters are initialized or preset to almost full or almost half according to the CNTPRSTLVL bit" "0: Counters Preset is disabled,1: Counters Preset is enabled" newline bitfld.long 0x0 3. "CNTFREEZ,MMC Counter Freeze When this bit is set it freezes all MMC counters to their current value" "0: MMC Counter Freeze is disabled,1: MMC Counter Freeze is enabled" newline bitfld.long 0x0 2. "RSTONRD,Reset on Read When this bit is set the MMC counters are reset to zero after Read (self-clearing after reset)" "0: Reset on Read is disabled,1: Reset on Read is enabled" newline bitfld.long 0x0 1. "CNTSTOPRO,Counter Stop Rollover When this bit is set the counter does not roll over to zero after reaching the maximum value" "0: Counter Stop Rollover is disabled,1: Counter Stop Rollover is enabled" newline bitfld.long 0x0 0. "CNTRST,Counters Reset When this bit is set all counters are reset" "0: Counters are not reset,1: All counters are reset" rgroup.long 0x704++0x7 line.long 0x0 "MMC_Rx_Interrupt,This register maintains the interrupts generated from all Receive statistics counters. The MMC Receive Interrupt register maintains the interrupts that are generated when the following occur: - Receive statistic counters reach half of.." hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_28,Reserved." newline bitfld.long 0x0 27. "Reserved_RXLPITRCIS,Reserved." "0,1" newline bitfld.long 0x0 26. "Reserved_RXLPIUSCIS,Reserved." "0,1" newline bitfld.long 0x0 25. "RXCTRLPIS,MMC Receive Control Packet Counter Interrupt Status This bit is set when the rxctrlpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Control Packet Counter Interrupt..,1: MMC Receive Control Packet Counter Interrupt.." newline bitfld.long 0x0 24. "RXRCVERRPIS,MMC Receive Error Packet Counter Interrupt Status This bit is set when the rxrcverror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Error Packet Counter Interrupt..,1: MMC Receive Error Packet Counter Interrupt.." newline bitfld.long 0x0 23. "RXWDOGPIS,MMC Receive Watchdog Error Packet Counter Interrupt Status This bit is set when the rxwatchdog error counter reaches half of the maximum value or the maximum value" "0: MMC Receive Watchdog Error Packet Counter..,1: MMC Receive Watchdog Error Packet Counter.." newline bitfld.long 0x0 22. "RXVLANGBPIS,MMC Receive VLAN Good Bad Packet Counter Interrupt Status This bit is set when the rxvlanpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive VLAN Good Bad Packet Counter..,1: MMC Receive VLAN Good Bad Packet Counter.." newline bitfld.long 0x0 21. "RXFOVPIS,MMC Receive FIFO Overflow Packet Counter Interrupt Status This bit is set when the rxfifooverflow counter reaches half of the maximum value or the maximum value" "0: MMC Receive FIFO Overflow Packet Counter..,1: MMC Receive FIFO Overflow Packet Counter.." newline bitfld.long 0x0 20. "RXPAUSPIS,MMC Receive Pause Packet Counter Interrupt Status This bit is set when the rxpausepackets counter reaches half of the maximum value or the maximum value" "0: MMC Receive Pause Packet Counter Interrupt..,1: MMC Receive Pause Packet Counter Interrupt.." newline bitfld.long 0x0 19. "RXORANGEPIS,MMC Receive Out Of Range Error Packet Counter Interrupt Status" "0: MMC Receive Out Of Range Error Packet Counter..,1: MMC Receive Out Of Range Error Packet Counter.." newline bitfld.long 0x0 18. "RXLENERPIS,MMC Receive Length Error Packet Counter Interrupt Status This bit is set when the rxlengtherror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Length Error Packet Counter..,1: MMC Receive Length Error Packet Counter.." newline bitfld.long 0x0 17. "RXUCGPIS,MMC Receive Unicast Good Packet Counter Interrupt Status This bit is set when the rxunicastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Unicast Good Packet Counter..,1: MMC Receive Unicast Good Packet Counter.." newline bitfld.long 0x0 16. "RX1024TMAXOCTGBPIS,MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 1024 to Maximum Octet Good Bad..,1: MMC Receive 1024 to Maximum Octet Good Bad.." newline bitfld.long 0x0 15. "RX512T1023OCTGBPIS,MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 512 to 1023 Octet Good Bad Packet..,1: MMC Receive 512 to 1023 Octet Good Bad Packet.." newline bitfld.long 0x0 14. "RX256T511OCTGBPIS,MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 256 to 511 Octet Good Bad Packet..,1: MMC Receive 256 to 511 Octet Good Bad Packet.." newline bitfld.long 0x0 13. "RX128T255OCTGBPIS,MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 128 to 255 Octet Good Bad Packet..,1: MMC Receive 128 to 255 Octet Good Bad Packet.." newline bitfld.long 0x0 12. "RX65T127OCTGBPIS,MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 65 to 127 Octet Good Bad Packet..,1: MMC Receive 65 to 127 Octet Good Bad Packet.." newline bitfld.long 0x0 11. "RX64OCTGBPIS,MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx64octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 64 Octet Good Bad Packet Counter..,1: MMC Receive 64 Octet Good Bad Packet Counter.." newline bitfld.long 0x0 10. "RXOSIZEGPIS,MMC Receive Oversize Good Packet Counter Interrupt Status This bit is set when the rxoversize_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Oversize Good Packet Counter..,1: MMC Receive Oversize Good Packet Counter.." newline bitfld.long 0x0 9. "RXUSIZEGPIS,MMC Receive Undersize Good Packet Counter Interrupt Status This bit is set when the rxundersize_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Undersize Good Packet Counter..,1: MMC Receive Undersize Good Packet Counter.." newline bitfld.long 0x0 8. "RXJABERPIS,MMC Receive Jabber Error Packet Counter Interrupt Status This bit is set when the rxjabbererror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Jabber Error Packet Counter..,1: MMC Receive Jabber Error Packet Counter.." newline bitfld.long 0x0 7. "RXRUNTPIS,MMC Receive Runt Packet Counter Interrupt Status This bit is set when the rxrunterror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Runt Packet Counter Interrupt Status..,1: MMC Receive Runt Packet Counter Interrupt Status.." newline bitfld.long 0x0 6. "RXALGNERPIS,MMC Receive Alignment Error Packet Counter Interrupt Status This bit is set when the rxalignmenterror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Alignment Error Packet Counter..,1: MMC Receive Alignment Error Packet Counter.." newline bitfld.long 0x0 5. "RXCRCERPIS,MMC Receive CRC Error Packet Counter Interrupt Status This bit is set when the rxcrcerror counter reaches half of the maximum value or the maximum value" "0: MMC Receive CRC Error Packet Counter Interrupt..,1: MMC Receive CRC Error Packet Counter Interrupt.." newline bitfld.long 0x0 4. "RXMCGPIS,MMC Receive Multicast Good Packet Counter Interrupt Status This bit is set when the rxmulticastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Multicast Good Packet Counter..,1: MMC Receive Multicast Good Packet Counter.." newline bitfld.long 0x0 3. "RXBCGPIS,MMC Receive Broadcast Good Packet Counter Interrupt Status This bit is set when the rxbroadcastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Broadcast Good Packet Counter..,1: MMC Receive Broadcast Good Packet Counter.." newline bitfld.long 0x0 2. "RXGOCTIS,MMC Receive Good Octet Counter Interrupt Status This bit is set when the rxoctetcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Octet Counter Interrupt Status..,1: MMC Receive Good Octet Counter Interrupt Status.." newline bitfld.long 0x0 1. "RXGBOCTIS,MMC Receive Good Bad Octet Counter Interrupt Status This bit is set when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Bad Octet Counter Interrupt..,1: MMC Receive Good Bad Octet Counter Interrupt.." newline bitfld.long 0x0 0. "RXGBPKTIS,MMC Receive Good Bad Packet Counter Interrupt Status This bit is set when the rxpacketcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Bad Packet Counter Interrupt..,1: MMC Receive Good Bad Packet Counter Interrupt.." line.long 0x4 "MMC_Tx_Interrupt,This register maintains the interrupts generated from all Transmit statistics counters. The MMC Transmit Interrupt register maintains the interrupts generated when transmit statistic counters reach half their maximum values (0x8000_0000.." hexmask.long.byte 0x4 28.--31. 1. "Reserved_31_28,Reserved." newline bitfld.long 0x4 27. "Reserved_TXLPITRCIS,Reserved." "0,1" newline bitfld.long 0x4 26. "Reserved_TXLPIUSCIS,Reserved." "0,1" newline bitfld.long 0x4 25. "TXOSIZEGPIS,MMC Transmit Oversize Good Packet Counter Interrupt Status This bit is set when the txoversize_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Oversize Good Packet Counter..,1: MMC Transmit Oversize Good Packet Counter.." newline bitfld.long 0x4 24. "TXVLANGPIS,MMC Transmit VLAN Good Packet Counter Interrupt Status This bit is set when the txvlanpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit VLAN Good Packet Counter Interrupt..,1: MMC Transmit VLAN Good Packet Counter Interrupt.." newline bitfld.long 0x4 23. "TXPAUSPIS,MMC Transmit Pause Packet Counter Interrupt Status This bit is set when the txpausepacketserror counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Pause Packet Counter Interrupt..,1: MMC Transmit Pause Packet Counter Interrupt.." newline bitfld.long 0x4 22. "TXEXDEFPIS,MMC Transmit Excessive Deferral Packet Counter Interrupt Status This bit is set when the txexcessdef counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Excessive Deferral Packet Counter..,1: MMC Transmit Excessive Deferral Packet Counter.." newline bitfld.long 0x4 21. "TXGPKTIS,MMC Transmit Good Packet Counter Interrupt Status This bit is set when the txpacketcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Packet Counter Interrupt..,1: MMC Transmit Good Packet Counter Interrupt.." newline bitfld.long 0x4 20. "TXGOCTIS,MMC Transmit Good Octet Counter Interrupt Status This bit is set when the txoctetcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Octet Counter Interrupt Status..,1: MMC Transmit Good Octet Counter Interrupt Status.." newline bitfld.long 0x4 19. "TXCARERPIS,MMC Transmit Carrier Error Packet Counter Interrupt Status This bit is set when the txcarriererror counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Carrier Error Packet Counter..,1: MMC Transmit Carrier Error Packet Counter.." newline bitfld.long 0x4 18. "TXEXCOLPIS,MMC Transmit Excessive Collision Packet Counter Interrupt Status This bit is set when the txexesscol counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Excessive Collision Packet Counter..,1: MMC Transmit Excessive Collision Packet Counter.." newline bitfld.long 0x4 17. "TXLATCOLPIS,MMC Transmit Late Collision Packet Counter Interrupt Status This bit is set when the txlatecol counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Late Collision Packet Counter..,1: MMC Transmit Late Collision Packet Counter.." newline bitfld.long 0x4 16. "TXDEFPIS,MMC Transmit Deferred Packet Counter Interrupt Status This bit is set when the txdeferred counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Deferred Packet Counter Interrupt..,1: MMC Transmit Deferred Packet Counter Interrupt.." newline bitfld.long 0x4 15. "TXMCOLGPIS,MMC Transmit Multiple Collision Good Packet Counter Interrupt Status This bit is set when the txmulticol_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multiple Collision Good Packet..,1: MMC Transmit Multiple Collision Good Packet.." newline bitfld.long 0x4 14. "TXSCOLGPIS,MMC Transmit Single Collision Good Packet Counter Interrupt Status This bit is set when the txsinglecol_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Single Collision Good Packet..,1: MMC Transmit Single Collision Good Packet.." newline bitfld.long 0x4 13. "TXUFLOWERPIS,MMC Transmit Underflow Error Packet Counter Interrupt Status This bit is set when the txunderflowerror counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Underflow Error Packet Counter..,1: MMC Transmit Underflow Error Packet Counter.." newline bitfld.long 0x4 12. "TXBCGBPIS,MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status This bit is set when the txbroadcastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Broadcast Good Bad Packet Counter..,1: MMC Transmit Broadcast Good Bad Packet Counter.." newline bitfld.long 0x4 11. "TXMCGBPIS,MMC Transmit Multicast Good Bad Packet Counter Interrupt Status The bit is set when the txmulticastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multicast Good Bad Packet Counter..,1: MMC Transmit Multicast Good Bad Packet Counter.." newline bitfld.long 0x4 10. "TXUCGBPIS,MMC Transmit Unicast Good Bad Packet Counter Interrupt Status This bit is set when the txunicastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Unicast Good Bad Packet Counter..,1: MMC Transmit Unicast Good Bad Packet Counter.." newline bitfld.long 0x4 9. "TX1024TMAXOCTGBPIS,MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 1024 to Maximum Octet Good Bad..,1: MMC Transmit 1024 to Maximum Octet Good Bad.." newline bitfld.long 0x4 8. "TX512T1023OCTGBPIS,MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 512 to 1023 Octet Good Bad Packet..,1: MMC Transmit 512 to 1023 Octet Good Bad Packet.." newline bitfld.long 0x4 7. "TX256T511OCTGBPIS,MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 256 to 511 Octet Good Bad Packet..,1: MMC Transmit 256 to 511 Octet Good Bad Packet.." newline bitfld.long 0x4 6. "TX128T255OCTGBPIS,MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 128 to 255 Octet Good Bad Packet..,1: MMC Transmit 128 to 255 Octet Good Bad Packet.." newline bitfld.long 0x4 5. "TX65T127OCTGBPIS,MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx65to127octets_gb counter reaches half the maximum value and also when it reaches the maximum value" "0: MMC Transmit 65 to 127 Octet Good Bad Packet..,1: MMC Transmit 65 to 127 Octet Good Bad Packet.." newline bitfld.long 0x4 4. "TX64OCTGBPIS,MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx64octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 64 Octet Good Bad Packet Counter..,1: MMC Transmit 64 Octet Good Bad Packet Counter.." newline bitfld.long 0x4 3. "TXMCGPIS,MMC Transmit Multicast Good Packet Counter Interrupt Status This bit is set when the txmulticastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multicast Good Packet Counter..,1: MMC Transmit Multicast Good Packet Counter.." newline bitfld.long 0x4 2. "TXBCGPIS,MMC Transmit Broadcast Good Packet Counter Interrupt Status This bit is set when the txbroadcastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Broadcast Good Packet Counter..,1: MMC Transmit Broadcast Good Packet Counter.." newline bitfld.long 0x4 1. "TXGBPKTIS,MMC Transmit Good Bad Packet Counter Interrupt Status This bit is set when the txpacketcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Bad Packet Counter Interrupt..,1: MMC Transmit Good Bad Packet Counter Interrupt.." newline bitfld.long 0x4 0. "TXGBOCTIS,MMC Transmit Good Bad Octet Counter Interrupt Status This bit is set when the txoctetcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Bad Octet Counter Interrupt..,1: MMC Transmit Good Bad Octet Counter Interrupt.." group.long 0x70C++0x7 line.long 0x0 "MMC_Rx_Interrupt_Mask,This register maintains the masks for interrupts generated from all Receive statistics counters. The MMC Receive Interrupt Mask register maintains the masks for the interrupts generated when receive statistic counters reach half of.." hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_28,Reserved." newline rbitfld.long 0x0 27. "Reserved_RXLPITRCIM,Reserved." "0,1" newline rbitfld.long 0x0 26. "Reserved_RXLPIUSCIM,Reserved." "0,1" newline bitfld.long 0x0 25. "RXCTRLPIM,MMC Receive Control Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxctrlpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Control Packet Counter Interrupt..,1: MMC Receive Control Packet Counter Interrupt.." newline bitfld.long 0x0 24. "RXRCVERRPIM,MMC Receive Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Error Packet Counter Interrupt Mask..,1: MMC Receive Error Packet Counter Interrupt Mask.." newline bitfld.long 0x0 23. "RXWDOGPIM,MMC Receive Watchdog Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value" "0: MMC Receive Watchdog Error Packet Counter..,1: MMC Receive Watchdog Error Packet Counter.." newline bitfld.long 0x0 22. "RXVLANGBPIM,MMC Receive VLAN Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxvlanpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive VLAN Good Bad Packet Counter..,1: MMC Receive VLAN Good Bad Packet Counter.." newline bitfld.long 0x0 21. "RXFOVPIM,MMC Receive FIFO Overflow Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value" "0: MMC Receive FIFO Overflow Packet Counter..,1: MMC Receive FIFO Overflow Packet Counter.." newline bitfld.long 0x0 20. "RXPAUSPIM,MMC Receive Pause Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxpausepackets counter reaches half of the maximum value or the maximum value" "0: MMC Receive Pause Packet Counter Interrupt Mask..,1: MMC Receive Pause Packet Counter Interrupt Mask.." newline bitfld.long 0x0 19. "RXORANGEPIM,MMC Receive Out Of Range Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the maximum value" "0: MMC Receive Out Of Range Error Packet Counter..,1: MMC Receive Out Of Range Error Packet Counter.." newline bitfld.long 0x0 18. "RXLENERPIM,MMC Receive Length Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Length Error Packet Counter..,1: MMC Receive Length Error Packet Counter.." newline bitfld.long 0x0 17. "RXUCGPIM,MMC Receive Unicast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxunicastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Unicast Good Packet Counter..,1: MMC Receive Unicast Good Packet Counter.." newline bitfld.long 0x0 16. "RX1024TMAXOCTGBPIM,MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask" "0: MMC Receive 1024 to Maximum Octet Good Bad..,1: MMC Receive 1024 to Maximum Octet Good Bad.." newline bitfld.long 0x0 15. "RX512T1023OCTGBPIM,MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 512 to 1023 Octet Good Bad Packet..,1: MMC Receive 512 to 1023 Octet Good Bad Packet.." newline bitfld.long 0x0 14. "RX256T511OCTGBPIM,MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 256 to 511 Octet Good Bad Packet..,1: MMC Receive 256 to 511 Octet Good Bad Packet.." newline bitfld.long 0x0 13. "RX128T255OCTGBPIM,MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 128 to 255 Octet Good Bad Packet..,1: MMC Receive 128 to 255 Octet Good Bad Packet.." newline bitfld.long 0x0 12. "RX65T127OCTGBPIM,MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 65 to 127 Octet Good Bad Packet..,1: MMC Receive 65 to 127 Octet Good Bad Packet.." newline bitfld.long 0x0 11. "RX64OCTGBPIM,MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 64 Octet Good Bad Packet Counter..,1: MMC Receive 64 Octet Good Bad Packet Counter.." newline bitfld.long 0x0 10. "RXOSIZEGPIM,MMC Receive Oversize Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Oversize Good Packet Counter..,1: MMC Receive Oversize Good Packet Counter.." newline bitfld.long 0x0 9. "RXUSIZEGPIM,MMC Receive Undersize Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Undersize Good Packet Counter..,1: MMC Receive Undersize Good Packet Counter.." newline bitfld.long 0x0 8. "RXJABERPIM,MMC Receive Jabber Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Jabber Error Packet Counter..,1: MMC Receive Jabber Error Packet Counter.." newline bitfld.long 0x0 7. "RXRUNTPIM,MMC Receive Runt Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxrunterror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Runt Packet Counter Interrupt Mask..,1: MMC Receive Runt Packet Counter Interrupt Mask.." newline bitfld.long 0x0 6. "RXALGNERPIM,MMC Receive Alignment Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxalignmenterror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Alignment Error Packet Counter..,1: MMC Receive Alignment Error Packet Counter.." newline bitfld.long 0x0 5. "RXCRCERPIM,MMC Receive CRC Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value" "0: MMC Receive CRC Error Packet Counter Interrupt..,1: MMC Receive CRC Error Packet Counter Interrupt.." newline bitfld.long 0x0 4. "RXMCGPIM,MMC Receive Multicast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxmulticastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Multicast Good Packet Counter..,1: MMC Receive Multicast Good Packet Counter.." newline bitfld.long 0x0 3. "RXBCGPIM,MMC Receive Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxbroadcastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Broadcast Good Packet Counter..,1: MMC Receive Broadcast Good Packet Counter.." newline bitfld.long 0x0 2. "RXGOCTIM,MMC Receive Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoctetcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Octet Counter Interrupt Mask is..,1: MMC Receive Good Octet Counter Interrupt Mask is.." newline bitfld.long 0x0 1. "RXGBOCTIM,MMC Receive Good Bad Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Bad Octet Counter Interrupt..,1: MMC Receive Good Bad Octet Counter Interrupt.." newline bitfld.long 0x0 0. "RXGBPKTIM,MMC Receive Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxpacketcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Bad Packet Counter Interrupt..,1: MMC Receive Good Bad Packet Counter Interrupt.." line.long 0x4 "MMC_Tx_Interrupt_Mask,This register maintains the masks for interrupts generated from all Transmit statistics counters. The MMC Transmit Interrupt Mask register maintains the masks for the interrupts generated when the transmit statistic counters reach.." hexmask.long.byte 0x4 28.--31. 1. "Reserved_31_28,Reserved." newline rbitfld.long 0x4 27. "Reserved_TXLPITRCIM,Reserved." "0,1" newline rbitfld.long 0x4 26. "Reserved_TXLPIUSCIM,Reserved." "0,1" newline bitfld.long 0x4 25. "TXOSIZEGPIM,MMC Transmit Oversize Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Oversize Good Packet Counter..,1: MMC Transmit Oversize Good Packet Counter.." newline bitfld.long 0x4 24. "TXVLANGPIM,MMC Transmit VLAN Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txvlanpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit VLAN Good Packet Counter Interrupt..,1: MMC Transmit VLAN Good Packet Counter Interrupt.." newline bitfld.long 0x4 23. "TXPAUSPIM,MMC Transmit Pause Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txpausepackets counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Pause Packet Counter Interrupt Mask..,1: MMC Transmit Pause Packet Counter Interrupt Mask.." newline bitfld.long 0x4 22. "TXEXDEFPIM,MMC Transmit Excessive Deferral Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Excessive Deferral Packet Counter..,1: MMC Transmit Excessive Deferral Packet Counter.." newline bitfld.long 0x4 21. "TXGPKTIM,MMC Transmit Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txpacketcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Packet Counter Interrupt Mask..,1: MMC Transmit Good Packet Counter Interrupt Mask.." newline bitfld.long 0x4 20. "TXGOCTIM,MMC Transmit Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the txoctetcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Octet Counter Interrupt Mask..,1: MMC Transmit Good Octet Counter Interrupt Mask.." newline bitfld.long 0x4 19. "TXCARERPIM,MMC Transmit Carrier Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txcarriererror counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Carrier Error Packet Counter..,1: MMC Transmit Carrier Error Packet Counter.." newline bitfld.long 0x4 18. "TXEXCOLPIM,MMC Transmit Excessive Collision Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Excessive Collision Packet Counter..,1: MMC Transmit Excessive Collision Packet Counter.." newline bitfld.long 0x4 17. "TXLATCOLPIM,MMC Transmit Late Collision Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Late Collision Packet Counter..,1: MMC Transmit Late Collision Packet Counter.." newline bitfld.long 0x4 16. "TXDEFPIM,MMC Transmit Deferred Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txdeferred counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Deferred Packet Counter Interrupt..,1: MMC Transmit Deferred Packet Counter Interrupt.." newline bitfld.long 0x4 15. "TXMCOLGPIM,MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multiple Collision Good Packet..,1: MMC Transmit Multiple Collision Good Packet.." newline bitfld.long 0x4 14. "TXSCOLGPIM,MMC Transmit Single Collision Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Single Collision Good Packet..,1: MMC Transmit Single Collision Good Packet.." newline bitfld.long 0x4 13. "TXUFLOWERPIM,MMC Transmit Underflow Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txunderflowerror counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Underflow Error Packet Counter..,1: MMC Transmit Underflow Error Packet Counter.." newline bitfld.long 0x4 12. "TXBCGBPIM,MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txbroadcastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Broadcast Good Bad Packet Counter..,1: MMC Transmit Broadcast Good Bad Packet Counter.." newline bitfld.long 0x4 11. "TXMCGBPIM,MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multicast Good Bad Packet Counter..,1: MMC Transmit Multicast Good Bad Packet Counter.." newline bitfld.long 0x4 10. "TXUCGBPIM,MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txunicastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Unicast Good Bad Packet Counter..,1: MMC Transmit Unicast Good Bad Packet Counter.." newline bitfld.long 0x4 9. "TX1024TMAXOCTGBPIM,MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 1024 to Maximum Octet Good Bad..,1: MMC Transmit 1024 to Maximum Octet Good Bad.." newline bitfld.long 0x4 8. "TX512T1023OCTGBPIM,MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 512 to 1023 Octet Good Bad Packet..,1: MMC Transmit 512 to 1023 Octet Good Bad Packet.." newline bitfld.long 0x4 7. "TX256T511OCTGBPIM,MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 256 to 511 Octet Good Bad Packet..,1: MMC Transmit 256 to 511 Octet Good Bad Packet.." newline bitfld.long 0x4 6. "TX128T255OCTGBPIM,MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 128 to 255 Octet Good Bad Packet..,1: MMC Transmit 128 to 255 Octet Good Bad Packet.." newline bitfld.long 0x4 5. "TX65T127OCTGBPIM,MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 65 to 127 Octet Good Bad Packet..,1: MMC Transmit 65 to 127 Octet Good Bad Packet.." newline bitfld.long 0x4 4. "TX64OCTGBPIM,MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 64 Octet Good Bad Packet Counter..,1: MMC Transmit 64 Octet Good Bad Packet Counter.." newline bitfld.long 0x4 3. "TXMCGPIM,MMC Transmit Multicast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multicast Good Packet Counter..,1: MMC Transmit Multicast Good Packet Counter.." newline bitfld.long 0x4 2. "TXBCGPIM,MMC Transmit Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txbroadcastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Broadcast Good Packet Counter..,1: MMC Transmit Broadcast Good Packet Counter.." newline bitfld.long 0x4 1. "TXGBPKTIM,MMC Transmit Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txpacketcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Bad Packet Counter Interrupt..,1: MMC Transmit Good Bad Packet Counter Interrupt.." newline bitfld.long 0x4 0. "TXGBOCTIM,MMC Transmit Good Bad Octet Counter Interrupt Mask Setting this bit masks the interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Bad Octet Counter Interrupt..,1: MMC Transmit Good Bad Octet Counter Interrupt.." rgroup.long 0x714++0x67 line.long 0x0 "Tx_Octet_Count_Good_Bad,This register provides the number of bytes transmitted by the DWC_ether_qos. exclusive of preamble and retried bytes. in good and bad packets." hexmask.long 0x0 0.--31. 1. "TXOCTGB,Tx Octet Count Good Bad This field indicates the number of bytes transmitted exclusive of preamble and retried bytes in good and bad packets" line.long 0x4 "Tx_Packet_Count_Good_Bad,This register provides the number of good and bad packets transmitted by DWC_ether_qos. exclusive of retried packets." hexmask.long 0x4 0.--31. 1. "TXPKTGB,Tx Packet Count Good Bad This field indicates the number of good and bad packets transmitted exclusive of retried packets" line.long 0x8 "Tx_Broadcast_Packets_Good,This register provides the number of good broadcast packets transmitted by DWC_ether_qos." hexmask.long 0x8 0.--31. 1. "TXBCASTG,Tx Broadcast Packets Good This field indicates the number of good broadcast packets transmitted." line.long 0xC "Tx_Multicast_Packets_Good,This register provides the number of good multicast packets transmitted by DWC_ether_qos." hexmask.long 0xC 0.--31. 1. "TXMCASTG,Tx Multicast Packets Good This field indicates the number of good multicast packets transmitted." line.long 0x10 "Tx_64Octets_Packets_Good_Bad,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length 64 bytes. exclusive of preamble and retried packets." hexmask.long 0x10 0.--31. 1. "TX64OCTGB,Tx 64Octets Packets Good_Bad This field indicates the number of good and bad packets transmitted with length 64 bytes exclusive of preamble and retried packets" line.long 0x14 "Tx_65To127Octets_Packets_Good_Bad,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length between 65 and 127 (inclusive) bytes. exclusive of preamble and retried packets." hexmask.long 0x14 0.--31. 1. "TX65_127OCTGB,Tx 65To127Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 65 and 127 (inclusive) bytes exclusive of preamble and retried packets" line.long 0x18 "Tx_128To255Octets_Packets_Good_Bad,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length between 128 to 255 (inclusive) bytes. exclusive of preamble and retried packets." hexmask.long 0x18 0.--31. 1. "TX128_255OCTGB,Tx 128To255Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 128 and 255 (inclusive) bytes exclusive of preamble and retried packets" line.long 0x1C "Tx_256To511Octets_Packets_Good_Bad,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length between 256 to 511 (inclusive) bytes. exclusive of preamble and retried packets." hexmask.long 0x1C 0.--31. 1. "TX256_511OCTGB,Tx 256To511Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 256 and 511 (inclusive) bytes exclusive of preamble and retried packets" line.long 0x20 "Tx_512To1023Octets_Packets_Good_Bad,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length 512 to 1023 (inclusive) bytes. exclusive of preamble and retried packets." hexmask.long 0x20 0.--31. 1. "TX512_1023OCTGB,Tx 512To1023Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 512 and 1023 (inclusive) bytes exclusive of preamble and retried packets" line.long 0x24 "Tx_1024ToMaxOctets_Packets_Good_Bad,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length 1024 to maxsize (inclusive) bytes. exclusive of preamble and retried packets." hexmask.long 0x24 0.--31. 1. "TX1024_MAXOCTGB,Tx 1024ToMaxOctets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 1024 and maxsize (inclusive) bytes exclusive of preamble and retried packets" line.long 0x28 "Tx_Unicast_Packets_Good_Bad,This register provides the number of good and bad unicast packets transmitted by DWC_ether_qos." hexmask.long 0x28 0.--31. 1. "TXUCASTGB,Tx Unicast Packets Good Bad This field indicates the number of good and bad unicast packets transmitted" line.long 0x2C "Tx_Multicast_Packets_Good_Bad,This register provides the number of good and bad multicast packets transmitted by DWC_ether_qos." hexmask.long 0x2C 0.--31. 1. "TXMCASTGB,Tx Multicast Packets Good Bad This field indicates the number of good and bad multicast packets transmitted" line.long 0x30 "Tx_Broadcast_Packets_Good_Bad,This register provides the number of good and bad broadcast packets transmitted by DWC_ether_qos." hexmask.long 0x30 0.--31. 1. "TXBCASTGB,Tx Broadcast Packets Good Bad This field indicates the number of good and bad broadcast packets transmitted" line.long 0x34 "Tx_Underflow_Error_Packets,This register provides the number of packets aborted by DWC_ether_qos because of packets underflow error." hexmask.long 0x34 0.--31. 1. "TXUNDRFLW,Tx Underflow Error Packets This field indicates the number of packets aborted because of packets underflow error" line.long 0x38 "Tx_Single_Collision_Good_Packets,This register provides the number of successfully transmitted packets by DWC_ether_qos after a single collision in the half-duplex mode." hexmask.long 0x38 0.--31. 1. "TXSNGLCOLG,Tx Single Collision Good Packets This field indicates the number of successfully transmitted packets after a single collision in the half-duplex mode" line.long 0x3C "Tx_Multiple_Collision_Good_Packets,This register provides the number of successfully transmitted packets by DWC_ether_qos after multiple collisions in the half-duplex mode." hexmask.long 0x3C 0.--31. 1. "TXMULTCOLG,Tx Multiple Collision Good Packets This field indicates the number of successfully transmitted packets after multiple collisions in the half-duplex mode" line.long 0x40 "Tx_Deferred_Packets,This register provides the number of successfully transmitted by DWC_ether_qos after a deferral in the half-duplex mode." hexmask.long 0x40 0.--31. 1. "TXDEFRD,Tx Deferred Packets This field indicates the number of successfully transmitted after a deferral in the half-duplex mode" line.long 0x44 "Tx_Late_Collision_Packets,This register provides the number of packets aborted by DWC_ether_qos because of late collision error." hexmask.long 0x44 0.--31. 1. "TXLATECOL,Tx Late Collision Packets This field indicates the number of packets aborted because of late collision error" line.long 0x48 "Tx_Excessive_Collision_Packets,This register provides the number of packets aborted by DWC_ether_qos because of excessive (16) collision errors." hexmask.long 0x48 0.--31. 1. "TXEXSCOL,Tx Excessive Collision Packets This field indicates the number of packets aborted because of excessive (16) collision errors" line.long 0x4C "Tx_Carrier_Error_Packets,This register provides the number of packets aborted by DWC_ether_qos because of carrier sense error (no carrier or loss of carrier)." hexmask.long 0x4C 0.--31. 1. "TXCARR,Tx Carrier Error Packets This field indicates the number of packets aborted because of carrier sense error (no carrier or loss of carrier)" line.long 0x50 "Tx_Octet_Count_Good,This register provides the number of bytes transmitted by DWC_ether_qos. exclusive of preamble. only in good packets." hexmask.long 0x50 0.--31. 1. "TXOCTG,Tx Octet Count Good This field indicates the number of bytes transmitted exclusive of preamble only in good packets" line.long 0x54 "Tx_Packet_Count_Good,This register provides the number of good packets transmitted by DWC_ether_qos." hexmask.long 0x54 0.--31. 1. "TXPKTG,Tx Packet Count Good This field indicates the number of good packets transmitted." line.long 0x58 "Tx_Excessive_Deferral_Error,This register provides the number of packets aborted by DWC_ether_qos because of excessive deferral error (deferred for more than two max-sized packet times)." hexmask.long 0x58 0.--31. 1. "TXEXSDEF,Tx Excessive Deferral Error This field indicates the number of packets aborted because of excessive deferral error (deferred for more than two max-sized packet times)" line.long 0x5C "Tx_Pause_Packets,This register provides the number of good Pause packets transmitted by DWC_ether_qos." hexmask.long 0x5C 0.--31. 1. "TXPAUSE,Tx Pause Packets This field indicates the number of good Pause packets transmitted." line.long 0x60 "Tx_VLAN_Packets_Good,This register provides the number of good VLAN packets transmitted by DWC_ether_qos." hexmask.long 0x60 0.--31. 1. "TXVLANG,Tx VLAN Packets Good This field provides the number of good VLAN packets transmitted." line.long 0x64 "Tx_OSize_Packets_Good,This register provides the number of packets transmitted by DWC_ether_qos without errors and with length greater than the maxsize (1.518 or 1.522 bytes for VLAN tagged packets; 2000 bytes if enabled in S2KP bit of the.." hexmask.long 0x64 0.--31. 1. "TXOSIZG,Tx OSize Packets Good This field indicates the number of packets transmitted without errors and with length greater than the maxsize (1 518 or 1 522 bytes for VLAN tagged packets; 2000 bytes if enabled in S2KP bit of the MAC_Configuration register)" rgroup.long 0x780++0x67 line.long 0x0 "Rx_Packets_Count_Good_Bad,This register provides the number of good and bad packets received by DWC_ether_qos." hexmask.long 0x0 0.--31. 1. "RXPKTGB,Rx Packets Count Good Bad This field indicates the number of good and bad packets received." line.long 0x4 "Rx_Octet_Count_Good_Bad,This register provides the number of bytes received by DWC_ther_qos. exclusive of preamble. in good and bad packets." hexmask.long 0x4 0.--31. 1. "RXOCTGB,Rx Octet Count Good Bad This field indicates the number of bytes received exclusive of preamble in good and bad packets" line.long 0x8 "Rx_Octet_Count_Good,This register provides the number of bytes received by DWC_ether_qos. exclusive of preamble. only in good packets." hexmask.long 0x8 0.--31. 1. "RXOCTG,Rx Octet Count Good This field indicates the number of bytes received exclusive of preamble only in good packets" line.long 0xC "Rx_Broadcast_Packets_Good,This register provides the number of good broadcast packets received by DWC_ether_qos." hexmask.long 0xC 0.--31. 1. "RXBCASTG,Rx Broadcast Packets Good This field indicates the number of good broadcast packets received." line.long 0x10 "Rx_Multicast_Packets_Good,This register provides the number of good multicast packets received by DWC_ether_qos." hexmask.long 0x10 0.--31. 1. "RXMCASTG,Rx Multicast Packets Good This field indicates the number of good multicast packets received." line.long 0x14 "Rx_CRC_Error_Packets,This register provides the number of packets received by DWC_ether_qos with CRC error." hexmask.long 0x14 0.--31. 1. "RXCRCERR,Rx CRC Error Packets This field indicates the number of packets received with CRC error." line.long 0x18 "Rx_Alignment_Error_Packets,This register provides the number of packets received by DWC_ether_qos with alignment (dribble) error. It is valid only in 10/100 mode." hexmask.long 0x18 0.--31. 1. "RXALGNERR,Rx Alignment Error Packets This field indicates the number of packets received with alignment (dribble) error" line.long 0x1C "Rx_Runt_Error_Packets,This register provides the number of packets received by DWC_ether_qos with runt (length less than 64 bytes and CRC error) error." hexmask.long 0x1C 0.--31. 1. "RXRUNTERR,Rx Runt Error Packets This field indicates the number of packets received with runt (length less than 64 bytes and CRC error) error" line.long 0x20 "Rx_Jabber_Error_Packets,This register provides the number of giant packets received by DWC_ether_qos with length (including CRC) greater than 1.518 bytes (1.522 bytes for VLAN tagged) and with CRC error. If Jumbo Packet mode is enabled. packets of length.." hexmask.long 0x20 0.--31. 1. "RXJABERR,Rx Jabber Error Packets This field indicates the number of giant packets received with length (including CRC) greater than 1 518 bytes (1 522 bytes for VLAN tagged) and with CRC error" line.long 0x24 "Rx_Undersize_Packets_Good,This register provides the number of packets received by DWC_ether_qos with length less than 64 bytes. without any errors." hexmask.long 0x24 0.--31. 1. "RXUNDERSZG,Rx Undersize Packets Good This field indicates the number of packets received with length less than 64 bytes without any errors" line.long 0x28 "Rx_Oversize_Packets_Good,This register provides the number of packets received by DWC_ether_qos without errors. with length greater than the maxsize (1.518 bytes or 1.522 bytes for VLAN tagged packets; 2000 bytes if enabled in the S2KP bit of the.." hexmask.long 0x28 0.--31. 1. "RXOVERSZG,Rx Oversize Packets Good This field indicates the number of packets received without errors with length greater than the maxsize (1 518 bytes or 1 522 bytes for VLAN tagged packets; 2000 bytes if enabled in the S2KP bit of the.." line.long 0x2C "Rx_64Octets_Packets_Good_Bad,This register provides the number of good and bad packets received by DWC_ether_qos with length 64 bytes. exclusive of the preamble." hexmask.long 0x2C 0.--31. 1. "RX64OCTGB,Rx 64 Octets Packets Good Bad This field indicates the number of good and bad packets received with length 64 bytes exclusive of the preamble" line.long 0x30 "Rx_65To127Octets_Packets_Good_Bad,This register provides the number of good and bad packets received by DWC_ether_qos with length between 65 and 127 (inclusive) bytes. exclusive of the preamble." hexmask.long 0x30 0.--31. 1. "RX65_127OCTGB,Rx 65-127 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 65 and 127 (inclusive) bytes exclusive of the preamble" line.long 0x34 "Rx_128To255Octets_Packets_Good_Bad,This register provides the number of good and bad packets received by DWC_ether_qos with length between 128 and 255 (inclusive) bytes. exclusive of the preamble." hexmask.long 0x34 0.--31. 1. "RX128_255OCTGB,Rx 128-255 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 128 and 255 (inclusive) bytes exclusive of the preamble" line.long 0x38 "Rx_256To511Octets_Packets_Good_Bad,This register provides the number of good and bad packets received by DWC_ether_qos with length between 256 and 511 (inclusive) bytes. exclusive of the preamble." hexmask.long 0x38 0.--31. 1. "RX256_511OCTGB,Rx 256-511 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 256 and 511 (inclusive) bytes exclusive of the preamble" line.long 0x3C "Rx_512To1023Octets_Packets_Good_Bad,This register provides the number of good and bad packets received by DWC_ether_qos with length between 512 and 1023 (inclusive) bytes. exclusive of the preamble." hexmask.long 0x3C 0.--31. 1. "RX512_1023OCTGB,RX 512-1023 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 512 and 1023 (inclusive) bytes exclusive of the preamble" line.long 0x40 "Rx_1024ToMaxOctets_Packets_Good_Bad,This register provides the number of good and bad packets received by DWC_ether_qos with length between 1024 and maxsize (inclusive) bytes. exclusive of the preamble." hexmask.long 0x40 0.--31. 1. "RX1024_MAXOCTGB,Rx 1024-Max Octets Good Bad This field indicates the number of good and bad packets received with length between 1024 and maxsize (inclusive) bytes exclusive of the preamble" line.long 0x44 "Rx_Unicast_Packets_Good,This register provides the number of good unicast packets received by DWC_ether_qos." hexmask.long 0x44 0.--31. 1. "RXUCASTG,Rx Unicast Packets Good This field indicates the number of good unicast packets received." line.long 0x48 "Rx_Length_Error_Packets,This register provides the number of packets received by DWC_ether_qos with length error (Length Type field not equal to packet size). for all packets with valid length field." hexmask.long 0x48 0.--31. 1. "RXLENERR,Rx Length Error Packets This field indicates the number of packets received with length error (Length Type field not equal to packet size) for all packets with valid length field" line.long 0x4C "Rx_Out_Of_Range_Type_Packets,This register provides the number of packets received by DWC_ether_qos with length field not equal to the valid packet size (greater than 1.500 but less than 1.536)." hexmask.long 0x4C 0.--31. 1. "RXOUTOFRNG,Rx Out of Range Type Packet This field indicates the number of packets received with length field not equal to the valid packet size (greater than 1 500 but less than 1 536)" line.long 0x50 "Rx_Pause_Packets,This register provides the number of good and valid Pause packets received by DWC_ether_qos." hexmask.long 0x50 0.--31. 1. "RXPAUSEPKT,Rx Pause Packets This field indicates the number of good and valid Pause packets received." line.long 0x54 "Rx_FIFO_Overflow_Packets,This register provides the number of missed received packets because of FIFO overflow in DWC_ether_qos." hexmask.long 0x54 0.--31. 1. "RXFIFOOVFL,Rx FIFO Overflow Packets This field indicates the number of missed received packets because of FIFO overflow" line.long 0x58 "Rx_VLAN_Packets_Good_Bad,This register provides the number of good and bad VLAN packets received by DWC_ether_qos." hexmask.long 0x58 0.--31. 1. "RXVLANPKTGB,Rx VLAN Packets Good Bad This field indicates the number of good and bad VLAN packets received." line.long 0x5C "Rx_Watchdog_Error_Packets,This register provides the number of packets received by DWC_ether_qos with error because of watchdog timeout error (packets with a data load larger than 2.048 bytes (when JE and WD bits are reset in MAC_Configuration register)..." hexmask.long 0x5C 0.--31. 1. "RXWDGERR,Rx Watchdog Error Packets This field indicates the number of packets received with error because of watchdog timeout error (packets with a data load larger than 2 048 bytes (when JE and WD bits are reset in MAC_Configuration register) 10 240.." line.long 0x60 "Rx_Receive_Error_Packets,This register provides the number of packets received by DWC_ether_qos with Receive error or Packet Extension error on the GMII or MII interface." hexmask.long 0x60 0.--31. 1. "RXRCVERR,Rx Receive Error Packets This field indicates the number of packets received with Receive error or Packet Extension error on the GMII or MII interface" line.long 0x64 "Rx_Control_Packets_Good,This register provides the number of good control packets received by DWC_ether_qos." hexmask.long 0x64 0.--31. 1. "RXCTRLG,Rx Control Packets Good This field indicates the number of good control packets received." rgroup.long 0x8A0++0x3 line.long 0x0 "MMC_FPE_Tx_Interrupt,This register maintains the interrupts generated from all FPE related Transmit statistics counters. The MMC FPE Transmit Interrupt register maintains the interrupts generated when transmit statistic counters reach half their maximum.." hexmask.long 0x0 2.--31. 1. "Reserved_31_2,Reserved." newline bitfld.long 0x0 1. "HRCIS,MMC Tx Hold Request Counter Interrupt Status This bit is set when the Tx_Hold_Req_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Tx Hold Request Counter Interrupt Status not..,1: MMC Tx Hold Request Counter Interrupt Status.." newline bitfld.long 0x0 0. "FCIS,MMC Tx FPE Fragment Counter Interrupt status This bit is set when the Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Tx FPE Fragment Counter Interrupt status not..,1: MMC Tx FPE Fragment Counter Interrupt status.." group.long 0x8A4++0x3 line.long 0x0 "MMC_FPE_Tx_Interrupt_Mask,This register maintains the masks for interrupts generated from all FPE related Transmit statistics counters. The MMC Receive Interrupt Mask register maintains the masks for the interrupts generated when FPE related receive.." hexmask.long 0x0 2.--31. 1. "Reserved_31_2,Reserved." newline bitfld.long 0x0 1. "HRCIM,MMC Transmit Hold Request Counter Interrupt Mask Setting this bit masks the interrupt when the Tx_Hold_Req_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Hold Request Counter Interrupt Mask..,1: MMC Transmit Hold Request Counter Interrupt Mask.." newline bitfld.long 0x0 0. "FCIM,MMC Transmit Fragment Counter Interrupt Mask Setting this bit masks the interrupt when the Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Fragment Counter Interrupt Mask is..,1: MMC Transmit Fragment Counter Interrupt Mask is.." rgroup.long 0x8A8++0x7 line.long 0x0 "MMC_Tx_FPE_Fragment_Cntr,This register provides the number of additional mPackets transmitted due to preemption." hexmask.long 0x0 0.--31. 1. "TXFFC,Tx FPE Fragment counter This field indicates the number of additional mPackets that has been transmitted due to preemption Exists when any one of the RX/TX MMC counters are enabled during FPE Enabled configuration" line.long 0x4 "MMC_Tx_Hold_Req_Cntr,This register provides the count of number of times a hold request is given to MAC" hexmask.long 0x4 0.--31. 1. "TXHRC,Tx Hold Request Counter This field indicates count of number of a hold request is given to MAC" rgroup.long 0x8C0++0x3 line.long 0x0 "MMC_FPE_Rx_Interrupt,This register maintains the interrupts generated from all FPE related Receive statistics counters. The MMC FPE Receive Interrupt register maintains the interrupts generated when transmit statistic counters reach half their maximum.." hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved." newline bitfld.long 0x0 3. "FCIS,MMC Rx FPE Fragment Counter Interrupt Status This bit is set when the Rx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx FPE Fragment Counter Interrupt Status not..,1: MMC Rx FPE Fragment Counter Interrupt Status.." newline bitfld.long 0x0 2. "PAOCIS,MMC Rx Packet Assembly OK Counter Interrupt Status This bit is set when the Rx_Packet_Assemble_Ok_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet Assembly OK Counter Interrupt..,1: MMC Rx Packet Assembly OK Counter Interrupt.." newline bitfld.long 0x0 1. "PSECIS,MMC Rx Packet SMD Error Counter Interrupt Status This bit is set when the Rx_Packet_SMD_Err_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet SMD Error Counter Interrupt Status..,1: MMC Rx Packet SMD Error Counter Interrupt Status.." newline bitfld.long 0x0 0. "PAECIS,MMC Rx Packet Assembly Error Counter Interrupt Status This bit is set when the Rx_Packet_Assemble_Err_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet Assembly Error Counter Interrupt..,1: MMC Rx Packet Assembly Error Counter Interrupt.." group.long 0x8C4++0x3 line.long 0x0 "MMC_FPE_Rx_Interrupt_Mask,This register maintains the masks for interrupts generated from all FPE related Receive statistics counters. The MMC Receive Interrupt Mask register maintains the masks for the interrupts generated when FPE related receive.." hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved." newline bitfld.long 0x0 3. "FCIM,MMC Rx FPE Fragment Counter Interrupt Mask Setting this bit masks the interrupt when the Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx FPE Fragment Counter Interrupt Mask is..,1: MMC Rx FPE Fragment Counter Interrupt Mask is.." newline bitfld.long 0x0 2. "PAOCIM,MMC Rx Packet Assembly OK Counter Interrupt Mask Setting this bit masks the interrupt when the Rx_Packet_Assemble_Ok_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet Assembly OK Counter Interrupt Mask..,1: MMC Rx Packet Assembly OK Counter Interrupt Mask.." newline bitfld.long 0x0 1. "PSECIM,MMC Rx Packet SMD Error Counter Interrupt Mask Setting this bit masks the interrupt when the R Rx_Packet_SMD_Err_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet SMD Error Counter Interrupt Mask..,1: MMC Rx Packet SMD Error Counter Interrupt Mask.." newline bitfld.long 0x0 0. "PAECIM,MMC Rx Packet Assembly Error Counter Interrupt Mask Setting this bit masks the interrupt when the R Rx_Packet_Assemble_Err_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet Assembly Error Counter Interrupt..,1: MMC Rx Packet Assembly Error Counter Interrupt.." rgroup.long 0x8C8++0xF line.long 0x0 "MMC_Rx_Packet_Assembly_Err_Cntr,This register provides the number of MAC frames with reassembly errors on the Receiver. due to mismatch in the Fragment Count value." hexmask.long 0x0 0.--31. 1. "PAEC,Rx Packet Assembly Error Counter This field indicates the number of MAC frames with reassembly errors on the Receiver due to mismatch in the Fragment Count value" line.long 0x4 "MMC_Rx_Packet_SMD_Err_Cntr,This register provides the number of received MAC frames rejected due to unknown SMD value and MAC frame fragments rejected due to arriving with an SMD-C when there was no preceding preempted frame." hexmask.long 0x4 0.--31. 1. "PSEC,Rx Packet SMD Error Counter This field indicates the number of MAC frames rejected due to unknown SMD value and MAC frame fragments rejected due to arriving with an SMD-C when there was no preceding preempted frame" line.long 0x8 "MMC_Rx_Packet_Assembly_OK_Cntr,This register provides the number of MAC frames that were successfully reassembled and delivered to MAC." hexmask.long 0x8 0.--31. 1. "PAOC,Rx Packet Assembly OK Counter This field indicates the number of MAC frames that were successfully reassembled and delivered to MAC" line.long 0xC "MMC_Rx_FPE_Fragment_Cntr,This register provides the number of additional mPackets received due to preemption." hexmask.long 0xC 0.--31. 1. "FFC,Rx FPE Fragment Counter This field indicates the number of additional mPackets received due to preemption Exists when at least one of the RX/TX MMC counters are enabled during FPE Enabled configuration" group.long 0x900++0x7 line.long 0x0 "MAC_L3_L4_Control0,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4." rbitfld.long 0x0 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "DMCHEN0,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled" newline rbitfld.long 0x0 26.--27. "Reserved_27_y,Reserved." "0,1,2,3" newline bitfld.long 0x0 24.--25. "DMCHN0,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3" newline rbitfld.long 0x0 22.--23. "Reserved_23_22,Reserved." "0,1,2,3" newline bitfld.long 0x0 21. "L4DPIM0,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is disabled,1: Layer 4 Destination Port Inverse Match is enabled" newline bitfld.long 0x0 20. "L4DPM0,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled" newline bitfld.long 0x0 19. "L4SPIM0,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled" newline bitfld.long 0x0 18. "L4SPM0,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled" newline rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1" newline bitfld.long 0x0 16. "L4PEN0,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled" newline hexmask.long.byte 0x0 11.--15. 1. "L3HDBM0,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" newline hexmask.long.byte 0x0 6.--10. 1. "L3HSBM0,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" newline bitfld.long 0x0 5. "L3DAIM0,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled" newline bitfld.long 0x0 4. "L3DAM0,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled" newline bitfld.long 0x0 3. "L3SAIM0,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled" newline bitfld.long 0x0 2. "L3SAM0,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled" newline rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1" newline bitfld.long 0x0 0. "L3PEN0,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled" line.long 0x4 "MAC_Layer4_Address0,The MAC_Layer4_Address(#i). MAC_L3_L4_Control(#i). MAC_Layer3_Addr0_Reg(#i). MAC_Layer3_Addr1_Reg(#i). MAC_Layer3_Addr2_Reg(#i) and MAC_Layer3_Addr3_Reg(#i) registers are reserved (RO with default value) if Enable Layer 3 and Layer 4.." hexmask.long.word 0x4 16.--31. 1. "L4DP0,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets" newline hexmask.long.word 0x4 0.--15. 1. "L4SP0,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets" group.long 0x910++0xF line.long 0x0 "MAC_Layer3_Addr0_Reg0,For IPv4 packets. the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x0 0.--31. 1. "L3A00,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets" line.long 0x4 "MAC_Layer3_Addr1_Reg0,For IPv4 packets. the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x4 0.--31. 1. "L3A10,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets" line.long 0x8 "MAC_Layer3_Addr2_Reg0,The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field." hexmask.long 0x8 0.--31. 1. "L3A20,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets" line.long 0xC "MAC_Layer3_Addr3_Reg0,The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field." hexmask.long 0xC 0.--31. 1. "L3A30,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets" group.long 0x930++0x7 line.long 0x0 "MAC_L3_L4_Control1,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4." rbitfld.long 0x0 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "DMCHEN1,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled" newline rbitfld.long 0x0 26.--27. "Reserved_27_y,Reserved." "0,1,2,3" newline bitfld.long 0x0 24.--25. "DMCHN1,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3" newline rbitfld.long 0x0 22.--23. "Reserved_23_22,Reserved." "0,1,2,3" newline bitfld.long 0x0 21. "L4DPIM1,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is disabled,1: Layer 4 Destination Port Inverse Match is enabled" newline bitfld.long 0x0 20. "L4DPM1,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled" newline bitfld.long 0x0 19. "L4SPIM1,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled" newline bitfld.long 0x0 18. "L4SPM1,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled" newline rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1" newline bitfld.long 0x0 16. "L4PEN1,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled" newline hexmask.long.byte 0x0 11.--15. 1. "L3HDBM1,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" newline hexmask.long.byte 0x0 6.--10. 1. "L3HSBM1,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" newline bitfld.long 0x0 5. "L3DAIM1,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled" newline bitfld.long 0x0 4. "L3DAM1,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled" newline bitfld.long 0x0 3. "L3SAIM1,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled" newline bitfld.long 0x0 2. "L3SAM1,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled" newline rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1" newline bitfld.long 0x0 0. "L3PEN1,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled" line.long 0x4 "MAC_Layer4_Address1,The MAC_Layer4_Address(#i). MAC_L3_L4_Control(#i). MAC_Layer3_Addr0_Reg(#i). MAC_Layer3_Addr1_Reg(#i). MAC_Layer3_Addr2_Reg(#i) and MAC_Layer3_Addr3_Reg(#i) registers are reserved (RO with default value) if Enable Layer 3 and Layer 4.." hexmask.long.word 0x4 16.--31. 1. "L4DP1,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets" newline hexmask.long.word 0x4 0.--15. 1. "L4SP1,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets" group.long 0x940++0xF line.long 0x0 "MAC_Layer3_Addr0_Reg1,For IPv4 packets. the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x0 0.--31. 1. "L3A01,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets" line.long 0x4 "MAC_Layer3_Addr1_Reg1,For IPv4 packets. the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x4 0.--31. 1. "L3A11,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets" line.long 0x8 "MAC_Layer3_Addr2_Reg1,The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field." hexmask.long 0x8 0.--31. 1. "L3A21,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets" line.long 0xC "MAC_Layer3_Addr3_Reg1,The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field." hexmask.long 0xC 0.--31. 1. "L3A31,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets" group.long 0x960++0x7 line.long 0x0 "MAC_L3_L4_Control2,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4." rbitfld.long 0x0 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "DMCHEN2,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled" newline rbitfld.long 0x0 26.--27. "Reserved_27_y,Reserved." "0,1,2,3" newline bitfld.long 0x0 24.--25. "DMCHN2,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3" newline rbitfld.long 0x0 22.--23. "Reserved_23_22,Reserved." "0,1,2,3" newline bitfld.long 0x0 21. "L4DPIM2,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is disabled,1: Layer 4 Destination Port Inverse Match is enabled" newline bitfld.long 0x0 20. "L4DPM2,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled" newline bitfld.long 0x0 19. "L4SPIM2,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled" newline bitfld.long 0x0 18. "L4SPM2,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled" newline rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1" newline bitfld.long 0x0 16. "L4PEN2,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled" newline hexmask.long.byte 0x0 11.--15. 1. "L3HDBM2,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" newline hexmask.long.byte 0x0 6.--10. 1. "L3HSBM2,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" newline bitfld.long 0x0 5. "L3DAIM2,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled" newline bitfld.long 0x0 4. "L3DAM2,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled" newline bitfld.long 0x0 3. "L3SAIM2,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled" newline bitfld.long 0x0 2. "L3SAM2,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled" newline rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1" newline bitfld.long 0x0 0. "L3PEN2,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled" line.long 0x4 "MAC_Layer4_Address2,The MAC_Layer4_Address(#i). MAC_L3_L4_Control(#i). MAC_Layer3_Addr0_Reg(#i). MAC_Layer3_Addr1_Reg(#i). MAC_Layer3_Addr2_Reg(#i) and MAC_Layer3_Addr3_Reg(#i) registers are reserved (RO with default value) if Enable Layer 3 and Layer 4.." hexmask.long.word 0x4 16.--31. 1. "L4DP2,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets" newline hexmask.long.word 0x4 0.--15. 1. "L4SP2,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets" group.long 0x970++0xF line.long 0x0 "MAC_Layer3_Addr0_Reg2,For IPv4 packets. the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x0 0.--31. 1. "L3A02,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets" line.long 0x4 "MAC_Layer3_Addr1_Reg2,For IPv4 packets. the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x4 0.--31. 1. "L3A12,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets" line.long 0x8 "MAC_Layer3_Addr2_Reg2,The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field." hexmask.long 0x8 0.--31. 1. "L3A22,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets" line.long 0xC "MAC_Layer3_Addr3_Reg2,The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field." hexmask.long 0xC 0.--31. 1. "L3A32,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets" group.long 0x990++0x7 line.long 0x0 "MAC_L3_L4_Control3,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4." rbitfld.long 0x0 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "DMCHEN3,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled" newline rbitfld.long 0x0 26.--27. "Reserved_27_y,Reserved." "0,1,2,3" newline bitfld.long 0x0 24.--25. "DMCHN3,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3" newline rbitfld.long 0x0 22.--23. "Reserved_23_22,Reserved." "0,1,2,3" newline bitfld.long 0x0 21. "L4DPIM3,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is disabled,1: Layer 4 Destination Port Inverse Match is enabled" newline bitfld.long 0x0 20. "L4DPM3,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled" newline bitfld.long 0x0 19. "L4SPIM3,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled" newline bitfld.long 0x0 18. "L4SPM3,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled" newline rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1" newline bitfld.long 0x0 16. "L4PEN3,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled" newline hexmask.long.byte 0x0 11.--15. 1. "L3HDBM3,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" newline hexmask.long.byte 0x0 6.--10. 1. "L3HSBM3,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" newline bitfld.long 0x0 5. "L3DAIM3,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled" newline bitfld.long 0x0 4. "L3DAM3,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled" newline bitfld.long 0x0 3. "L3SAIM3,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled" newline bitfld.long 0x0 2. "L3SAM3,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled" newline rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1" newline bitfld.long 0x0 0. "L3PEN3,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled" line.long 0x4 "MAC_Layer4_Address3,The MAC_Layer4_Address(#i). MAC_L3_L4_Control(#i). MAC_Layer3_Addr0_Reg(#i). MAC_Layer3_Addr1_Reg(#i). MAC_Layer3_Addr2_Reg(#i) and MAC_Layer3_Addr3_Reg(#i) registers are reserved (RO with default value) if Enable Layer 3 and Layer 4.." hexmask.long.word 0x4 16.--31. 1. "L4DP3,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets" newline hexmask.long.word 0x4 0.--15. 1. "L4SP3,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets" group.long 0x9A0++0xF line.long 0x0 "MAC_Layer3_Addr0_Reg3,For IPv4 packets. the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x0 0.--31. 1. "L3A03,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets" line.long 0x4 "MAC_Layer3_Addr1_Reg3,For IPv4 packets. the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x4 0.--31. 1. "L3A13,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets" line.long 0x8 "MAC_Layer3_Addr2_Reg3,The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field." hexmask.long 0x8 0.--31. 1. "L3A23,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets" line.long 0xC "MAC_Layer3_Addr3_Reg3,The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field." hexmask.long 0xC 0.--31. 1. "L3A33,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets" group.long 0x9C0++0x7 line.long 0x0 "MAC_L3_L4_Control4,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4." rbitfld.long 0x0 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "DMCHEN4,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled" newline rbitfld.long 0x0 26.--27. "Reserved_27_y,Reserved." "0,1,2,3" newline bitfld.long 0x0 24.--25. "DMCHN4,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3" newline rbitfld.long 0x0 22.--23. "Reserved_23_22,Reserved." "0,1,2,3" newline bitfld.long 0x0 21. "L4DPIM4,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is disabled,1: Layer 4 Destination Port Inverse Match is enabled" newline bitfld.long 0x0 20. "L4DPM4,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled" newline bitfld.long 0x0 19. "L4SPIM4,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled" newline bitfld.long 0x0 18. "L4SPM4,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled" newline rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1" newline bitfld.long 0x0 16. "L4PEN4,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled" newline hexmask.long.byte 0x0 11.--15. 1. "L3HDBM4,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" newline hexmask.long.byte 0x0 6.--10. 1. "L3HSBM4,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" newline bitfld.long 0x0 5. "L3DAIM4,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled" newline bitfld.long 0x0 4. "L3DAM4,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled" newline bitfld.long 0x0 3. "L3SAIM4,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled" newline bitfld.long 0x0 2. "L3SAM4,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled" newline rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1" newline bitfld.long 0x0 0. "L3PEN4,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled" line.long 0x4 "MAC_Layer4_Address4,The MAC_Layer4_Address(#i). MAC_L3_L4_Control(#i). MAC_Layer3_Addr0_Reg(#i). MAC_Layer3_Addr1_Reg(#i). MAC_Layer3_Addr2_Reg(#i) and MAC_Layer3_Addr3_Reg(#i) registers are reserved (RO with default value) if Enable Layer 3 and Layer 4.." hexmask.long.word 0x4 16.--31. 1. "L4DP4,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets" newline hexmask.long.word 0x4 0.--15. 1. "L4SP4,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets" group.long 0x9D0++0xF line.long 0x0 "MAC_Layer3_Addr0_Reg4,For IPv4 packets. the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x0 0.--31. 1. "L3A04,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets" line.long 0x4 "MAC_Layer3_Addr1_Reg4,For IPv4 packets. the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x4 0.--31. 1. "L3A14,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets" line.long 0x8 "MAC_Layer3_Addr2_Reg4,The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field." hexmask.long 0x8 0.--31. 1. "L3A24,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets" line.long 0xC "MAC_Layer3_Addr3_Reg4,The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field." hexmask.long 0xC 0.--31. 1. "L3A34,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets" group.long 0x9F0++0x7 line.long 0x0 "MAC_L3_L4_Control5,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4." rbitfld.long 0x0 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "DMCHEN5,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled" newline rbitfld.long 0x0 26.--27. "Reserved_27_y,Reserved." "0,1,2,3" newline bitfld.long 0x0 24.--25. "DMCHN5,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3" newline rbitfld.long 0x0 22.--23. "Reserved_23_22,Reserved." "0,1,2,3" newline bitfld.long 0x0 21. "L4DPIM5,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is disabled,1: Layer 4 Destination Port Inverse Match is enabled" newline bitfld.long 0x0 20. "L4DPM5,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled" newline bitfld.long 0x0 19. "L4SPIM5,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled" newline bitfld.long 0x0 18. "L4SPM5,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled" newline rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1" newline bitfld.long 0x0 16. "L4PEN5,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled" newline hexmask.long.byte 0x0 11.--15. 1. "L3HDBM5,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" newline hexmask.long.byte 0x0 6.--10. 1. "L3HSBM5,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" newline bitfld.long 0x0 5. "L3DAIM5,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled" newline bitfld.long 0x0 4. "L3DAM5,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled" newline bitfld.long 0x0 3. "L3SAIM5,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled" newline bitfld.long 0x0 2. "L3SAM5,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled" newline rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1" newline bitfld.long 0x0 0. "L3PEN5,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled" line.long 0x4 "MAC_Layer4_Address5,The MAC_Layer4_Address(#i). MAC_L3_L4_Control(#i). MAC_Layer3_Addr0_Reg(#i). MAC_Layer3_Addr1_Reg(#i). MAC_Layer3_Addr2_Reg(#i) and MAC_Layer3_Addr3_Reg(#i) registers are reserved (RO with default value) if Enable Layer 3 and Layer 4.." hexmask.long.word 0x4 16.--31. 1. "L4DP5,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets" newline hexmask.long.word 0x4 0.--15. 1. "L4SP5,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets" group.long 0xA00++0xF line.long 0x0 "MAC_Layer3_Addr0_Reg5,For IPv4 packets. the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x0 0.--31. 1. "L3A05,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets" line.long 0x4 "MAC_Layer3_Addr1_Reg5,For IPv4 packets. the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x4 0.--31. 1. "L3A15,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets" line.long 0x8 "MAC_Layer3_Addr2_Reg5,The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field." hexmask.long 0x8 0.--31. 1. "L3A25,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets" line.long 0xC "MAC_Layer3_Addr3_Reg5,The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field." hexmask.long 0xC 0.--31. 1. "L3A35,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets" group.long 0xA20++0x7 line.long 0x0 "MAC_L3_L4_Control6,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4." rbitfld.long 0x0 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "DMCHEN6,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled" newline rbitfld.long 0x0 26.--27. "Reserved_27_y,Reserved." "0,1,2,3" newline bitfld.long 0x0 24.--25. "DMCHN6,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3" newline rbitfld.long 0x0 22.--23. "Reserved_23_22,Reserved." "0,1,2,3" newline bitfld.long 0x0 21. "L4DPIM6,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is disabled,1: Layer 4 Destination Port Inverse Match is enabled" newline bitfld.long 0x0 20. "L4DPM6,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled" newline bitfld.long 0x0 19. "L4SPIM6,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled" newline bitfld.long 0x0 18. "L4SPM6,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled" newline rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1" newline bitfld.long 0x0 16. "L4PEN6,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled" newline hexmask.long.byte 0x0 11.--15. 1. "L3HDBM6,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" newline hexmask.long.byte 0x0 6.--10. 1. "L3HSBM6,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" newline bitfld.long 0x0 5. "L3DAIM6,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled" newline bitfld.long 0x0 4. "L3DAM6,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled" newline bitfld.long 0x0 3. "L3SAIM6,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled" newline bitfld.long 0x0 2. "L3SAM6,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled" newline rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1" newline bitfld.long 0x0 0. "L3PEN6,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled" line.long 0x4 "MAC_Layer4_Address6,The MAC_Layer4_Address(#i). MAC_L3_L4_Control(#i). MAC_Layer3_Addr0_Reg(#i). MAC_Layer3_Addr1_Reg(#i). MAC_Layer3_Addr2_Reg(#i) and MAC_Layer3_Addr3_Reg(#i) registers are reserved (RO with default value) if Enable Layer 3 and Layer 4.." hexmask.long.word 0x4 16.--31. 1. "L4DP6,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets" newline hexmask.long.word 0x4 0.--15. 1. "L4SP6,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets" group.long 0xA30++0xF line.long 0x0 "MAC_Layer3_Addr0_Reg6,For IPv4 packets. the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x0 0.--31. 1. "L3A06,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets" line.long 0x4 "MAC_Layer3_Addr1_Reg6,For IPv4 packets. the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x4 0.--31. 1. "L3A16,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets" line.long 0x8 "MAC_Layer3_Addr2_Reg6,The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field." hexmask.long 0x8 0.--31. 1. "L3A26,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets" line.long 0xC "MAC_Layer3_Addr3_Reg6,The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field." hexmask.long 0xC 0.--31. 1. "L3A36,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets" group.long 0xA50++0x7 line.long 0x0 "MAC_L3_L4_Control7,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4." rbitfld.long 0x0 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "DMCHEN7,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled" newline rbitfld.long 0x0 26.--27. "Reserved_27_y,Reserved." "0,1,2,3" newline bitfld.long 0x0 24.--25. "DMCHN7,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1,2,3" newline rbitfld.long 0x0 22.--23. "Reserved_23_22,Reserved." "0,1,2,3" newline bitfld.long 0x0 21. "L4DPIM7,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is disabled,1: Layer 4 Destination Port Inverse Match is enabled" newline bitfld.long 0x0 20. "L4DPM7,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled" newline bitfld.long 0x0 19. "L4SPIM7,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled" newline bitfld.long 0x0 18. "L4SPM7,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled" newline rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1" newline bitfld.long 0x0 16. "L4PEN7,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled" newline hexmask.long.byte 0x0 11.--15. 1. "L3HDBM7,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" newline hexmask.long.byte 0x0 6.--10. 1. "L3HSBM7,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" newline bitfld.long 0x0 5. "L3DAIM7,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled" newline bitfld.long 0x0 4. "L3DAM7,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled" newline bitfld.long 0x0 3. "L3SAIM7,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled" newline bitfld.long 0x0 2. "L3SAM7,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled" newline rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1" newline bitfld.long 0x0 0. "L3PEN7,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled" line.long 0x4 "MAC_Layer4_Address7,The MAC_Layer4_Address(#i). MAC_L3_L4_Control(#i). MAC_Layer3_Addr0_Reg(#i). MAC_Layer3_Addr1_Reg(#i). MAC_Layer3_Addr2_Reg(#i) and MAC_Layer3_Addr3_Reg(#i) registers are reserved (RO with default value) if Enable Layer 3 and Layer 4.." hexmask.long.word 0x4 16.--31. 1. "L4DP7,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets" newline hexmask.long.word 0x4 0.--15. 1. "L4SP7,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets" group.long 0xA60++0x17 line.long 0x0 "MAC_Layer3_Addr0_Reg7,For IPv4 packets. the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x0 0.--31. 1. "L3A07,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets" line.long 0x4 "MAC_Layer3_Addr1_Reg7,For IPv4 packets. the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x4 0.--31. 1. "L3A17,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets" line.long 0x8 "MAC_Layer3_Addr2_Reg7,The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field." hexmask.long 0x8 0.--31. 1. "L3A27,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets" line.long 0xC "MAC_Layer3_Addr3_Reg7,The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field." hexmask.long 0xC 0.--31. 1. "L3A37,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets" line.long 0x10 "MAC_Indir_Access_Ctrl,This register provides the Indirect Access control and status for MAC__ registers." hexmask.long.word 0x10 20.--31. 1. "Reserved_31_20,Reserved." newline hexmask.long.byte 0x10 16.--19. 1. "MSEL,Mode Select This field is used in indirect access of MAC__" newline hexmask.long.byte 0x10 8.--15. 1. "AOFF,Address Offset This field is used in indirect access of MAC__" newline rbitfld.long 0x10 6.--7. "Reserved_7_6,Reserved." "0,1,2,3" newline bitfld.long 0x10 5. "AUTO,Auto increment - 1: AOFF is incremented by 1" "?,1: AOFF is incremented by 1" newline rbitfld.long 0x10 2.--4. "Reserved_4_2,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 1. "COM,Command type This bit indicates the register access type" "0: Write operation,1: Read operation" newline bitfld.long 0x10 0. "OB,Operation Busy" "0,1" line.long 0x14 "MAC_Indir_Access_Data,This register holds the read/write data for Indirect Access of MAC_ registers." hexmask.long 0x14 0.--31. 1. "DATA,This field contains data to read/write for Indirect address access associated with MAC_Indir_Access_Ctrl register" group.long 0xA74++0x3 line.long 0x0 "MAC_TMRQ_Regs0,This register contains the type. associated queue number and paket type (Pre emption/EXpress) related to Type based RXQ mapping." hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved." newline bitfld.long 0x0 20. "PFEX,Preemption or Express Packet This bit indicates if it is a preemption packet or express packet." "0,1" newline rbitfld.long 0x0 19. "Reserved_19,Reserved." "0,1" newline bitfld.long 0x0 16.--18. "TMRQ,Type Match Rx Queue Number Indicates the receive queue number to which the packet needs to be forwarded on detecting a type match" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--15. 1. "TYP,Type field Value Indicates the type value of packet that needs to be compared with received Ethernet packet" group.long 0xA74++0x3 line.long 0x0 "MAC_TMRQ_Regs1,This register contains the type. associated queue number and paket type (Pre emption/EXpress) related to Type based RXQ mapping." hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved." newline bitfld.long 0x0 20. "PFEX,Preemption or Express Packet This bit indicates if it is a preemption packet or express packet." "0,1" newline rbitfld.long 0x0 19. "Reserved_19,Reserved." "0,1" newline bitfld.long 0x0 16.--18. "TMRQ,Type Match Rx Queue Number Indicates the receive queue number to which the packet needs to be forwarded on detecting a type match" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--15. 1. "TYP,Type field Value Indicates the type value of packet that needs to be compared with received Ethernet packet" group.long 0xA74++0x3 line.long 0x0 "MAC_TMRQ_Regs2,This register contains the type. associated queue number and paket type (Pre emption/EXpress) related to Type based RXQ mapping." hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved." newline bitfld.long 0x0 20. "PFEX,Preemption or Express Packet This bit indicates if it is a preemption packet or express packet." "0,1" newline rbitfld.long 0x0 19. "Reserved_19,Reserved." "0,1" newline bitfld.long 0x0 16.--18. "TMRQ,Type Match Rx Queue Number Indicates the receive queue number to which the packet needs to be forwarded on detecting a type match" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--15. 1. "TYP,Type field Value Indicates the type value of packet that needs to be compared with received Ethernet packet" group.long 0xA74++0x3 line.long 0x0 "MAC_TMRQ_Regs3,This register contains the type. associated queue number and paket type (Pre emption/EXpress) related to Type based RXQ mapping." hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved." newline bitfld.long 0x0 20. "PFEX,Preemption or Express Packet This bit indicates if it is a preemption packet or express packet." "0,1" newline rbitfld.long 0x0 19. "Reserved_19,Reserved." "0,1" newline bitfld.long 0x0 16.--18. "TMRQ,Type Match Rx Queue Number Indicates the receive queue number to which the packet needs to be forwarded on detecting a type match" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--15. 1. "TYP,Type field Value Indicates the type value of packet that needs to be compared with received Ethernet packet" group.long 0xA74++0x3 line.long 0x0 "MAC_TMRQ_Regs4,This register contains the type. associated queue number and paket type (Pre emption/EXpress) related to Type based RXQ mapping." hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved." newline bitfld.long 0x0 20. "PFEX,Preemption or Express Packet This bit indicates if it is a preemption packet or express packet." "0,1" newline rbitfld.long 0x0 19. "Reserved_19,Reserved." "0,1" newline bitfld.long 0x0 16.--18. "TMRQ,Type Match Rx Queue Number Indicates the receive queue number to which the packet needs to be forwarded on detecting a type match" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--15. 1. "TYP,Type field Value Indicates the type value of packet that needs to be compared with received Ethernet packet" group.long 0xA74++0x3 line.long 0x0 "MAC_TMRQ_Regs5,This register contains the type. associated queue number and paket type (Pre emption/EXpress) related to Type based RXQ mapping." hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved." newline bitfld.long 0x0 20. "PFEX,Preemption or Express Packet This bit indicates if it is a preemption packet or express packet." "0,1" newline rbitfld.long 0x0 19. "Reserved_19,Reserved." "0,1" newline bitfld.long 0x0 16.--18. "TMRQ,Type Match Rx Queue Number Indicates the receive queue number to which the packet needs to be forwarded on detecting a type match" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--15. 1. "TYP,Type field Value Indicates the type value of packet that needs to be compared with received Ethernet packet" group.long 0xA74++0x3 line.long 0x0 "MAC_TMRQ_Regs6,This register contains the type. associated queue number and paket type (Pre emption/EXpress) related to Type based RXQ mapping." hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved." newline bitfld.long 0x0 20. "PFEX,Preemption or Express Packet This bit indicates if it is a preemption packet or express packet." "0,1" newline rbitfld.long 0x0 19. "Reserved_19,Reserved." "0,1" newline bitfld.long 0x0 16.--18. "TMRQ,Type Match Rx Queue Number Indicates the receive queue number to which the packet needs to be forwarded on detecting a type match" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--15. 1. "TYP,Type field Value Indicates the type value of packet that needs to be compared with received Ethernet packet" group.long 0xA74++0x3 line.long 0x0 "MAC_TMRQ_Regs7,This register contains the type. associated queue number and paket type (Pre emption/EXpress) related to Type based RXQ mapping." hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved." newline bitfld.long 0x0 20. "PFEX,Preemption or Express Packet This bit indicates if it is a preemption packet or express packet." "0,1" newline rbitfld.long 0x0 19. "Reserved_19,Reserved." "0,1" newline bitfld.long 0x0 16.--18. "TMRQ,Type Match Rx Queue Number Indicates the receive queue number to which the packet needs to be forwarded on detecting a type match" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--15. 1. "TYP,Type field Value Indicates the type value of packet that needs to be compared with received Ethernet packet" group.long 0xB00++0x7 line.long 0x0 "MAC_Timestamp_Control,This register controls the operation of the System Time generator and processing of PTP packets for timestamping in the Receiver." rbitfld.long 0x0 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "AV8021ASMEN,AV 802" "0: AV 802.1AS Mode is disabled,1: AV 802.1AS Mode is enabled" newline rbitfld.long 0x0 25.--27. "Reserved_27_25,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24. "TXTSSTSM,Transmit Timestamp Status Mode When this bit is set the MAC overwrites the earlier transmit timestamp status even if it is not read by the software" "0: Transmit Timestamp Status Mode is disabled,1: Transmit Timestamp Status Mode is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ESTI,External System Time Input When this bit is set the MAC uses the external 64-bit reference System Time input for the following: - To take the timestamp provided as status - To insert the timestamp in transmit PTP packets when One-step Timestamp or.." "0: External System Time Input is disabled,1: External System Time Input is enabled" newline rbitfld.long 0x0 19. "Reserved_CSC,Reserved." "0,1" newline bitfld.long 0x0 18. "TSENMACADDR,Enable MAC Address for PTP Packet Filtering When this bit is set the DA MAC address (that matches any MAC Address register) is used to filter the PTP packets when PTP is directly sent over Ethernet" "0: MAC Address for PTP Packet Filtering is disabled,1: MAC Address for PTP Packet Filtering is enabled" newline bitfld.long 0x0 16.--17. "SNAPTYPSEL,Select PTP packets for Taking Snapshots These bits along with Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken" "0,1,2,3" newline bitfld.long 0x0 15. "TSMSTRENA,Enable Snapshot for Messages Relevant to Master When this bit is set the snapshot is taken only for the messages that are relevant to the master node" "0: Snapshot for Messages Relevant to Master is..,1: Snapshot for Messages Relevant to Master is.." newline bitfld.long 0x0 14. "TSEVNTENA,Enable Timestamp Snapshot for Event Messages When this bit is set the timestamp snapshot is taken only for event messages (SYNC Delay_Req Pdelay_Req or Pdelay_Resp)" "0: Timestamp Snapshot for Event Messages is disabled,1: Timestamp Snapshot for Event Messages is enabled" newline bitfld.long 0x0 13. "TSIPV4ENA,Enable Processing of PTP Packets Sent over IPv4-UDP When this bit is set the MAC receiver processes the PTP packets encapsulated in IPv4-UDP packets" "0: Processing of PTP Packets Sent over IPv4-UDP is..,1: Processing of PTP Packets Sent over IPv4-UDP is.." newline bitfld.long 0x0 12. "TSIPV6ENA,Enable Processing of PTP Packets Sent over IPv6-UDP When this bit is set the MAC receiver processes the PTP packets encapsulated in IPv6-UDP packets" "0: Processing of PTP Packets Sent over IPv6-UDP is..,1: Processing of PTP Packets Sent over IPv6-UDP is.." newline bitfld.long 0x0 11. "TSIPENA,Enable Processing of PTP over Ethernet Packets When this bit is set the MAC receiver processes the PTP packets encapsulated directly in the Ethernet packets" "0: Processing of PTP over Ethernet Packets is..,1: Processing of PTP over Ethernet Packets is enabled" newline bitfld.long 0x0 10. "TSVER2ENA,Enable PTP Packet Processing for Version 2 Format When this bit is set the IEEE 1588 version 2 format is used to process the PTP packets" "0: PTP Packet Processing for Version 2 Format is..,1: PTP Packet Processing for Version 2 Format is.." newline bitfld.long 0x0 9. "TSCTRLSSR,Timestamp Digital or Binary Rollover Control When this bit is set the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is 1 nanosecond accuracy) and increments the timestamp (High) seconds" "0: Timestamp Digital or Binary Rollover Control is..,1: Timestamp Digital or Binary Rollover Control is.." newline bitfld.long 0x0 8. "TSENALL,Enable Timestamp for All Packets When this bit is set the timestamp snapshot is enabled for all packets received by the MAC" "0: Timestamp for All Packets disabled,1: Timestamp for All Packets enabled" newline rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1" newline bitfld.long 0x0 6. "PTGE,Presentation Time Generation Enable When this bit is set the Presentation Time generation is enabled" "0: Presentation Time Generation is disabled,1: Presentation Time Generation is enabled" newline bitfld.long 0x0 5. "TSADDREG,Update Addend Register When this bit is set the content of the Timestamp Addend register is updated in the PTP block for fine correction" "0: Addend Register is not updated,1: Addend Register is updated" newline rbitfld.long 0x0 4. "Reserved_TSTRIG,Reserved." "0,1" newline bitfld.long 0x0 3. "TSUPDT,Update Timestamp When this bit is set the system time is updated (added or subtracted) with the value specified in MAC_System_Time_Seconds_Update and MAC_System_Time_Nanoseconds_Update registers" "0: Timestamp is not updated,1: Timestamp is updated" newline bitfld.long 0x0 2. "TSINIT,Initialize Timestamp When this bit is set the system time is initialized (overwritten) with the value specified in the MAC_System_Time_Seconds_Update and MAC_System_Time_Nanoseconds_Update registers" "0: Timestamp is not initialized,1: Timestamp is initialized" newline bitfld.long 0x0 1. "TSCFUPDT,Fine or Coarse Timestamp Update When this bit is set the Fine method is used to update system timestamp" "0: Coarse method is used to update system timestamp,1: Fine method is used to update system timestamp" newline bitfld.long 0x0 0. "TSENA,Enable Timestamp When this bit is set the timestamp is added for Transmit and Receive packets" "0: Timestamp is disabled,1: Timestamp is enabled" line.long 0x4 "MAC_Sub_Second_Increment,This register specifies the value to be added to the internal system time register every cycle of clk_ptp_ref_i clock." hexmask.long.byte 0x4 24.--31. 1. "Reserved_31_24,Reserved." newline hexmask.long.byte 0x4 16.--23. 1. "SSINC,Sub-second Increment Value The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register" newline hexmask.long.byte 0x4 8.--15. 1. "SNSINC,Sub-nanosecond Increment Value This field contains the sub-nanosecond increment value represented in nanoseconds multiplied by 2^8" newline hexmask.long.byte 0x4 0.--7. 1. "Reserved_7_0,Reserved." rgroup.long 0xB08++0x7 line.long 0x0 "MAC_System_Time_Seconds,The System Time Seconds register. along with System Time Nanoseconds register. indicates the current value of the system time maintained by the MAC. Though it is updated on a continuous basis. there is some delay from the actual.." hexmask.long 0x0 0.--31. 1. "TSS,Timestamp Second The value in this field indicates the current value in seconds of the System Time maintained by the MAC" line.long 0x4 "MAC_System_Time_Nanoseconds,The System Time Nanoseconds register. along with System Time Seconds register. indicates the current value of the system time maintained by the MAC." bitfld.long 0x4 31. "Reserved_31,Reserved." "0,1" newline hexmask.long 0x4 0.--30. 1. "TSSS,Timestamp Sub Seconds The value in this field has the sub-second representation of time with an accuracy of 0" group.long 0xB10++0xF line.long 0x0 "MAC_System_Time_Seconds_Update,The System Time Seconds Update register. along with the System Time Nanoseconds Update register. initializes or updates the system time maintained by the MAC. You must write both registers before setting the TSINIT or.." hexmask.long 0x0 0.--31. 1. "TSS,Timestamp Seconds The value in this field is the seconds part of the update" line.long 0x4 "MAC_System_Time_Nanoseconds_Update,MAC System Time Nanoseconds Update register." bitfld.long 0x4 31. "ADDSUB,Add or Subtract Time When this bit is set the time value is subtracted with the contents of the update register" "0: Add time,1: Subtract time" newline hexmask.long 0x4 0.--30. 1. "TSSS,Timestamp Sub Seconds The value in this field is the sub-seconds part of the update" line.long 0x8 "MAC_Timestamp_Addend,Timestamp Addend register. This register value is used only when the system time is configured for Fine Update mode (TSCFUPDT bit in the MAC_Timestamp_Control register). The content of this register is added to a 32-bit accumulator.." hexmask.long 0x8 0.--31. 1. "TSAR,Timestamp Addend Register This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization" line.long 0xC "MAC_System_Time_Higher_Word_Seconds,System Time - Higher Word Seconds register." hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved." newline hexmask.long.word 0xC 0.--15. 1. "TSHWR,Timestamp Higher Word Register This field contains the most-significant 16-bits of timestamp seconds value" rgroup.long 0xB20++0x3 line.long 0x0 "MAC_Timestamp_Status,Timestamp Status register. All bits except Bits[27:25] gets cleared when the application reads this register." bitfld.long 0x0 30.--31. "Reserved_31_30,Reserved." "0,1,2,3" newline hexmask.long.byte 0x0 25.--29. 1. "Reserved_ATSNS,Reserved." newline bitfld.long 0x0 24. "Reserved_ATSSTM,Reserved." "0,1" newline hexmask.long.byte 0x0 20.--23. 1. "Reserved_23_20,Reserved." newline hexmask.long.byte 0x0 16.--19. 1. "Reserved_ATSSTN,Reserved." newline bitfld.long 0x0 15. "TXTSSIS,Tx Timestamp Status Interrupt Status In non-EQOS_CORE configurations when drop transmit status is enabled in MTL this bit is set when the captured transmit timestamp is updated in the MAC_Tx_Timestamp_Status_Nanoseconds and.." "0: Tx Timestamp Status Interrupt status not detected,1: Tx Timestamp Status Interrupt status detected" newline hexmask.long.byte 0x0 10.--14. 1. "Reserved_14_10,Reserved." newline bitfld.long 0x0 9. "TSTRGTERR3,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS3_Target_Time_Seconds and MAC_PPS3_Target_Time_Nanoseconds registers elapses" "0: Timestamp Target Time Error status not detected,1: Timestamp Target Time Error status detected" newline bitfld.long 0x0 8. "TSTARGT3,Timestamp Target Time Reached for Target Time PPS3 When this bit is set and MCGREN3 of MAC_PPS_Control register is reset it indicates that the value of system time is greater than or equal to the value specified in the.." "0: Timestamp Target Time Reached for Target Time..,1: Timestamp Target Time Reached for Target Time.." newline bitfld.long 0x0 7. "TSTRGTERR2,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS2_Target_Time_Seconds and MAC_PPS2_Target_Time_Nanoseconds registers elapses" "0: Timestamp Target Time Error status not detected,1: Timestamp Target Time Error status detected" newline bitfld.long 0x0 6. "TSTARGT2,Timestamp Target Time Reached for Target Time PPS2 When this bit is set and MCGREN2 of MAC_PPS_Control register is reset it indicates that the value of system time is greater than or equal to the value specified in the.." "0: Timestamp Target Time Reached for Target Time..,1: Timestamp Target Time Reached for Target Time.." newline bitfld.long 0x0 5. "TSTRGTERR1,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS1_Target_Time_Seconds and MAC_PPS1_Target_Time_Nanoseconds registers elapses" "0: Timestamp Target Time Error status not detected,1: Timestamp Target Time Error status detected" newline bitfld.long 0x0 4. "TSTARGT1,Timestamp Target Time Reached for Target Time PPS1 When this bit is set and MCGREN1 of MAC_PPS_Control register is reset it indicates that the value of system time is greater than or equal to the value specified in the.." "0: Timestamp Target Time Reached for Target Time..,1: Timestamp Target Time Reached for Target Time.." newline bitfld.long 0x0 3. "TSTRGTERR0,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS0_Target_Time_Seconds and MAC_PPS0_Target_Time_Nanoseconds registers elapses" "0: Timestamp Target Time Error status not detected,1: Timestamp Target Time Error status detected" newline bitfld.long 0x0 2. "Reserved_AUXTSTRIG,Reserved." "0,1" newline bitfld.long 0x0 1. "TSTARGT0,Timestamp Target Time Reached When this bit is set and MCGREN0 of MAC_PPS_Control register is reset it indicates that the value of system time is greater than or equal to the value specified in the MAC_PPS0_Target_Time_Seconds and.." "0: Timestamp Target Time Reached status not detected,1: Timestamp Target Time Reached status detected" newline bitfld.long 0x0 0. "TSSOVF,Timestamp Seconds Overflow When this bit is set it indicates that the seconds value of the timestamp (when supporting version 2 format) has overflowed beyond 32'hFFFF_FFFF" "0: Timestamp Seconds Overflow status not detected,1: Timestamp Seconds Overflow status detected" rgroup.long 0xB30++0x7 line.long 0x0 "MAC_Tx_Timestamp_Status_Nanoseconds,This register contains the nanosecond part of timestamp captured for Transmit packets when Tx status is disabled. The MAC_Tx_Timestamp_Status_Nanoseconds register. along with MAC_Tx_Timestamp_Status_Seconds. gives the.." bitfld.long 0x0 31. "TXTSSMIS,Transmit Timestamp Status Missed When this bit is set it indicates one of the following: - The timestamp of the current packet is ignored if TXTSSTSM bit of the MAC_Timestamp_Control register is reset - The timestamp of the previous packet is.." "0: Transmit Timestamp Status Missed status not..,1: Transmit Timestamp Status Missed status detected" newline hexmask.long 0x0 0.--30. 1. "TXTSSLO,Transmit Timestamp Status Low This field contains the 31 bits of the Nanoseconds field of the Transmit packet's captured timestamp" line.long 0x4 "MAC_Tx_Timestamp_Status_Seconds,The register contains the higher 32 bits of the timestamp (in seconds) captured when a PTP packet is transmitted." hexmask.long 0x4 0.--31. 1. "TXTSSHI,Transmit Timestamp Status High This field contains the lower 32 bits of the Seconds field of Transmit packet's captured timestamp" group.long 0xB50++0x17 line.long 0x0 "MAC_Timestamp_Ingress_Asym_Corr,The MAC Timestamp Ingress Asymmetry Correction register contains the Ingress Asymmetry Correction value to be used while updating correction field in PDelay_Resp PTP messages." hexmask.long 0x0 0.--31. 1. "OSTIAC,One-Step Timestamp Ingress Asymmetry Correction This field contains the ingress path asymmetry value to be added to correctionField of Pdelay_Resp PTP packet" line.long 0x4 "MAC_Timestamp_Egress_Asym_Corr,The MAC Timestamp Egress Asymmetry Correction register contains the Egress Asymmetry Correction value to be used while updating the correction field in PDelay_Req PTP messages." hexmask.long 0x4 0.--31. 1. "OSTEAC,One-Step Timestamp Egress Asymmetry Correction This field contains the egress path asymmetry value to be subtracted from correctionField of Pdelay_Resp PTP packet" line.long 0x8 "MAC_Timestamp_Ingress_Corr_Nanosecond,This register contains the correction value in nanoseconds to be used with the captured timestamp value in the ingress path." hexmask.long 0x8 0.--31. 1. "TSIC,Timestamp Ingress Correction This field contains the ingress path correction value as defined by the Ingress Correction expression" line.long 0xC "MAC_Timestamp_Egress_Corr_Nanosecond,This register contains the correction value in nanoseconds to be used with the captured timestamp value in the egress path." hexmask.long 0xC 0.--31. 1. "TSEC,Timestamp Egress Correction This field contains the nanoseconds part of the egress path correction value as defined by the Egress Correction expression" line.long 0x10 "MAC_Timestamp_Ingress_Corr_Subnanosec,This register contains the sub-nanosecond part of the correction value to be used with the captured timestamp value. for ingress direction." hexmask.long.word 0x10 16.--31. 1. "Reserved_31_16,Reserved." newline hexmask.long.byte 0x10 8.--15. 1. "TSICSNS,Timestamp Ingress Correction sub-nanoseconds This field contains the sub-nanoseconds part of the ingress path correction value as defined by the 'Ingress Correction' expression" newline hexmask.long.byte 0x10 0.--7. 1. "Reserved_7_0,Reserved." line.long 0x14 "MAC_Timestamp_Egress_Corr_Subnanosec,This register contains the sub-nanosecond part of the correction value to be used with the captured timestamp value. for egress direction." hexmask.long.word 0x14 16.--31. 1. "Reserved_31_16,Reserved." newline hexmask.long.byte 0x14 8.--15. 1. "TSECSNS,Timestamp Egress Correction sub-nanoseconds This field contains the sub-nanoseconds part of the egress path correction value as defined by the 'Egress Correction' expression" newline hexmask.long.byte 0x14 0.--7. 1. "Reserved_7_0,Reserved." rgroup.long 0xB68++0x7 line.long 0x0 "MAC_Timestamp_Ingress_Latency,This register holds the Ingress MAC latency." hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_28,Reserved." newline hexmask.long.word 0x0 16.--27. 1. "ITLNS,Ingress Timestamp Latency in sub-nanoseconds This register holds the average latency in sub-nanoseconds between the input ports (phy_rxd_i) of MAC and the actual point (GMII/MII) where the ingress timestamp is taken" newline hexmask.long.byte 0x0 8.--15. 1. "ITLSNS,Ingress Timestamp Latency in nanoseconds This register holds the average latency in nanoseconds between the input ports (phy_rxd_i) of MAC and the actual point (GMII/MII) where the ingress timestamp is taken" newline hexmask.long.byte 0x0 0.--7. 1. "Reserved_7_0,Reserved." line.long 0x4 "MAC_Timestamp_Egress_Latency,This register holds the Egress MAC latency." hexmask.long.byte 0x4 28.--31. 1. "Reserved_31_28,Reserved." newline hexmask.long.word 0x4 16.--27. 1. "ETLNS,Egress Timestamp Latency in nanoseconds This register holds the average latency in nanoseconds between the actual point (GMII/MII) where the egress timestamp is taken and the output ports (phy_txd_o) of the MAC" newline hexmask.long.byte 0x4 8.--15. 1. "ETLSNS,Egress Timestamp Latency in sub-nanoseconds This register holds the average latency in sub-nanoseconds between the actual point (GMII/MII) where the egress timestamp is taken and the output ports (phy_txd_o) of the MAC" newline hexmask.long.byte 0x4 0.--7. 1. "Reserved_7_0,Reserved." group.long 0xB70++0x3 line.long 0x0 "MAC_PPS_Control,PPS Control register. Bits[30:24] of this register are valid only when four Flexible PPS outputs are selected. Bits[22:16] are valid only when three or more Flexible PPS outputs are selected. Bits[14:8] are valid only when two or more.." bitfld.long 0x0 31. "MCGREN3,MCGR Mode Enable for PPS3 Output This field enables the 3rd PPS instance to operate in PPS or MCGR mode" "0,1" newline bitfld.long 0x0 29.--30. "TRGTMODSEL3,Target Time Register Mode for PPS3 Output This field indicates the Target Time registers (MAC_PPS3_Target_Time_Seconds and MAC_PPS3_Target_Time_Nanoseconds) mode for PPS3 output signal" "0: Target Time registers are programmed only for..,1: Enables MCGR Interrupt whose status bit is..,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.." newline bitfld.long 0x0 28. "TIMESEL,Time Select When this bit is set 64 bit PTP time is used to capture time at MCGR trigger[0] input When this bit is reset presentation time is used to capture time at trigger input maintaining backward compatibility" "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "PPSCMD3,Flexible PPS3 Output Control This field controls the flexible PPS3 output (ptp_pps_o[3]) signal" newline bitfld.long 0x0 23. "MCGREN2,MCGR Mode Enable for PPS2 Output This field enables the 2nd PPS instance to operate in PPS or MCGR mode" "0: 2nd PPS instance is disabled to operate in PPS..,1: 2nd PPS instance is enabled to operate in PPS or.." newline bitfld.long 0x0 21.--22. "TRGTMODSEL2,Target Time Register Mode for PPS2 Output This field indicates the Target Time registers (MAC_PPS2_Target_Time_Seconds and MAC_PPS2_Target_Time_Nanoseconds) mode for PPS2 output signal" "0: Target Time registers are programmed only for..,1: Enables MCGR Interrupt whose status bit is..,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.." newline rbitfld.long 0x0 20. "Reserved_20,Reserved." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "PPSCMD2,Flexible PPS2 Output Control This field controls the flexible PPS2 output (ptp_pps_o[2]) signal" newline bitfld.long 0x0 15. "MCGREN1,MCGR Mode Enable for PPS1 Output This field enables the 1st PPS instance to operate in PPS or MCGR mode" "0: 1st PPS instance is disabled to operate in PPS..,1: 1st PPS instance is enabled to operate in PPS or.." newline bitfld.long 0x0 13.--14. "TRGTMODSEL1,Target Time Register Mode for PPS1 Output This field indicates the Target Time registers (MAC_PPS1_Target_Time_Seconds and MAC_PPS1_Target_Time_Nanoseconds) mode for PPS1 output signal" "0: Target Time registers are programmed only for..,1: Enables MCGR Interrupt whose status bit is..,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.." newline rbitfld.long 0x0 12. "Reserved_12,Reserved." "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "PPSCMD1,Flexible PPS1 Output Control This field controls the flexible PPS1 output (ptp_pps_o[1]) signal" newline bitfld.long 0x0 7. "MCGREN0,MCGR Mode Enable for PPS0 Output This field enables the 0th PPS instance to operate in PPS or MCGR mode" "0: 0th PPS instance is enabled to operate in PPS mode,1: 0th PPS instance is enabled to operate in MCGR.." newline bitfld.long 0x0 5.--6. "TRGTMODSEL0,Target Time Register Mode for PPS0 Output This field indicates the Target Time registers (MAC_PPS0_Target_Time_Seconds and MAC_PPS0_Target_Time_Nanoseconds) mode for PPS0 output signal:" "0: Target Time registers are programmed only for..,1: Enables MCGR Interrupt whose status bit is..,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.." newline bitfld.long 0x0 4. "PPSEN0,Flexible PPS Output Mode Enable When this bit is - 1: Bits[3:0] function as PPSCMD" "0: Flexible PPS Output Mode is disabled,1: Bits[3:0] function as PPSCMD" newline hexmask.long.byte 0x0 0.--3. 1. "PPSCTRL_PPSCMD,PPS Output Frequency Control This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal" group.long 0xB80++0x3F line.long 0x0 "MAC_PPS0_Target_Time_Seconds,The PPS Target Time Seconds register. along with PPS Target Time Nanoseconds register. is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these registers." hexmask.long 0x0 0.--31. 1. "TSTRH0,PPS Target Time Seconds Register This field stores the time in seconds" line.long 0x4 "MAC_PPS0_Target_Time_Nanoseconds,PPS0 Target Time Nanoseconds register." bitfld.long 0x4 31. "TRGTBUSY0,PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the MAC_PPS_Control register is programmed to 010 or 011" "0: PPS Target Time Register Busy status is not..,1: PPS Target Time Register Busy is detected" newline hexmask.long 0x4 0.--30. 1. "TTSL0,Target Time Low for PPS Register This register stores the time in (signed) nanoseconds" line.long 0x8 "MAC_PPS0_Interval,The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0x8 0.--31. 1. "PPSINT0,PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output" line.long 0xC "MAC_PPS0_Width,The PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0xC 0.--31. 1. "PPSWIDTH0,PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output" line.long 0x10 "MAC_PPS1_Target_Time_Seconds,The PPS Target Time Seconds register. along with PPS Target Time Nanoseconds register. is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these registers." hexmask.long 0x10 0.--31. 1. "TSTRH1,PPS Target Time Seconds Register This field stores the time in seconds" line.long 0x14 "MAC_PPS1_Target_Time_Nanoseconds,PPS0 Target Time Nanoseconds register." bitfld.long 0x14 31. "TRGTBUSY1,PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the MAC_PPS_Control register is programmed to 010 or 011" "0: PPS Target Time Register Busy status is not..,1: PPS Target Time Register Busy is detected" newline hexmask.long 0x14 0.--30. 1. "TTSL1,Target Time Low for PPS Register This register stores the time in (signed) nanoseconds" line.long 0x18 "MAC_PPS1_Interval,The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0x18 0.--31. 1. "PPSINT1,PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output" line.long 0x1C "MAC_PPS1_Width,The PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0x1C 0.--31. 1. "PPSWIDTH1,PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output" line.long 0x20 "MAC_PPS2_Target_Time_Seconds,The PPS Target Time Seconds register. along with PPS Target Time Nanoseconds register. is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these registers." hexmask.long 0x20 0.--31. 1. "TSTRH2,PPS Target Time Seconds Register This field stores the time in seconds" line.long 0x24 "MAC_PPS2_Target_Time_Nanoseconds,PPS0 Target Time Nanoseconds register." bitfld.long 0x24 31. "TRGTBUSY2,PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the MAC_PPS_Control register is programmed to 010 or 011" "0: PPS Target Time Register Busy status is not..,1: PPS Target Time Register Busy is detected" newline hexmask.long 0x24 0.--30. 1. "TTSL2,Target Time Low for PPS Register This register stores the time in (signed) nanoseconds" line.long 0x28 "MAC_PPS2_Interval,The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0x28 0.--31. 1. "PPSINT2,PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output" line.long 0x2C "MAC_PPS2_Width,The PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0x2C 0.--31. 1. "PPSWIDTH2,PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output" line.long 0x30 "MAC_PPS3_Target_Time_Seconds,The PPS Target Time Seconds register. along with PPS Target Time Nanoseconds register. is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these registers." hexmask.long 0x30 0.--31. 1. "TSTRH3,PPS Target Time Seconds Register This field stores the time in seconds" line.long 0x34 "MAC_PPS3_Target_Time_Nanoseconds,PPS0 Target Time Nanoseconds register." bitfld.long 0x34 31. "TRGTBUSY3,PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the MAC_PPS_Control register is programmed to 010 or 011" "0: PPS Target Time Register Busy status is not..,1: PPS Target Time Register Busy is detected" newline hexmask.long 0x34 0.--30. 1. "TTSL3,Target Time Low for PPS Register This register stores the time in (signed) nanoseconds" line.long 0x38 "MAC_PPS3_Interval,The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0x38 0.--31. 1. "PPSINT3,PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output" line.long 0x3C "MAC_PPS3_Width,The PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0x3C 0.--31. 1. "PPSWIDTH3,PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output" group.long 0xC00++0x3 line.long 0x0 "MTL_Operation_Mode,The Operation Mode register establishes the Transmit and Receive operating modes and commands." hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved." newline bitfld.long 0x0 15. "FRPE,Flexible Rx parser Enable - 1: Enables Programmable Rx Parser - 0: Disables Programmable Rx Parser When the Rx parser is disabled when parsing is in progress the Rx parser is disabled only after the current packet parsing complete" "0: Disables Programmable Rx Parser When the Rx..,1: Enables Programmable Rx Parser" newline bitfld.long 0x0 14. "RXPED,RxParser Software Error/Incomplete Parsing Packet Drop Enable when this bit is set to 0 packets encountering software programming errors (NPE/NVE/frame offset overflow errors) or incomplete parsing are forwarded to application with the.." "0: Flexible Rx parser packet drop in case software..,1: Flexible Rx parser packet drop in case software.." newline hexmask.long.byte 0x0 10.--13. 1. "Reserved_13_10,Reserved." newline bitfld.long 0x0 9. "CNTCLR,Counters Reset When this bit is set all counters are reset" "0: Counters are not reset,1: All counters are reset" newline bitfld.long 0x0 8. "CNTPRST,Counters Preset When this bit is set - MTL_TxQ[0-7]_Underflow register is initialized/preset to 12'h7F0" "0: Counters Preset is disabled,1: Counters Preset is enabled" newline rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1" newline bitfld.long 0x0 5.--6. "SCHALG,Tx Scheduling Algorithm This field indicates the algorithm for Tx scheduling:" "0: WRR algorithm,1: WFQ algorithm when DCB feature is..,2: DWRR algorithm when DCB feature is..,3: Strict priority algorithm" newline rbitfld.long 0x0 3.--4. "Reserved_4_3,Reserved." "0,1,2,3" newline bitfld.long 0x0 2. "RAA,Receive Arbitration Algorithm This field is used to select the arbitration algorithm for the Rx side" "0: Strict priority (SP),1: Weighted Strict Priority (WSP)" newline bitfld.long 0x0 1. "DTXSTS,Drop Transmit Status - 1: Tx packet status received from the MAC is dropped in the MTL - 0: Tx packet status received from the MAC is forwarded to the application" "0: Tx packet status received from the MAC is..,1: Tx packet status received from the MAC is.." newline rbitfld.long 0x0 0. "Reserved_0,Reserved." "0,1" group.long 0xC08++0xB line.long 0x0 "MTL_DBG_CTL,The FIFO Debug Access Control and Status register controls the operation mode of FIFO debug access." hexmask.long.word 0x0 19.--31. 1. "Reserved_31_19,Reserved." newline bitfld.long 0x0 18. "EIEC,ECC Inject Error Control for Tx Rx TSO and DCACHE memories When EIEE or EIAEE bit of this register is set following are the errors inserted based on the value encoded in this field" "0: Insert 1 bit error,1: insert 2 bit errors" newline bitfld.long 0x0 17. "EIAEE,ECC Inject Address Error for Tx Rx TSO and DCACHE memories - 1: Enables the ECC address error injection feature - 0: Disables the ECC address error injection feature" "0: Disables the ECC address error injection feature,1: Enables the ECC address error injection feature" newline bitfld.long 0x0 16. "EIEE,ECC Inject Error Enable for Tx Rx TSO and DCACHE memories - 1: Enables the ECC error injection feature - 0: Disables the ECC error injection feature" "0: Disables the ECC error injection feature,1: Enables the ECC error injection feature" newline bitfld.long 0x0 15. "STSIE,Transmit Status Available Interrupt Status Enable When this bit is set an interrupt is generated when Transmit status is available in slave mode" "0: Transmit Packet Available Interrupt Status is..,1: Transmit Packet Available Interrupt Status is.." newline bitfld.long 0x0 14. "PKTIE,Receive Packet Available Interrupt Status Enable When this bit is set an interrupt is generated when EOP of received packet is written to the Rx FIFO" "0: Receive Packet Available Interrupt Status is..,1: Receive Packet Available Interrupt Status is.." newline bitfld.long 0x0 12.--13. "FIFOSEL,FIFO Selected for Access This field indicates the FIFO selected for debug access." "0: Tx FIFO,1: Tx Status FIFO (only read access when SLVMOD is..,2: TSO FIFO (cannot be accessed when SLVMOD is set),3: Rx FIFO" newline bitfld.long 0x0 11. "FIFOWREN,FIFO Write Enable When this bit is set it enables the Write operation on selected FIFO when FIFO Debug Access is enabled" "0: FIFO Write is disabled,1: FIFO Write is enabled" newline bitfld.long 0x0 10. "FIFORDEN,FIFO Read Enable When this bit is set it enables the Read operation on selected FIFO when FIFO Debug Access is enabled" "0: FIFO Read is disabled,1: FIFO Read is enabled" newline bitfld.long 0x0 9. "RSTSEL,Reset Pointers of Selected FIFO When this bit is set the pointers of the currently-selected FIFO are reset when FIFO Debug Access is enabled" "0: Reset Pointers of Selected FIFO is disabled,1: Reset Pointers of Selected FIFO is enabled" newline bitfld.long 0x0 8. "RSTALL,Reset All Pointers When this bit is set the pointers of all FIFOs are reset when FIFO Debug Access is enabled" "0: Reset All Pointers is disabled,1: Reset All Pointers is enabled" newline rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1" newline bitfld.long 0x0 5.--6. "PKTSTATE,Encoded Packet State This field is used to write the control information to the Tx FIFO or Rx FIFO" "0: Packet Data,1: Control Word/Normal Status,2: SOP Data/Last Status,3: EOP Data/EOP" newline rbitfld.long 0x0 4. "Reserved_4,Reserved." "0,1" newline bitfld.long 0x0 2.--3. "BYTEEN,Byte Enables This field indicates the number of data bytes valid in the data register during Write operation" "0: Byte 0 valid,1: Byte 0 and Byte 1 are valid,2: Byte 0 Byte 1 and Byte 2 are valid,3: All four bytes are valid" newline bitfld.long 0x0 1. "DBGMOD,Debug Mode Access to FIFO - 1: Indicates that the current access to the FIFO is read write and debug access" "0: Debug Mode Access to FIFO is disabled,1: Indicates that the current access to the FIFO is.." newline bitfld.long 0x0 0. "FDBGEN,FIFO Debug Access Enable - 1: Indicates that the debug mode access to the FIFO is enabled" "0: FIFO Debug Access is disabled,1: Indicates that the debug mode access to the FIFO.." line.long 0x4 "MTL_DBG_STS,The FIFO Debug Status register contains the status of FIFO debug access." hexmask.long.tbyte 0x4 15.--31. 1. "LOCR,Remaining Locations in the FIFO - Slave Access Mode: This field indicates the space available in the selected FIFO" newline hexmask.long.byte 0x4 10.--14. 1. "Reserved_14_10,Reserved." newline bitfld.long 0x4 9. "STSI,Transmit Status Available Interrupt Status When set this bit indicates that the Slave mode Tx packet is transmitted and the status is available in Tx Status FIFO" "0: Transmit Status Available Interrupt Status not..,1: Transmit Status Available Interrupt Status.." newline bitfld.long 0x4 8. "PKTI,Receive Packet Available Interrupt Status When set this bit indicates that MAC layer has written the EOP of received packet to the Rx FIFO" "0: Receive Packet Available Interrupt Status not..,1: Receive Packet Available Interrupt Status detected" newline rbitfld.long 0x4 5.--7. "Reserved_7_5,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 3.--4. "BYTEEN,Byte Enables This field indicates the number of data bytes valid in the data register during Read operation" "0: Byte 0 valid,1: Byte 0 and Byte 1 are valid,2: Byte 0 Byte 1 and Byte 2 are valid,3: All four bytes are valid" newline rbitfld.long 0x4 1.--2. "PKTSTATE,Encoded Packet State This field is used to get the control or status information of the selected FIFO" "0: Packet Data,1: Control Word/Normal Status,2: SOP Data/Last Status,3: EOP Data/EOP" newline rbitfld.long 0x4 0. "FIFOBUSY,FIFO Busy When set this bit indicates that a FIFO operation is in progress in the MAC and content of the following fields is not valid: - All other fields of this register - All fields of the MTL_FIFO_Debug_Data register" "0: FIFO Busy not detected,1: FIFO Busy detected" line.long 0x8 "MTL_FIFO_Debug_Data,The FIFO Debug Data register contains the data to be written to or read from the FIFOs." hexmask.long 0x8 0.--31. 1. "FDBGDATA,FIFO Debug Data During debug or slave access write operation this field contains the data to be written to the Tx FIFO Rx FIFO or TSO FIFO" rgroup.long 0xC20++0x3 line.long 0x0 "MTL_Interrupt_Status,The software driver (application) reads this register during interrupt service routine or polling to determine the interrupt status of MTL queues and the MAC." hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved." newline bitfld.long 0x0 23. "MTLPIS,MTL Rx Parser Interrupt Status This bit indicates that there is an interrupt from Rx Parser Block" "0: MTL Rx Parser Interrupt status not detected,1: MTL Rx Parser Interrupt status detected" newline hexmask.long.byte 0x0 19.--22. 1. "Reserved_22_19,Reserved." newline bitfld.long 0x0 18. "ESTIS,EST (TAS- 802" "0: EST (TAS- 802.1Qbv) Interrupt status not detected,1: EST (TAS- 802.1Qbv) Interrupt status detected" newline bitfld.long 0x0 17. "DBGIS,Debug Interrupt status This bit indicates an interrupt event during the slave access" "0: Debug Interrupt status not detected,1: Debug Interrupt status detected" newline bitfld.long 0x0 16. "Reserved_MACIS,Reserved." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "Reserved_15_8,Reserved." newline bitfld.long 0x0 7. "Reserved_Q7IS,Reserved." "0,1" newline bitfld.long 0x0 6. "Reserved_Q6IS,Reserved." "0,1" newline bitfld.long 0x0 5. "Reserved_Q5IS,Reserved." "0,1" newline bitfld.long 0x0 4. "Reserved_Q4IS,Reserved." "0,1" newline bitfld.long 0x0 3. "Reserved_Q3IS,Reserved." "0,1" newline bitfld.long 0x0 2. "Q2IS,Queue 2 Interrupt status This bit indicates that there is an interrupt from Queue 2" "0: Queue 2 Interrupt status not detected,1: Queue 2 Interrupt status detected" newline bitfld.long 0x0 1. "Q1IS,Queue 1 Interrupt status This bit indicates that there is an interrupt from Queue 1" "0: Queue 1 Interrupt status not detected,1: Queue 1 Interrupt status detected" newline bitfld.long 0x0 0. "Q0IS,Queue 0 Interrupt status This bit indicates that there is an interrupt from Queue 0" "0: Queue 0 Interrupt status not detected,1: Queue 0 Interrupt status detected" group.long 0xC30++0x3 line.long 0x0 "MTL_RxQ_DMA_Map0,The Receive Queue and DMA Channel Mapping 0 register is reserved in EQOS-CORE and EQOS-MTL configurations." rbitfld.long 0x0 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 28. "Reserved_Q3DDMACH,Reserved." "0,1" newline rbitfld.long 0x0 26.--27. "Reserved_27_y,Reserved." "0,1,2,3" newline rbitfld.long 0x0 24.--25. "Reserved_Q3MDMACH,Reserved." "0,1,2,3" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "Q2DDMACH,Queue 2 Enabled for DA-based DMA Channel Selection When set this bit indicates that the packets received in Queue 2 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4.." "0: Queue 2 disabled for DA-based DMA Channel..,1: Queue 2 enabled for DA-based DMA Channel Selection" newline rbitfld.long 0x0 18.--19. "Reserved_19_y,Reserved." "0,1,2,3" newline bitfld.long 0x0 16.--17. "Q2MDMACH,Queue 2 Mapped to DMA Channel This field controls the routing of the received packet in Queue 2 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: DMA Channel 5 -.." "0: DMA Channel 0,1: DMA Channel 1,?,?" newline rbitfld.long 0x0 13.--15. "Reserved_15_13,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12. "Q1DDMACH,Queue 1 Enabled for DA-based DMA Channel Selection When set this bit indicates that the packets received in Queue 1 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4.." "0: Queue 1 disabled for DA-based DMA Channel..,1: Queue 1 enabled for DA-based DMA Channel Selection" newline rbitfld.long 0x0 10.--11. "Reserved_11_y,Reserved." "0,1,2,3" newline bitfld.long 0x0 8.--9. "Q1MDMACH,Queue 1 Mapped to DMA Channel This field controls the routing of the received packet in Queue 1 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: DMA Channel 5 -.." "0: DMA Channel 0,1: DMA Channel 1,?,?" newline rbitfld.long 0x0 5.--7. "Reserved_7_5,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "Q0DDMACH,Queue 0 Enabled for DA-based DMA Channel Selection When set this bit indicates that the packets received in Queue 0 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4.." "0: Queue 0 disabled for DA-based DMA Channel..,1: Queue 0 enabled for DA-based DMA Channel Selection" newline rbitfld.long 0x0 2.--3. "Reserved_3_y,Reserved." "0,1,2,3" newline bitfld.long 0x0 0.--1. "Q0MDMACH,Queue 0 Mapped to DMA Channel This field controls the routing of the packet received in Queue 0 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: DMA Channel 5 -.." "0: DMA Channel 0,1: DMA Channel 1,?,?" group.long 0xC40++0x3 line.long 0x0 "MTL_TBS_CTRL,This register controls the operation of Time Based Scheduling." hexmask.long.tbyte 0x0 8.--31. 1. "LEOS,Launch Expiry Offset The value in units of 256 nanoseconds that has to be added to the Launch time to compute the Launch Expiry time" newline rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1" newline bitfld.long 0x0 4.--6. "LEGOS,Launch Expiry GSN Offset The number GSN slots that has to be added to the Launch GSN to compute the Launch Expiry time" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 2.--3. "Reserved_3_2,Reserved." "0,1,2,3" newline bitfld.long 0x0 1. "LEOV,Launch Expiry Offset Valid When set indicates the LEOS field is valid" "0: LEOS field is invalid,1: LEOS field is valid" newline bitfld.long 0x0 0. "ESTM,EST offset Mode When this bit is set the Launch Time value used in Time Based Scheduling is interpreted as an EST offset value and is added to the Base Time Register (BTR) of the current list" "0: EST offset Mode is disabled,1: EST offset Mode is enabled" group.long 0xC50++0xB line.long 0x0 "MTL_EST_Control,This register controls the operation of Enhancements to Scheduled Transmission (IEEE802.1Qbv)." hexmask.long.byte 0x0 24.--31. 1. "PTOV,PTP Time Offset Value The value of PTP Clock period multiplied by 6 in nanoseconds" newline hexmask.long.word 0x0 12.--23. 1. "CTOV,Current Time Offset Value Provides a 12 bit time offset value in nano second that is added to the current time to compensate for all the implementation pipeline delays such as the CDC sync delay buffering delays data path delays and so on" newline rbitfld.long 0x0 11. "Reserved_11,Reserved." "0,1" newline bitfld.long 0x0 8.--10. "TILS,Time Interval Left Shift Amount This field provides the left shift amount for the programmed Time Interval values used in the Gate Control Lists" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "LCSE,Loop Count to report Scheduling Error Programmable number of GCL list iterations before reporting an HLBS error defined in EST_Status register" "0: 4 iterations,1: 8 iterations,2: 16 iterations,3: 32 iterations" newline bitfld.long 0x0 5. "DFBS,Drop Frames causing Scheduling Error When set frames reported to cause HOL Blocking due to not getting scheduled (HLBS field of EST_Status register) after 4 8 16 32 (based on LCSE field of this register) GCL iterations are dropped" "0: Do not Drop Frames causing Scheduling Error,1: Drop Frames causing Scheduling Error" newline bitfld.long 0x0 4. "DDBF,Do not Drop frames during Frame Size Error When set frames are not be dropped during Head-of-Line blocking due to Frame Size Error (HLBF field of EST_Status register)" "0: Drop frames during Frame Size Error,1: Do not Drop frames during Frame Size Error" newline bitfld.long 0x0 3. "QHLBF,Quick Assertion of HLBF Error When set Time Window for Head-of-Line blocking due to Frame Size Error is 1 to 2 loop count of GCL list" "0: Disable Quick assertion of HLBF error,1: Quick Assertion of HLBF Error" newline rbitfld.long 0x0 2. "Reserved_2,Reserved." "0,1" newline bitfld.long 0x0 1. "SSWL,Switch to S/W owned list When set indicates that the software has programmed that list that it currently owns (SWOL) and the hardware should switch to the new list based on the new BTR" "0: Switch to S/W owned list is disabled,1: Switch to S/W owned list is enabled" newline bitfld.long 0x0 0. "EEST,Enable EST When reset the gate control list processing is halted and all gates are assumed to be in Open state" "0: EST is disabled,1: EST is enabled" line.long 0x4 "MTL_EST_Ext_Control,This register indicates the number of Overhead bytes for EST related scheduling." hexmask.long 0x4 6.--31. 1. "Reserved_31_6,Reserved." newline hexmask.long.byte 0x4 0.--5. 1. "OVHD,Overhead Bytes Value This field indicates the fixed overhead for every packet to account for EST Scheduler Delay IPG or EIPG and Preamble bytes" line.long 0x8 "MTL_EST_Status,This register provides Status related to Enhancements to Scheduled Transmission (IEEE802.1Qbv)." hexmask.long.word 0x8 20.--31. 1. "Reserved_31_20,Reserved." newline hexmask.long.byte 0x8 16.--19. 1. "CGSN,Current GCL Slot Number Indicates the slot number of the GCL list" newline hexmask.long.byte 0x8 8.--15. 1. "BTRL,BTR Error Loop Count Provides the minimum count (N) for which the equation Current Time =< New BTR + (N * New Cycle Time) becomes true" newline rbitfld.long 0x8 7. "SWOL,S/W owned list When '0' indicates Gate control list number '0' is owned by software and when '1' indicates the Gate Control list '1' is owned by the software" "0: Gate control list number '0' is owned by software,1: Gate control list number '1' is owned by software" newline rbitfld.long 0x8 5.--6. "Reserved_6_5,Reserved." "0,1,2,3" newline bitfld.long 0x8 4. "CGCE,Constant Gate Control Error This error occurs when the list length (LLR) is 1 and the Cycle Time (CTR) is less than or equal to the programmed Time Interval (TI) value after the optional Left Shifting" "0: Constant Gate Control Error not detected,1: Constant Gate Control Error detected" newline rbitfld.long 0x8 3. "HLBS,Head-Of-Line Blocking due to Scheduling Set when the frame is not able to win arbitration and get scheduled even after 4 iterations of the GCL" "0: Head-Of-Line Blocking due to Scheduling not..,1: Head-Of-Line Blocking due to Scheduling detected" newline rbitfld.long 0x8 2. "HLBF,Head-Of-Line Blocking due to Frame Size Set when HOL Blocking is noticed on one or more Queues as a result of none of the Time Intervals of gate open in the GCL being greater than or equal to the duration needed for frame size (or frame fragment.." "0: Head-Of-Line Blocking due to Frame Size not..,1: Head-Of-Line Blocking due to Frame Size detected" newline bitfld.long 0x8 1. "BTRE,BTR Error When '1' indicates a programming error in the BTR of SWOL where the programmed value is less than current time" "0: BTR Error not detected,1: BTR Error detected" newline bitfld.long 0x8 0. "SWLC,Switch to S/W owned list Complete When '1' indicates the hardware has successfully switched to the SWOL and the SWOL bit has been updated to that effect" "0: Switch to S/W owned list Complete not detected,1: Switch to S/W owned list Complete detected" group.long 0xC60++0x7 line.long 0x0 "MTL_EST_Sch_Error,This register provides the One Hot encoded Queue Numbers that are having the Scheduling related error (timeout)." hexmask.long 0x0 3.--31. 1. "Reserved_31_x,Reserved." newline bitfld.long 0x0 0.--2. "SEQN,Schedule Error Queue Number The One Hot Encoded Queue Numbers that have experienced error/timeout described in HLBS field of status register" "0,1,2,3,4,5,6,7" line.long 0x4 "MTL_EST_Frm_Size_Error,This register provides the One Hot encoded Queue Numbers that are having the Frame Size related error." hexmask.long 0x4 3.--31. 1. "Reserved_31_x,Reserved." newline bitfld.long 0x4 0.--2. "FEQN,Frame Size Error Queue Number The One Hot Encoded Queue Numbers that have experienced error described in HLBF field of status register" "0,1,2,3,4,5,6,7" rgroup.long 0xC68++0x3 line.long 0x0 "MTL_EST_Frm_Size_Capture,This register captures the Frame Size and Queue Number of the first occurrence of the Frame Size related error. Up on clearing it captures the data of immediate next occurrence of a similar error." hexmask.long.word 0x0 18.--31. 1. "Reserved_31_x,Reserved." newline bitfld.long 0x0 16.--17. "HBFQ,Queue Number of HLBF Captures the binary value of the of the first Queue (number) experiencing HLBF error (see HLBF field of status register)" "0,1,2,3" newline bitfld.long 0x0 15. "Reserved_15,Reserved." "0,1" newline hexmask.long.word 0x0 0.--14. 1. "HBFS,Frame Size of HLBF Captures the Frame Size of the dropped frame related to queue number indicated in HBFQ field of this register" group.long 0xC70++0x3 line.long 0x0 "MTL_EST_Intr_Enable,This register implements the Interrupt Enable bits for the various events that generate an interrupt. Bit positions have a 1 to 1 correlation with the status bit positions in MTL_ETS_Status register." hexmask.long 0x0 5.--31. 1. "Reserved_31_5,Reserved." newline bitfld.long 0x0 4. "CGCE,Interrupt Enable for CGCE When set generates interrupt when the Constant Gate Control Error occurs and is indicated in the status" "0: Interrupt for CGCE is disabled,1: Interrupt for CGCE is enabled" newline bitfld.long 0x0 3. "IEHS,Interrupt Enable for HLBS When set generates interrupt when the Head-of-Line Blocking due to Scheduling issue and is indicated in the status" "0: Interrupt for HLBS is disabled,1: Interrupt for HLBS is enabled" newline bitfld.long 0x0 2. "IEHF,Interrupt Enable for HLBF When set generates interrupt when the Head-of-Line Blocking due to Frame Size error occurs and is indicated in the status" "0: Interrupt for HLBF is disabled,1: Interrupt for HLBF is enabled" newline bitfld.long 0x0 1. "IEBE,Interrupt Enable for BTR Error When set generates interrupt when the BTR Error occurs and is indicated in the status" "0: Interrupt for BTR Error is disabled,1: Interrupt for BTR Error is enabled" newline bitfld.long 0x0 0. "IECC,Interrupt Enable for Switch List When set generates interrupt when the configuration change is successful and the hardware has switched to the new list" "0: Interrupt for Switch List is disabled,1: Interrupt for Switch List is enabled" group.long 0xC80++0x7 line.long 0x0 "MTL_EST_GCL_Control,This register provides the control information for reading/writing to the Gate Control lists." hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved." newline bitfld.long 0x0 23. "ESTEIEC,ECC Inject Error Control for EST Memory When ESTEIEE or ESTEIAEE bit of this register is set following are the errors inserted based on the value encoded in this field" "0: Insert 1 bit error,1: Insert 2 bit errors" newline bitfld.long 0x0 22. "ESTEIAEE,EST ECC Inject Address Error Enable When set along with EEST bit of MTL_EST_Control register enables the ECC address error injection feature" "0: EST ECC Inject Address Error is disabled,1: EST ECC Inject Address Error is enabled" newline bitfld.long 0x0 21. "ESTEIEE,EST ECC Inject Error Enable When set along with EEST bit of MTL_EST_Control register enables the ECC error injection feature" "0: EST ECC Inject Error is disabled,1: EST ECC Inject Error is enabled" newline hexmask.long.byte 0x0 16.--20. 1. "Reserved_20_y,Reserved." newline hexmask.long.byte 0x0 8.--15. 1. "ADDR,Gate Control List Address: (GCLA when GCRR is '0')" newline bitfld.long 0x0 6.--7. "Reserved_7_6,Reserved." "0,1,2,3" newline bitfld.long 0x0 5. "DBGB,Debug Mode Bank Select When set to '0' indicates R/W in debug mode should be directed to Bank 0 (GCL0 and corresponding Time related registers)" "0: R/W in debug mode should be directed to Bank 0,1: R/W in debug mode should be directed to Bank 1" newline bitfld.long 0x0 4. "DBGM,Debug Mode When set to '1' indicates R/W in debug mode where the memory bank (for GCL and Time related registers) is explicitly provided by DBGB value when set to '0' SWOL bit is used to determine which bank to use" "0: Debug Mode is disabled,1: Debug Mode is enabled" newline bitfld.long 0x0 3. "Reserved_3,Reserved." "0,1" newline bitfld.long 0x0 2. "GCRR,Gate Control Related Registers When set to '1' indicates the R/W access is for the GCL related registers (BTR CTR TER LLR) whose address is provided by GCRA" "0: Gate Control Related Registers are disabled,1: Gate Control Related Registers are enabled" newline bitfld.long 0x0 1. "R1W0,Read '1' Write '0': - 1: Read operation - 0: Write operation." "0: Write operation,1: Read operation" newline bitfld.long 0x0 0. "SRWO,Start Read/Write Op - 1: Indicates the start/progress of a Read/Write operation" "0: Start Read/Write Op disabled,1: Indicates the start/progress of a Read/Write.." line.long 0x4 "MTL_EST_GCL_Data,This register holds the read data or write data in case of reads and writes respectively." hexmask.long 0x4 0.--31. 1. "GCD,Gate Control Data The data corresponding to the address selected in the GCL_Control register" group.long 0xC90++0x7 line.long 0x0 "MTL_FPE_CTRL_STS,This register controls the operation of. and provides status for Frame Preemption (IEEE802.1Qbu/802.3br)." rbitfld.long 0x0 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 28. "HRS,Hold/Release Status - 1: Indicates a Set-and-Hold-MAC operation was last executed and the pMAC is in Hold State" "0: Indicates a Set-and-Release-MAC operation was..,1: Indicates a Set-and-Hold-MAC operation was last.." newline hexmask.long.word 0x0 16.--27. 1. "Reserved_27_16,Reserved." newline hexmask.long.byte 0x0 11.--15. 1. "Reserved_15_y,Reserved." newline bitfld.long 0x0 8.--10. "PEC,Preemption Classification When set indicates the corresponding Queue must be classified as preemptable when '0' Queue is classified as express" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 2.--7. 1. "Reserved_7_2,Reserved." newline bitfld.long 0x0 0.--1. "AFSZ,Additional Fragment Size used to indicate in units of 64 bytes the minimum number of bytes over 64 bytes required in non-final fragments of preempted frames" "0,1,2,3" line.long 0x4 "MTL_FPE_Advance,This register holds the Hold and Release Advance time." hexmask.long.word 0x4 16.--31. 1. "RADV,Release Advance The maximum time in nanoseconds that can elapse between issuing a RELEASE to the MAC and the MAC being ready to resume transmission of preemptable frames in the absence of there being any express frames available for transmission" newline hexmask.long.word 0x4 0.--15. 1. "HADV,Hold Advance The maximum time in nanoseconds that can elapse between issuing a HOLD to the MAC and the MAC ceasing to transmit any preemptable frame that is in the process of transmission or any preemptable frames that are queued for transmission" group.long 0xCA0++0x7 line.long 0x0 "MTL_RXP_Control_Status,The MTL_RXP_Control_Status register establishes the operating mode of Rx Parser and provides some status." rbitfld.long 0x0 31. "RXPI,RX Parser in Idle state This status bit is set to 1 when the Rx parser is in Idle State and waiting for a new packet for processing" "0: RX Parser not in Idle state,1: RX Parser in Idle state" newline bitfld.long 0x0 30. "ELIRS,Enable Last Instruction in RX Status When this bit is set RDES2[31:16] indicates the index of the last instruction excecuted in Rx Parse when set to 0 indicates MAC filter status" "0,1" newline hexmask.long.byte 0x0 22.--29. 1. "Reserved_29_x,Reserved." newline hexmask.long.byte 0x0 16.--21. 1. "NPE,Number of parsable entries in the Instruction table This control indicates the number of parsable entries in the Instruction Memory" newline hexmask.long.word 0x0 6.--15. 1. "Reserved_15_x,Reserved." newline hexmask.long.byte 0x0 0.--5. 1. "NVE,Number of valid entry address/index in the Instruction table This control indicates the number of valid entries address/index in the Instruction Memory (i" line.long 0x4 "MTL_RXP_Interrupt_Control_Status,The MTL_RXP_Interrupt_Control_Status registers provides enable control for the interrupts and provides interrupt status." hexmask.long.word 0x4 20.--31. 1. "Reserved_31_20,Reserved." newline bitfld.long 0x4 19. "PDRFIE,Packet Drop due to RF Interrupt Enable When this bit is set the PDRFIS interrupt is enabled" "0: Packet Drop due to RF Interrupt is disabled,1: Packet Drop due to RF Interrupt is enabled" newline bitfld.long 0x4 18. "FOOVIE,Frame Offset Overflow Interrupt Enable When this bit is set the FOOVIS interrupt is enabled" "0: Frame Offset Overflow Interrupt is disabled,1: Frame Offset Overflow Interrupt is enabled" newline bitfld.long 0x4 17. "NPEOVIE,Number of Parsable Entries Overflow Interrupt Enable When this bit is set the NPEOVIS interrupt is enabled" "0: Number of Parsable Entries Overflow Interrupt is..,1: Number of Parsable Entries Overflow Interrupt is.." newline bitfld.long 0x4 16. "NVEOVIE,Number of Valid Entries Overflow Interrupt Enable When this bit is set the NVEOVIS interrupt is enabled" "0: Number of Valid Entries Overflow Interrupt is..,1: Number of Valid Entries Overflow Interrupt is.." newline hexmask.long.word 0x4 4.--15. 1. "Reserved_15_4,Reserved." newline bitfld.long 0x4 3. "PDRFIS,Packet Dropped due to RF Interrupt Status If the Rx Parser result says to drop the packet by setting RF=1 in the instruction memory then this bit is set to 1" "0: Packet Dropped due to RF Interrupt Status not..,1: Packet Dropped due to RF Interrupt Status detected" newline bitfld.long 0x4 2. "FOOVIS,Frame Offset Overflow Interrupt Status While parsing if the Instruction table entry's 'Frame Offset' found to be more than EOF offset then then this bit is set" "0: Frame Offset Overflow Interrupt Status not..,1: Frame Offset Overflow Interrupt Status detected" newline bitfld.long 0x4 1. "NPEOVIS,Number of Parsable Entries Overflow Interrupt Status While parsing a packet if the number of parsed entries found to be more than NPE[] (Number of Parseable Entries in MTL_RXP_Control register) then this bit is set to 1" "0: Number of Parsable Entries Overflow Interrupt..,1: Number of Parsable Entries Overflow Interrupt.." newline bitfld.long 0x4 0. "NVEOVIS,Number of Valid Entry Address/Index Overflow Interrupt Status While parsing if the Instruction address found to be more than NVE (Number of Valid Entry Address/index in MTL_RXP_Control register) then this bit is set to 1" "0: Number of Valid Entries Overflow Interrupt..,1: Number of Valid Entries Overflow Interrupt.." rgroup.long 0xCA8++0x7 line.long 0x0 "MTL_RXP_Drop_Cnt,The MTL_RXP_Drop_Cnt register provides the drop count of Rx Parser initiated drops." bitfld.long 0x0 31. "RXPDCOVF,Rx Parser Drop Counter Overflow Bit When set this bit indicates that the MTL_RXP_Drop_cnt (RXPDC) Counter field crossed the maximum limit" "0: Rx Parser Drop count overflow not occurred,1: Rx Parser Drop count overflow occurred" newline hexmask.long 0x0 0.--30. 1. "RXPDC,Rx Parser Drop count This 31-bit counter is implemented when a Rx Parser Drops a packet due to RF =1" line.long 0x4 "MTL_RXP_Error_Cnt,The MTL_RXP_Error_Cnt register provides the Rx Parser related error occurrence count." bitfld.long 0x4 31. "RXPECOVF,Rx Parser Error Counter Overflow Bit When set this bit indicates that the MTL_RXP_Error_cnt (RXPEC) Counter field crossed the maximum limit" "0: Rx Parser Error count overflow not occurred,1: Rx Parser Error count overflow occurred" newline hexmask.long 0x4 0.--30. 1. "RXPEC,Rx Parser Error count This 31-bit counter is implemented whenr a Rx Parser encounters following Error scenarios - Entry address >= NVE[] - Number Parsed Entries >= NPE[] - Entry address > EOF data entry address The counter is cleared when the.." group.long 0xCB0++0x3 line.long 0x0 "MTL_RXP_Indirect_Acc_Control_Status,The MTL_RXP_Indirect_Acc_Control_Status register provides the Indirect Access control and status for Rx Parser memory." bitfld.long 0x0 31. "STARTBUSY,FRP Instruction Table Access Busy - Set to 1 by the software indicates to start the Read/Write operation from/to the Rx Parser Memory" "0: hardware not busy,1: hardware is busy (Read/Write operation from/to.." newline hexmask.long.byte 0x0 23.--30. 1. "Reserved_30_23,Reserved." newline bitfld.long 0x0 22. "RXPEIEC,ECC Inject Error Control for Rx Parser Memory When RXPEIEE or RXPEIAEE bit of this register is set following are the errors inserted based on the value encoded in this field: - 1: Insert 1 bit error" "0: Insert 1 bit error,1: Insert 1 bit error" newline bitfld.long 0x0 21. "RXPEIAEE,ECC Inject Address Error Enable for Rx Parser Memory - 1: Enables the ECC address error injection feature" "0: ECC Inject Address Error for Rx Parser Memory is..,1: Enables the ECC address error injection feature" newline bitfld.long 0x0 20. "RXPEIEE,ECC Inject Error Enable for Rx Parser Memory - 1: Enables the ECC error injection feature" "0: ECC Inject Error for Rx Parser Memory is disabled,1: Enables the ECC error injection feature" newline rbitfld.long 0x0 17.--19. "Reserved_19_17,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "WRRDN,Read Write Control - 1: Indicates the write operation to the Rx Parser Memory" "0: Read operation to the Rx Parser Memory,1: Indicates the write operation to the Rx Parser.." newline hexmask.long.byte 0x0 8.--15. 1. "Reserved_15_x,Reserved." newline hexmask.long.byte 0x0 0.--7. 1. "ADDR,FRP Instruction Table Offset Address This field indicates the ADDR of the 32-bit entry in Rx parser instruction table" rgroup.long 0xCB4++0x7 line.long 0x0 "MTL_RXP_Indirect_Acc_Data,The MTL_RXP_Indirect_Acc_Data registers holds the data associated to Indirect Access to Rx Parser memory." hexmask.long 0x0 0.--31. 1. "DATA,FRP Instruction Table Write/Read Data Software should write this register before issuing any write command" line.long 0x4 "MTL_RXP_Bypass_Cnt,The MTL_RXP_Bypass_Cnt register provides the bypass count of Rx Parser." bitfld.long 0x4 31. "RXPBCOF,Rx Parser bypass Counter Overflow Bit When set this bit indicates that the MTL_RXP_Bypass_cnt (RXPBC) Counter field crossed the maximum limit" "0: Rx Parser Bypass count overflow not occurred,1: Rx Parser Bypass count overflow occurred" newline hexmask.long 0x4 0.--30. 1. "RXPBC,Rx Parser Bypass count This 31-bit counter is implemented when a Rx Parser bypass a packet due to AF=1 and RF =1" group.long 0xCC0++0x3 line.long 0x0 "MTL_ECC_Control,The MTL_ECC_Control register establishes the operating mode of ECC related to MTL memories." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_31_9,Reserved." newline bitfld.long 0x0 8. "MEEAO,MTL ECC Error Address Status Over-ride - 1: The EUEAS/ECEAS field of MTL_ECC_Err_Addr_Status register holds the last valid address where the error is detected" "0: MTL ECC Error Address Status Over-ride is disabled,1: The EUEAS/ECEAS field of MTL_ECC_Err_Addr_Status.." newline rbitfld.long 0x0 6.--7. "Reserved_7_6,Reserved." "0,1,2,3" newline rbitfld.long 0x0 5. "Reserved_DSCEE,Reserved." "0,1" newline rbitfld.long 0x0 4. "Reserved_TSOEE,Reserved." "0,1" newline bitfld.long 0x0 3. "MRXPEE,MTL Rx Parser ECC Enable - 1: Enables the ECC feature for Rx Parser memory - 0: Disables the ECC feature for Rx Parser memory" "0: Disables the ECC feature for Rx Parser memory,1: Enables the ECC feature for Rx Parser memory" newline bitfld.long 0x0 2. "MESTEE,MTL EST ECC Enable - 1: Enables the ECC feature for EST memory - 0: Disables the ECC feature for EST memory" "0: Disables the ECC feature for EST memory,1: Enables the ECC feature for EST memory" newline bitfld.long 0x0 1. "MRXEE,MTL Rx FIFO ECC Enable - 1: Enables the ECC feature for MTL Rx FIFO memory" "0: MTL Rx FIFO ECC is disabled,1: Enables the ECC feature for MTL Rx FIFO memory" newline bitfld.long 0x0 0. "MTXEE,MTL Tx FIFO ECC Enable - 1: Enables the ECC feature for MTL Tx FIFO memory - 0: Disables the ECC feature for MTL Tx FIFO memory" "0: Disables the ECC feature for MTL Tx FIFO memory,1: Enables the ECC feature for MTL Tx FIFO memory" rgroup.long 0xCC4++0x3 line.long 0x0 "MTL_Safety_Interrupt_Status,The MTL_Safety_Interrupt_Status registers provides Safety interrupt status." bitfld.long 0x0 31. "Reserved_MCSIS,Reserved." "0: MAC Safety Uncorrectable Interrupt Status not..,1: MAC Safety Uncorrectable Interrupt Status detected" newline hexmask.long 0x0 2.--30. 1. "Reserved_30_2,Reserved." newline bitfld.long 0x0 1. "MEUIS,MTL ECC Uncorrectable error Interrupt Status This bit indicates that an uncorrectable error interrupt event in the MTL ECC safety feature" "0: MTL ECC Uncorrectable error Interrupt Status not..,1: MTL ECC Uncorrectable error Interrupt Status.." newline bitfld.long 0x0 0. "MECIS,MTL ECC Correctable error Interrupt Status This bit indicates that a correctable error interrupt event in the MTL ECC safety feature" "0: MTL ECC Correctable error Interrupt Status not..,1: MTL ECC Correctable error Interrupt Status.." group.long 0xCC8++0xB line.long 0x0 "MTL_ECC_Interrupt_Enable,The MTL_ECC_Interrupt_Enable register provides enable bits for the ECC interrupts." hexmask.long.tbyte 0x0 13.--31. 1. "Reserved_31_13,Reserved." newline bitfld.long 0x0 12. "RPCEIE,Rx Parser memory Correctable Error Interrupt Enable When set generates an interrupt when an uncorrectable error is detected at the Rx Parser memory interface" "0: Rx Parser memory Correctable Error Interrupt is..,1: Rx Parser memory Correctable Error Interrupt is.." newline rbitfld.long 0x0 9.--11. "Reserved_11_9,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8. "ECEIE,EST memory Correctable Error Interrupt Enable When set generates an interrupt when a correctable error is detected at the MTL EST memory interface" "0: EST memory Correctable Error Interrupt is disabled,1: EST memory Correctable Error Interrupt is enabled" newline rbitfld.long 0x0 5.--7. "Reserved_7_5,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "RXCEIE,Rx memory Correctable Error Interrupt Enable When set generates an interrupt when a correctable error is detected at the MTL Rx memory interface" "0: Rx memory Correctable Error Interrupt is disabled,1: Rx memory Correctable Error Interrupt is enabled" newline rbitfld.long 0x0 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "TXCEIE,Tx memory Correctable Error Interrupt Enable When set generates an interrupt when a correctable error is detected at the MTL Tx memory interface" "0: Tx memory Correctable Error Interrupt is disabled,1: Tx memory Correctable Error Interrupt is enabled" line.long 0x4 "MTL_ECC_Interrupt_Status,The MTL_ECC_Interrupt_Status register provides MTL ECC Interrupt Status." hexmask.long.tbyte 0x4 15.--31. 1. "Reserved_31_15,Reserved." newline bitfld.long 0x4 14. "RPUES,Rx Parser memory Uncorrectable Error Status When set indicates that an uncorrectable error is detected at Rx Parser memory interface" "0: Rx Parser memory Uncorrectable Error Status not..,1: Rx Parser memory Uncorrectable Error Status.." newline bitfld.long 0x4 13. "RPAMS,MTL Rx Parser memory Address Mismatch Status This bit when set indicates that address mismatch is found for address bus of Rx Parser memory" "0: MTL Rx Parser memory Address Mismatch Status not..,1: MTL Rx Parser memory Address Mismatch Status.." newline bitfld.long 0x4 12. "RPCES,MTL Rx Parser memory Correctable Error Status This bit when set indicates that correctable error is detected at RX Parser memory interface" "0: MTL Rx Parser memory Correctable Error Status..,1: MTL Rx Parser memory Correctable Error Status.." newline rbitfld.long 0x4 11. "Reserved_11,Reserved." "0,1" newline bitfld.long 0x4 10. "EUES,MTL EST memory Uncorrectable Error Status When set indicates that an uncorrectable error is detected at MTL EST memory interface" "0: MTL EST memory Uncorrectable Error Status not..,1: MTL EST memory Uncorrectable Error Status detected" newline bitfld.long 0x4 9. "EAMS,MTL EST memory Address Mismatch Status This bit when set indicates that address mismatch is found for address bus of MTL EST memory" "0: MTL EST memory Address Mismatch Status not..,1: MTL EST memory Address Mismatch Status detected" newline bitfld.long 0x4 8. "ECES,MTL EST memory Correctable Error Status This bit when set indicates that correctable error is detected at the MTL EST memory" "0: MTL EST memory Correctable Error Status not..,1: MTL EST memory Correctable Error Status detected" newline rbitfld.long 0x4 7. "Reserved_7,Reserved." "0,1" newline bitfld.long 0x4 6. "RXUES,MTL Rx memory Uncorrectable Error Status When set indicates that an uncorrectable error is detected at the MTL Rx memory interface" "0: MTL Rx memory Uncorrectable Error Status not..,1: MTL Rx memory Uncorrectable Error Status detected" newline bitfld.long 0x4 5. "RXAMS,MTL Rx memory Address Mismatch Status This bit when set indicates that address mismatch is found for address bus of the MTL Rx memory" "0: MTL Rx memory Address Mismatch Status not detected,1: MTL Rx memory Address Mismatch Status detected" newline bitfld.long 0x4 4. "RXCES,MTL Rx memory Correctable Error Status This bit when set indicates that correctable error is detected at the MTL Rx memory" "0: MTL Rx memory correctable Error Status not..,1: MTL Rx memory correctable Error Status detected" newline rbitfld.long 0x4 3. "Reserved_3,Reserved." "0,1" newline bitfld.long 0x4 2. "TXUES,MTL Tx memory Uncorrectable Error Status When set indicates that an uncorrectable error is detected at the MTL TX memory interface" "0: MTL Tx memory Uncorrectable Error Status not..,1: MTL Tx memory Uncorrectable Error Status detected" newline bitfld.long 0x4 1. "TXAMS,MTL Tx memory Address Mismatch Status This bit when set indicates that address mismatch is found for address bus of the MTL Tx memory" "0: MTL Tx memory Address Mismatch Status not detected,1: MTL Tx memory Address Mismatch Status detected" newline bitfld.long 0x4 0. "TXCES,MTL Tx memory Correctable Error Status This bit when set indicates that a correctable error is detected at the MTL Tx memory" "0: MTL Tx memory Correctable Error Status not..,1: MTL Tx memory Correctable Error Status detected" line.long 0x8 "MTL_ECC_Err_Sts_Rctl,The MTL_ECC_Err_Sts_Rctl register establishes the control for ECC Error status capture." hexmask.long 0x8 6.--31. 1. "Reserved_31_6,Reserved." newline bitfld.long 0x8 5. "CUES,Clear Uncorrectable Error Status When this bit is set along with EESRE bit of this register based on the EMS field of this register the respective memory's uncorrectable error address and uncorrectable error count values are cleared upon reading" "0: Clear Uncorrectable Error Status not detected,1: Clear Uncorrectable Error Status detected" newline bitfld.long 0x8 4. "CCES,Clear Correctable Error Status When this bit is set along with EESRE bit of this register based on the EMS field of this register the respective memory's correctable error address and correctable error count values are cleared upon reading" "0: Clear Correctable Error Status not detected,1: Clear Correctable Error Status detected" newline bitfld.long 0x8 1.--3. "EMS,MTL ECC Memory Selection When EESRE bit of this register is set this field indicates which memory's error status value to be read" "0: MTL Tx memory,1: MTL Rx memory,2: MTL EST memory,3: MTL Rx Parser memory,4: DMA TSO memory,5: DMA DCACHE memory,?,?" newline bitfld.long 0x8 0. "EESRE,MTL ECC Error Status Read Enable When this bit is set based on the EMS field of this register the respective memory's error status values are captured as described: - The correctable and uncorrectable error count values are captured into.." "0: MTL ECC Error Status Read is disabled,1: MTL ECC Error Status Read is enabled" rgroup.long 0xCD4++0x7 line.long 0x0 "MTL_ECC_Err_Addr_Status,The MTL_ECC_Err_Addr_Status register provides the memory addresses for the correctable and uncorrectable errors." hexmask.long.word 0x0 16.--31. 1. "EUEAS,MTL ECC Uncorrectable Error Address Status Based on the EMS field of MTL_ECC_Err_Sts_Rctl register this field holds the respective memory's address locations for which an uncorrectable error or address mismatch is detected" newline hexmask.long.word 0x0 0.--15. 1. "ECEAS,MTL ECC Correctable Error Address Status Based on the EMS field of MTL_ECC_Err_Sts_Rctl register this field holds the respective memory's address locations for which a correctable error is detected" line.long 0x4 "MTL_ECC_Err_Cntr_Status,The MTL_ECC_Err_Cntr_Status register provides ECC Error count for Correctable and uncorrectable errors." hexmask.long.word 0x4 20.--31. 1. "Reserved_31_20,Reserved." newline hexmask.long.byte 0x4 16.--19. 1. "EUECS,MTL ECC Uncorrectable Error Counter Status Based on the EMS field of MTL_ECC_Err_Cntr_Rctl register this field holds the respective memory's uncorrectable error count value" newline hexmask.long.byte 0x4 8.--15. 1. "Reserved_15_8,Reserved." newline hexmask.long.byte 0x4 0.--7. 1. "ECECS,MTL ECC Correctable Error Counter Status Based on the EMS field of MTL_ECC_Err_Cntr_Rctl register this field holds the respective memory's correctable error count value" group.long 0xCE0++0x7 line.long 0x0 "MTL_DPP_Control,The MTL_DPP_Control establishes the operating mode of Data Parity protection and error injection." hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved." newline rbitfld.long 0x0 16. "Reserved_IPEDC,Reserved." "0,1" newline bitfld.long 0x0 15. "IPEMRWC,no description available" "0: Insert Parity error in MTL RWC data parity..,1: Insert Parity error in MTL RWC data parity.." newline bitfld.long 0x0 14. "IPEMTFC,Insert Parity error in MAC TFC data parity checker When set to 1 parity/data bit of first valid input parity/data of the MAC TFC data parity checker (or at PC11 as shown in Transmit Data path parity protection diagram) is flipped" "0: Insert Parity error in MAC TFC data parity..,1: Insert Parity error in MAC TFC data parity.." newline bitfld.long 0x0 13. "IPEMTBU,Insert Parity error in MTL RWC data parity checker When set to 1 parity/data bit of first valid input parity/data of the MTL RWC data parity checker (or at PC12 as shown in Recieve data path parity protection diagram) is flipped" "0: Insert Parity error in MAC TBU data parity..,1: Insert Parity error in MAC TBU data parity.." newline rbitfld.long 0x0 12. "Reserved_IPEASR,Reserved." "0,1" newline rbitfld.long 0x0 11. "Reserved_IPEMSW,Reserved." "0,1" newline rbitfld.long 0x0 10. "Reserved_IPEASW,Reserved." "0,1" newline bitfld.long 0x0 9. "IPERID,Insert Parity Error in RX Interface Data parity checker When set to 1 parity/data bit of first valid input parity/data of the RX Interface Data parity checker is (or at PC6 as shown in Receive data path parity protection diagram) flipped" "0: Insert Parity Error in Rx Interface Data parity..,1: Insert Parity Error in Rx Interface Data parity.." newline bitfld.long 0x0 8. "IPEMTS,Insert Parity Error in MTL Tx Status FIFO parity checker When set to 1 parity/data bit of first valid input parity/data of the MTL Tx Status FIFO parity checker (or at PC5 as shown in Transmit data path parity protection diagram) is flipped" "0: Insert Parity Error in MTL TX Status FIFO parity..,1: Insert Parity Error in MTL TX Status FIFO parity.." newline bitfld.long 0x0 7. "IPEMTF,Insert Parity Error in MTL Tx FIFO write data parity checker When set to 1 parity/data bit of first valid input parity/data of the MTL Tx FIFO write data parity checker (or at PC4 as shown in Transmit data path parity protection diagram) is flipped" "0: Insert Parity Error in MTL Tx FIFO write data..,1: Insert Parity Error in MTL Tx FIFO write data.." newline bitfld.long 0x0 6. "IPETRD,Insert Parity Error in DMA Tx/Rx Descriptor parity checker When set to 1 parity/data bit of first valid input parity/data of the DMA Tx/Rx Descriptor parity checker (or at PC3 as shown in Transmit data path parity protection diagram) is flipped" "0: Insert Parity Error in DMA Tx/Rx Descriptor..,1: Insert Parity Error in DMA Tx/Rx Descriptor.." newline rbitfld.long 0x0 5. "Reserved_IPETH,Reserved." "0,1" newline rbitfld.long 0x0 4. "Reserved_IPETID,Reserved." "0,1" newline rbitfld.long 0x0 3. "Reserved_3,Reserved." "0,1" newline rbitfld.long 0x0 2. "Reserved_EPSI,Reserved." "0,1" newline rbitfld.long 0x0 1. "OPE,Odd Parity Enable When set to 1 enables odd parity protection on all the external interfaces and when set to 0 enables even parity protection on all the external interfaces" "0: Odd Parity is disabled,1: Odd Parity is enabled" newline bitfld.long 0x0 0. "EDPP,Enable Data path Parity Protection When set to 1 enables the parity protection for EQOS datapath by generating and checking the parity on EQOS datapath" "0: Data path Parity Protection is disabled,1: Data path Parity Protection is enabled" line.long 0x4 "MTL_DPP_ECC_EIC,The MTL_DPP_ECC_EIC establishes the operating mode of ECC/DPP error injection." hexmask.long.word 0x4 17.--31. 1. "Reserved_31_17,Reserved." newline bitfld.long 0x4 16. "EIM,Error Injection Mode When it set to 0 indicate error injection on data; When it set to 1 indicate error injection on ECC/Parity bits(need to check the address error injection mode is disabled)" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "Reserved_15_8,Reserved." newline hexmask.long.byte 0x4 0.--7. 1. "BLEI,Bit Location of error injection This field indicates the bit location of DPP/ECC error injection determination of error in Parity/ECC bits or Data (being protected) depends on the Error Injection Mode(EIM field)" group.long 0xD00++0x3 line.long 0x0 "MTL_TxQ0_Operation_Mode,The Queue 0 Transmit Operation Mode register establishes the Transmit queue operating modes and commands." hexmask.long.word 0x0 22.--31. 1. "Reserved_31_y,Reserved." newline hexmask.long.byte 0x0 16.--21. 1. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes" newline hexmask.long.word 0x0 7.--15. 1. "Reserved_15_7,Reserved." newline bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue" "0: 32,1: 64,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512" newline bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0" "0: Not enabled,1: Enable in AV mode (Reserved in non-AV),2: Enabled,?" newline bitfld.long 0x0 1. "TSF,Transmit Store and Forward When this bit is set the transmission starts when a full packet resides in the MTL Tx queue" "0: Transmit Store and Forward is disabled,1: Transmit Store and Forward is enabled" newline bitfld.long 0x0 0. "FTQ,Flush Transmit Queue When this bit is set the Tx queue controller logic is reset to its default values" "0: Flush Transmit Queue is disabled,1: Flush Transmit Queue is enabled" rgroup.long 0xD04++0x7 line.long 0x0 "MTL_TxQ0_Underflow,The Queue 0 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow and packets missed because of Receive queue packet flush" hexmask.long.tbyte 0x0 12.--31. 1. "Reserved_31_12,Reserved." newline bitfld.long 0x0 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows that is it has crossed the maximum count" "0: Overflow not detected for Underflow Packet Counter,1: Overflow detected for Underflow Packet Counter" newline hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow" line.long 0x4 "MTL_TxQ0_Debug,The Queue 0 Transmit Debug register gives the debug status of various blocks related to the Transmit queue." hexmask.long.word 0x4 23.--31. 1. "Reserved_31_23,Reserved." newline bitfld.long 0x4 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 19. "Reserved_19,Reserved." "0,1" newline bitfld.long 0x4 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4 6.--15. 1. "Reserved_15_6,Reserved." newline bitfld.long 0x4 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high this bit indicates that the MTL Tx Status FIFO is full" "0: MTL Tx Status FIFO Full status is not detected,1: MTL Tx Status FIFO Full status is detected" newline bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high it indicates that the MTL Tx Queue is not empty and some data is left for transmission" "0: MTL Tx Queue Not Empty status is not detected,1: MTL Tx Queue Not Empty status is detected" newline bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status When high this bit indicates that the MTL Tx Queue Write Controller is active and it is transferring the data to the Tx Queue" "0: MTL Tx Queue Write Controller status is not..,1: MTL Tx Queue Write Controller status is detected" newline bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller:" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.." newline bitfld.long 0x4 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "0: Transmit Queue in Pause status is not detected,1: Transmit Queue in Pause status is detected" rgroup.long 0xD14++0x3 line.long 0x0 "MTL_TxQ0_ETS_Status,The Queue 0 ETS Status register provides the average traffic transmitted in Queue 0." hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved." newline hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot This field contains the average transmitted bits per slot" group.long 0xD18++0x3 line.long 0x0 "MTL_TxQ0_Quantum_Weight,The Queue 0 Quantum or Weights register contains the quantum value for Deficit Weighted Round Robin (DWRR). weights for the Weighted Round Robin (WRR). and Weighted Fair Queuing (WFQ) for Queue 0." hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved." newline hexmask.long.tbyte 0x0 0.--20. 1. "ISCQW,Quantum or Weights When the DCB operation is enabled with DWRR algorithm for Queue 0 traffic this field contains the quantum value in bytes to be added to credit during every queue scanning cycle" group.long 0xD2C++0x7 line.long 0x0 "MTL_Q0_Interrupt_Control_Status,This register contains the interrupt enable and status bits for the queue 0 interrupts." hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved." newline bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set the Receive Queue Overflow interrupt is enabled" "0: Receive Queue Overflow Interrupt is disabled,1: Receive Queue Overflow Interrupt is enabled" newline hexmask.long.byte 0x0 17.--23. 1. "Reserved_23_17,Reserved." newline bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet" "0: Receive Queue Overflow Interrupt Status not..,1: Receive Queue Overflow Interrupt Status detected" newline hexmask.long.byte 0x0 10.--15. 1. "Reserved_15_10,Reserved." newline bitfld.long 0x0 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated" "0: Average Bits Per Slot Interrupt is disabled,1: Average Bits Per Slot Interrupt is enabled" newline bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set the Transmit Queue Underflow interrupt is enabled" "0: Transmit Queue Underflow Interrupt Status is..,1: Transmit Queue Underflow Interrupt Status is.." newline hexmask.long.byte 0x0 2.--7. 1. "Reserved_7_2,Reserved." newline bitfld.long 0x0 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set this bit indicates that the MAC has updated the ABS value" "0: Average Bits Per Slot Interrupt Status not..,1: Average Bits Per Slot Interrupt Status detected" newline bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet" "0: Transmit Queue Underflow Interrupt Status not..,1: Transmit Queue Underflow Interrupt Status detected" line.long 0x4 "MTL_RxQ0_Operation_Mode,The Queue 0 Receive Operation Mode register establishes the Receive queue operating modes and command. The RFA and RFD fields are not backward compatible with the RFA and RFD fields of 4.00a release" hexmask.long.byte 0x4 26.--31. 1. "Reserved_31_y,Reserved." newline hexmask.long.byte 0x4 20.--25. 1. "RQS,Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes" newline rbitfld.long 0x4 19. "Reserved_19_y,Reserved." "0,1" newline hexmask.long.byte 0x4 14.--18. 1. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation: - 0: Full minus 1 KB that is FULL 1 KB - 1: Full.." newline rbitfld.long 0x4 13. "Reserved_13_y,Reserved." "0,1" newline hexmask.long.byte 0x4 8.--12. 1. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field see RFD" newline bitfld.long 0x4 7. "EHFC,Enable Hardware Flow Control When this bit is set the flow control signal operation based on the fill-level of Rx queue is enabled" "0: Hardware Flow Control is disabled,1: Hardware Flow Control is enabled" newline bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine" "0: Dropping of TCP/IP Checksum Error Packets is..,1: Dropping of TCP/IP Checksum Error Packets is.." newline bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward When this bit is set the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it ignoring the RTC field of this register" "0: Receive Queue Store and Forward is disabled,1: Receive Queue Store and Forward is enabled" newline bitfld.long 0x4 4. "FEP,Forward Error Packets When this bit is reset the Rx queue drops packets with error status (CRC error GMII_ER watchdog timeout or overflow)" "0: Forward Error Packets is disabled,1: Forward Error Packets is enabled" newline bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets When this bit is set the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes) including pad-bytes and CRC" "0: Forward Undersized Good Packets is disabled,1: Forward Undersized Good Packets is enabled" newline rbitfld.long 0x4 2. "Reserved_2,Reserved." "0,1" newline bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold" "0: 64,1: 32,2: 96,3: 128" rgroup.long 0xD34++0x7 line.long 0x0 "MTL_RxQ0_Missed_Packet_Overflow_Cnt,The Queue 0 Missed Packet and Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow." hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_28,Reserved." newline bitfld.long 0x0 27. "MISCNTOVF,Missed Packet Counter Overflow Bit When set this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit" "0: Missed Packet Counter overflow not detected,1: Missed Packet Counter overflow detected" newline hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue" newline hexmask.long.byte 0x0 12.--15. 1. "Reserved_15_12,Reserved." newline bitfld.long 0x0 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit" "0: Overflow Counter overflow not detected,1: Overflow Counter overflow detected" newline hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow" line.long 0x4 "MTL_RxQ0_Debug,The Queue 0 Receive Debug register gives the debug status of various blocks related to the Receive queue." bitfld.long 0x4 30.--31. "Reserved_31_30,Reserved." "0,1,2,3" newline hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue" newline hexmask.long.word 0x4 6.--15. 1. "Reserved_15_6,Reserved." newline bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue:" "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full" newline bitfld.long 0x4 3. "Reserved_3,Reserved." "0,1" newline bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller:" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status" newline bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high this bit indicates that the MTL Rx queue Write controller is active and it is transferring a received packet to the Rx Queue" "0: MTL Rx Queue Write Controller Active Status not..,1: MTL Rx Queue Write Controller Active Status.." group.long 0xD3C++0x7 line.long 0x0 "MTL_RxQ0_Control,The Queue Receive Control register controls the receive arbitration and passing of received packets to the application." hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved." newline bitfld.long 0x0 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue" "0: Receive Queue Packet Arbitration is disabled,1: Receive Queue Packet Arbitration is enabled" newline bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0" "0,1,2,3,4,5,6,7" line.long 0x4 "MTL_TxQ1_Operation_Mode,The Queue 1 Transmit Operation Mode register establishes the Transmit queue operating modes and commands." hexmask.long.word 0x4 22.--31. 1. "Reserved_31_y,Reserved." newline hexmask.long.byte 0x4 16.--21. 1. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes" newline hexmask.long.word 0x4 7.--15. 1. "Reserved_15_7,Reserved." newline bitfld.long 0x4 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue" "0: 32,1: 64,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512" newline bitfld.long 0x4 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0" "0: Not enabled,1: Enable in AV mode (Reserved in non-AV),2: Enabled,?" newline bitfld.long 0x4 1. "TSF,Transmit Store and Forward When this bit is set the transmission starts when a full packet resides in the MTL Tx queue" "0: Transmit Store and Forward is disabled,1: Transmit Store and Forward is enabled" newline bitfld.long 0x4 0. "FTQ,Flush Transmit Queue When this bit is set the Tx queue controller logic is reset to its default values" "0: Flush Transmit Queue is disabled,1: Flush Transmit Queue is enabled" rgroup.long 0xD44++0x7 line.long 0x0 "MTL_TxQ1_Underflow,The Queue 1 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow and packets missed because of Receive queue packet flush" hexmask.long.tbyte 0x0 12.--31. 1. "Reserved_31_12,Reserved." newline bitfld.long 0x0 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows that is it has crossed the maximum count" "0: Overflow not detected for Underflow Packet Counter,1: Overflow detected for Underflow Packet Counter" newline hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow" line.long 0x4 "MTL_TxQ1_Debug,The Queue 1 Transmit Debug register gives the debug status of various blocks related to the Transmit queue." hexmask.long.word 0x4 23.--31. 1. "Reserved_31_23,Reserved." newline bitfld.long 0x4 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 19. "Reserved_19,Reserved." "0,1" newline bitfld.long 0x4 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4 6.--15. 1. "Reserved_15_6,Reserved." newline bitfld.long 0x4 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high this bit indicates that the MTL Tx Status FIFO is full" "0: MTL Tx Status FIFO Full status is not detected,1: MTL Tx Status FIFO Full status is detected" newline bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high it indicates that the MTL Tx Queue is not empty and some data is left for transmission" "0: MTL Tx Queue Not Empty status is not detected,1: MTL Tx Queue Not Empty status is detected" newline bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status When high this bit indicates that the MTL Tx Queue Write Controller is active and it is transferring the data to the Tx Queue" "0: MTL Tx Queue Write Controller status is not..,1: MTL Tx Queue Write Controller status is detected" newline bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller:" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.." newline bitfld.long 0x4 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "0: Transmit Queue in Pause status is not detected,1: Transmit Queue in Pause status is detected" group.long 0xD50++0x3 line.long 0x0 "MTL_TxQ1_ETS_Control,The Queue ETS Control register controls the enhanced transmission selection operation." hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved." newline bitfld.long 0x0 4.--6. "SLC,Slot Count If the credit-based shaper algorithm is enabled the software can program the number of slots (of duration programmed in DMA_CH(#i)_Slot_Interval register) over which the average transmitted bits per slot provided in the.." "0: 1 slot,1: 2 slots,2: 4 slots,3: 8 slots,4: 16 slots,?,?,?" newline bitfld.long 0x0 3. "CC,Credit Control When this bit is set the accumulated credit parameter in the credit-based shaper algorithm logic is not reset to zero when there is positive credit and no packet to transmit in Channel 1" "0: Credit Control is disabled,1: Credit Control is enabled" newline bitfld.long 0x0 2. "AVALG,AV Algorithm When Queue 1 is programmed for AV this field configures the scheduling algorithm for this queue: This bit when set indicates credit based shaper algorithm (CBS) is selected for Queue 1 traffic" "0: CBS Algorithm is disabled,1: CBS Algorithm is enabled" newline rbitfld.long 0x0 0.--1. "Reserved_1_0,Reserved." "0,1,2,3" rgroup.long 0xD54++0x3 line.long 0x0 "MTL_TxQ1_ETS_Status,The Queue 1 ETS Status register provides the average traffic transmitted in Queue 1." hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved." newline hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot This field contains the average transmitted bits per slot" group.long 0xD58++0xF line.long 0x0 "MTL_TxQ1_Quantum_Weight,The Queue 1 idleSlopeCredit. Quantum or Weights register provides the average traffic transmitted in Queue 1." hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved." newline hexmask.long.tbyte 0x0 0.--20. 1. "ISCQW,idleSlopeCredit Quantum or Weights - idleSlopeCredit When AV feature is enabled this field contains the idleSlopeCredit value required for the credit-based shaper algorithm for Queue 1" line.long 0x4 "MTL_TxQ1_SendSlopeCredit,The sendSlopeCredit register contains the sendSlope credit value required for the credit-based shaper algorithm for the Queue." hexmask.long.tbyte 0x4 14.--31. 1. "Reserved_31_14,Reserved." newline hexmask.long.word 0x4 0.--13. 1. "SSC,sendSlopeCredit Value When AV operation is enabled this field contains the sendSlopeCredit value required for credit-based shaper algorithm for Queue 1" line.long 0x8 "MTL_TxQ1_HiCredit,The hiCredit register contains the hiCredit value required for the credit-based shaper algorithm for the Queue." rbitfld.long 0x8 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long 0x8 0.--28. 1. "HC,hiCredit Value When the AV feature is enabled this field contains the hiCredit value required for the credit-based shaper algorithm" line.long 0xC "MTL_TxQ1_LoCredit,The loCredit register contains the loCredit value required for the credit-based shaper algorithm for the Queue." rbitfld.long 0xC 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long 0xC 0.--28. 1. "LC,loCredit Value When AV operation is enabled this field contains the loCredit value required for the credit-based shaper algorithm" group.long 0xD6C++0x7 line.long 0x0 "MTL_Q1_Interrupt_Control_Status,This register contains the interrupt enable and status bits for the queue 1 interrupts." hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved." newline bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set the Receive Queue Overflow interrupt is enabled" "0: Receive Queue Overflow Interrupt is disabled,1: Receive Queue Overflow Interrupt is enabled" newline hexmask.long.byte 0x0 17.--23. 1. "Reserved_23_17,Reserved." newline bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet" "0: Receive Queue Overflow Interrupt Status not..,1: Receive Queue Overflow Interrupt Status detected" newline hexmask.long.byte 0x0 10.--15. 1. "Reserved_15_10,Reserved." newline bitfld.long 0x0 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated" "0: Average Bits Per Slot Interrupt is disabled,1: Average Bits Per Slot Interrupt is enabled" newline bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set the Transmit Queue Underflow interrupt is enabled" "0: Transmit Queue Underflow Interrupt Status is..,1: Transmit Queue Underflow Interrupt Status is.." newline hexmask.long.byte 0x0 2.--7. 1. "Reserved_7_2,Reserved." newline bitfld.long 0x0 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set this bit indicates that the MAC has updated the ABS value" "0: Average Bits Per Slot Interrupt Status not..,1: Average Bits Per Slot Interrupt Status detected" newline bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet" "0: Transmit Queue Underflow Interrupt Status not..,1: Transmit Queue Underflow Interrupt Status detected" line.long 0x4 "MTL_RxQ1_Operation_Mode,The Queue 1 Receive Operation Mode register establishes the Receive queue operating modes and command. The RFA and RFD fields are not backward compatible with the RFA and RFD fields of 4.00a release" hexmask.long.byte 0x4 26.--31. 1. "Reserved_31_y,Reserved." newline hexmask.long.byte 0x4 20.--25. 1. "RQS,Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes" newline rbitfld.long 0x4 19. "Reserved_19_y,Reserved." "0,1" newline hexmask.long.byte 0x4 14.--18. 1. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation: - 0: Full minus 1 KB that is FULL 1 KB - 1: Full.." newline rbitfld.long 0x4 13. "Reserved_13_y,Reserved." "0,1" newline hexmask.long.byte 0x4 8.--12. 1. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field see RFD" newline bitfld.long 0x4 7. "EHFC,Enable Hardware Flow Control When this bit is set the flow control signal operation based on the fill-level of Rx queue is enabled" "0: Hardware Flow Control is disabled,1: Hardware Flow Control is enabled" newline bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine" "0: Dropping of TCP/IP Checksum Error Packets is..,1: Dropping of TCP/IP Checksum Error Packets is.." newline bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward When this bit is set the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it ignoring the RTC field of this register" "0: Receive Queue Store and Forward is disabled,1: Receive Queue Store and Forward is enabled" newline bitfld.long 0x4 4. "FEP,Forward Error Packets When this bit is reset the Rx queue drops packets with error status (CRC error GMII_ER watchdog timeout or overflow)" "0: Forward Error Packets is disabled,1: Forward Error Packets is enabled" newline bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets When this bit is set the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes) including pad-bytes and CRC" "0: Forward Undersized Good Packets is disabled,1: Forward Undersized Good Packets is enabled" newline rbitfld.long 0x4 2. "Reserved_2,Reserved." "0,1" newline bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold" "0: 64,1: 32,2: 96,3: 128" rgroup.long 0xD74++0x7 line.long 0x0 "MTL_RxQ1_Missed_Packet_Overflow_Cnt,The Queue 1 Missed Packet and Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow." hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_28,Reserved." newline bitfld.long 0x0 27. "MISCNTOVF,Missed Packet Counter Overflow Bit When set this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit" "0: Missed Packet Counter overflow not detected,1: Missed Packet Counter overflow detected" newline hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue" newline hexmask.long.byte 0x0 12.--15. 1. "Reserved_15_12,Reserved." newline bitfld.long 0x0 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit" "0: Overflow Counter overflow not detected,1: Overflow Counter overflow detected" newline hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow" line.long 0x4 "MTL_RxQ1_Debug,The Queue 1 Receive Debug register gives the debug status of various blocks related to the Receive queue." bitfld.long 0x4 30.--31. "Reserved_31_30,Reserved." "0,1,2,3" newline hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue" newline hexmask.long.word 0x4 6.--15. 1. "Reserved_15_6,Reserved." newline bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue:" "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full" newline bitfld.long 0x4 3. "Reserved_3,Reserved." "0,1" newline bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller:" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status" newline bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high this bit indicates that the MTL Rx queue Write controller is active and it is transferring a received packet to the Rx Queue" "0: MTL Rx Queue Write Controller Active Status not..,1: MTL Rx Queue Write Controller Active Status.." group.long 0xD7C++0x7 line.long 0x0 "MTL_RxQ1_Control,The Queue Receive Control register controls the receive arbitration and passing of received packets to the application." hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved." newline bitfld.long 0x0 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue" "0: Receive Queue Packet Arbitration is disabled,1: Receive Queue Packet Arbitration is enabled" newline bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0" "0,1,2,3,4,5,6,7" line.long 0x4 "MTL_TxQ2_Operation_Mode,The Queue 2 Transmit Operation Mode register establishes the Transmit queue operating modes and commands." hexmask.long.word 0x4 22.--31. 1. "Reserved_31_y,Reserved." newline hexmask.long.byte 0x4 16.--21. 1. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes" newline hexmask.long.word 0x4 7.--15. 1. "Reserved_15_7,Reserved." newline bitfld.long 0x4 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue" "0: 32,1: 64,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512" newline bitfld.long 0x4 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0" "0: Not enabled,1: Enable in AV mode (Reserved in non-AV),2: Enabled,?" newline bitfld.long 0x4 1. "TSF,Transmit Store and Forward When this bit is set the transmission starts when a full packet resides in the MTL Tx queue" "0: Transmit Store and Forward is disabled,1: Transmit Store and Forward is enabled" newline bitfld.long 0x4 0. "FTQ,Flush Transmit Queue When this bit is set the Tx queue controller logic is reset to its default values" "0: Flush Transmit Queue is disabled,1: Flush Transmit Queue is enabled" rgroup.long 0xD84++0x7 line.long 0x0 "MTL_TxQ2_Underflow,The Queue 2 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow and packets missed because of Receive queue packet flush" hexmask.long.tbyte 0x0 12.--31. 1. "Reserved_31_12,Reserved." newline bitfld.long 0x0 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows that is it has crossed the maximum count" "0: Overflow not detected for Underflow Packet Counter,1: Overflow detected for Underflow Packet Counter" newline hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow" line.long 0x4 "MTL_TxQ2_Debug,The Queue 2 Transmit Debug register gives the debug status of various blocks related to the Transmit queue." hexmask.long.word 0x4 23.--31. 1. "Reserved_31_23,Reserved." newline bitfld.long 0x4 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 19. "Reserved_19,Reserved." "0,1" newline bitfld.long 0x4 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4 6.--15. 1. "Reserved_15_6,Reserved." newline bitfld.long 0x4 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high this bit indicates that the MTL Tx Status FIFO is full" "0: MTL Tx Status FIFO Full status is not detected,1: MTL Tx Status FIFO Full status is detected" newline bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high it indicates that the MTL Tx Queue is not empty and some data is left for transmission" "0: MTL Tx Queue Not Empty status is not detected,1: MTL Tx Queue Not Empty status is detected" newline bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status When high this bit indicates that the MTL Tx Queue Write Controller is active and it is transferring the data to the Tx Queue" "0: MTL Tx Queue Write Controller status is not..,1: MTL Tx Queue Write Controller status is detected" newline bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller:" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.." newline bitfld.long 0x4 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "0: Transmit Queue in Pause status is not detected,1: Transmit Queue in Pause status is detected" group.long 0xD90++0x3 line.long 0x0 "MTL_TxQ2_ETS_Control,The Queue ETS Control register controls the enhanced transmission selection operation." hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved." newline bitfld.long 0x0 4.--6. "SLC,Slot Count If the credit-based shaper algorithm is enabled the software can program the number of slots (of duration programmed in DMA_CH(#i)_Slot_Interval register) over which the average transmitted bits per slot provided in the.." "0: 1 slot,1: 2 slots,2: 4 slots,3: 8 slots,4: 16 slots,?,?,?" newline bitfld.long 0x0 3. "CC,Credit Control When this bit is set the accumulated credit parameter in the credit-based shaper algorithm logic is not reset to zero when there is positive credit and no packet to transmit in Channel 1" "0: Credit Control is disabled,1: Credit Control is enabled" newline bitfld.long 0x0 2. "AVALG,AV Algorithm When Queue 1 is programmed for AV this field configures the scheduling algorithm for this queue: This bit when set indicates credit based shaper algorithm (CBS) is selected for Queue 1 traffic" "0: CBS Algorithm is disabled,1: CBS Algorithm is enabled" newline rbitfld.long 0x0 0.--1. "Reserved_1_0,Reserved." "0,1,2,3" rgroup.long 0xD94++0x3 line.long 0x0 "MTL_TxQ2_ETS_Status,The Queue 2 ETS Status register provides the average traffic transmitted in Queue 2." hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved." newline hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot This field contains the average transmitted bits per slot" group.long 0xD98++0xF line.long 0x0 "MTL_TxQ2_Quantum_Weight,The Queue 2 idleSlopeCredit. Quantum or Weights register provides the average traffic transmitted in Queue 2." hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved." newline hexmask.long.tbyte 0x0 0.--20. 1. "ISCQW,idleSlopeCredit Quantum or Weights - idleSlopeCredit When AV feature is enabled this field contains the idleSlopeCredit value required for the credit-based shaper algorithm for Queue 1" line.long 0x4 "MTL_TxQ2_SendSlopeCredit,The sendSlopeCredit register contains the sendSlope credit value required for the credit-based shaper algorithm for the Queue." hexmask.long.tbyte 0x4 14.--31. 1. "Reserved_31_14,Reserved." newline hexmask.long.word 0x4 0.--13. 1. "SSC,sendSlopeCredit Value When AV operation is enabled this field contains the sendSlopeCredit value required for credit-based shaper algorithm for Queue 1" line.long 0x8 "MTL_TxQ2_HiCredit,The hiCredit register contains the hiCredit value required for the credit-based shaper algorithm for the Queue." rbitfld.long 0x8 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long 0x8 0.--28. 1. "HC,hiCredit Value When the AV feature is enabled this field contains the hiCredit value required for the credit-based shaper algorithm" line.long 0xC "MTL_TxQ2_LoCredit,The loCredit register contains the loCredit value required for the credit-based shaper algorithm for the Queue." rbitfld.long 0xC 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long 0xC 0.--28. 1. "LC,loCredit Value When AV operation is enabled this field contains the loCredit value required for the credit-based shaper algorithm" group.long 0xDAC++0x7 line.long 0x0 "MTL_Q2_Interrupt_Control_Status,This register contains the interrupt enable and status bits for the queue 2 interrupts." hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved." newline bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set the Receive Queue Overflow interrupt is enabled" "0: Receive Queue Overflow Interrupt is disabled,1: Receive Queue Overflow Interrupt is enabled" newline hexmask.long.byte 0x0 17.--23. 1. "Reserved_23_17,Reserved." newline bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet" "0: Receive Queue Overflow Interrupt Status not..,1: Receive Queue Overflow Interrupt Status detected" newline hexmask.long.byte 0x0 10.--15. 1. "Reserved_15_10,Reserved." newline bitfld.long 0x0 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated" "0: Average Bits Per Slot Interrupt is disabled,1: Average Bits Per Slot Interrupt is enabled" newline bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set the Transmit Queue Underflow interrupt is enabled" "0: Transmit Queue Underflow Interrupt Status is..,1: Transmit Queue Underflow Interrupt Status is.." newline hexmask.long.byte 0x0 2.--7. 1. "Reserved_7_2,Reserved." newline bitfld.long 0x0 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set this bit indicates that the MAC has updated the ABS value" "0: Average Bits Per Slot Interrupt Status not..,1: Average Bits Per Slot Interrupt Status detected" newline bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet" "0: Transmit Queue Underflow Interrupt Status not..,1: Transmit Queue Underflow Interrupt Status detected" line.long 0x4 "MTL_RxQ2_Operation_Mode,The Queue 2 Receive Operation Mode register establishes the Receive queue operating modes and command. The RFA and RFD fields are not backward compatible with the RFA and RFD fields of 4.00a release" hexmask.long.byte 0x4 26.--31. 1. "Reserved_31_y,Reserved." newline hexmask.long.byte 0x4 20.--25. 1. "RQS,Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes" newline rbitfld.long 0x4 19. "Reserved_19_y,Reserved." "0,1" newline hexmask.long.byte 0x4 14.--18. 1. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation: - 0: Full minus 1 KB that is FULL 1 KB - 1: Full.." newline rbitfld.long 0x4 13. "Reserved_13_y,Reserved." "0,1" newline hexmask.long.byte 0x4 8.--12. 1. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field see RFD" newline bitfld.long 0x4 7. "EHFC,Enable Hardware Flow Control When this bit is set the flow control signal operation based on the fill-level of Rx queue is enabled" "0: Hardware Flow Control is disabled,1: Hardware Flow Control is enabled" newline bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine" "0: Dropping of TCP/IP Checksum Error Packets is..,1: Dropping of TCP/IP Checksum Error Packets is.." newline bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward When this bit is set the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it ignoring the RTC field of this register" "0: Receive Queue Store and Forward is disabled,1: Receive Queue Store and Forward is enabled" newline bitfld.long 0x4 4. "FEP,Forward Error Packets When this bit is reset the Rx queue drops packets with error status (CRC error GMII_ER watchdog timeout or overflow)" "0: Forward Error Packets is disabled,1: Forward Error Packets is enabled" newline bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets When this bit is set the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes) including pad-bytes and CRC" "0: Forward Undersized Good Packets is disabled,1: Forward Undersized Good Packets is enabled" newline rbitfld.long 0x4 2. "Reserved_2,Reserved." "0,1" newline bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold" "0: 64,1: 32,2: 96,3: 128" rgroup.long 0xDB4++0x7 line.long 0x0 "MTL_RxQ2_Missed_Packet_Overflow_Cnt,The Queue 2 Missed Packet and Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow." hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_28,Reserved." newline bitfld.long 0x0 27. "MISCNTOVF,Missed Packet Counter Overflow Bit When set this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit" "0: Missed Packet Counter overflow not detected,1: Missed Packet Counter overflow detected" newline hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue" newline hexmask.long.byte 0x0 12.--15. 1. "Reserved_15_12,Reserved." newline bitfld.long 0x0 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit" "0: Overflow Counter overflow not detected,1: Overflow Counter overflow detected" newline hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow" line.long 0x4 "MTL_RxQ2_Debug,The Queue 2 Receive Debug register gives the debug status of various blocks related to the Receive queue." bitfld.long 0x4 30.--31. "Reserved_31_30,Reserved." "0,1,2,3" newline hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue" newline hexmask.long.word 0x4 6.--15. 1. "Reserved_15_6,Reserved." newline bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue:" "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full" newline bitfld.long 0x4 3. "Reserved_3,Reserved." "0,1" newline bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller:" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status" newline bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high this bit indicates that the MTL Rx queue Write controller is active and it is transferring a received packet to the Rx Queue" "0: MTL Rx Queue Write Controller Active Status not..,1: MTL Rx Queue Write Controller Active Status.." group.long 0xDBC++0x3 line.long 0x0 "MTL_RxQ2_Control,The Queue Receive Control register controls the receive arbitration and passing of received packets to the application." hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved." newline bitfld.long 0x0 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue" "0: Receive Queue Packet Arbitration is disabled,1: Receive Queue Packet Arbitration is enabled" newline bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0" "0,1,2,3,4,5,6,7" group.long 0x1000++0x7 line.long 0x0 "DMA_Mode,The Bus Mode register establishes the bus operating modes for the DMA." hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved." newline rbitfld.long 0x0 22.--23. "Reserved_RNDF,Reserved." "0,1,2,3" newline rbitfld.long 0x0 20.--21. "Reserved_TNDF,Reserved." "0,1,2,3" newline rbitfld.long 0x0 19. "Reserved_DCHE,Reserved." "0,1" newline rbitfld.long 0x0 18. "Reserved_18,Reserved." "0,1" newline bitfld.long 0x0 16.--17. "INTM,Interrupt Mode This field defines the interrupt mode of DWC_ether_qos" "0: See above description,1: See above description,2: See above description,?" newline rbitfld.long 0x0 15. "Reserved_15,Reserved." "0,1" newline bitfld.long 0x0 12.--14. "PR,Priority Ratio These bits control the priority ratio in weighted round-robin arbitration between the Rx DMA and Tx DMA" "0: The priority ratio is 1:1,1: The priority ratio is 2:1,2: The priority ratio is 3:1,3: The priority ratio is 4:1,4: The priority ratio is 5:1,5: The priority ratio is 6:1,6: The priority ratio is 7:1,7: The priority ratio is 8:1" newline bitfld.long 0x0 11. "TXPR,Transmit Priority When set this bit indicates that the Tx DMA has higher priority than the Rx DMA during arbitration for the system-side bus or Descriptor reads from DCACHE memory when DWC_EQOS_DCEXT is enabled" "0: Transmit Priority is disabled,1: Transmit Priority is enabled" newline rbitfld.long 0x0 10. "Reserved_SCSW,Reserved." "0,1" newline bitfld.long 0x0 9. "ARBC,ARBC is NXP Reserved This field must be set to '0'" "0: NXP reserved field disabled,1: NXP reserved field enabled up on NXP request" newline rbitfld.long 0x0 8. "Reserved_DSPW,Reserved." "0,1" newline rbitfld.long 0x0 5.--7. "Reserved_7_5,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--4. "TAA,Transmit Arbitration Algorithm This field is used to select the arbitration algorithm for the Transmit side when multiple Tx DMAs are selected" "0: Fixed priority (Channel 0 has the lowest..,1: Weighted Strict Priority (WSP),2: Weighted Round-Robin (WRR),?,?,?,?,?" newline bitfld.long 0x0 1. "DA,DMA Tx or Rx Arbitration Scheme This bit specifies the arbitration scheme between the Transmit and Receive paths of all channels: - 0: Weighted Round-Robin with Rx:Tx or Tx:Rx The priority between the paths is according to the priority specified in.." "0: Weighted Round-Robin with Rx:Tx or Tx:Rx The..,1: Fixed Priority" newline bitfld.long 0x0 0. "SWR,Software Reset When this bit is set the MAC and the DMA controller reset the logic and all internal registers of the DMA MTL and MAC" "0: Software Reset is disabled,1: Software Reset is enabled" line.long 0x4 "DMA_SysBus_Mode,The System Bus mode register controls the behavior of the AHB or AXI master. It mainly controls burst splitting and number of outstanding requests." rbitfld.long 0x4 31. "Reserved_EN_LPI,Reserved." "0,1" newline rbitfld.long 0x4 30. "Reserved_LPI_XIT_PKT,Reserved." "0,1" newline rbitfld.long 0x4 27.--29. "Reserved_29_y,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 24.--26. "Reserved_WR_OSR_LMT,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 19.--23. 1. "Reserved_23_y,Reserved." newline rbitfld.long 0x4 16.--18. "Reserved_RD_OSR_LMT,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 15. "RB,Rebuild INCRx Burst When this bit is set high and the AHB master gets SPLIT RETRY or Early Burst Termination (EBT) response the AHB master interface rebuilds the pending beats of any initiated burst transfer with INCRx and SINGLE transfers" "0: Rebuild INCRx Burst is disabled,1: Rebuild INCRx Burst is enabled" newline bitfld.long 0x4 14. "MB,Mixed Burst When this bit is high and the FB bit is low the AHB master performs undefined bursts transfers (INCR) for burst length of 16 or more" "0: Mixed Burst is disabled,1: Mixed Burst is enabled" newline rbitfld.long 0x4 13. "Reserved_ONEKBBE,Reserved." "0,1" newline bitfld.long 0x4 12. "AAL,Address-Aligned Beats When this bit is set to 1 the EQOS-AXI or EQOS-AHB master performs address-aligned burst transfers on Read and Write channels" "0: Address-Aligned Beats is disabled,1: Address-Aligned Beats is enabled" newline rbitfld.long 0x4 11. "Reserved_EAME,Reserved." "0,1" newline rbitfld.long 0x4 10. "Reserved_AALE,Reserved." "0,1" newline rbitfld.long 0x4 8.--9. "Reserved_9_8,Reserved." "0,1,2,3" newline rbitfld.long 0x4 7. "Reserved_BLEN256,Reserved." "0,1" newline rbitfld.long 0x4 6. "Reserved_BLEN128,Reserved." "0,1" newline rbitfld.long 0x4 5. "Reserved_BLEN64,Reserved." "0,1" newline rbitfld.long 0x4 4. "Reserved_BLEN32,Reserved." "0,1" newline rbitfld.long 0x4 3. "Reserved_BLEN16,Reserved." "0,1" newline rbitfld.long 0x4 2. "Reserved_BLEN8,Reserved." "0,1" newline rbitfld.long 0x4 1. "Reserved_BLEN4,Reserved." "0,1" newline bitfld.long 0x4 0. "FB,Fixed Burst Length - 1: AHB master initiates burst transfers of specified length (INCRx or SINGLE)" "0: Fixed Burst Length is disabled,1: AHB master initiates burst transfers of.." rgroup.long 0x1008++0x7 line.long 0x0 "DMA_Interrupt_Status,The application reads this Interrupt Status register during interrupt service routine or polling to determine the interrupt status of DMA channels. MTL queues. and the MAC." hexmask.long.word 0x0 18.--31. 1. "Reserved_31_18,Reserved." newline bitfld.long 0x0 17. "MACIS,MAC Interrupt Status This bit indicates an interrupt event in the MAC" "0: MAC Interrupt Status not detected,1: MAC Interrupt Status detected" newline bitfld.long 0x0 16. "MTLIS,MTL Interrupt Status This bit indicates an interrupt event in the MTL" "0: MTL Interrupt Status not detected,1: MTL Interrupt Status detected" newline hexmask.long.byte 0x0 8.--15. 1. "Reserved_15_8,Reserved." newline bitfld.long 0x0 7. "Reserved_DC7IS,Reserved." "0,1" newline bitfld.long 0x0 6. "Reserved_DC6IS,Reserved." "0,1" newline bitfld.long 0x0 5. "Reserved_DC5IS,Reserved." "0,1" newline bitfld.long 0x0 4. "Reserved_DC4IS,Reserved." "0,1" newline bitfld.long 0x0 3. "Reserved_DC3IS,Reserved." "0,1" newline bitfld.long 0x0 2. "DC2IS,DMA Channel 2 Interrupt Status This bit indicates an interrupt event in DMA Channel 2" "0: DMA Channel 2 Interrupt Status not detected,1: DMA Channel 2 Interrupt Status detected" newline bitfld.long 0x0 1. "DC1IS,DMA Channel 1 Interrupt Status This bit indicates an interrupt event in DMA Channel 1" "0: DMA Channel 1 Interrupt Status not detected,1: DMA Channel 1 Interrupt Status detected" newline bitfld.long 0x0 0. "DC0IS,DMA Channel 0 Interrupt Status This bit indicates an interrupt event in DMA Channel 0" "0: DMA Channel 0 Interrupt Status not detected,1: DMA Channel 0 Interrupt Status detected" line.long 0x4 "DMA_Debug_Status0,The Debug Status 0 register gives the Receive and Transmit process status for DMA Channel 0-Channel 2 for debugging purpose." hexmask.long.byte 0x4 28.--31. 1. "TPS2,DMA Channel 2 Transmit Process State This field indicates the Tx DMA FSM state for Channel 2" newline hexmask.long.byte 0x4 24.--27. 1. "RPS2,DMA Channel 2 Receive Process State This field indicates the Rx DMA FSM state for Channel 2" newline hexmask.long.byte 0x4 20.--23. 1. "TPS1,DMA Channel 1 Transmit Process State This field indicates the Tx DMA FSM state for Channel 1" newline hexmask.long.byte 0x4 16.--19. 1. "RPS1,DMA Channel 1 Receive Process State This field indicates the Rx DMA FSM state for Channel 1" newline hexmask.long.byte 0x4 12.--15. 1. "TPS0,DMA Channel 0 Transmit Process State This field indicates the Tx DMA FSM state for Channel 0" newline hexmask.long.byte 0x4 8.--11. 1. "RPS0,DMA Channel 0 Receive Process State This field indicates the Rx DMA FSM state for Channel 0" newline hexmask.long.byte 0x4 2.--7. 1. "Reserved_7_2,Reserved." newline bitfld.long 0x4 1. "Reserved_AXRHSTS,Reserved." "0,1" newline bitfld.long 0x4 0. "AXWHSTS,AHB Master Status When high this bit indicates that the AHB master FSMs are in the non-idle state." "0: AXI Master Write Channel or AHB Master Status..,1: AXI Master Write Channel or AHB Master Status.." group.long 0x1050++0xF line.long 0x0 "DMA_TBS_CTRL0,This register is used to control the TBS attributes." hexmask.long.tbyte 0x0 8.--31. 1. "FTOS,Fetch Time Offset The value in units of 256 nanoseconds that has to be deducted from the Launch time to compute the Fetch Time" newline rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1" newline bitfld.long 0x0 4.--6. "FGOS,Fetch GSN Offset The number GSN slots that must be deducted from the Launch GSN to compute the Fetch GSN" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "FTOV,Fetch Time Offset Valid When set indicates the FTOS field is valid" "0: Fetch Time Offset is invalid,1: Fetch Time Offset is valid" line.long 0x4 "DMA_TBS_CTRL1,This register is used to control the TBS attributes." hexmask.long.tbyte 0x4 8.--31. 1. "FTOS,Fetch Time Offset The value in units of 256 nanoseconds that has to be deducted from the Launch time to compute the Fetch Time" newline rbitfld.long 0x4 7. "Reserved_7,Reserved." "0,1" newline bitfld.long 0x4 4.--6. "FGOS,Fetch GSN Offset The number GSN slots that must be deducted from the Launch GSN to compute the Fetch GSN" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "FTOV,Fetch Time Offset Valid When set indicates the FTOS field is valid" "0: Fetch Time Offset is invalid,1: Fetch Time Offset is valid" line.long 0x8 "DMA_TBS_CTRL2,This register is used to control the TBS attributes." hexmask.long.tbyte 0x8 8.--31. 1. "FTOS,Fetch Time Offset The value in units of 256 nanoseconds that has to be deducted from the Launch time to compute the Fetch Time" newline rbitfld.long 0x8 7. "Reserved_7,Reserved." "0,1" newline bitfld.long 0x8 4.--6. "FGOS,Fetch GSN Offset The number GSN slots that must be deducted from the Launch GSN to compute the Fetch GSN" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "FTOV,Fetch Time Offset Valid When set indicates the FTOS field is valid" "0: Fetch Time Offset is invalid,1: Fetch Time Offset is valid" line.long 0xC "DMA_TBS_CTRL3,This register is used to control the TBS attributes." hexmask.long.tbyte 0xC 8.--31. 1. "FTOS,Fetch Time Offset The value in units of 256 nanoseconds that has to be deducted from the Launch time to compute the Fetch Time" newline rbitfld.long 0xC 7. "Reserved_7,Reserved." "0,1" newline bitfld.long 0xC 4.--6. "FGOS,Fetch GSN Offset The number GSN slots that must be deducted from the Launch GSN to compute the Fetch GSN" "0,1,2,3,4,5,6,7" newline rbitfld.long 0xC 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "FTOV,Fetch Time Offset Valid When set indicates the FTOS field is valid" "0: Fetch Time Offset is invalid,1: Fetch Time Offset is valid" rgroup.long 0x1080++0x3 line.long 0x0 "DMA_Safety_Interrupt_Status,This register indicates summary (whether error occured in DMA/MTL/MAC and correctable/uncorrectable) of the Automotive Safety related error interrupts." bitfld.long 0x0 31. "MCSIS,MAC Safety Uncorrectable Interrupt Status Indicates a uncorrectable Safety related Interrupt is set in the MAC module" "0: MAC Safety Uncorrectable Interrupt Status not..,1: MAC Safety Uncorrectable Interrupt Status detected" newline bitfld.long 0x0 30. "Reserved_30,Reserved." "0,1" newline bitfld.long 0x0 29. "MSUIS,MTL Safety Uncorrectable error Interrupt Status This bit indicates an uncorrectable error interrupt event in MTL" "0: MTL Safety Uncorrectable error Interrupt Status..,1: MTL Safety Uncorrectable error Interrupt Status.." newline bitfld.long 0x0 28. "MSCIS,MTL Safety Correctable error Interrupt Status This bit indicates a correctable error interrupt event in MTL" "0: MTL Safety Correctable error Interrupt Status..,1: MTL Safety Correctable error Interrupt Status.." newline hexmask.long 0x0 2.--27. 1. "Reserved_27_2,Reserved." newline bitfld.long 0x0 1. "DEUIS,DMA ECC Uncorrectable error Interrupt Status This bit indicates an interrupt event in the DMA ECC safety feature" "0: DMA ECC Uncorrectable error Interrupt Status not..,1: DMA ECC Uncorrectable error Interrupt Status.." newline bitfld.long 0x0 0. "DECIS,DMA ECC Correctable error Interrupt Status This bit indicates an interrupt event in the DMA ECC safety feature" "0: DMA ECC Correctable error Interrupt Status not..,1: DMA ECC Correctable error Interrupt Status.." group.long 0x1100++0xB line.long 0x0 "DMA_CH0_Control,The DMA Channeli Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode." hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved." newline bitfld.long 0x0 24. "SPH,Split Headers When this bit is set the DMA splits the header and payload in the Receive path" "0: Split Headers feature is disabled,1: Split Headers feature is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length This bit specifies the Word Dword or Lword number (depending on the 32-bit 64-bit or 128-bit bus) to skip between two unchained descriptors" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1" newline bitfld.long 0x0 16. "PBLx8,8xPBL mode When this bit is set the PBL value programmed in Bits[21:16] in DMA_CH(#i)_Tx_Control and Bits[21:16] in DMA_CH(#i)_Rx_Control is multiplied by eight times" "0: 8xPBL mode is disabled,1: 8xPBL mode is enabled" newline rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3" newline hexmask.long.word 0x0 0.--13. 1. "Reserved_MSS,Reserved." line.long 0x4 "DMA_CH0_Tx_Control,The DMA Channeli Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights." rbitfld.long 0x4 31. "Reserved_31,Reserved." "0,1" newline bitfld.long 0x4 29.--30. "TFSEL,TBS Fetch Select Select bits for one of the four DMA_TBS_CTRL register fields (FTOS FGSN FTOV) for the channel Values: - 2'b00: DMA_TBS_CTRL0 - 2'b01: DMA_TBS_CTRL1 - 2'b10: DMA_TBS_CTRL2 - 2'b11: DMA_TBS_CTRL3 (Reserved if DWC_EQOS_NUM_DMA_TX_CH=3)" "0: DMA_TBS_CTRL0,1: DMA_TBS_CTRL1,2: DMA_TBS_CTRL2,3: DMA_TBS_CTRL3" newline bitfld.long 0x4 28. "EDSE,Enhanced Descriptor Enable When this bit is set the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors" "0: Enhanced Descriptor is disabled,1: Enhanced Descriptor is enabled" newline hexmask.long.byte 0x4 24.--27. 1. "Reserved_TQOS,Reserved." newline rbitfld.long 0x4 23. "Reserved_23,Reserved." "0,1" newline bitfld.long 0x4 22. "ETIC,Early Transmit Interrupt Control When this bit is set Early Transmit Interrupt (ETI) status is set after completion of transfer of data from buffers of a transmit descriptor in which IOC bit (TDES2[31]) is set" "0: Early Transmit Interrupt is disabled,1: Early Transmit Interrupt is enabled" newline hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" newline rbitfld.long 0x4 15. "Reserved_IPBL,Reserved." "0,1" newline rbitfld.long 0x4 13.--14. "Reserved_TSE_MODE,Reserved." "0,1,2,3" newline rbitfld.long 0x4 12. "Reserved_TSE,Reserved." "0,1" newline hexmask.long.byte 0x4 5.--11. 1. "Reserved_11_5,Reserved." newline bitfld.long 0x4 4. "OSF,Operate on Second Packet When this bit is set it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained" "0: Operate on Second Packet disabled,1: Operate on Second Packet enabled" newline bitfld.long 0x4 1.--3. "TCW,Transmit Channel Weight This field indicates the weight assigned to the corresponding Transmit channel" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "ST,Start or Stop Transmission Command When this bit is set transmission is placed in the Running state" "0: Stop Transmission Command,1: Start Transmission Command" line.long 0x8 "DMA_CH0_Rx_Control,The DMA Channeli Receive Control register controls the Rx features such as PBL. buffer size. and extended status." bitfld.long 0x8 31. "RPF,Rx Packet Flush" "0: Rx Packet Flush is disabled,1: Rx Packet Flush is enabled" newline rbitfld.long 0x8 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 24.--27. 1. "Reserved_RQOS,Reserved." newline rbitfld.long 0x8 23. "Reserved_23,Reserved." "0,1" newline bitfld.long 0x8 22. "ERIC,Early Receive Interrupt Control When this bit is set Early Receive Interrupt (ERI) status is set after the completion of every burst transfer of data from the Rx DMA to the buffer" "0: Early Receive Interrupt is disabled,1: Early Receive Interrupt is enabled" newline hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" newline rbitfld.long 0x8 15. "Reserved_15,Reserved." "0,1" newline hexmask.long.word 0x8 4.--14. 1. "RBSZ_13_y,Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0" newline rbitfld.long 0x8 1.--3. "RBSZ_x_0,Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "SR,Start or Stop Receive When this bit is set the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets" "0: Stop Receive,1: Start Receive" group.long 0x1114++0x3 line.long 0x0 "DMA_CH0_TxDesc_List_Address,The Channeli Tx Descriptor List Address register points the DMA to the start of Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Word. Dword. or Lword-aligned.." hexmask.long 0x0 3.--31. 1. "TDESLA,Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list" newline rbitfld.long 0x0 0.--2. "Reserved_LSb,Reserved." "0,1,2,3,4,5,6,7" group.long 0x111C++0x7 line.long 0x0 "DMA_CH0_RxDesc_List_Address,The Channeli Rx Descriptor List Address register points the DMA to the start of Receive descriptor list. This register points to the start of the Receive Descriptor List. The descriptor lists reside in the physical memory.." hexmask.long 0x0 3.--31. 1. "RDESLA,Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list" newline rbitfld.long 0x0 0.--2. "Reserved_LSb,Reserved." "0,1,2,3,4,5,6,7" line.long 0x4 "DMA_CH0_TxDesc_Tail_Pointer,The Channeli Tx Descriptor Tail Pointer register points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x4 3.--31. 1. "TDTP,Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring" newline rbitfld.long 0x4 0.--2. "Reserved_LSb,Reserved." "0,1,2,3,4,5,6,7" group.long 0x1128++0x17 line.long 0x0 "DMA_CH0_RxDesc_Tail_Pointer,The Channeli Rx Descriptor Tail Pointer Points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x0 3.--31. 1. "RDTP,Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring" newline rbitfld.long 0x0 0.--2. "Reserved_LSb,Reserved." "0,1,2,3,4,5,6,7" line.long 0x4 "DMA_CH0_TxDesc_Ring_Length,The Tx Descriptor Ring Length register contains the length of the Transmit descriptor ring." hexmask.long.tbyte 0x4 10.--31. 1. "Reserved_31_10,Reserved." newline hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring" line.long 0x8 "DMA_CH0_Rx_Control2,The Channeli Receive Control register controls the Rx features such as Rx Descriptor Ring Length and Alternate Rx Buffer Size." hexmask.long.byte 0x8 24.--31. 1. "Reserved_31_24,Reserved." newline hexmask.long.byte 0x8 17.--23. 1. "ARBS,Alternate Receive Buffer Size Indicates size in bytes for Buffer 1 when ARBS is programmed to a non-zero value (when split header feature is not enabled)" newline hexmask.long.byte 0x8 10.--16. 1. "Reserved_x_10,Reserved." newline hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring" line.long 0xC "DMA_CH0_Interrupt_Enable,The Channeli Interrupt Enable register enables the interrupts reported by the Status register." hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved." newline bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable When this bit is set the normal interrupt summary is enabled" "0: Normal Interrupt Summary is disabled,1: Normal Interrupt Summary is enabled" newline bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable When this bit is set the abnormal interrupt summary is enabled" "0: Abnormal Interrupt Summary is disabled,1: Abnormal Interrupt Summary is enabled" newline bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable When this bit is set along with the AIE bit the Descriptor error interrupt is enabled" "0: Context Descriptor Error is disabled,1: Context Descriptor Error is enabled" newline bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable When this bit is set along with the AIE bit the Fatal Bus error interrupt is enabled" "0: Fatal Bus Error is disabled,1: Fatal Bus Error is enabled" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt Enable When this bit is set along with the NIE bit the Early Receive interrupt is enabled" "0: Early Receive Interrupt is disabled,1: Early Receive Interrupt is enabled" newline bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt Enable When this bit is set along with the AIE bit the Early Transmit interrupt is enabled" "0: Early Transmit Interrupt is disabled,1: Early Transmit Interrupt is enabled" newline bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout Enable When this bit is set along with the AIE bit the Receive Watchdog Timeout interrupt is enabled" "0: Receive Watchdog Timeout is disabled,1: Receive Watchdog Timeout is enabled" newline bitfld.long 0xC 8. "RSE,Receive Stopped Enable When this bit is set along with the AIE bit the Receive Stopped Interrupt is enabled" "0: Receive Stopped is disabled,1: Receive Stopped is enabled" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable When this bit is set along with the AIE bit the Receive Buffer Unavailable interrupt is enabled" "0: Receive Buffer Unavailable is disabled,1: Receive Buffer Unavailable is enabled" newline bitfld.long 0xC 6. "RIE,Receive Interrupt Enable When this bit is set along with the NIE bit the Receive Interrupt is enabled" "0: Receive Interrupt is disabled,1: Receive Interrupt is enabled" newline rbitfld.long 0xC 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit the Transmit Buffer Unavailable interrupt is enabled" "0: Transmit Buffer Unavailable is disabled,1: Transmit Buffer Unavailable is enabled" newline bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable When this bit is set along with the AIE bit the Transmission Stopped interrupt is enabled" "0: Transmit Stopped is disabled,1: Transmit Stopped is enabled" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable When this bit is set along with the NIE bit the Transmit Interrupt is enabled" "0: Transmit Interrupt is disabled,1: Transmit Interrupt is enabled" line.long 0x10 "DMA_CH0_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. When this register is written with a non-zero value. it enables the watchdog timer for the RI bit of.." hexmask.long.word 0x10 18.--31. 1. "Reserved_31_18,Reserved." newline bitfld.long 0x10 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field" "0,1,2,3" newline hexmask.long.byte 0x10 8.--15. 1. "Reserved_15_8,Reserved." newline hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles multiplied by factor indicated in RWTU field for which the watchdog timer is set" line.long 0x14 "DMA_CH0_Slot_Function_Control_Status,The Slot Function Control and Status register contains the control bits for slot function and the status for Transmit path." hexmask.long.word 0x14 20.--31. 1. "Reserved_31_20,Reserved." newline hexmask.long.byte 0x14 16.--19. 1. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA" newline hexmask.long.word 0x14 4.--15. 1. "SIV,Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets" newline rbitfld.long 0x14 2.--3. "Reserved_3_2,Reserved." "0,1,2,3" newline bitfld.long 0x14 1. "ASC,Advance Slot Check When set this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot.." "0: Advance Slot Check is disabled,1: Advance Slot Check is enabled" newline bitfld.long 0x14 0. "ESC,Enable Slot Comparison When set this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field" "0: Slot Comparison is disabled,1: Slot Comparison is enabled" rgroup.long 0x1144++0x3 line.long 0x0 "DMA_CH0_Current_App_TxDesc,The Channeli Current Application Transmit Descriptor register points to the current Transmit descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation" rgroup.long 0x114C++0x3 line.long 0x0 "DMA_CH0_Current_App_RxDesc,The Channeli Current Application Receive Descriptor register points to the current Receive descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation" rgroup.long 0x1154++0x3 line.long 0x0 "DMA_CH0_Current_App_TxBuffer,The Channeli Current Application Transmit Buffer Address register points to the current Tx buffer address read by the DMA." hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation" rgroup.long 0x115C++0x3 line.long 0x0 "DMA_CH0_Current_App_RxBuffer,The Channel 0 Current Application Receive Buffer Address register points to the current Rx buffer address read by the DMA." hexmask.long 0x0 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation" group.long 0x1160++0x3 line.long 0x0 "DMA_CH0_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA. Note: The number of DMA_CH(#i)_Status register in the configuration is the higher of number of Rx.." hexmask.long.word 0x0 22.--31. 1. "Reserved_31_22,Reserved." newline rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer.." "0: Transmit Interrupt,1: Normal Interrupt Summary status detected" newline bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer.." "0: Abnormal Interrupt Summary status not detected,1: Transmit Process Stopped" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates.." "0: Context Descriptor Error status not detected,1: Context Descriptor Error status detected" newline bitfld.long 0x0 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field)" "0: Fatal Bus Error status not detected,1: Fatal Bus Error status detected" newline bitfld.long 0x0 11. "ERI,Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory" "0: Early Receive Interrupt status not detected,1: Early Receive Interrupt status detected" newline bitfld.long 0x0 10. "ETI,Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory" "0: Early Transmit Interrupt status not detected,1: Early Transmit Interrupt status detected" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received" "0: Receive Watchdog Timeout status not detected,1: Receive Watchdog Timeout status detected" newline bitfld.long 0x0 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state" "0: Receive Process Stopped status not detected,1: Receive Process Stopped status detected" newline bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list and the DMA cannot acquire it" "0: Receive Buffer Unavailable status not detected,1: Receive Buffer Unavailable status detected" newline bitfld.long 0x0 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete" "0: Receive Interrupt status not detected,1: Receive Interrupt status detected" newline rbitfld.long 0x0 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list and the DMA cannot acquire it" "0: Transmit Buffer Unavailable status not detected,1: Transmit Buffer Unavailable status detected" newline bitfld.long 0x0 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped" "0: Transmit Process Stopped status not detected,1: Transmit Process Stopped status detected" newline bitfld.long 0x0 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete" "0: Transmit Interrupt status not detected,1: Transmit Interrupt status detected" rgroup.long 0x1164++0xB line.long 0x0 "DMA_CH0_Miss_Frame_Cnt,This register has the number of packet counter that got dropped by the DMA either due to Bus Error or due to programming RPF field in DMA_CH{i}_Rx_Control register." hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved." newline bitfld.long 0x0 15. "MFCO,Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further" "0: Miss Frame Counter overflow not occurred,1: Miss Frame Counter overflow occurred" newline hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved." newline hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programing RPF field in DMA_CH{i}_Rx_Control register" line.long 0x4 "DMA_CH0_RXP_Accept_Cnt,The DMA_CH(#i)_RXP_Accept_Cnt registers provides the count of the number of frames accepted by Rx Parser." bitfld.long 0x4 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit When set this bit indicates that the RXPAC Counter field crossed the maximum limit" "0: Rx Parser Accept Counter overflow not occurred,1: Rx Parser Accept Counter overflow occurred" newline hexmask.long 0x4 0.--30. 1. "RXPAC,Rx Parser Accept Counter This 31-bit counter is implemented when a Rx Parser Accept a packet due to AF =1" line.long 0x8 "DMA_CH0_RX_ERI_Cnt,The DMA_CH(#i)_RX_ERI_Cnt registers provides the count of the number of times ERI was asserted." hexmask.long.tbyte 0x8 12.--31. 1. "Reserved_31_12,Reserved." newline hexmask.long.word 0x8 0.--11. 1. "ECNT,ERI Counter When ERIC bit of DMA_CH(#i)_RX_Control register is set this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer" group.long 0x1180++0xB line.long 0x0 "DMA_CH1_Control,The DMA Channeli Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode." hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved." newline bitfld.long 0x0 24. "SPH,Split Headers When this bit is set the DMA splits the header and payload in the Receive path" "0: Split Headers feature is disabled,1: Split Headers feature is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length This bit specifies the Word Dword or Lword number (depending on the 32-bit 64-bit or 128-bit bus) to skip between two unchained descriptors" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1" newline bitfld.long 0x0 16. "PBLx8,8xPBL mode When this bit is set the PBL value programmed in Bits[21:16] in DMA_CH(#i)_Tx_Control and Bits[21:16] in DMA_CH(#i)_Rx_Control is multiplied by eight times" "0: 8xPBL mode is disabled,1: 8xPBL mode is enabled" newline rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3" newline hexmask.long.word 0x0 0.--13. 1. "Reserved_MSS,Reserved." line.long 0x4 "DMA_CH1_Tx_Control,The DMA Channeli Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights." rbitfld.long 0x4 31. "Reserved_31,Reserved." "0,1" newline bitfld.long 0x4 29.--30. "TFSEL,TBS Fetch Select Select bits for one of the four DMA_TBS_CTRL register fields (FTOS FGSN FTOV) for the channel Values: - 2'b00: DMA_TBS_CTRL0 - 2'b01: DMA_TBS_CTRL1 - 2'b10: DMA_TBS_CTRL2 - 2'b11: DMA_TBS_CTRL3 (Reserved if DWC_EQOS_NUM_DMA_TX_CH=3)" "0: DMA_TBS_CTRL0,1: DMA_TBS_CTRL1,2: DMA_TBS_CTRL2,3: DMA_TBS_CTRL3" newline bitfld.long 0x4 28. "EDSE,Enhanced Descriptor Enable When this bit is set the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors" "0: Enhanced Descriptor is disabled,1: Enhanced Descriptor is enabled" newline hexmask.long.byte 0x4 24.--27. 1. "Reserved_TQOS,Reserved." newline rbitfld.long 0x4 23. "Reserved_23,Reserved." "0,1" newline bitfld.long 0x4 22. "ETIC,Early Transmit Interrupt Control When this bit is set Early Transmit Interrupt (ETI) status is set after completion of transfer of data from buffers of a transmit descriptor in which IOC bit (TDES2[31]) is set" "0: Early Transmit Interrupt is disabled,1: Early Transmit Interrupt is enabled" newline hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" newline rbitfld.long 0x4 15. "Reserved_IPBL,Reserved." "0,1" newline rbitfld.long 0x4 13.--14. "Reserved_TSE_MODE,Reserved." "0,1,2,3" newline rbitfld.long 0x4 12. "Reserved_TSE,Reserved." "0,1" newline hexmask.long.byte 0x4 5.--11. 1. "Reserved_11_5,Reserved." newline bitfld.long 0x4 4. "OSF,Operate on Second Packet When this bit is set it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained" "0: Operate on Second Packet disabled,1: Operate on Second Packet enabled" newline bitfld.long 0x4 1.--3. "TCW,Transmit Channel Weight This field indicates the weight assigned to the corresponding Transmit channel" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "ST,Start or Stop Transmission Command When this bit is set transmission is placed in the Running state" "0: Stop Transmission Command,1: Start Transmission Command" line.long 0x8 "DMA_CH1_Rx_Control,The DMA Channeli Receive Control register controls the Rx features such as PBL. buffer size. and extended status." bitfld.long 0x8 31. "RPF,Rx Packet Flush" "0: Rx Packet Flush is disabled,1: Rx Packet Flush is enabled" newline rbitfld.long 0x8 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 24.--27. 1. "Reserved_RQOS,Reserved." newline rbitfld.long 0x8 23. "Reserved_23,Reserved." "0,1" newline bitfld.long 0x8 22. "ERIC,Early Receive Interrupt Control When this bit is set Early Receive Interrupt (ERI) status is set after the completion of every burst transfer of data from the Rx DMA to the buffer" "0: Early Receive Interrupt is disabled,1: Early Receive Interrupt is enabled" newline hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" newline rbitfld.long 0x8 15. "Reserved_15,Reserved." "0,1" newline hexmask.long.word 0x8 4.--14. 1. "RBSZ_13_y,Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0" newline rbitfld.long 0x8 1.--3. "RBSZ_x_0,Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "SR,Start or Stop Receive When this bit is set the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets" "0: Stop Receive,1: Start Receive" group.long 0x1194++0x3 line.long 0x0 "DMA_CH1_TxDesc_List_Address,The Channeli Tx Descriptor List Address register points the DMA to the start of Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Word. Dword. or Lword-aligned.." hexmask.long 0x0 3.--31. 1. "TDESLA,Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list" newline rbitfld.long 0x0 0.--2. "Reserved_LSb,Reserved." "0,1,2,3,4,5,6,7" group.long 0x119C++0x7 line.long 0x0 "DMA_CH1_RxDesc_List_Address,The Channeli Rx Descriptor List Address register points the DMA to the start of Receive descriptor list. This register points to the start of the Receive Descriptor List. The descriptor lists reside in the physical memory.." hexmask.long 0x0 3.--31. 1. "RDESLA,Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list" newline rbitfld.long 0x0 0.--2. "Reserved_LSb,Reserved." "0,1,2,3,4,5,6,7" line.long 0x4 "DMA_CH1_TxDesc_Tail_Pointer,The Channeli Tx Descriptor Tail Pointer register points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x4 3.--31. 1. "TDTP,Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring" newline rbitfld.long 0x4 0.--2. "Reserved_LSb,Reserved." "0,1,2,3,4,5,6,7" group.long 0x11A8++0x17 line.long 0x0 "DMA_CH1_RxDesc_Tail_Pointer,The Channeli Rx Descriptor Tail Pointer Points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x0 3.--31. 1. "RDTP,Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring" newline rbitfld.long 0x0 0.--2. "Reserved_LSb,Reserved." "0,1,2,3,4,5,6,7" line.long 0x4 "DMA_CH1_TxDesc_Ring_Length,The Tx Descriptor Ring Length register contains the length of the Transmit descriptor ring." hexmask.long.tbyte 0x4 10.--31. 1. "Reserved_31_10,Reserved." newline hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring Length" line.long 0x8 "DMA_CH1_Rx_Control2,The Channeli Receive Control register controls the Rx features such as Rx Descriptor Ring Length and Alternate Rx Buffer Size." hexmask.long.byte 0x8 24.--31. 1. "Reserved_31_24,Reserved." newline hexmask.long.byte 0x8 17.--23. 1. "ARBS,Alternate Receive Buffer Size Indicates size in bytes for Buffer 1 when ARBS is programmed to a non-zero value (when split header feature is not enabled)" newline hexmask.long.byte 0x8 10.--16. 1. "Reserved_x_10,Reserved." newline hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring" line.long 0xC "DMA_CH1_Interrupt_Enable,The Channeli Interrupt Enable register enables the interrupts reported by the Status register." hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved." newline bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable When this bit is set the normal interrupt summary is enabled" "0: Normal Interrupt Summary is disabled,1: Normal Interrupt Summary is enabled" newline bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable When this bit is set the abnormal interrupt summary is enabled" "0: Abnormal Interrupt Summary is disabled,1: Abnormal Interrupt Summary is enabled" newline bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable When this bit is set along with the AIE bit the Descriptor error interrupt is enabled" "0: Context Descriptor Error is disabled,1: Context Descriptor Error is enabled" newline bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable When this bit is set along with the AIE bit the Fatal Bus error interrupt is enabled" "0: Fatal Bus Error is disabled,1: Fatal Bus Error is enabled" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt Enable When this bit is set along with the NIE bit the Early Receive interrupt is enabled" "0: Early Receive Interrupt is disabled,1: Early Receive Interrupt is enabled" newline bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt Enable When this bit is set along with the AIE bit the Early Transmit interrupt is enabled" "0: Early Transmit Interrupt is disabled,1: Early Transmit Interrupt is enabled" newline bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout Enable When this bit is set along with the AIE bit the Receive Watchdog Timeout interrupt is enabled" "0: Receive Watchdog Timeout is disabled,1: Receive Watchdog Timeout is enabled" newline bitfld.long 0xC 8. "RSE,Receive Stopped Enable When this bit is set along with the AIE bit the Receive Stopped Interrupt is enabled" "0: Receive Stopped is disabled,1: Receive Stopped is enabled" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable When this bit is set along with the AIE bit the Receive Buffer Unavailable interrupt is enabled" "0: Receive Buffer Unavailable is disabled,1: Receive Buffer Unavailable is enabled" newline bitfld.long 0xC 6. "RIE,Receive Interrupt Enable When this bit is set along with the NIE bit the Receive Interrupt is enabled" "0: Receive Interrupt is disabled,1: Receive Interrupt is enabled" newline rbitfld.long 0xC 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit the Transmit Buffer Unavailable interrupt is enabled" "0: Transmit Buffer Unavailable is disabled,1: Transmit Buffer Unavailable is enabled" newline bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable When this bit is set along with the AIE bit the Transmission Stopped interrupt is enabled" "0: Transmit Stopped is disabled,1: Transmit Stopped is enabled" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable When this bit is set along with the NIE bit the Transmit Interrupt is enabled" "0: Transmit Interrupt is disabled,1: Transmit Interrupt is enabled" line.long 0x10 "DMA_CH1_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. When this register is written with a non-zero value. it enables the watchdog timer for the RI bit of.." hexmask.long.word 0x10 18.--31. 1. "Reserved_31_18,Reserved." newline bitfld.long 0x10 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field" "0,1,2,3" newline hexmask.long.byte 0x10 8.--15. 1. "Reserved_15_8,Reserved." newline hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles multiplied by factor indicated in RWTU field for which the watchdog timer is set" line.long 0x14 "DMA_CH1_Slot_Function_Control_Status,The Slot Function Control and Status register contains the control bits for slot function and the status for Transmit path." hexmask.long.word 0x14 20.--31. 1. "Reserved_31_20,Reserved." newline hexmask.long.byte 0x14 16.--19. 1. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA" newline hexmask.long.word 0x14 4.--15. 1. "SIV,Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets" newline rbitfld.long 0x14 2.--3. "Reserved_3_2,Reserved." "0,1,2,3" newline bitfld.long 0x14 1. "ASC,Advance Slot Check When set this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot.." "0: Advance Slot Check is disabled,1: Advance Slot Check is enabled" newline bitfld.long 0x14 0. "ESC,Enable Slot Comparison When set this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field" "0: Slot Comparison is disabled,1: Slot Comparison is enabled" rgroup.long 0x11C4++0x3 line.long 0x0 "DMA_CH1_Current_App_TxDesc,The Channeli Current Application Transmit Descriptor register points to the current Transmit descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation" rgroup.long 0x11CC++0x3 line.long 0x0 "DMA_CH1_Current_App_RxDesc,The Channeli Current Application Receive Descriptor register points to the current Receive descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation" rgroup.long 0x11D4++0x3 line.long 0x0 "DMA_CH1_Current_App_TxBuffer,The Channeli Current Application Transmit Buffer Address register points to the current Tx buffer address read by the DMA." hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation" rgroup.long 0x11DC++0x3 line.long 0x0 "DMA_CH1_Current_App_RxBuffer,The Channel 0 Current Application Receive Buffer Address register points to the current Rx buffer address read by the DMA." hexmask.long 0x0 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation" group.long 0x11E0++0x3 line.long 0x0 "DMA_CH1_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA. Note: The number of DMA_CH(#i)_Status register in the configuration is the higher of number of Rx.." hexmask.long.word 0x0 22.--31. 1. "Reserved_31_22,Reserved." newline rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer.." "0: Transmit Interrupt,1: Normal Interrupt Summary status detected" newline bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer.." "0: Abnormal Interrupt Summary status not detected,1: Transmit Process Stopped" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates.." "0: Context Descriptor Error status not detected,1: Context Descriptor Error status detected" newline bitfld.long 0x0 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field)" "0: Fatal Bus Error status not detected,1: Fatal Bus Error status detected" newline bitfld.long 0x0 11. "ERI,Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory" "0: Early Receive Interrupt status not detected,1: Early Receive Interrupt status detected" newline bitfld.long 0x0 10. "ETI,Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory" "0: Early Transmit Interrupt status not detected,1: Early Transmit Interrupt status detected" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received" "0: Receive Watchdog Timeout status not detected,1: Receive Watchdog Timeout status detected" newline bitfld.long 0x0 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state" "0: Receive Process Stopped status not detected,1: Receive Process Stopped status detected" newline bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list and the DMA cannot acquire it" "0: Receive Buffer Unavailable status not detected,1: Receive Buffer Unavailable status detected" newline bitfld.long 0x0 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete" "0: Receive Interrupt status not detected,1: Receive Interrupt status detected" newline rbitfld.long 0x0 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list and the DMA cannot acquire it" "0: Transmit Buffer Unavailable status not detected,1: Transmit Buffer Unavailable status detected" newline bitfld.long 0x0 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped" "0: Transmit Process Stopped status not detected,1: Transmit Process Stopped status detected" newline bitfld.long 0x0 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete" "0: Transmit Interrupt status not detected,1: Transmit Interrupt status detected" rgroup.long 0x11E4++0xB line.long 0x0 "DMA_CH1_Miss_Frame_Cnt,This register has the number of packet counter that got dropped by the DMA either due to Bus Error or due to programming RPF field in DMA_CH{i}_Rx_Control register." hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved." newline bitfld.long 0x0 15. "MFCO,Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further" "0: Miss Frame Counter overflow not occurred,1: Miss Frame Counter overflow occurred" newline hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved." newline hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programing RPF field in DMA_CH{i}_Rx_Control register" line.long 0x4 "DMA_CH1_RXP_Accept_Cnt,The DMA_CH(#i)_RXP_Accept_Cnt registers provides the count of the number of frames accepted by Rx Parser." bitfld.long 0x4 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit When set this bit indicates that the RXPAC Counter field crossed the maximum limit" "0: Rx Parser Accept Counter overflow not occurred,1: Rx Parser Accept Counter overflow occurred" newline hexmask.long 0x4 0.--30. 1. "RXPAC,Rx Parser Accept Counter This 31-bit counter is implemented when a Rx Parser Accept a packet due to AF =1" line.long 0x8 "DMA_CH1_RX_ERI_Cnt,The DMA_CH(#i)_RX_ERI_Cnt registers provides the count of the number of times ERI was asserted." hexmask.long.tbyte 0x8 12.--31. 1. "Reserved_31_12,Reserved." newline hexmask.long.word 0x8 0.--11. 1. "ECNT,ERI Counter When ERIC bit of DMA_CH(#i)_RX_Control register is set this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer" group.long 0x1200++0xB line.long 0x0 "DMA_CH2_Control,The DMA Channeli Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode." hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved." newline bitfld.long 0x0 24. "SPH,Split Headers When this bit is set the DMA splits the header and payload in the Receive path" "0: Split Headers feature is disabled,1: Split Headers feature is enabled" newline rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length This bit specifies the Word Dword or Lword number (depending on the 32-bit 64-bit or 128-bit bus) to skip between two unchained descriptors" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1" newline bitfld.long 0x0 16. "PBLx8,8xPBL mode When this bit is set the PBL value programmed in Bits[21:16] in DMA_CH(#i)_Tx_Control and Bits[21:16] in DMA_CH(#i)_Rx_Control is multiplied by eight times" "0: 8xPBL mode is disabled,1: 8xPBL mode is enabled" newline rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3" newline hexmask.long.word 0x0 0.--13. 1. "Reserved_MSS,Reserved." line.long 0x4 "DMA_CH2_Tx_Control,The DMA Channeli Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights." rbitfld.long 0x4 31. "Reserved_31,Reserved." "0,1" newline bitfld.long 0x4 29.--30. "TFSEL,TBS Fetch Select Select bits for one of the four DMA_TBS_CTRL register fields (FTOS FGSN FTOV) for the channel Values: - 2'b00: DMA_TBS_CTRL0 - 2'b01: DMA_TBS_CTRL1 - 2'b10: DMA_TBS_CTRL2 - 2'b11: DMA_TBS_CTRL3 (Reserved if DWC_EQOS_NUM_DMA_TX_CH=3)" "0: DMA_TBS_CTRL0,1: DMA_TBS_CTRL1,2: DMA_TBS_CTRL2,3: DMA_TBS_CTRL3" newline bitfld.long 0x4 28. "EDSE,Enhanced Descriptor Enable When this bit is set the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors" "0: Enhanced Descriptor is disabled,1: Enhanced Descriptor is enabled" newline hexmask.long.byte 0x4 24.--27. 1. "Reserved_TQOS,Reserved." newline rbitfld.long 0x4 23. "Reserved_23,Reserved." "0,1" newline bitfld.long 0x4 22. "ETIC,Early Transmit Interrupt Control When this bit is set Early Transmit Interrupt (ETI) status is set after completion of transfer of data from buffers of a transmit descriptor in which IOC bit (TDES2[31]) is set" "0: Early Transmit Interrupt is disabled,1: Early Transmit Interrupt is enabled" newline hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" newline rbitfld.long 0x4 15. "Reserved_IPBL,Reserved." "0,1" newline rbitfld.long 0x4 13.--14. "Reserved_TSE_MODE,Reserved." "0,1,2,3" newline rbitfld.long 0x4 12. "Reserved_TSE,Reserved." "0,1" newline hexmask.long.byte 0x4 5.--11. 1. "Reserved_11_5,Reserved." newline bitfld.long 0x4 4. "OSF,Operate on Second Packet When this bit is set it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained" "0: Operate on Second Packet disabled,1: Operate on Second Packet enabled" newline bitfld.long 0x4 1.--3. "TCW,Transmit Channel Weight This field indicates the weight assigned to the corresponding Transmit channel" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "ST,Start or Stop Transmission Command When this bit is set transmission is placed in the Running state" "0: Stop Transmission Command,1: Start Transmission Command" line.long 0x8 "DMA_CH2_Rx_Control,The DMA Channeli Receive Control register controls the Rx features such as PBL. buffer size. and extended status." bitfld.long 0x8 31. "RPF,Rx Packet Flush" "0: Rx Packet Flush is disabled,1: Rx Packet Flush is enabled" newline rbitfld.long 0x8 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 24.--27. 1. "Reserved_RQOS,Reserved." newline rbitfld.long 0x8 23. "Reserved_23,Reserved." "0,1" newline bitfld.long 0x8 22. "ERIC,Early Receive Interrupt Control When this bit is set Early Receive Interrupt (ERI) status is set after the completion of every burst transfer of data from the Rx DMA to the buffer" "0: Early Receive Interrupt is disabled,1: Early Receive Interrupt is enabled" newline hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" newline rbitfld.long 0x8 15. "Reserved_15,Reserved." "0,1" newline hexmask.long.word 0x8 4.--14. 1. "RBSZ_13_y,Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0" newline rbitfld.long 0x8 1.--3. "RBSZ_x_0,Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "SR,Start or Stop Receive When this bit is set the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets" "0: Stop Receive,1: Start Receive" group.long 0x1214++0x3 line.long 0x0 "DMA_CH2_TxDesc_List_Address,The Channeli Tx Descriptor List Address register points the DMA to the start of Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Word. Dword. or Lword-aligned.." hexmask.long 0x0 3.--31. 1. "TDESLA,Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list" newline rbitfld.long 0x0 0.--2. "Reserved_LSb,Reserved." "0,1,2,3,4,5,6,7" group.long 0x121C++0x7 line.long 0x0 "DMA_CH2_RxDesc_List_Address,The Channeli Rx Descriptor List Address register points the DMA to the start of Receive descriptor list. This register points to the start of the Receive Descriptor List. The descriptor lists reside in the physical memory.." hexmask.long 0x0 3.--31. 1. "RDESLA,Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list" newline rbitfld.long 0x0 0.--2. "Reserved_LSb,Reserved." "0,1,2,3,4,5,6,7" line.long 0x4 "DMA_CH2_TxDesc_Tail_Pointer,The Channeli Tx Descriptor Tail Pointer register points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x4 3.--31. 1. "TDTP,Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring" newline rbitfld.long 0x4 0.--2. "Reserved_LSb,Reserved." "0,1,2,3,4,5,6,7" group.long 0x1228++0x17 line.long 0x0 "DMA_CH2_RxDesc_Tail_Pointer,The Channeli Rx Descriptor Tail Pointer Points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x0 3.--31. 1. "RDTP,Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring" newline rbitfld.long 0x0 0.--2. "Reserved_LSb,Reserved." "0,1,2,3,4,5,6,7" line.long 0x4 "DMA_CH2_TxDesc_Ring_Length,The Tx Descriptor Ring Length register contains the length of the Transmit descriptor ring." hexmask.long.tbyte 0x4 10.--31. 1. "Reserved_31_10,Reserved." newline hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring Length" line.long 0x8 "DMA_CH2_Rx_Control2,The Channeli Receive Control register controls the Rx features such as Rx Descriptor Ring Length and Alternate Rx Buffer Size." hexmask.long.byte 0x8 24.--31. 1. "Reserved_31_24,Reserved." newline hexmask.long.byte 0x8 17.--23. 1. "ARBS,Alternate Receive Buffer Size Indicates size in bytes for Buffer 1 when ARBS is programmed to a non-zero value (when split header feature is not enabled)" newline hexmask.long.byte 0x8 10.--16. 1. "Reserved_x_10,Reserved." newline hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring" line.long 0xC "DMA_CH2_Interrupt_Enable,The Channeli Interrupt Enable register enables the interrupts reported by the Status register." hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved." newline bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable When this bit is set the normal interrupt summary is enabled" "0: Normal Interrupt Summary is disabled,1: Normal Interrupt Summary is enabled" newline bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable When this bit is set the abnormal interrupt summary is enabled" "0: Abnormal Interrupt Summary is disabled,1: Abnormal Interrupt Summary is enabled" newline bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable When this bit is set along with the AIE bit the Descriptor error interrupt is enabled" "0: Context Descriptor Error is disabled,1: Context Descriptor Error is enabled" newline bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable When this bit is set along with the AIE bit the Fatal Bus error interrupt is enabled" "0: Fatal Bus Error is disabled,1: Fatal Bus Error is enabled" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt Enable When this bit is set along with the NIE bit the Early Receive interrupt is enabled" "0: Early Receive Interrupt is disabled,1: Early Receive Interrupt is enabled" newline bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt Enable When this bit is set along with the AIE bit the Early Transmit interrupt is enabled" "0: Early Transmit Interrupt is disabled,1: Early Transmit Interrupt is enabled" newline bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout Enable When this bit is set along with the AIE bit the Receive Watchdog Timeout interrupt is enabled" "0: Receive Watchdog Timeout is disabled,1: Receive Watchdog Timeout is enabled" newline bitfld.long 0xC 8. "RSE,Receive Stopped Enable When this bit is set along with the AIE bit the Receive Stopped Interrupt is enabled" "0: Receive Stopped is disabled,1: Receive Stopped is enabled" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable When this bit is set along with the AIE bit the Receive Buffer Unavailable interrupt is enabled" "0: Receive Buffer Unavailable is disabled,1: Receive Buffer Unavailable is enabled" newline bitfld.long 0xC 6. "RIE,Receive Interrupt Enable When this bit is set along with the NIE bit the Receive Interrupt is enabled" "0: Receive Interrupt is disabled,1: Receive Interrupt is enabled" newline rbitfld.long 0xC 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit the Transmit Buffer Unavailable interrupt is enabled" "0: Transmit Buffer Unavailable is disabled,1: Transmit Buffer Unavailable is enabled" newline bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable When this bit is set along with the AIE bit the Transmission Stopped interrupt is enabled" "0: Transmit Stopped is disabled,1: Transmit Stopped is enabled" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable When this bit is set along with the NIE bit the Transmit Interrupt is enabled" "0: Transmit Interrupt is disabled,1: Transmit Interrupt is enabled" line.long 0x10 "DMA_CH2_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. When this register is written with a non-zero value. it enables the watchdog timer for the RI bit of.." hexmask.long.word 0x10 18.--31. 1. "Reserved_31_18,Reserved." newline bitfld.long 0x10 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field" "0,1,2,3" newline hexmask.long.byte 0x10 8.--15. 1. "Reserved_15_8,Reserved." newline hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles multiplied by factor indicated in RWTU field for which the watchdog timer is set" line.long 0x14 "DMA_CH2_Slot_Function_Control_Status,The Slot Function Control and Status register contains the control bits for slot function and the status for Transmit path." hexmask.long.word 0x14 20.--31. 1. "Reserved_31_20,Reserved." newline hexmask.long.byte 0x14 16.--19. 1. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA" newline hexmask.long.word 0x14 4.--15. 1. "SIV,Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets" newline rbitfld.long 0x14 2.--3. "Reserved_3_2,Reserved." "0,1,2,3" newline bitfld.long 0x14 1. "ASC,Advance Slot Check When set this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot.." "0: Advance Slot Check is disabled,1: Advance Slot Check is enabled" newline bitfld.long 0x14 0. "ESC,Enable Slot Comparison When set this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field" "0: Slot Comparison is disabled,1: Slot Comparison is enabled" rgroup.long 0x1244++0x3 line.long 0x0 "DMA_CH2_Current_App_TxDesc,The Channeli Current Application Transmit Descriptor register points to the current Transmit descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation" rgroup.long 0x124C++0x3 line.long 0x0 "DMA_CH2_Current_App_RxDesc,The Channeli Current Application Receive Descriptor register points to the current Receive descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation" rgroup.long 0x1254++0x3 line.long 0x0 "DMA_CH2_Current_App_TxBuffer,The Channeli Current Application Transmit Buffer Address register points to the current Tx buffer address read by the DMA." hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation" rgroup.long 0x125C++0x3 line.long 0x0 "DMA_CH2_Current_App_RxBuffer,The Channel 0 Current Application Receive Buffer Address register points to the current Rx buffer address read by the DMA." hexmask.long 0x0 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation" group.long 0x1260++0x3 line.long 0x0 "DMA_CH2_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA. Note: The number of DMA_CH(#i)_Status register in the configuration is the higher of number of Rx.." hexmask.long.word 0x0 22.--31. 1. "Reserved_31_22,Reserved." newline rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer.." "0: Transmit Interrupt,1: Normal Interrupt Summary status detected" newline bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer.." "0: Abnormal Interrupt Summary status not detected,1: Transmit Process Stopped" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates.." "0: Context Descriptor Error status not detected,1: Context Descriptor Error status detected" newline bitfld.long 0x0 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field)" "0: Fatal Bus Error status not detected,1: Fatal Bus Error status detected" newline bitfld.long 0x0 11. "ERI,Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory" "0: Early Receive Interrupt status not detected,1: Early Receive Interrupt status detected" newline bitfld.long 0x0 10. "ETI,Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory" "0: Early Transmit Interrupt status not detected,1: Early Transmit Interrupt status detected" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received" "0: Receive Watchdog Timeout status not detected,1: Receive Watchdog Timeout status detected" newline bitfld.long 0x0 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state" "0: Receive Process Stopped status not detected,1: Receive Process Stopped status detected" newline bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list and the DMA cannot acquire it" "0: Receive Buffer Unavailable status not detected,1: Receive Buffer Unavailable status detected" newline bitfld.long 0x0 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete" "0: Receive Interrupt status not detected,1: Receive Interrupt status detected" newline rbitfld.long 0x0 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list and the DMA cannot acquire it" "0: Transmit Buffer Unavailable status not detected,1: Transmit Buffer Unavailable status detected" newline bitfld.long 0x0 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped" "0: Transmit Process Stopped status not detected,1: Transmit Process Stopped status detected" newline bitfld.long 0x0 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete" "0: Transmit Interrupt status not detected,1: Transmit Interrupt status detected" rgroup.long 0x1264++0xB line.long 0x0 "DMA_CH2_Miss_Frame_Cnt,This register has the number of packet counter that got dropped by the DMA either due to Bus Error or due to programming RPF field in DMA_CH{i}_Rx_Control register." hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved." newline bitfld.long 0x0 15. "MFCO,Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further" "0: Miss Frame Counter overflow not occurred,1: Miss Frame Counter overflow occurred" newline hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved." newline hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programing RPF field in DMA_CH{i}_Rx_Control register" line.long 0x4 "DMA_CH2_RXP_Accept_Cnt,The DMA_CH(#i)_RXP_Accept_Cnt registers provides the count of the number of frames accepted by Rx Parser." bitfld.long 0x4 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit When set this bit indicates that the RXPAC Counter field crossed the maximum limit" "0: Rx Parser Accept Counter overflow not occurred,1: Rx Parser Accept Counter overflow occurred" newline hexmask.long 0x4 0.--30. 1. "RXPAC,Rx Parser Accept Counter This 31-bit counter is implemented when a Rx Parser Accept a packet due to AF =1" line.long 0x8 "DMA_CH2_RX_ERI_Cnt,The DMA_CH(#i)_RX_ERI_Cnt registers provides the count of the number of times ERI was asserted." hexmask.long.tbyte 0x8 12.--31. 1. "Reserved_31_12,Reserved." newline hexmask.long.word 0x8 0.--11. 1. "ECNT,ERI Counter When ERIC bit of DMA_CH(#i)_RX_Control register is set this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer" tree.end tree.end tree "INTM (Interrupt Monitor)" base ad:0x4027C000 group.long 0x0++0x3 line.long 0x0 "INTM_MM,Monitor Mode" bitfld.long 0x0 0. "MM,Monitor Mode" "0: Disable,1: Enable" wgroup.long 0x4++0x3 line.long 0x0 "INTM_IACK,Interrupt Acknowledge" hexmask.long.word 0x0 0.--9. 1. "IRQ,Interrupt Request" repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x4027C008 ad:0x4027C018 ad:0x4027C028 ad:0x4027C038) tree "mon[$1]" base $2 group.long ($2)++0xB line.long 0x0 "INTM_IRQSEL,Interrupt Request Select for Monitor mon_index" hexmask.long.word 0x0 0.--9. 1. "IRQ,Interrupt Request" line.long 0x4 "INTM_LATENCY,Interrupt Latency for Monitor mon_index" hexmask.long.tbyte 0x4 0.--23. 1. "LAT,Latency" line.long 0x8 "INTM_TIMER,Timer for Monitor mon_index" hexmask.long.tbyte 0x8 0.--23. 1. "TIMER,Timer" rgroup.long ($2+0xC)++0x3 line.long 0x0 "INTM_STATUS,Status for Monitor mon_index" bitfld.long 0x0 0. "STATUS,Monitor status" "0: Did not exceed,1: Exceeded" tree.end repeat.end tree.end tree "JDC (JTAG Data Communication)" base ad:0x40394000 group.long 0x0++0xB line.long 0x0 "MCR,Module Configuration Register" bitfld.long 0x0 16. "JIN_IEN,JIN Interrupt Enable" "0: Setting MSR[JIN_INT] bit does not assert the JIN..,1: Setting MSR[JIN_INT] bit asserts the JIN interrupt" bitfld.long 0x0 0. "JOUT_IEN,JOUT Interrupt Enable" "0: Setting MSR[JOUT_INT] bit does not assert the..,1: Setting MSR[JOUT_INT] bit asserts the JOUT.." line.long 0x4 "MSR,Module Status Register" rbitfld.long 0x4 18. "JIN_RDY,JIN Ready (read only)" "0: Cleared upon software read of JIN_IPS contents..,1: Set when new data is written to the JIN_IPS.." eventfld.long 0x4 16. "JIN_INT,JIN Interrupt" "0: Cleared by writing logic 1,1: Set when new data is written to the JIN_IPS.." newline rbitfld.long 0x4 2. "JOUT_RDY,JOUT Ready (read only)" "0: Cleared upon tool read of JOUT register via JTAG..,1: Set when new data is written to the JOUT_IPS.." eventfld.long 0x4 0. "JOUT_INT,JOUT Interrupt" "0: Cleared by writing logic 1,1: Set when JOUT_RDY bit is cleared by tool reading.." line.long 0x8 "JOUT_IPS,JTAG Output Data Register" hexmask.long 0x8 0.--31. 1. "Data,JOUT_IPS Data" rgroup.long 0xC++0x3 line.long 0x0 "JIN_IPS,JTAG Input Data Register" hexmask.long 0x0 0.--31. 1. "Data,JIN_IPS data" tree.end tree "LCU (Logic Control Unit)" base ad:0x0 tree "LCU_0" base ad:0x40098000 repeat 3. (list 0x0 0x1 0x2)(list ad:0x40098000 ad:0x40098040 ad:0x40098080) tree "LC[$1]" base $2 repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "LC_LUTCTRL$1,LC n Output m LUT Control" hexmask.long.word 0x0 0.--15. 1. "LUTCTRL,LUT Control" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "LC_FILT$1,LC n Output m Filter" hexmask.long.word 0x0 16.--31. 1. "LUT_RISE_FILT,Rise Filter" hexmask.long.word 0x0 0.--15. 1. "LUT_FALL_FILT,Fall Filter" repeat.end group.long ($2+0x20)++0x17 line.long 0x0 "LC_INTDMAEN,LC n Interrupt and DMA Enable" hexmask.long.byte 0x0 24.--27. 1. "FORCE_DMA_EN,Force DMA Enable" hexmask.long.byte 0x0 16.--19. 1. "FORCE_INT_EN,Force Interrupt Enable" newline hexmask.long.byte 0x0 8.--11. 1. "LUT_DMA_EN,LUT DMA Enable" hexmask.long.byte 0x0 0.--3. 1. "LUT_INT_EN,LUT Interrupt Enable" line.long 0x4 "LC_STS,LC n Status" hexmask.long.byte 0x4 8.--11. 1. "FORCESTS,Force Event" hexmask.long.byte 0x4 0.--3. 1. "LUT_STS,LUT Event" line.long 0x8 "LC_OUTPOL,LC n Output Polarity Control" hexmask.long.byte 0x8 0.--3. 1. "OUTPOL,Output Polarity" line.long 0xC "LC_FFILT,LC n Force Filter" hexmask.long.byte 0xC 28.--31. 1. "COMB_FORCE,Combined Sensed Force Input" bitfld.long 0xC 24.--26. "COMB_EN,Combinational Force Path (CFP) Enable" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 16.--18. "FORCE_POL,Force Input Polarity" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 0.--7. 1. "FORCE_FILT,Force Filter" line.long 0x10 "LC_FCTRL,LC n Force Control" bitfld.long 0x10 30.--31. "SYNC_SEL3,Sync Select" "0: Sync input 0,1: Sync input 1,?,?" bitfld.long 0x10 28.--29. "FORCE_MODE3,Force Clearing Mode" "0: Deassertion,1: Rising sync after deassertion,2: Writing 1 after deassertion,3: Rising sync after writing 1 and deassertion" newline hexmask.long.byte 0x10 24.--27. 1. "FORCE_SENSE3,Force Input Sensitivity" bitfld.long 0x10 22.--23. "SYNC_SEL2,Sync Select" "0: Sync input 0,1: Sync input 1,?,?" newline bitfld.long 0x10 20.--21. "FORCE_MODE2,Force Clearing Mode" "0: Deassertion,1: Rising sync after deassertion,2: Writing 1 after deassertion,3: Rising sync after writing 1 and deassertion" hexmask.long.byte 0x10 16.--19. 1. "FORCE_SENSE2,Force Input Sensitivity" newline bitfld.long 0x10 14.--15. "SYNC_SEL1,Sync Select" "0: Sync input 0,1: Sync input 1,?,?" bitfld.long 0x10 12.--13. "FORCE_MODE1,Force Clearing Mode" "0: Deassertion,1: Rising sync after deassertion,2: Writing 1 after deassertion,3: Rising sync after writing 1 and deassertion" newline hexmask.long.byte 0x10 8.--11. 1. "FORCE_SENSE1,Force Input Sensitivity" bitfld.long 0x10 6.--7. "SYNC_SEL0,Sync Select" "0: Sync input 0,1: Sync input 1,?,?" newline bitfld.long 0x10 4.--5. "FORCE_MODE0,Force Clearing Mode" "0: Deassertion,1: Rising sync after deassertion,2: Writing 1 after deassertion,3: Rising sync after writing 1 and deassertion" hexmask.long.byte 0x10 0.--3. 1. "FORCE_SENSE0,Force Input Sensitivity" line.long 0x14 "LC_SCTRL,LC n Sync Control" bitfld.long 0x14 8. "SW_SYNC_SEL,Software Sync Select" "0: Sync input 0,1: Sync input 1" hexmask.long.byte 0x14 0.--3. 1. "SW_MODE,Software Sync Mode" tree.end repeat.end base ad:0x40098000 repeat 12. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x200)++0x3 line.long 0x0 "MUXSEL[$1],Mux Select" hexmask.long.byte 0x0 0.--7. 1. "MUXSEL,Mux Select" repeat.end group.long 0x280++0xF line.long 0x0 "CFG,Configuration" hexmask.long.byte 0x0 24.--31. 1. "NUM_LOGIC_CELLS,LCs" hexmask.long.byte 0x0 16.--23. 1. "NUM_FORCES,Force Inputs" hexmask.long.byte 0x0 8.--15. 1. "NUM_SYNCS,Sync Inputs" rbitfld.long 0x0 7. "INCL_MUXES,Input Muxing" "0: Not supported,1: Supported" newline bitfld.long 0x0 0. "WP,Write Protect" "0: No effect,1: Turn on write protection" line.long 0x4 "SWEN,Software Override Enable" hexmask.long.word 0x4 0.--11. 1. "SWEN,Software Override Enable" line.long 0x8 "SWVALUE,Software Override Value" hexmask.long.word 0x8 0.--11. 1. "SWVALUE,Software Override Value" line.long 0xC "OUTEN,Output Enable" hexmask.long.word 0xC 0.--11. 1. "OUTEN,Output Enables" rgroup.long 0x290++0xF line.long 0x0 "LCIN,Logic Inputs" hexmask.long.word 0x0 0.--11. 1. "LC_INPUTS,Logic Inputs" line.long 0x4 "SWOUT,Overridden Inputs" hexmask.long.word 0x4 0.--11. 1. "SWOUT,Overridden Inputs" line.long 0x8 "LCOUT,Logic Outputs" hexmask.long.word 0x8 0.--11. 1. "LCOUT,Logic Outputs" line.long 0xC "FORCEOUT,Forced Outputs" hexmask.long.word 0xC 0.--11. 1. "FORCEOUT,Forced Outputs" group.long 0x2A0++0x3 line.long 0x0 "FORCESTS,Force Status" hexmask.long.word 0x0 0.--11. 1. "FORCESTS,Force Status" group.long 0x2A8++0x3 line.long 0x0 "DBGEN,Debug Mode Enable" hexmask.long.word 0x0 0.--11. 1. "DBGEN,Debug Mode Enable" tree.end tree "LCU_1" base ad:0x4009C000 repeat 3. (list 0x0 0x1 0x2)(list ad:0x4009C000 ad:0x4009C040 ad:0x4009C080) tree "LC[$1]" base $2 repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "LC_LUTCTRL$1,LC n Output m LUT Control" hexmask.long.word 0x0 0.--15. 1. "LUTCTRL,LUT Control" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "LC_FILT$1,LC n Output m Filter" hexmask.long.word 0x0 16.--31. 1. "LUT_RISE_FILT,Rise Filter" hexmask.long.word 0x0 0.--15. 1. "LUT_FALL_FILT,Fall Filter" repeat.end group.long ($2+0x20)++0x17 line.long 0x0 "LC_INTDMAEN,LC n Interrupt and DMA Enable" hexmask.long.byte 0x0 24.--27. 1. "FORCE_DMA_EN,Force DMA Enable" hexmask.long.byte 0x0 16.--19. 1. "FORCE_INT_EN,Force Interrupt Enable" newline hexmask.long.byte 0x0 8.--11. 1. "LUT_DMA_EN,LUT DMA Enable" hexmask.long.byte 0x0 0.--3. 1. "LUT_INT_EN,LUT Interrupt Enable" line.long 0x4 "LC_STS,LC n Status" hexmask.long.byte 0x4 8.--11. 1. "FORCESTS,Force Event" hexmask.long.byte 0x4 0.--3. 1. "LUT_STS,LUT Event" line.long 0x8 "LC_OUTPOL,LC n Output Polarity Control" hexmask.long.byte 0x8 0.--3. 1. "OUTPOL,Output Polarity" line.long 0xC "LC_FFILT,LC n Force Filter" hexmask.long.byte 0xC 28.--31. 1. "COMB_FORCE,Combined Sensed Force Input" bitfld.long 0xC 24.--26. "COMB_EN,Combinational Force Path (CFP) Enable" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 16.--18. "FORCE_POL,Force Input Polarity" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 0.--7. 1. "FORCE_FILT,Force Filter" line.long 0x10 "LC_FCTRL,LC n Force Control" bitfld.long 0x10 30.--31. "SYNC_SEL3,Sync Select" "0: Sync input 0,1: Sync input 1,?,?" bitfld.long 0x10 28.--29. "FORCE_MODE3,Force Clearing Mode" "0: Deassertion,1: Rising sync after deassertion,2: Writing 1 after deassertion,3: Rising sync after writing 1 and deassertion" newline hexmask.long.byte 0x10 24.--27. 1. "FORCE_SENSE3,Force Input Sensitivity" bitfld.long 0x10 22.--23. "SYNC_SEL2,Sync Select" "0: Sync input 0,1: Sync input 1,?,?" newline bitfld.long 0x10 20.--21. "FORCE_MODE2,Force Clearing Mode" "0: Deassertion,1: Rising sync after deassertion,2: Writing 1 after deassertion,3: Rising sync after writing 1 and deassertion" hexmask.long.byte 0x10 16.--19. 1. "FORCE_SENSE2,Force Input Sensitivity" newline bitfld.long 0x10 14.--15. "SYNC_SEL1,Sync Select" "0: Sync input 0,1: Sync input 1,?,?" bitfld.long 0x10 12.--13. "FORCE_MODE1,Force Clearing Mode" "0: Deassertion,1: Rising sync after deassertion,2: Writing 1 after deassertion,3: Rising sync after writing 1 and deassertion" newline hexmask.long.byte 0x10 8.--11. 1. "FORCE_SENSE1,Force Input Sensitivity" bitfld.long 0x10 6.--7. "SYNC_SEL0,Sync Select" "0: Sync input 0,1: Sync input 1,?,?" newline bitfld.long 0x10 4.--5. "FORCE_MODE0,Force Clearing Mode" "0: Deassertion,1: Rising sync after deassertion,2: Writing 1 after deassertion,3: Rising sync after writing 1 and deassertion" hexmask.long.byte 0x10 0.--3. 1. "FORCE_SENSE0,Force Input Sensitivity" line.long 0x14 "LC_SCTRL,LC n Sync Control" bitfld.long 0x14 8. "SW_SYNC_SEL,Software Sync Select" "0: Sync input 0,1: Sync input 1" hexmask.long.byte 0x14 0.--3. 1. "SW_MODE,Software Sync Mode" tree.end repeat.end base ad:0x4009C000 repeat 12. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x200)++0x3 line.long 0x0 "MUXSEL[$1],Mux Select" hexmask.long.byte 0x0 0.--7. 1. "MUXSEL,Mux Select" repeat.end group.long 0x280++0xF line.long 0x0 "CFG,Configuration" hexmask.long.byte 0x0 24.--31. 1. "NUM_LOGIC_CELLS,LCs" hexmask.long.byte 0x0 16.--23. 1. "NUM_FORCES,Force Inputs" hexmask.long.byte 0x0 8.--15. 1. "NUM_SYNCS,Sync Inputs" rbitfld.long 0x0 7. "INCL_MUXES,Input Muxing" "0: Not supported,1: Supported" newline bitfld.long 0x0 0. "WP,Write Protect" "0: No effect,1: Turn on write protection" line.long 0x4 "SWEN,Software Override Enable" hexmask.long.word 0x4 0.--11. 1. "SWEN,Software Override Enable" line.long 0x8 "SWVALUE,Software Override Value" hexmask.long.word 0x8 0.--11. 1. "SWVALUE,Software Override Value" line.long 0xC "OUTEN,Output Enable" hexmask.long.word 0xC 0.--11. 1. "OUTEN,Output Enables" rgroup.long 0x290++0xF line.long 0x0 "LCIN,Logic Inputs" hexmask.long.word 0x0 0.--11. 1. "LC_INPUTS,Logic Inputs" line.long 0x4 "SWOUT,Overridden Inputs" hexmask.long.word 0x4 0.--11. 1. "SWOUT,Overridden Inputs" line.long 0x8 "LCOUT,Logic Outputs" hexmask.long.word 0x8 0.--11. 1. "LCOUT,Logic Outputs" line.long 0xC "FORCEOUT,Forced Outputs" hexmask.long.word 0xC 0.--11. 1. "FORCEOUT,Forced Outputs" group.long 0x2A0++0x3 line.long 0x0 "FORCESTS,Force Status" hexmask.long.word 0x0 0.--11. 1. "FORCESTS,Force Status" group.long 0x2A8++0x3 line.long 0x0 "DBGEN,Debug Mode Enable" hexmask.long.word 0x0 0.--11. 1. "DBGEN,Debug Mode Enable" tree.end tree.end tree "LPCMP (Low Power Comparator)" base ad:0x0 tree "LPCMP_0" base ad:0x40370000 rgroup.long 0x0++0x7 line.long 0x0 "VERID,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Specification Number" line.long 0x4 "PARAM,Parameter" hexmask.long.byte 0x4 0.--3. 1. "DAC_RES,DAC Resolution" group.long 0x8++0xB line.long 0x0 "CCR0,Comparator Control Register 0" bitfld.long 0x0 2. "LINKEN,CMP-to-DAC Link Enable" "0: Disable the CMP-to-DAC link: enabling or..,1: Enable the CMP-to-DAC link: the DAC.." bitfld.long 0x0 1. "CMP_STOP_EN,Comparator STOP Mode Enable" "0: Disable the analog comparator regardless of..,1: Allows CMP_EN to enable the analog comparator." newline bitfld.long 0x0 0. "CMP_EN,Comparator Enable" "0: Disables (The analog logic remains off and..,1: Enables" line.long 0x4 "CCR1,Comparator Control Register 1" hexmask.long.byte 0x4 24.--31. 1. "FILT_PER,Filter Sample Period" bitfld.long 0x4 16.--18. "FILT_CNT,Filter Sample Count" "0: Filter is bypassed: COUT = COUTA,1: 1 consecutive sample (Comparator output is..,2: 2 consecutive samples,3: 3 consecutive samples,4: 4 consecutive samples,5: 5 consecutive samples,6: 6 consecutive samples,7: 7 consecutive samples" newline bitfld.long 0x4 10.--11. "EVT_SEL,CMPO Event Select" "0: Both edges,1: Falling edge,2: Both edges,3: Both edges" bitfld.long 0x4 9. "WINDOW_CLS,CMPO Event Window Close" "0: CMPO event cannot close the window,1: CMPO event can close the window" newline bitfld.long 0x4 8. "WINDOW_INV,WINDOW/SAMPLE Signal Invert" "0: Do not invert,1: Invert" bitfld.long 0x4 7. "COUTA_OW,COUTA Output Level for Closed Window" "0: COUTA is 0,1: COUTA is 1" newline bitfld.long 0x4 6. "COUTA_OWEN,COUTA_OW Enable" "0: COUTA holds the last sampled value.,1: Enables the COUTA signal value to be defined by.." bitfld.long 0x4 5. "COUT_PEN,Comparator Output Pin Enable" "0: Not available,1: Available" newline bitfld.long 0x4 4. "COUT_SEL,Comparator Output Select" "0: Use COUT (filtered),1: Use COUTA (unfiltered)" bitfld.long 0x4 3. "COUT_INV,Comparator Invert" "0: Do not invert,1: Invert" newline bitfld.long 0x4 2. "DMA_EN,DMA Enable" "0: Disables,1: Enables" bitfld.long 0x4 1. "SAMPLE_EN,Sampling Enable" "0: Disables,1: Enables" newline bitfld.long 0x4 0. "WINDOW_EN,Windowing Enable" "0: Disables,1: Enables" line.long 0x8 "CCR2,Comparator Control Register 2" bitfld.long 0x8 28.--29. "INMSEL,Input Minus Select" "0: IN0: from the 8-bit DAC output,1: IN1: from the analog 8-1 mux,?,?" bitfld.long 0x8 24.--25. "INPSEL,Input Plus Select" "0: IN0: from the 8-bit DAC output,1: IN1: from the analog 8-1 mux,?,?" newline bitfld.long 0x8 20.--22. "MSEL,Minus Input MUX Select" "0: Input channel 0,1: Input channel 1,2: Input channel 2,3: Input channel 3,4: Input channel 4,5: Input channel 5,6: Input channel 6,7: Input channel 7" bitfld.long 0x8 16.--18. "PSEL,Plus Input MUX Select" "0: Input channel 0,1: Input channel 1,2: Input channel 2,3: Input channel 3,4: Input channel 4,5: Input channel 5,6: Input channel 6,7: Input channel 7" newline bitfld.long 0x8 4.--5. "HYSTCTR,Comparator Hysteresis Control" "0: Level 0,1: Level 1,2: Level 2,3: Level 3" bitfld.long 0x8 2. "OFFSET,Comparator Offset Control" "0: Level 0: The hysteresis selected by HYSTCTR is..,1: Level 1: Hysteresis does not apply when INP.." newline bitfld.long 0x8 0. "CMP_HPMD,CMP High Power Mode Select" "0: Low power (speed) comparison mode,1: High power (speed) comparison mode" group.long 0x18++0x1B line.long 0x0 "DCR,DAC Control" hexmask.long.byte 0x0 16.--23. 1. "DAC_DATA,DAC Output Voltage Select" bitfld.long 0x0 8. "VRSEL,DAC Reference High Voltage Source Select" "0: vrefh0,1: vrefh1" newline bitfld.long 0x0 0. "DAC_EN,DAC Enable" "0: Disables,1: Enables" line.long 0x4 "IER,Interrupt Enable" bitfld.long 0x4 2. "RRF_IE,Round-Robin Flag Interrupt Enable" "0: Disables the round-robin flag interrupt.,1: Enables the round-robin flag interrupt when the.." bitfld.long 0x4 1. "CFF_IE,Comparator Flag Falling Interrupt Enable" "0: Disables the comparator flag falling interrupt.,1: Enables the comparator flag falling interrupt.." newline bitfld.long 0x4 0. "CFR_IE,Comparator Flag Rising Interrupt Enable" "0: Disables the comparator flag rising interrupt.,1: Enables the comparator flag rising interrupt.." line.long 0x8 "CSR,Comparator Status" rbitfld.long 0x8 8. "COUT,Analog Comparator Output" "0,1" eventfld.long 0x8 2. "RRF,Round-Robin Flag" "0: Not detected,1: Detected" newline eventfld.long 0x8 1. "CFF,Analog Comparator Flag Falling" "0: Not detected,1: Detected" eventfld.long 0x8 0. "CFR,Analog Comparator Flag Rising" "0: Not detected,1: Detected" line.long 0xC "RRCR0,Round Robin Control Register 0" hexmask.long.byte 0xC 16.--21. 1. "RR_INITMOD,Initialization Delay Modulus" bitfld.long 0xC 8.--9. "RR_NSAM,Number of Sample Clocks" "0: 0 clock,1: 1 clock,2: 2 clocks,3: 3 clocks" newline bitfld.long 0xC 0. "RR_EN,Round-Robin Enable" "0: Disables,1: Enables" line.long 0x10 "RRCR1,Round Robin Control Register 1" bitfld.long 0x10 20.--22. "FIXCH,Fixed Channel Select" "0: Channel 0,1: Channel 1,2: Channel 2,3: Channel 3,4: Channel 4,5: Channel 5,6: Channel 6,7: Channel 7" bitfld.long 0x10 16. "FIXP,Fixed Port" "0: Fix the plus port. Sweep only the inputs to the..,1: Fix the minus port. Sweep only the inputs to the.." newline bitfld.long 0x10 7. "RR_CH7EN,Channel 7 Input Enable in Trigger Mode" "0: Disables,1: Enables" bitfld.long 0x10 6. "RR_CH6EN,Channel 6 Input Enable in Trigger Mode" "0: Disables,1: Enables" newline bitfld.long 0x10 5. "RR_CH5EN,Channel 5 Input Enable in Trigger Mode" "0: Disables,1: Enables" bitfld.long 0x10 4. "RR_CH4EN,Channel 4 Input Enable in Trigger Mode" "0: Disables,1: Enables" newline bitfld.long 0x10 3. "RR_CH3EN,Channel 3 Input Enable in Trigger Mode" "0: Disables,1: Enables" bitfld.long 0x10 2. "RR_CH2EN,Channel 2 Input Enable in Trigger Mode" "0: Disables,1: Enables" newline bitfld.long 0x10 1. "RR_CH1EN,Channel 1 Input Enable in Trigger Mode" "0: Disables,1: Enables" bitfld.long 0x10 0. "RR_CH0EN,Channel 0 Input Enable in Trigger Mode" "0: Disables,1: Enables" line.long 0x14 "RRCSR,Round Robin Control and Status" bitfld.long 0x14 7. "RR_CH7OUT,Comparison Result for Channel 7" "0,1" bitfld.long 0x14 6. "RR_CH6OUT,Comparison Result for Channel 6" "0,1" newline bitfld.long 0x14 5. "RR_CH5OUT,Comparison Result for Channel 5" "0,1" bitfld.long 0x14 4. "RR_CH4OUT,Comparison Result for Channel 4" "0,1" newline bitfld.long 0x14 3. "RR_CH3OUT,Comparison Result for Channel 3" "0,1" bitfld.long 0x14 2. "RR_CH2OUT,Comparison Result for Channel 2" "0,1" newline bitfld.long 0x14 1. "RR_CH1OUT,Comparison Result for Channel 1" "0,1" bitfld.long 0x14 0. "RR_CH0OUT,Comparison Result for Channel 0" "0,1" line.long 0x18 "RRSR,Round Robin Status" eventfld.long 0x18 7. "RR_CH7F,Channel 7 Input Changed Flag" "0: Not different,1: Different" eventfld.long 0x18 6. "RR_CH6F,Channel 6 Input Changed Flag" "0: Not different,1: Different" newline eventfld.long 0x18 5. "RR_CH5F,Channel 5 Input Changed Flag" "0: Not different,1: Different" eventfld.long 0x18 4. "RR_CH4F,Channel 4 Input Changed Flag" "0: Not different,1: Different" newline eventfld.long 0x18 3. "RR_CH3F,Channel 3 Input Changed Flag" "0: Not different,1: Different" eventfld.long 0x18 2. "RR_CH2F,Channel 2 Input Changed Flag" "0: Not different,1: Different" newline eventfld.long 0x18 1. "RR_CH1F,Channel 1 Input Changed Flag" "0: Not different,1: Different" eventfld.long 0x18 0. "RR_CH0F,Channel 0 Input Changed Flag" "0: Not different,1: Different" tree.end tree "LPCMP_1" base ad:0x40374000 rgroup.long 0x0++0x7 line.long 0x0 "VERID,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Specification Number" line.long 0x4 "PARAM,Parameter" hexmask.long.byte 0x4 0.--3. 1. "DAC_RES,DAC Resolution" group.long 0x8++0xB line.long 0x0 "CCR0,Comparator Control Register 0" bitfld.long 0x0 2. "LINKEN,CMP-to-DAC Link Enable" "0: Disable the CMP-to-DAC link: enabling or..,1: Enable the CMP-to-DAC link: the DAC.." bitfld.long 0x0 1. "CMP_STOP_EN,Comparator STOP Mode Enable" "0: Disable the analog comparator regardless of..,1: Allows CMP_EN to enable the analog comparator." newline bitfld.long 0x0 0. "CMP_EN,Comparator Enable" "0: Disables (The analog logic remains off and..,1: Enables" line.long 0x4 "CCR1,Comparator Control Register 1" hexmask.long.byte 0x4 24.--31. 1. "FILT_PER,Filter Sample Period" bitfld.long 0x4 16.--18. "FILT_CNT,Filter Sample Count" "0: Filter is bypassed: COUT = COUTA,1: 1 consecutive sample (Comparator output is..,2: 2 consecutive samples,3: 3 consecutive samples,4: 4 consecutive samples,5: 5 consecutive samples,6: 6 consecutive samples,7: 7 consecutive samples" newline bitfld.long 0x4 10.--11. "EVT_SEL,CMPO Event Select" "0: Both edges,1: Falling edge,2: Both edges,3: Both edges" bitfld.long 0x4 9. "WINDOW_CLS,CMPO Event Window Close" "0: CMPO event cannot close the window,1: CMPO event can close the window" newline bitfld.long 0x4 8. "WINDOW_INV,WINDOW/SAMPLE Signal Invert" "0: Do not invert,1: Invert" bitfld.long 0x4 7. "COUTA_OW,COUTA Output Level for Closed Window" "0: COUTA is 0,1: COUTA is 1" newline bitfld.long 0x4 6. "COUTA_OWEN,COUTA_OW Enable" "0: COUTA holds the last sampled value.,1: Enables the COUTA signal value to be defined by.." bitfld.long 0x4 5. "COUT_PEN,Comparator Output Pin Enable" "0: Not available,1: Available" newline bitfld.long 0x4 4. "COUT_SEL,Comparator Output Select" "0: Use COUT (filtered),1: Use COUTA (unfiltered)" bitfld.long 0x4 3. "COUT_INV,Comparator Invert" "0: Do not invert,1: Invert" newline bitfld.long 0x4 2. "DMA_EN,DMA Enable" "0: Disables,1: Enables" bitfld.long 0x4 1. "SAMPLE_EN,Sampling Enable" "0: Disables,1: Enables" newline bitfld.long 0x4 0. "WINDOW_EN,Windowing Enable" "0: Disables,1: Enables" line.long 0x8 "CCR2,Comparator Control Register 2" bitfld.long 0x8 28.--29. "INMSEL,Input Minus Select" "0: IN0: from the 8-bit DAC output,1: IN1: from the analog 8-1 mux,?,?" bitfld.long 0x8 24.--25. "INPSEL,Input Plus Select" "0: IN0: from the 8-bit DAC output,1: IN1: from the analog 8-1 mux,?,?" newline bitfld.long 0x8 20.--22. "MSEL,Minus Input MUX Select" "0: Input channel 0,1: Input channel 1,2: Input channel 2,3: Input channel 3,4: Input channel 4,5: Input channel 5,6: Input channel 6,7: Input channel 7" bitfld.long 0x8 16.--18. "PSEL,Plus Input MUX Select" "0: Input channel 0,1: Input channel 1,2: Input channel 2,3: Input channel 3,4: Input channel 4,5: Input channel 5,6: Input channel 6,7: Input channel 7" newline bitfld.long 0x8 4.--5. "HYSTCTR,Comparator Hysteresis Control" "0: Level 0,1: Level 1,2: Level 2,3: Level 3" bitfld.long 0x8 2. "OFFSET,Comparator Offset Control" "0: Level 0: The hysteresis selected by HYSTCTR is..,1: Level 1: Hysteresis does not apply when INP.." newline bitfld.long 0x8 0. "CMP_HPMD,CMP High Power Mode Select" "0: Low power (speed) comparison mode,1: High power (speed) comparison mode" group.long 0x18++0x1B line.long 0x0 "DCR,DAC Control" hexmask.long.byte 0x0 16.--23. 1. "DAC_DATA,DAC Output Voltage Select" bitfld.long 0x0 8. "VRSEL,DAC Reference High Voltage Source Select" "0: vrefh0,1: vrefh1" newline bitfld.long 0x0 0. "DAC_EN,DAC Enable" "0: Disables,1: Enables" line.long 0x4 "IER,Interrupt Enable" bitfld.long 0x4 2. "RRF_IE,Round-Robin Flag Interrupt Enable" "0: Disables the round-robin flag interrupt.,1: Enables the round-robin flag interrupt when the.." bitfld.long 0x4 1. "CFF_IE,Comparator Flag Falling Interrupt Enable" "0: Disables the comparator flag falling interrupt.,1: Enables the comparator flag falling interrupt.." newline bitfld.long 0x4 0. "CFR_IE,Comparator Flag Rising Interrupt Enable" "0: Disables the comparator flag rising interrupt.,1: Enables the comparator flag rising interrupt.." line.long 0x8 "CSR,Comparator Status" rbitfld.long 0x8 8. "COUT,Analog Comparator Output" "0,1" eventfld.long 0x8 2. "RRF,Round-Robin Flag" "0: Not detected,1: Detected" newline eventfld.long 0x8 1. "CFF,Analog Comparator Flag Falling" "0: Not detected,1: Detected" eventfld.long 0x8 0. "CFR,Analog Comparator Flag Rising" "0: Not detected,1: Detected" line.long 0xC "RRCR0,Round Robin Control Register 0" hexmask.long.byte 0xC 16.--21. 1. "RR_INITMOD,Initialization Delay Modulus" bitfld.long 0xC 8.--9. "RR_NSAM,Number of Sample Clocks" "0: 0 clock,1: 1 clock,2: 2 clocks,3: 3 clocks" newline bitfld.long 0xC 0. "RR_EN,Round-Robin Enable" "0: Disables,1: Enables" line.long 0x10 "RRCR1,Round Robin Control Register 1" bitfld.long 0x10 20.--22. "FIXCH,Fixed Channel Select" "0: Channel 0,1: Channel 1,2: Channel 2,3: Channel 3,4: Channel 4,5: Channel 5,6: Channel 6,7: Channel 7" bitfld.long 0x10 16. "FIXP,Fixed Port" "0: Fix the plus port. Sweep only the inputs to the..,1: Fix the minus port. Sweep only the inputs to the.." newline bitfld.long 0x10 7. "RR_CH7EN,Channel 7 Input Enable in Trigger Mode" "0: Disables,1: Enables" bitfld.long 0x10 6. "RR_CH6EN,Channel 6 Input Enable in Trigger Mode" "0: Disables,1: Enables" newline bitfld.long 0x10 5. "RR_CH5EN,Channel 5 Input Enable in Trigger Mode" "0: Disables,1: Enables" bitfld.long 0x10 4. "RR_CH4EN,Channel 4 Input Enable in Trigger Mode" "0: Disables,1: Enables" newline bitfld.long 0x10 3. "RR_CH3EN,Channel 3 Input Enable in Trigger Mode" "0: Disables,1: Enables" bitfld.long 0x10 2. "RR_CH2EN,Channel 2 Input Enable in Trigger Mode" "0: Disables,1: Enables" newline bitfld.long 0x10 1. "RR_CH1EN,Channel 1 Input Enable in Trigger Mode" "0: Disables,1: Enables" bitfld.long 0x10 0. "RR_CH0EN,Channel 0 Input Enable in Trigger Mode" "0: Disables,1: Enables" line.long 0x14 "RRCSR,Round Robin Control and Status" bitfld.long 0x14 7. "RR_CH7OUT,Comparison Result for Channel 7" "0,1" bitfld.long 0x14 6. "RR_CH6OUT,Comparison Result for Channel 6" "0,1" newline bitfld.long 0x14 5. "RR_CH5OUT,Comparison Result for Channel 5" "0,1" bitfld.long 0x14 4. "RR_CH4OUT,Comparison Result for Channel 4" "0,1" newline bitfld.long 0x14 3. "RR_CH3OUT,Comparison Result for Channel 3" "0,1" bitfld.long 0x14 2. "RR_CH2OUT,Comparison Result for Channel 2" "0,1" newline bitfld.long 0x14 1. "RR_CH1OUT,Comparison Result for Channel 1" "0,1" bitfld.long 0x14 0. "RR_CH0OUT,Comparison Result for Channel 0" "0,1" line.long 0x18 "RRSR,Round Robin Status" eventfld.long 0x18 7. "RR_CH7F,Channel 7 Input Changed Flag" "0: Not different,1: Different" eventfld.long 0x18 6. "RR_CH6F,Channel 6 Input Changed Flag" "0: Not different,1: Different" newline eventfld.long 0x18 5. "RR_CH5F,Channel 5 Input Changed Flag" "0: Not different,1: Different" eventfld.long 0x18 4. "RR_CH4F,Channel 4 Input Changed Flag" "0: Not different,1: Different" newline eventfld.long 0x18 3. "RR_CH3F,Channel 3 Input Changed Flag" "0: Not different,1: Different" eventfld.long 0x18 2. "RR_CH2F,Channel 2 Input Changed Flag" "0: Not different,1: Different" newline eventfld.long 0x18 1. "RR_CH1F,Channel 1 Input Changed Flag" "0: Not different,1: Different" eventfld.long 0x18 0. "RR_CH0F,Channel 0 Input Changed Flag" "0: Not different,1: Different" tree.end tree "LPCMP_2" base ad:0x404E8000 rgroup.long 0x0++0x7 line.long 0x0 "VERID,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Specification Number" line.long 0x4 "PARAM,Parameter" hexmask.long.byte 0x4 0.--3. 1. "DAC_RES,DAC Resolution" group.long 0x8++0xB line.long 0x0 "CCR0,Comparator Control Register 0" bitfld.long 0x0 2. "LINKEN,CMP-to-DAC Link Enable" "0: Disable the CMP-to-DAC link: enabling or..,1: Enable the CMP-to-DAC link: the DAC.." bitfld.long 0x0 1. "CMP_STOP_EN,Comparator STOP Mode Enable" "0: Disable the analog comparator regardless of..,1: Allows CMP_EN to enable the analog comparator." newline bitfld.long 0x0 0. "CMP_EN,Comparator Enable" "0: Disables (The analog logic remains off and..,1: Enables" line.long 0x4 "CCR1,Comparator Control Register 1" hexmask.long.byte 0x4 24.--31. 1. "FILT_PER,Filter Sample Period" bitfld.long 0x4 16.--18. "FILT_CNT,Filter Sample Count" "0: Filter is bypassed: COUT = COUTA,1: 1 consecutive sample (Comparator output is..,2: 2 consecutive samples,3: 3 consecutive samples,4: 4 consecutive samples,5: 5 consecutive samples,6: 6 consecutive samples,7: 7 consecutive samples" newline bitfld.long 0x4 10.--11. "EVT_SEL,CMPO Event Select" "0: Both edges,1: Falling edge,2: Both edges,3: Both edges" bitfld.long 0x4 9. "WINDOW_CLS,CMPO Event Window Close" "0: CMPO event cannot close the window,1: CMPO event can close the window" newline bitfld.long 0x4 8. "WINDOW_INV,WINDOW/SAMPLE Signal Invert" "0: Do not invert,1: Invert" bitfld.long 0x4 7. "COUTA_OW,COUTA Output Level for Closed Window" "0: COUTA is 0,1: COUTA is 1" newline bitfld.long 0x4 6. "COUTA_OWEN,COUTA_OW Enable" "0: COUTA holds the last sampled value.,1: Enables the COUTA signal value to be defined by.." bitfld.long 0x4 5. "COUT_PEN,Comparator Output Pin Enable" "0: Not available,1: Available" newline bitfld.long 0x4 4. "COUT_SEL,Comparator Output Select" "0: Use COUT (filtered),1: Use COUTA (unfiltered)" bitfld.long 0x4 3. "COUT_INV,Comparator Invert" "0: Do not invert,1: Invert" newline bitfld.long 0x4 2. "DMA_EN,DMA Enable" "0: Disables,1: Enables" bitfld.long 0x4 1. "SAMPLE_EN,Sampling Enable" "0: Disables,1: Enables" newline bitfld.long 0x4 0. "WINDOW_EN,Windowing Enable" "0: Disables,1: Enables" line.long 0x8 "CCR2,Comparator Control Register 2" bitfld.long 0x8 28.--29. "INMSEL,Input Minus Select" "0: IN0: from the 8-bit DAC output,1: IN1: from the analog 8-1 mux,?,?" bitfld.long 0x8 24.--25. "INPSEL,Input Plus Select" "0: IN0: from the 8-bit DAC output,1: IN1: from the analog 8-1 mux,?,?" newline bitfld.long 0x8 20.--22. "MSEL,Minus Input MUX Select" "0: Input channel 0,1: Input channel 1,2: Input channel 2,3: Input channel 3,4: Input channel 4,5: Input channel 5,6: Input channel 6,7: Input channel 7" bitfld.long 0x8 16.--18. "PSEL,Plus Input MUX Select" "0: Input channel 0,1: Input channel 1,2: Input channel 2,3: Input channel 3,4: Input channel 4,5: Input channel 5,6: Input channel 6,7: Input channel 7" newline bitfld.long 0x8 4.--5. "HYSTCTR,Comparator Hysteresis Control" "0: Level 0,1: Level 1,2: Level 2,3: Level 3" bitfld.long 0x8 2. "OFFSET,Comparator Offset Control" "0: Level 0: The hysteresis selected by HYSTCTR is..,1: Level 1: Hysteresis does not apply when INP.." newline bitfld.long 0x8 0. "CMP_HPMD,CMP High Power Mode Select" "0: Low power (speed) comparison mode,1: High power (speed) comparison mode" group.long 0x18++0x1B line.long 0x0 "DCR,DAC Control" hexmask.long.byte 0x0 16.--23. 1. "DAC_DATA,DAC Output Voltage Select" bitfld.long 0x0 8. "VRSEL,DAC Reference High Voltage Source Select" "0: vrefh0,1: vrefh1" newline bitfld.long 0x0 0. "DAC_EN,DAC Enable" "0: Disables,1: Enables" line.long 0x4 "IER,Interrupt Enable" bitfld.long 0x4 2. "RRF_IE,Round-Robin Flag Interrupt Enable" "0: Disables the round-robin flag interrupt.,1: Enables the round-robin flag interrupt when the.." bitfld.long 0x4 1. "CFF_IE,Comparator Flag Falling Interrupt Enable" "0: Disables the comparator flag falling interrupt.,1: Enables the comparator flag falling interrupt.." newline bitfld.long 0x4 0. "CFR_IE,Comparator Flag Rising Interrupt Enable" "0: Disables the comparator flag rising interrupt.,1: Enables the comparator flag rising interrupt.." line.long 0x8 "CSR,Comparator Status" rbitfld.long 0x8 8. "COUT,Analog Comparator Output" "0,1" eventfld.long 0x8 2. "RRF,Round-Robin Flag" "0: Not detected,1: Detected" newline eventfld.long 0x8 1. "CFF,Analog Comparator Flag Falling" "0: Not detected,1: Detected" eventfld.long 0x8 0. "CFR,Analog Comparator Flag Rising" "0: Not detected,1: Detected" line.long 0xC "RRCR0,Round Robin Control Register 0" hexmask.long.byte 0xC 16.--21. 1. "RR_INITMOD,Initialization Delay Modulus" bitfld.long 0xC 8.--9. "RR_NSAM,Number of Sample Clocks" "0: 0 clock,1: 1 clock,2: 2 clocks,3: 3 clocks" newline bitfld.long 0xC 0. "RR_EN,Round-Robin Enable" "0: Disables,1: Enables" line.long 0x10 "RRCR1,Round Robin Control Register 1" bitfld.long 0x10 20.--22. "FIXCH,Fixed Channel Select" "0: Channel 0,1: Channel 1,2: Channel 2,3: Channel 3,4: Channel 4,5: Channel 5,6: Channel 6,7: Channel 7" bitfld.long 0x10 16. "FIXP,Fixed Port" "0: Fix the plus port. Sweep only the inputs to the..,1: Fix the minus port. Sweep only the inputs to the.." newline bitfld.long 0x10 7. "RR_CH7EN,Channel 7 Input Enable in Trigger Mode" "0: Disables,1: Enables" bitfld.long 0x10 6. "RR_CH6EN,Channel 6 Input Enable in Trigger Mode" "0: Disables,1: Enables" newline bitfld.long 0x10 5. "RR_CH5EN,Channel 5 Input Enable in Trigger Mode" "0: Disables,1: Enables" bitfld.long 0x10 4. "RR_CH4EN,Channel 4 Input Enable in Trigger Mode" "0: Disables,1: Enables" newline bitfld.long 0x10 3. "RR_CH3EN,Channel 3 Input Enable in Trigger Mode" "0: Disables,1: Enables" bitfld.long 0x10 2. "RR_CH2EN,Channel 2 Input Enable in Trigger Mode" "0: Disables,1: Enables" newline bitfld.long 0x10 1. "RR_CH1EN,Channel 1 Input Enable in Trigger Mode" "0: Disables,1: Enables" bitfld.long 0x10 0. "RR_CH0EN,Channel 0 Input Enable in Trigger Mode" "0: Disables,1: Enables" line.long 0x14 "RRCSR,Round Robin Control and Status" bitfld.long 0x14 7. "RR_CH7OUT,Comparison Result for Channel 7" "0,1" bitfld.long 0x14 6. "RR_CH6OUT,Comparison Result for Channel 6" "0,1" newline bitfld.long 0x14 5. "RR_CH5OUT,Comparison Result for Channel 5" "0,1" bitfld.long 0x14 4. "RR_CH4OUT,Comparison Result for Channel 4" "0,1" newline bitfld.long 0x14 3. "RR_CH3OUT,Comparison Result for Channel 3" "0,1" bitfld.long 0x14 2. "RR_CH2OUT,Comparison Result for Channel 2" "0,1" newline bitfld.long 0x14 1. "RR_CH1OUT,Comparison Result for Channel 1" "0,1" bitfld.long 0x14 0. "RR_CH0OUT,Comparison Result for Channel 0" "0,1" line.long 0x18 "RRSR,Round Robin Status" eventfld.long 0x18 7. "RR_CH7F,Channel 7 Input Changed Flag" "0: Not different,1: Different" eventfld.long 0x18 6. "RR_CH6F,Channel 6 Input Changed Flag" "0: Not different,1: Different" newline eventfld.long 0x18 5. "RR_CH5F,Channel 5 Input Changed Flag" "0: Not different,1: Different" eventfld.long 0x18 4. "RR_CH4F,Channel 4 Input Changed Flag" "0: Not different,1: Different" newline eventfld.long 0x18 3. "RR_CH3F,Channel 3 Input Changed Flag" "0: Not different,1: Different" eventfld.long 0x18 2. "RR_CH2F,Channel 2 Input Changed Flag" "0: Not different,1: Different" newline eventfld.long 0x18 1. "RR_CH1F,Channel 1 Input Changed Flag" "0: Not different,1: Different" eventfld.long 0x18 0. "RR_CH0F,Channel 0 Input Changed Flag" "0: Not different,1: Different" tree.end tree.end tree "LPI2C (Low Power Inter-Integrated Circuit)" base ad:0x0 tree "LPI2C_0" base ad:0x40350000 rgroup.long 0x0++0x7 line.long 0x0 "VERID,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Specification Number" line.long 0x4 "PARAM,Parameter" hexmask.long.byte 0x4 8.--11. 1. "MRXFIFO,Controller Receive FIFO Size" hexmask.long.byte 0x4 0.--3. 1. "MTXFIFO,Controller Transmit FIFO Size" group.long 0x10++0x1F line.long 0x0 "MCR,Controller Control" bitfld.long 0x0 9. "RRF,Reset Receive FIFO" "0: No effect,1: Reset receive FIFO" bitfld.long 0x0 8. "RTF,Reset Transmit FIFO" "0: No effect,1: Reset transmit FIFO" newline bitfld.long 0x0 3. "DBGEN,Debug Enable" "0: Disable,1: Enable" bitfld.long 0x0 2. "DOZEN,Doze Mode Enable" "0: Enable,1: Disable" newline bitfld.long 0x0 1. "RST,Software Reset" "0: No effect,1: Reset" bitfld.long 0x0 0. "MEN,Controller Enable" "0: Disable,1: Enable" line.long 0x4 "MSR,Controller Status" rbitfld.long 0x4 25. "BBF,Bus Busy Flag" "0: Idle,1: Busy" rbitfld.long 0x4 24. "MBF,Controller Busy Flag" "0: Idle,1: Busy" newline eventfld.long 0x4 14. "DMF,Data Match Flag" "0: Matching data not received,1: Matching data received" eventfld.long 0x4 13. "PLTF,Pin Low Timeout Flag" "0: Pin low timeout did not occur,1: Pin low timeout occurred" newline eventfld.long 0x4 12. "FEF,FIFO Error Flag" "0: No FIFO error,1: FIFO error" eventfld.long 0x4 11. "ALF,Arbitration Lost Flag" "0: Controller did not lose arbitration,1: Controller lost arbitration" newline eventfld.long 0x4 10. "NDF,NACK Detect Flag" "0: No unexpected NACK detected,1: Unexpected NACK detected" eventfld.long 0x4 9. "SDF,Stop Detect Flag" "0: No Stop condition generated,1: Stop condition generated" newline eventfld.long 0x4 8. "EPF,End Packet Flag" "0: No Stop or repeated Start generated,1: Stop or repeated Start generated" rbitfld.long 0x4 1. "RDF,Receive Data Flag" "0: Receive data not ready,1: Receive data ready" newline rbitfld.long 0x4 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data requested" line.long 0x8 "MIER,Controller Interrupt Enable" bitfld.long 0x8 14. "DMIE,Data Match Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 13. "PLTIE,Pin Low Timeout Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x8 12. "FEIE,FIFO Error Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 11. "ALIE,Arbitration Lost Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x8 10. "NDIE,NACK Detect Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 9. "SDIE,Stop Detect Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x8 8. "EPIE,End Packet Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 1. "RDIE,Receive Data Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x8 0. "TDIE,Transmit Data Interrupt Enable" "0: Disable,1: Enable" line.long 0xC "MDER,Controller DMA Enable" bitfld.long 0xC 1. "RDDE,Receive Data DMA Enable" "0: Disable,1: Enable" bitfld.long 0xC 0. "TDDE,Transmit Data DMA Enable" "0: Disable,1: Enable" line.long 0x10 "MCFGR0,Controller Configuration 0" bitfld.long 0x10 9. "RDMO,Receive Data Match Only" "0: Received data is stored in the receive FIFO,1: Received data is discarded unless MSR[DMF] is set" bitfld.long 0x10 8. "CIRFIFO,Circular FIFO Enable" "0: Disable,1: Enable" newline bitfld.long 0x10 2. "HRSEL,Host Request Select" "0: Host request input is pin HREQ,1: Host request input is input trigger" bitfld.long 0x10 1. "HRPOL,Host Request Polarity" "0: Active low,1: Active high" newline bitfld.long 0x10 0. "HREN,Host Request Enable" "0: Disable,1: Enable" line.long 0x14 "MCFGR1,Controller Configuration 1" bitfld.long 0x14 24.--26. "PINCFG,Pin Configuration" "0: Two-pin open drain mode,1: Two-pin output only mode (Ultra-Fast mode),2: Two-pin push-pull mode,3: Four-pin push-pull mode,4: Two-pin open-drain mode with separate LPI2C target,5: Two-pin output only mode (Ultra-Fast mode) with..,6: Two-pin push-pull mode with separate LPI2C target,7: Four-pin push-pull mode (inverted outputs)" bitfld.long 0x14 16.--18. "MATCFG,Match Configuration" "0: Match is disabled,?,2: Match is enabled: first data word equals..,3: Match is enabled: any data word equals..,4: Match is enabled: (first data word equals..,5: Match is enabled: (any data word equals..,6: Match is enabled: (first data word AND..,7: Match is enabled: (any data word AND.." newline bitfld.long 0x14 10. "TIMECFG,Timeout Configuration" "0: SCL,1: SCL or SDA" bitfld.long 0x14 9. "IGNACK,Ignore NACK" "0: No effect,1: Treat a received NACK as an ACK" newline bitfld.long 0x14 8. "AUTOSTOP,Automatic Stop Generation" "0: No effect,1: Stop automatically generated" bitfld.long 0x14 0.--2. "PRESCALE,Prescaler" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128" line.long 0x18 "MCFGR2,Controller Configuration 2" hexmask.long.byte 0x18 24.--27. 1. "FILTSDA,Glitch Filter SDA" hexmask.long.byte 0x18 16.--19. 1. "FILTSCL,Glitch Filter SCL" newline hexmask.long.word 0x18 0.--11. 1. "BUSIDLE,Bus Idle Timeout" line.long 0x1C "MCFGR3,Controller Configuration 3" hexmask.long.word 0x1C 8.--19. 1. "PINLOW,Pin Low Timeout" group.long 0x40++0x3 line.long 0x0 "MDMR,Controller Data Match" hexmask.long.byte 0x0 16.--23. 1. "MATCH1,Match 1 Value" hexmask.long.byte 0x0 0.--7. 1. "MATCH0,Match 0 Value" group.long 0x48++0x3 line.long 0x0 "MCCR0,Controller Clock Configuration 0" hexmask.long.byte 0x0 24.--29. 1. "DATAVD,Data Valid Delay" hexmask.long.byte 0x0 16.--21. 1. "SETHOLD,Setup Hold Delay" newline hexmask.long.byte 0x0 8.--13. 1. "CLKHI,Clock High Period" hexmask.long.byte 0x0 0.--5. 1. "CLKLO,Clock Low Period" group.long 0x50++0x3 line.long 0x0 "MCCR1,Controller Clock Configuration 1" hexmask.long.byte 0x0 24.--29. 1. "DATAVD,Data Valid Delay" hexmask.long.byte 0x0 16.--21. 1. "SETHOLD,Setup Hold Delay" newline hexmask.long.byte 0x0 8.--13. 1. "CLKHI,Clock High Period" hexmask.long.byte 0x0 0.--5. 1. "CLKLO,Clock Low Period" group.long 0x58++0x3 line.long 0x0 "MFCR,Controller FIFO Control" bitfld.long 0x0 16.--17. "RXWATER,Receive FIFO Watermark" "0,1,2,3" bitfld.long 0x0 0.--1. "TXWATER,Transmit FIFO Watermark" "0,1,2,3" rgroup.long 0x5C++0x3 line.long 0x0 "MFSR,Controller FIFO Status" bitfld.long 0x0 16.--18. "RXCOUNT,Receive FIFO Count" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "TXCOUNT,Transmit FIFO Count" "0,1,2,3,4,5,6,7" wgroup.long 0x60++0x3 line.long 0x0 "MTDR,Controller Transmit Data" bitfld.long 0x0 8.--10. "CMD,Command Data" "0: Transmit the value in DATA[7:0],1: Receive (DATA[7:0] + 1) bytes,2: Generate Stop condition on I2C bus,3: Receive and discard (DATA[7:0] + 1) bytes,4: Generate (repeated) Start on the I2C bus and..,5: Generate (repeated) Start on the I2C bus and..,6: Generate (repeated) Start on the I2C bus and..,7: Generate (repeated) Start on the I2C bus and.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Transmit Data" rgroup.long 0x70++0x3 line.long 0x0 "MRDR,Controller Receive Data" bitfld.long 0x0 14. "RXEMPTY,Receive Empty" "0: Not empty,1: Empty" hexmask.long.byte 0x0 0.--7. 1. "DATA,Receive Data" group.long 0x110++0xF line.long 0x0 "SCR,Target Control" bitfld.long 0x0 9. "RRF,Reset Receive FIFO" "0: No effect,1: SRDR is now empty" bitfld.long 0x0 8. "RTF,Reset Transmit FIFO" "0: No effect,1: STDR is now empty" newline bitfld.long 0x0 5. "FILTDZ,Filter Doze Enable" "0: Enable,1: Disable" bitfld.long 0x0 4. "FILTEN,Filter Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "RST,Software Reset" "0: Not reset,1: Reset" bitfld.long 0x0 0. "SEN,Target Enable" "0: Disable,1: Enable" line.long 0x4 "SSR,Target Status" rbitfld.long 0x4 25. "BBF,Bus Busy Flag" "0: Idle,1: Busy" rbitfld.long 0x4 24. "SBF,Target Busy Flag" "0: Idle,1: Busy" newline rbitfld.long 0x4 15. "SARF,SMBus Alert Response Flag" "0: Disabled or not detected,1: Enabled and detected" rbitfld.long 0x4 14. "GCF,General Call Flag" "0: General call address disabled or not detected,1: General call address detected" newline rbitfld.long 0x4 13. "AM1F,Address Match 1 Flag" "0: Matching address not received,1: Matching address received" rbitfld.long 0x4 12. "AM0F,Address Match 0 Flag" "0: ADDR0 matching address not received,1: ADDR0 matching address received" newline eventfld.long 0x4 11. "FEF,FIFO Error Flag" "0: No FIFO error,1: FIFO error" eventfld.long 0x4 10. "BEF,Bit Error Flag" "0: No bit error occurred,1: Bit error occurred" newline eventfld.long 0x4 9. "SDF,Stop Detect Flag" "0: No Stop detected,1: Stop detected" eventfld.long 0x4 8. "RSF,Repeated Start Flag" "0: No repeated Start detected,1: Repeated Start detected" newline rbitfld.long 0x4 3. "TAF,Transmit ACK Flag" "0: Not required,1: Required" rbitfld.long 0x4 2. "AVF,Address Valid Flag" "0: Not valid,1: Valid" newline rbitfld.long 0x4 1. "RDF,Receive Data Flag" "0: Not ready,1: Ready" rbitfld.long 0x4 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested" line.long 0x8 "SIER,Target Interrupt Enable" bitfld.long 0x8 15. "SARIE,SMBus Alert Response Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 14. "GCIE,General Call Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x8 13. "AM1IE,Address Match 1 Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 12. "AM0IE,Address Match 0 Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x8 11. "FEIE,FIFO Error Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 10. "BEIE,Bit Error Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x8 9. "SDIE,Stop Detect Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 8. "RSIE,Repeated Start Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x8 3. "TAIE,Transmit ACK Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 2. "AVIE,Address Valid Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x8 1. "RDIE,Receive Data Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 0. "TDIE,Transmit Data Interrupt Enable" "0: Disable,1: Enable" line.long 0xC "SDER,Target DMA Enable" bitfld.long 0xC 2. "AVDE,Address Valid DMA Enable" "0: Disable,1: Enable" bitfld.long 0xC 1. "RDDE,Receive Data DMA Enable" "0: Disable DMA request,1: Enable DMA request" newline bitfld.long 0xC 0. "TDDE,Transmit Data DMA Enable" "0: Disable,1: Enable" group.long 0x124++0x7 line.long 0x0 "SCFGR1,Target Configuration 1" bitfld.long 0x0 16.--18. "ADDRCFG,Address Configuration" "0: Address match 0 (7-bit),1: Address match 0 (10-bit),2: Address match 0 (7-bit) or address match 1 (7-bit),3: Address match 0 (10-bit) or address match 1..,4: Address match 0 (7-bit) or address match 1..,5: Address match 0 (10-bit) or address match 1..,6: From address match 0 (7-bit) to address match 1..,7: From address match 0 (10-bit) to address match 1.." bitfld.long 0x0 13. "HSMEN,HS Mode Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 12. "IGNACK,Ignore NACK" "0: End transfer on NACK,1: Do not end transfer on NACK" bitfld.long 0x0 11. "RXCFG,Receive Data Configuration" "0: Return received data clear MSR[RDF],1: Return SASR and clear SSR[AVF] when SSR[AVF] is.." newline bitfld.long 0x0 10. "TXCFG,Transmit Flag Configuration" "0: MSR[TDF] is set only during a target-transmit..,1: MSR[TDF] is set whenever STDR is empty" bitfld.long 0x0 9. "SAEN,SMBus Alert Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 8. "GCEN,General Call Enable" "0: Disable,1: Enable" bitfld.long 0x0 3. "ACKSTALL,ACK SCL Stall" "0: Disable,1: Enable" newline bitfld.long 0x0 2. "TXDSTALL,Transmit Data SCL Stall" "0: Disable,1: Enable" bitfld.long 0x0 1. "RXSTALL,RX SCL Stall" "0: Disable,1: Enable" newline bitfld.long 0x0 0. "ADRSTALL,Address SCL Stall" "0: Disable,1: Enable" line.long 0x4 "SCFGR2,Target Configuration 2" hexmask.long.byte 0x4 24.--27. 1. "FILTSDA,Glitch Filter SDA" hexmask.long.byte 0x4 16.--19. 1. "FILTSCL,Glitch Filter SCL" newline hexmask.long.byte 0x4 8.--13. 1. "DATAVD,Data Valid Delay" hexmask.long.byte 0x4 0.--3. 1. "CLKHOLD,Clock Hold Time" group.long 0x140++0x3 line.long 0x0 "SAMR,Target Address Match" hexmask.long.word 0x0 17.--26. 1. "ADDR1,Address 1 Value" hexmask.long.word 0x0 1.--10. 1. "ADDR0,Address 0 Value" rgroup.long 0x150++0x3 line.long 0x0 "SASR,Target Address Status" bitfld.long 0x0 14. "ANV,Address Not Valid" "0: Valid,1: Not valid" hexmask.long.word 0x0 0.--10. 1. "RADDR,Received Address" group.long 0x154++0x3 line.long 0x0 "STAR,Target Transmit ACK" bitfld.long 0x0 0. "TXNACK,Transmit NACK" "0: Transmit ACK,1: Transmit NACK" wgroup.long 0x160++0x3 line.long 0x0 "STDR,Target Transmit Data" hexmask.long.byte 0x0 0.--7. 1. "DATA,Transmit Data" rgroup.long 0x170++0x3 line.long 0x0 "SRDR,Target Receive Data" bitfld.long 0x0 15. "SOF,Start of Frame" "0: Not first,1: First" bitfld.long 0x0 14. "RXEMPTY,Receive Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 8.--10. "RADDR,Received Address" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data" tree.end tree "LPI2C_1" base ad:0x40354000 rgroup.long 0x0++0x7 line.long 0x0 "VERID,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Specification Number" line.long 0x4 "PARAM,Parameter" hexmask.long.byte 0x4 8.--11. 1. "MRXFIFO,Controller Receive FIFO Size" hexmask.long.byte 0x4 0.--3. 1. "MTXFIFO,Controller Transmit FIFO Size" group.long 0x10++0x1F line.long 0x0 "MCR,Controller Control" bitfld.long 0x0 9. "RRF,Reset Receive FIFO" "0: No effect,1: Reset receive FIFO" bitfld.long 0x0 8. "RTF,Reset Transmit FIFO" "0: No effect,1: Reset transmit FIFO" newline bitfld.long 0x0 3. "DBGEN,Debug Enable" "0: Disable,1: Enable" bitfld.long 0x0 2. "DOZEN,Doze Mode Enable" "0: Enable,1: Disable" newline bitfld.long 0x0 1. "RST,Software Reset" "0: No effect,1: Reset" bitfld.long 0x0 0. "MEN,Controller Enable" "0: Disable,1: Enable" line.long 0x4 "MSR,Controller Status" rbitfld.long 0x4 25. "BBF,Bus Busy Flag" "0: Idle,1: Busy" rbitfld.long 0x4 24. "MBF,Controller Busy Flag" "0: Idle,1: Busy" newline eventfld.long 0x4 14. "DMF,Data Match Flag" "0: Matching data not received,1: Matching data received" eventfld.long 0x4 13. "PLTF,Pin Low Timeout Flag" "0: Pin low timeout did not occur,1: Pin low timeout occurred" newline eventfld.long 0x4 12. "FEF,FIFO Error Flag" "0: No FIFO error,1: FIFO error" eventfld.long 0x4 11. "ALF,Arbitration Lost Flag" "0: Controller did not lose arbitration,1: Controller lost arbitration" newline eventfld.long 0x4 10. "NDF,NACK Detect Flag" "0: No unexpected NACK detected,1: Unexpected NACK detected" eventfld.long 0x4 9. "SDF,Stop Detect Flag" "0: No Stop condition generated,1: Stop condition generated" newline eventfld.long 0x4 8. "EPF,End Packet Flag" "0: No Stop or repeated Start generated,1: Stop or repeated Start generated" rbitfld.long 0x4 1. "RDF,Receive Data Flag" "0: Receive data not ready,1: Receive data ready" newline rbitfld.long 0x4 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data requested" line.long 0x8 "MIER,Controller Interrupt Enable" bitfld.long 0x8 14. "DMIE,Data Match Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 13. "PLTIE,Pin Low Timeout Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x8 12. "FEIE,FIFO Error Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 11. "ALIE,Arbitration Lost Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x8 10. "NDIE,NACK Detect Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 9. "SDIE,Stop Detect Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x8 8. "EPIE,End Packet Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 1. "RDIE,Receive Data Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x8 0. "TDIE,Transmit Data Interrupt Enable" "0: Disable,1: Enable" line.long 0xC "MDER,Controller DMA Enable" bitfld.long 0xC 1. "RDDE,Receive Data DMA Enable" "0: Disable,1: Enable" bitfld.long 0xC 0. "TDDE,Transmit Data DMA Enable" "0: Disable,1: Enable" line.long 0x10 "MCFGR0,Controller Configuration 0" bitfld.long 0x10 9. "RDMO,Receive Data Match Only" "0: Received data is stored in the receive FIFO,1: Received data is discarded unless MSR[DMF] is set" bitfld.long 0x10 8. "CIRFIFO,Circular FIFO Enable" "0: Disable,1: Enable" newline bitfld.long 0x10 2. "HRSEL,Host Request Select" "0: Host request input is pin HREQ,1: Host request input is input trigger" bitfld.long 0x10 1. "HRPOL,Host Request Polarity" "0: Active low,1: Active high" newline bitfld.long 0x10 0. "HREN,Host Request Enable" "0: Disable,1: Enable" line.long 0x14 "MCFGR1,Controller Configuration 1" bitfld.long 0x14 24.--26. "PINCFG,Pin Configuration" "0: Two-pin open drain mode,1: Two-pin output only mode (Ultra-Fast mode),2: Two-pin push-pull mode,3: Four-pin push-pull mode,4: Two-pin open-drain mode with separate LPI2C target,5: Two-pin output only mode (Ultra-Fast mode) with..,6: Two-pin push-pull mode with separate LPI2C target,7: Four-pin push-pull mode (inverted outputs)" bitfld.long 0x14 16.--18. "MATCFG,Match Configuration" "0: Match is disabled,?,2: Match is enabled: first data word equals..,3: Match is enabled: any data word equals..,4: Match is enabled: (first data word equals..,5: Match is enabled: (any data word equals..,6: Match is enabled: (first data word AND..,7: Match is enabled: (any data word AND.." newline bitfld.long 0x14 10. "TIMECFG,Timeout Configuration" "0: SCL,1: SCL or SDA" bitfld.long 0x14 9. "IGNACK,Ignore NACK" "0: No effect,1: Treat a received NACK as an ACK" newline bitfld.long 0x14 8. "AUTOSTOP,Automatic Stop Generation" "0: No effect,1: Stop automatically generated" bitfld.long 0x14 0.--2. "PRESCALE,Prescaler" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128" line.long 0x18 "MCFGR2,Controller Configuration 2" hexmask.long.byte 0x18 24.--27. 1. "FILTSDA,Glitch Filter SDA" hexmask.long.byte 0x18 16.--19. 1. "FILTSCL,Glitch Filter SCL" newline hexmask.long.word 0x18 0.--11. 1. "BUSIDLE,Bus Idle Timeout" line.long 0x1C "MCFGR3,Controller Configuration 3" hexmask.long.word 0x1C 8.--19. 1. "PINLOW,Pin Low Timeout" group.long 0x40++0x3 line.long 0x0 "MDMR,Controller Data Match" hexmask.long.byte 0x0 16.--23. 1. "MATCH1,Match 1 Value" hexmask.long.byte 0x0 0.--7. 1. "MATCH0,Match 0 Value" group.long 0x48++0x3 line.long 0x0 "MCCR0,Controller Clock Configuration 0" hexmask.long.byte 0x0 24.--29. 1. "DATAVD,Data Valid Delay" hexmask.long.byte 0x0 16.--21. 1. "SETHOLD,Setup Hold Delay" newline hexmask.long.byte 0x0 8.--13. 1. "CLKHI,Clock High Period" hexmask.long.byte 0x0 0.--5. 1. "CLKLO,Clock Low Period" group.long 0x50++0x3 line.long 0x0 "MCCR1,Controller Clock Configuration 1" hexmask.long.byte 0x0 24.--29. 1. "DATAVD,Data Valid Delay" hexmask.long.byte 0x0 16.--21. 1. "SETHOLD,Setup Hold Delay" newline hexmask.long.byte 0x0 8.--13. 1. "CLKHI,Clock High Period" hexmask.long.byte 0x0 0.--5. 1. "CLKLO,Clock Low Period" group.long 0x58++0x3 line.long 0x0 "MFCR,Controller FIFO Control" bitfld.long 0x0 16.--17. "RXWATER,Receive FIFO Watermark" "0,1,2,3" bitfld.long 0x0 0.--1. "TXWATER,Transmit FIFO Watermark" "0,1,2,3" rgroup.long 0x5C++0x3 line.long 0x0 "MFSR,Controller FIFO Status" bitfld.long 0x0 16.--18. "RXCOUNT,Receive FIFO Count" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "TXCOUNT,Transmit FIFO Count" "0,1,2,3,4,5,6,7" wgroup.long 0x60++0x3 line.long 0x0 "MTDR,Controller Transmit Data" bitfld.long 0x0 8.--10. "CMD,Command Data" "0: Transmit the value in DATA[7:0],1: Receive (DATA[7:0] + 1) bytes,2: Generate Stop condition on I2C bus,3: Receive and discard (DATA[7:0] + 1) bytes,4: Generate (repeated) Start on the I2C bus and..,5: Generate (repeated) Start on the I2C bus and..,6: Generate (repeated) Start on the I2C bus and..,7: Generate (repeated) Start on the I2C bus and.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Transmit Data" rgroup.long 0x70++0x3 line.long 0x0 "MRDR,Controller Receive Data" bitfld.long 0x0 14. "RXEMPTY,Receive Empty" "0: Not empty,1: Empty" hexmask.long.byte 0x0 0.--7. 1. "DATA,Receive Data" group.long 0x110++0xF line.long 0x0 "SCR,Target Control" bitfld.long 0x0 9. "RRF,Reset Receive FIFO" "0: No effect,1: SRDR is now empty" bitfld.long 0x0 8. "RTF,Reset Transmit FIFO" "0: No effect,1: STDR is now empty" newline bitfld.long 0x0 5. "FILTDZ,Filter Doze Enable" "0: Enable,1: Disable" bitfld.long 0x0 4. "FILTEN,Filter Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "RST,Software Reset" "0: Not reset,1: Reset" bitfld.long 0x0 0. "SEN,Target Enable" "0: Disable,1: Enable" line.long 0x4 "SSR,Target Status" rbitfld.long 0x4 25. "BBF,Bus Busy Flag" "0: Idle,1: Busy" rbitfld.long 0x4 24. "SBF,Target Busy Flag" "0: Idle,1: Busy" newline rbitfld.long 0x4 15. "SARF,SMBus Alert Response Flag" "0: Disabled or not detected,1: Enabled and detected" rbitfld.long 0x4 14. "GCF,General Call Flag" "0: General call address disabled or not detected,1: General call address detected" newline rbitfld.long 0x4 13. "AM1F,Address Match 1 Flag" "0: Matching address not received,1: Matching address received" rbitfld.long 0x4 12. "AM0F,Address Match 0 Flag" "0: ADDR0 matching address not received,1: ADDR0 matching address received" newline eventfld.long 0x4 11. "FEF,FIFO Error Flag" "0: No FIFO error,1: FIFO error" eventfld.long 0x4 10. "BEF,Bit Error Flag" "0: No bit error occurred,1: Bit error occurred" newline eventfld.long 0x4 9. "SDF,Stop Detect Flag" "0: No Stop detected,1: Stop detected" eventfld.long 0x4 8. "RSF,Repeated Start Flag" "0: No repeated Start detected,1: Repeated Start detected" newline rbitfld.long 0x4 3. "TAF,Transmit ACK Flag" "0: Not required,1: Required" rbitfld.long 0x4 2. "AVF,Address Valid Flag" "0: Not valid,1: Valid" newline rbitfld.long 0x4 1. "RDF,Receive Data Flag" "0: Not ready,1: Ready" rbitfld.long 0x4 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested" line.long 0x8 "SIER,Target Interrupt Enable" bitfld.long 0x8 15. "SARIE,SMBus Alert Response Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 14. "GCIE,General Call Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x8 13. "AM1IE,Address Match 1 Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 12. "AM0IE,Address Match 0 Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x8 11. "FEIE,FIFO Error Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 10. "BEIE,Bit Error Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x8 9. "SDIE,Stop Detect Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 8. "RSIE,Repeated Start Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x8 3. "TAIE,Transmit ACK Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 2. "AVIE,Address Valid Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x8 1. "RDIE,Receive Data Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 0. "TDIE,Transmit Data Interrupt Enable" "0: Disable,1: Enable" line.long 0xC "SDER,Target DMA Enable" bitfld.long 0xC 2. "AVDE,Address Valid DMA Enable" "0: Disable,1: Enable" bitfld.long 0xC 1. "RDDE,Receive Data DMA Enable" "0: Disable DMA request,1: Enable DMA request" newline bitfld.long 0xC 0. "TDDE,Transmit Data DMA Enable" "0: Disable,1: Enable" group.long 0x124++0x7 line.long 0x0 "SCFGR1,Target Configuration 1" bitfld.long 0x0 16.--18. "ADDRCFG,Address Configuration" "0: Address match 0 (7-bit),1: Address match 0 (10-bit),2: Address match 0 (7-bit) or address match 1 (7-bit),3: Address match 0 (10-bit) or address match 1..,4: Address match 0 (7-bit) or address match 1..,5: Address match 0 (10-bit) or address match 1..,6: From address match 0 (7-bit) to address match 1..,7: From address match 0 (10-bit) to address match 1.." bitfld.long 0x0 13. "HSMEN,HS Mode Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 12. "IGNACK,Ignore NACK" "0: End transfer on NACK,1: Do not end transfer on NACK" bitfld.long 0x0 11. "RXCFG,Receive Data Configuration" "0: Return received data clear MSR[RDF],1: Return SASR and clear SSR[AVF] when SSR[AVF] is.." newline bitfld.long 0x0 10. "TXCFG,Transmit Flag Configuration" "0: MSR[TDF] is set only during a target-transmit..,1: MSR[TDF] is set whenever STDR is empty" bitfld.long 0x0 9. "SAEN,SMBus Alert Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 8. "GCEN,General Call Enable" "0: Disable,1: Enable" bitfld.long 0x0 3. "ACKSTALL,ACK SCL Stall" "0: Disable,1: Enable" newline bitfld.long 0x0 2. "TXDSTALL,Transmit Data SCL Stall" "0: Disable,1: Enable" bitfld.long 0x0 1. "RXSTALL,RX SCL Stall" "0: Disable,1: Enable" newline bitfld.long 0x0 0. "ADRSTALL,Address SCL Stall" "0: Disable,1: Enable" line.long 0x4 "SCFGR2,Target Configuration 2" hexmask.long.byte 0x4 24.--27. 1. "FILTSDA,Glitch Filter SDA" hexmask.long.byte 0x4 16.--19. 1. "FILTSCL,Glitch Filter SCL" newline hexmask.long.byte 0x4 8.--13. 1. "DATAVD,Data Valid Delay" hexmask.long.byte 0x4 0.--3. 1. "CLKHOLD,Clock Hold Time" group.long 0x140++0x3 line.long 0x0 "SAMR,Target Address Match" hexmask.long.word 0x0 17.--26. 1. "ADDR1,Address 1 Value" hexmask.long.word 0x0 1.--10. 1. "ADDR0,Address 0 Value" rgroup.long 0x150++0x3 line.long 0x0 "SASR,Target Address Status" bitfld.long 0x0 14. "ANV,Address Not Valid" "0: Valid,1: Not valid" hexmask.long.word 0x0 0.--10. 1. "RADDR,Received Address" group.long 0x154++0x3 line.long 0x0 "STAR,Target Transmit ACK" bitfld.long 0x0 0. "TXNACK,Transmit NACK" "0: Transmit ACK,1: Transmit NACK" wgroup.long 0x160++0x3 line.long 0x0 "STDR,Target Transmit Data" hexmask.long.byte 0x0 0.--7. 1. "DATA,Transmit Data" rgroup.long 0x170++0x3 line.long 0x0 "SRDR,Target Receive Data" bitfld.long 0x0 15. "SOF,Start of Frame" "0: Not first,1: First" bitfld.long 0x0 14. "RXEMPTY,Receive Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 8.--10. "RADDR,Received Address" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data" tree.end tree.end tree "LPSPI (Low Power Serial Peripheral Interface)" base ad:0x0 tree "LPSPI_0" base ad:0x40358000 rgroup.long 0x0++0x7 line.long 0x0 "VERID,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Module Identification Number" line.long 0x4 "PARAM,Parameter" hexmask.long.byte 0x4 16.--23. 1. "PCSNUM,PCS Number" hexmask.long.byte 0x4 8.--15. 1. "RXFIFO,Receive FIFO Size" newline hexmask.long.byte 0x4 0.--7. 1. "TXFIFO,Transmit FIFO Size" group.long 0x10++0x17 line.long 0x0 "CR,Control" bitfld.long 0x0 9. "RRF,Reset Receive FIFO" "0: No effect,1: Reset" bitfld.long 0x0 8. "RTF,Reset Transmit FIFO" "0: No effect,1: Reset" newline bitfld.long 0x0 3. "DBGEN,Debug Enable" "0: Disable,1: Enable" bitfld.long 0x0 1. "RST,Software Reset" "0: Not reset,1: Reset" newline bitfld.long 0x0 0. "MEN,Module Enable" "0: Disable,1: Enable" line.long 0x4 "SR,Status" rbitfld.long 0x4 24. "MBF,Module Busy Flag" "0: LPSPI is idle,1: LPSPI is busy" eventfld.long 0x4 13. "DMF,Data Match Flag" "0: No match,1: Match" newline eventfld.long 0x4 12. "REF,Receive Error Flag" "0: No overflow,1: Overflow" eventfld.long 0x4 11. "TEF,Transmit Error Flag" "0: No underrun,1: Underrun" newline eventfld.long 0x4 10. "TCF,Transfer Complete Flag" "0: Not complete,1: Complete" eventfld.long 0x4 9. "FCF,Frame Complete Flag" "0: Not complete,1: Complete" newline eventfld.long 0x4 8. "WCF,Word Complete Flag" "0: Not complete,1: Complete" rbitfld.long 0x4 1. "RDF,Receive Data Flag" "0: Receive data not ready,1: Receive data is ready" newline rbitfld.long 0x4 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested" line.long 0x8 "IER,Interrupt Enable" bitfld.long 0x8 13. "DMIE,Data Match Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 12. "REIE,Receive Error Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x8 11. "TEIE,Transmit Error Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 10. "TCIE,Transfer Complete Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x8 9. "FCIE,Frame Complete Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 8. "WCIE,Word Complete Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x8 1. "RDIE,Receive Data Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 0. "TDIE,Transmit Data Interrupt Enable" "0: Disable,1: Enable" line.long 0xC "DER,DMA Enable" bitfld.long 0xC 1. "RDDE,Receive Data DMA Enable" "0: Disable,1: Enable" bitfld.long 0xC 0. "TDDE,Transmit Data DMA Enable" "0: Disable,1: Enable" line.long 0x10 "CFGR0,Configuration 0" bitfld.long 0x10 9. "RDMO,Receive Data Match Only" "0: Disable,1: Enable" bitfld.long 0x10 8. "CIRFIFO,Circular FIFO Enable" "0: Disable,1: Enable" newline bitfld.long 0x10 3. "HRDIR,Host Request Direction" "0: Input,1: Output" bitfld.long 0x10 2. "HRSEL,Host Request Select" "0: HREQ pin,1: Input trigger" newline bitfld.long 0x10 1. "HRPOL,Host Request Polarity" "0: Active high,1: Active low" bitfld.long 0x10 0. "HREN,Host Request Enable" "0: Disable,1: Enable" line.long 0x14 "CFGR1,Configuration 1" bitfld.long 0x14 27.--28. "PCSCFG,Peripheral Chip Select Configuration" "0: PCS[7:2] are configured for chip select function,1: PCS[3:2] are configured for half-duplex 4-bit..,?,3: PCS[7:2] are configured for half-duplex 4-bit.." bitfld.long 0x14 26. "OUTCFG,Output Configuration" "0: Output data retains last value.,1: Output data is 3-stated." newline bitfld.long 0x14 24.--25. "PINCFG,Pin Configuration" "0: SIN is used for input data; SOUT is used for..,1: SIN is used for both input and output data. Only..,2: SOUT is used for both input and output data.,3: SOUT is used for input data; SIN is used for.." bitfld.long 0x14 16.--18. "MATCFG,Match Configuration" "0: Match is disabled,?,2: Match first data word with compare word,3: Match any data word with compare word,4: Sequential match first data word,5: Sequential match any data word,6: Match first data word (masked) with compare word..,7: Match any data word (masked) with compare word.." newline hexmask.long.byte 0x14 8.--15. 1. "PCSPOL,Peripheral Chip Select Polarity" bitfld.long 0x14 4. "PARTIAL,Partial Enable" "0: Discard,1: Store" newline bitfld.long 0x14 3. "NOSTALL,No Stall" "0: Disable,1: Enable" bitfld.long 0x14 2. "AUTOPCS,Automatic PCS" "0: Disable,1: Enable" newline bitfld.long 0x14 1. "SAMPLE,Sample Point" "0: SCK edge,1: Delayed SCK edge" bitfld.long 0x14 0. "MASTER,Master Mode" "0: Slave mode,1: Master mode" group.long 0x30++0x7 line.long 0x0 "DMR0,Data Match 0" hexmask.long 0x0 0.--31. 1. "MATCH0,Match 0 Value" line.long 0x4 "DMR1,Data Match 1" hexmask.long 0x4 0.--31. 1. "MATCH1,Match 1 Value" group.long 0x40++0x7 line.long 0x0 "CCR,Clock Configuration" hexmask.long.byte 0x0 24.--31. 1. "SCKPCS,SCK-to-PCS Delay" hexmask.long.byte 0x0 16.--23. 1. "PCSSCK,PCS-to-SCK Delay" newline hexmask.long.byte 0x0 8.--15. 1. "DBT,Delay Between Transfers" hexmask.long.byte 0x0 0.--7. 1. "SCKDIV,SCK Divider" line.long 0x4 "CCR1,Clock Configuration 1" hexmask.long.byte 0x4 24.--31. 1. "SCKSCK,SCK Inter-Frame Delay" hexmask.long.byte 0x4 16.--23. 1. "PCSPCS,PCS to PCS delay" newline hexmask.long.byte 0x4 8.--15. 1. "SCKHLD,SCK Hold" hexmask.long.byte 0x4 0.--7. 1. "SCKSET,SCK Setup" group.long 0x58++0x3 line.long 0x0 "FCR,FIFO Control" bitfld.long 0x0 16.--17. "RXWATER,Receive FIFO Watermark" "0,1,2,3" bitfld.long 0x0 0.--1. "TXWATER,Transmit FIFO Watermark" "0,1,2,3" rgroup.long 0x5C++0x3 line.long 0x0 "FSR,FIFO Status" bitfld.long 0x0 16.--18. "RXCOUNT,Receive FIFO Count" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "TXCOUNT,Transmit FIFO Count" "0,1,2,3,4,5,6,7" group.long 0x60++0x3 line.long 0x0 "TCR,Transmit Command" bitfld.long 0x0 31. "CPOL,Clock Polarity" "0: Inactive low,1: Inactive high" bitfld.long 0x0 30. "CPHA,Clock Phase" "0: Captured,1: Changed" newline bitfld.long 0x0 27.--29. "PRESCALE,Prescaler Value" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128" bitfld.long 0x0 24.--26. "PCS,Peripheral Chip Select" "0: Transfer using PCS[0],1: Transfer using PCS[1],2: Transfer using PCS[2],3: Transfer using PCS[3],4: Transfer using PCS[4],5: Transfer using PCS[5],6: Transfer using PCS[6],7: Transfer using PCS[7]" newline bitfld.long 0x0 23. "LSBF,LSB First" "0: Data is transferred MSB first,1: Data is transferred LSB first" bitfld.long 0x0 22. "BYSW,Byte Swap" "0: Disabled,1: Enabled" newline bitfld.long 0x0 21. "CONT,Continuous Transfer" "0: Continuous transfer is disabled,1: Continuous transfer is enabled" bitfld.long 0x0 20. "CONTC,Continuing Command" "0: Command word for start of new transfer,1: Command word for continuing transfer" newline bitfld.long 0x0 19. "RXMSK,Receive Data Mask" "0: Normal transfer,1: Receive data is masked" bitfld.long 0x0 18. "TXMSK,Transmit Data Mask" "0: Normal transfer,1: Mask transmit data" newline bitfld.long 0x0 16.--17. "WIDTH,Transfer Width" "0: 1-bit transfer,1: 2-bit transfer,2: 4-bit transfer,3: 8-bit transfer" hexmask.long.word 0x0 0.--11. 1. "FRAMESZ,Frame Size" wgroup.long 0x64++0x3 line.long 0x0 "TDR,Transmit Data" hexmask.long 0x0 0.--31. 1. "DATA,Transmit Data" rgroup.long 0x70++0xB line.long 0x0 "RSR,Receive Status" bitfld.long 0x0 1. "RXEMPTY,RX FIFO Empty" "0: Not empty,1: Empty" bitfld.long 0x0 0. "SOF,Start Of Frame" "0: Subsequent data word,1: First data word" line.long 0x4 "RDR,Receive Data" hexmask.long 0x4 0.--31. 1. "DATA,Receive Data" line.long 0x8 "RDROR,Receive Data Read Only" hexmask.long 0x8 0.--31. 1. "DATA,Receive Data" wgroup.long 0x3FC++0x3 line.long 0x0 "TCBR,Transmit Command Burst" hexmask.long 0x0 0.--31. 1. "DATA,Command Data" repeat 128. (increment 0x0 0x1)(increment 0x0 0x4) wgroup.long ($2+0x400)++0x3 line.long 0x0 "TDBR[$1],Transmit Data Burst" hexmask.long 0x0 0.--31. 1. "DATA,Data" repeat.end repeat 128. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x600)++0x3 line.long 0x0 "RDBR[$1],Receive Data Burst" hexmask.long 0x0 0.--31. 1. "DATA,Data" repeat.end tree.end tree "LPSPI_1" base ad:0x4035C000 rgroup.long 0x0++0x7 line.long 0x0 "VERID,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Module Identification Number" line.long 0x4 "PARAM,Parameter" hexmask.long.byte 0x4 16.--23. 1. "PCSNUM,PCS Number" hexmask.long.byte 0x4 8.--15. 1. "RXFIFO,Receive FIFO Size" newline hexmask.long.byte 0x4 0.--7. 1. "TXFIFO,Transmit FIFO Size" group.long 0x10++0x17 line.long 0x0 "CR,Control" bitfld.long 0x0 9. "RRF,Reset Receive FIFO" "0: No effect,1: Reset" bitfld.long 0x0 8. "RTF,Reset Transmit FIFO" "0: No effect,1: Reset" newline bitfld.long 0x0 3. "DBGEN,Debug Enable" "0: Disable,1: Enable" bitfld.long 0x0 1. "RST,Software Reset" "0: Not reset,1: Reset" newline bitfld.long 0x0 0. "MEN,Module Enable" "0: Disable,1: Enable" line.long 0x4 "SR,Status" rbitfld.long 0x4 24. "MBF,Module Busy Flag" "0: LPSPI is idle,1: LPSPI is busy" eventfld.long 0x4 13. "DMF,Data Match Flag" "0: No match,1: Match" newline eventfld.long 0x4 12. "REF,Receive Error Flag" "0: No overflow,1: Overflow" eventfld.long 0x4 11. "TEF,Transmit Error Flag" "0: No underrun,1: Underrun" newline eventfld.long 0x4 10. "TCF,Transfer Complete Flag" "0: Not complete,1: Complete" eventfld.long 0x4 9. "FCF,Frame Complete Flag" "0: Not complete,1: Complete" newline eventfld.long 0x4 8. "WCF,Word Complete Flag" "0: Not complete,1: Complete" rbitfld.long 0x4 1. "RDF,Receive Data Flag" "0: Receive data not ready,1: Receive data is ready" newline rbitfld.long 0x4 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested" line.long 0x8 "IER,Interrupt Enable" bitfld.long 0x8 13. "DMIE,Data Match Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 12. "REIE,Receive Error Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x8 11. "TEIE,Transmit Error Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 10. "TCIE,Transfer Complete Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x8 9. "FCIE,Frame Complete Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 8. "WCIE,Word Complete Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x8 1. "RDIE,Receive Data Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 0. "TDIE,Transmit Data Interrupt Enable" "0: Disable,1: Enable" line.long 0xC "DER,DMA Enable" bitfld.long 0xC 1. "RDDE,Receive Data DMA Enable" "0: Disable,1: Enable" bitfld.long 0xC 0. "TDDE,Transmit Data DMA Enable" "0: Disable,1: Enable" line.long 0x10 "CFGR0,Configuration 0" bitfld.long 0x10 9. "RDMO,Receive Data Match Only" "0: Disable,1: Enable" bitfld.long 0x10 8. "CIRFIFO,Circular FIFO Enable" "0: Disable,1: Enable" newline bitfld.long 0x10 3. "HRDIR,Host Request Direction" "0: Input,1: Output" bitfld.long 0x10 2. "HRSEL,Host Request Select" "0: HREQ pin,1: Input trigger" newline bitfld.long 0x10 1. "HRPOL,Host Request Polarity" "0: Active high,1: Active low" bitfld.long 0x10 0. "HREN,Host Request Enable" "0: Disable,1: Enable" line.long 0x14 "CFGR1,Configuration 1" bitfld.long 0x14 27. "PCSCFG,Peripheral Chip Select Configuration" "0: PCS[5:2] are configured for chip select function,1: PCS[3:2] are configured for half-duplex 4-bit.." bitfld.long 0x14 26. "OUTCFG,Output Configuration" "0: Output data retains last value.,1: Output data is 3-stated." newline bitfld.long 0x14 24.--25. "PINCFG,Pin Configuration" "0: SIN is used for input data; SOUT is used for..,1: SIN is used for both input and output data. Only..,2: SOUT is used for both input and output data.,3: SOUT is used for input data; SIN is used for.." bitfld.long 0x14 16.--18. "MATCFG,Match Configuration" "0: Match is disabled,?,2: Match first data word with compare word,3: Match any data word with compare word,4: Sequential match first data word,5: Sequential match any data word,6: Match first data word (masked) with compare word..,7: Match any data word (masked) with compare word.." newline hexmask.long.byte 0x14 8.--13. 1. "PCSPOL,Peripheral Chip Select Polarity" bitfld.long 0x14 4. "PARTIAL,Partial Enable" "0: Discard,1: Store" newline bitfld.long 0x14 3. "NOSTALL,No Stall" "0: Disable,1: Enable" bitfld.long 0x14 2. "AUTOPCS,Automatic PCS" "0: Disable,1: Enable" newline bitfld.long 0x14 1. "SAMPLE,Sample Point" "0: SCK edge,1: Delayed SCK edge" bitfld.long 0x14 0. "MASTER,Master Mode" "0: Slave mode,1: Master mode" group.long 0x30++0x7 line.long 0x0 "DMR0,Data Match 0" hexmask.long 0x0 0.--31. 1. "MATCH0,Match 0 Value" line.long 0x4 "DMR1,Data Match 1" hexmask.long 0x4 0.--31. 1. "MATCH1,Match 1 Value" group.long 0x40++0x7 line.long 0x0 "CCR,Clock Configuration" hexmask.long.byte 0x0 24.--31. 1. "SCKPCS,SCK-to-PCS Delay" hexmask.long.byte 0x0 16.--23. 1. "PCSSCK,PCS-to-SCK Delay" newline hexmask.long.byte 0x0 8.--15. 1. "DBT,Delay Between Transfers" hexmask.long.byte 0x0 0.--7. 1. "SCKDIV,SCK Divider" line.long 0x4 "CCR1,Clock Configuration 1" hexmask.long.byte 0x4 24.--31. 1. "SCKSCK,SCK Inter-Frame Delay" hexmask.long.byte 0x4 16.--23. 1. "PCSPCS,PCS to PCS delay" newline hexmask.long.byte 0x4 8.--15. 1. "SCKHLD,SCK Hold" hexmask.long.byte 0x4 0.--7. 1. "SCKSET,SCK Setup" group.long 0x58++0x3 line.long 0x0 "FCR,FIFO Control" bitfld.long 0x0 16.--17. "RXWATER,Receive FIFO Watermark" "0,1,2,3" bitfld.long 0x0 0.--1. "TXWATER,Transmit FIFO Watermark" "0,1,2,3" rgroup.long 0x5C++0x3 line.long 0x0 "FSR,FIFO Status" bitfld.long 0x0 16.--18. "RXCOUNT,Receive FIFO Count" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "TXCOUNT,Transmit FIFO Count" "0,1,2,3,4,5,6,7" group.long 0x60++0x3 line.long 0x0 "TCR,Transmit Command" bitfld.long 0x0 31. "CPOL,Clock Polarity" "0: Inactive low,1: Inactive high" bitfld.long 0x0 30. "CPHA,Clock Phase" "0: Captured,1: Changed" newline bitfld.long 0x0 27.--29. "PRESCALE,Prescaler Value" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128" bitfld.long 0x0 24.--26. "PCS,Peripheral Chip Select" "0: Transfer using PCS[0],1: Transfer using PCS[1],2: Transfer using PCS[2],3: Transfer using PCS[3],4: Transfer using PCS[4],5: Transfer using PCS[5],?,?" newline bitfld.long 0x0 23. "LSBF,LSB First" "0: Data is transferred MSB first,1: Data is transferred LSB first" bitfld.long 0x0 22. "BYSW,Byte Swap" "0: Disabled,1: Enabled" newline bitfld.long 0x0 21. "CONT,Continuous Transfer" "0: Continuous transfer is disabled,1: Continuous transfer is enabled" bitfld.long 0x0 20. "CONTC,Continuing Command" "0: Command word for start of new transfer,1: Command word for continuing transfer" newline bitfld.long 0x0 19. "RXMSK,Receive Data Mask" "0: Normal transfer,1: Receive data is masked" bitfld.long 0x0 18. "TXMSK,Transmit Data Mask" "0: Normal transfer,1: Mask transmit data" newline bitfld.long 0x0 16.--17. "WIDTH,Transfer Width" "0: 1-bit transfer,1: 2-bit transfer,2: 4-bit transfer,?" hexmask.long.word 0x0 0.--11. 1. "FRAMESZ,Frame Size" wgroup.long 0x64++0x3 line.long 0x0 "TDR,Transmit Data" hexmask.long 0x0 0.--31. 1. "DATA,Transmit Data" rgroup.long 0x70++0xB line.long 0x0 "RSR,Receive Status" bitfld.long 0x0 1. "RXEMPTY,RX FIFO Empty" "0: Not empty,1: Empty" bitfld.long 0x0 0. "SOF,Start Of Frame" "0: Subsequent data word,1: First data word" line.long 0x4 "RDR,Receive Data" hexmask.long 0x4 0.--31. 1. "DATA,Receive Data" line.long 0x8 "RDROR,Receive Data Read Only" hexmask.long 0x8 0.--31. 1. "DATA,Receive Data" wgroup.long 0x3FC++0x3 line.long 0x0 "TCBR,Transmit Command Burst" hexmask.long 0x0 0.--31. 1. "DATA,Command Data" repeat 128. (increment 0x0 0x1)(increment 0x0 0x4) wgroup.long ($2+0x400)++0x3 line.long 0x0 "TDBR[$1],Transmit Data Burst" hexmask.long 0x0 0.--31. 1. "DATA,Data" repeat.end repeat 128. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x600)++0x3 line.long 0x0 "RDBR[$1],Receive Data Burst" hexmask.long 0x0 0.--31. 1. "DATA,Data" repeat.end tree.end tree "LPSPI_2" base ad:0x40360000 rgroup.long 0x0++0x7 line.long 0x0 "VERID,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Module Identification Number" line.long 0x4 "PARAM,Parameter" hexmask.long.byte 0x4 16.--23. 1. "PCSNUM,PCS Number" hexmask.long.byte 0x4 8.--15. 1. "RXFIFO,Receive FIFO Size" newline hexmask.long.byte 0x4 0.--7. 1. "TXFIFO,Transmit FIFO Size" group.long 0x10++0x17 line.long 0x0 "CR,Control" bitfld.long 0x0 9. "RRF,Reset Receive FIFO" "0: No effect,1: Reset" bitfld.long 0x0 8. "RTF,Reset Transmit FIFO" "0: No effect,1: Reset" newline bitfld.long 0x0 3. "DBGEN,Debug Enable" "0: Disable,1: Enable" bitfld.long 0x0 1. "RST,Software Reset" "0: Not reset,1: Reset" newline bitfld.long 0x0 0. "MEN,Module Enable" "0: Disable,1: Enable" line.long 0x4 "SR,Status" rbitfld.long 0x4 24. "MBF,Module Busy Flag" "0: LPSPI is idle,1: LPSPI is busy" eventfld.long 0x4 13. "DMF,Data Match Flag" "0: No match,1: Match" newline eventfld.long 0x4 12. "REF,Receive Error Flag" "0: No overflow,1: Overflow" eventfld.long 0x4 11. "TEF,Transmit Error Flag" "0: No underrun,1: Underrun" newline eventfld.long 0x4 10. "TCF,Transfer Complete Flag" "0: Not complete,1: Complete" eventfld.long 0x4 9. "FCF,Frame Complete Flag" "0: Not complete,1: Complete" newline eventfld.long 0x4 8. "WCF,Word Complete Flag" "0: Not complete,1: Complete" rbitfld.long 0x4 1. "RDF,Receive Data Flag" "0: Receive data not ready,1: Receive data is ready" newline rbitfld.long 0x4 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested" line.long 0x8 "IER,Interrupt Enable" bitfld.long 0x8 13. "DMIE,Data Match Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 12. "REIE,Receive Error Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x8 11. "TEIE,Transmit Error Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 10. "TCIE,Transfer Complete Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x8 9. "FCIE,Frame Complete Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 8. "WCIE,Word Complete Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x8 1. "RDIE,Receive Data Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 0. "TDIE,Transmit Data Interrupt Enable" "0: Disable,1: Enable" line.long 0xC "DER,DMA Enable" bitfld.long 0xC 1. "RDDE,Receive Data DMA Enable" "0: Disable,1: Enable" bitfld.long 0xC 0. "TDDE,Transmit Data DMA Enable" "0: Disable,1: Enable" line.long 0x10 "CFGR0,Configuration 0" bitfld.long 0x10 9. "RDMO,Receive Data Match Only" "0: Disable,1: Enable" bitfld.long 0x10 8. "CIRFIFO,Circular FIFO Enable" "0: Disable,1: Enable" newline bitfld.long 0x10 3. "HRDIR,Host Request Direction" "0: Input,1: Output" bitfld.long 0x10 2. "HRSEL,Host Request Select" "0: HREQ pin,1: Input trigger" newline bitfld.long 0x10 1. "HRPOL,Host Request Polarity" "0: Active high,1: Active low" bitfld.long 0x10 0. "HREN,Host Request Enable" "0: Disable,1: Enable" line.long 0x14 "CFGR1,Configuration 1" bitfld.long 0x14 27. "PCSCFG,Peripheral Chip Select Configuration" "0: PCS[3:2] are configured for chip select function,1: PCS[3:2] are configured for half-duplex 4-bit.." bitfld.long 0x14 26. "OUTCFG,Output Configuration" "0: Output data retains last value.,1: Output data is 3-stated." newline bitfld.long 0x14 24.--25. "PINCFG,Pin Configuration" "0: SIN is used for input data; SOUT is used for..,1: SIN is used for both input and output data. Only..,2: SOUT is used for both input and output data.,3: SOUT is used for input data; SIN is used for.." bitfld.long 0x14 16.--18. "MATCFG,Match Configuration" "0: Match is disabled,?,2: Match first data word with compare word,3: Match any data word with compare word,4: Sequential match first data word,5: Sequential match any data word,6: Match first data word (masked) with compare word..,7: Match any data word (masked) with compare word.." newline hexmask.long.byte 0x14 8.--11. 1. "PCSPOL,Peripheral Chip Select Polarity" bitfld.long 0x14 4. "PARTIAL,Partial Enable" "0: Discard,1: Store" newline bitfld.long 0x14 3. "NOSTALL,No Stall" "0: Disable,1: Enable" bitfld.long 0x14 2. "AUTOPCS,Automatic PCS" "0: Disable,1: Enable" newline bitfld.long 0x14 1. "SAMPLE,Sample Point" "0: SCK edge,1: Delayed SCK edge" bitfld.long 0x14 0. "MASTER,Master Mode" "0: Slave mode,1: Master mode" group.long 0x30++0x7 line.long 0x0 "DMR0,Data Match 0" hexmask.long 0x0 0.--31. 1. "MATCH0,Match 0 Value" line.long 0x4 "DMR1,Data Match 1" hexmask.long 0x4 0.--31. 1. "MATCH1,Match 1 Value" group.long 0x40++0x7 line.long 0x0 "CCR,Clock Configuration" hexmask.long.byte 0x0 24.--31. 1. "SCKPCS,SCK-to-PCS Delay" hexmask.long.byte 0x0 16.--23. 1. "PCSSCK,PCS-to-SCK Delay" newline hexmask.long.byte 0x0 8.--15. 1. "DBT,Delay Between Transfers" hexmask.long.byte 0x0 0.--7. 1. "SCKDIV,SCK Divider" line.long 0x4 "CCR1,Clock Configuration 1" hexmask.long.byte 0x4 24.--31. 1. "SCKSCK,SCK Inter-Frame Delay" hexmask.long.byte 0x4 16.--23. 1. "PCSPCS,PCS to PCS delay" newline hexmask.long.byte 0x4 8.--15. 1. "SCKHLD,SCK Hold" hexmask.long.byte 0x4 0.--7. 1. "SCKSET,SCK Setup" group.long 0x58++0x3 line.long 0x0 "FCR,FIFO Control" bitfld.long 0x0 16.--17. "RXWATER,Receive FIFO Watermark" "0,1,2,3" bitfld.long 0x0 0.--1. "TXWATER,Transmit FIFO Watermark" "0,1,2,3" rgroup.long 0x5C++0x3 line.long 0x0 "FSR,FIFO Status" bitfld.long 0x0 16.--18. "RXCOUNT,Receive FIFO Count" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "TXCOUNT,Transmit FIFO Count" "0,1,2,3,4,5,6,7" group.long 0x60++0x3 line.long 0x0 "TCR,Transmit Command" bitfld.long 0x0 31. "CPOL,Clock Polarity" "0: Inactive low,1: Inactive high" bitfld.long 0x0 30. "CPHA,Clock Phase" "0: Captured,1: Changed" newline bitfld.long 0x0 27.--29. "PRESCALE,Prescaler Value" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128" bitfld.long 0x0 24.--25. "PCS,Peripheral Chip Select" "0: Transfer using PCS[0],1: Transfer using PCS[1],2: Transfer using PCS[2],3: Transfer using PCS[3]" newline bitfld.long 0x0 23. "LSBF,LSB First" "0: Data is transferred MSB first,1: Data is transferred LSB first" bitfld.long 0x0 22. "BYSW,Byte Swap" "0: Disabled,1: Enabled" newline bitfld.long 0x0 21. "CONT,Continuous Transfer" "0: Continuous transfer is disabled,1: Continuous transfer is enabled" bitfld.long 0x0 20. "CONTC,Continuing Command" "0: Command word for start of new transfer,1: Command word for continuing transfer" newline bitfld.long 0x0 19. "RXMSK,Receive Data Mask" "0: Normal transfer,1: Receive data is masked" bitfld.long 0x0 18. "TXMSK,Transmit Data Mask" "0: Normal transfer,1: Mask transmit data" newline bitfld.long 0x0 16.--17. "WIDTH,Transfer Width" "0: 1-bit transfer,1: 2-bit transfer,2: 4-bit transfer,?" hexmask.long.word 0x0 0.--11. 1. "FRAMESZ,Frame Size" wgroup.long 0x64++0x3 line.long 0x0 "TDR,Transmit Data" hexmask.long 0x0 0.--31. 1. "DATA,Transmit Data" rgroup.long 0x70++0xB line.long 0x0 "RSR,Receive Status" bitfld.long 0x0 1. "RXEMPTY,RX FIFO Empty" "0: Not empty,1: Empty" bitfld.long 0x0 0. "SOF,Start Of Frame" "0: Subsequent data word,1: First data word" line.long 0x4 "RDR,Receive Data" hexmask.long 0x4 0.--31. 1. "DATA,Receive Data" line.long 0x8 "RDROR,Receive Data Read Only" hexmask.long 0x8 0.--31. 1. "DATA,Receive Data" wgroup.long 0x3FC++0x3 line.long 0x0 "TCBR,Transmit Command Burst" hexmask.long 0x0 0.--31. 1. "DATA,Command Data" repeat 128. (increment 0x0 0x1)(increment 0x0 0x4) wgroup.long ($2+0x400)++0x3 line.long 0x0 "TDBR[$1],Transmit Data Burst" hexmask.long 0x0 0.--31. 1. "DATA,Data" repeat.end repeat 128. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x600)++0x3 line.long 0x0 "RDBR[$1],Receive Data Burst" hexmask.long 0x0 0.--31. 1. "DATA,Data" repeat.end tree.end tree "LPSPI_3" base ad:0x40364000 rgroup.long 0x0++0x7 line.long 0x0 "VERID,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Module Identification Number" line.long 0x4 "PARAM,Parameter" hexmask.long.byte 0x4 16.--23. 1. "PCSNUM,PCS Number" hexmask.long.byte 0x4 8.--15. 1. "RXFIFO,Receive FIFO Size" newline hexmask.long.byte 0x4 0.--7. 1. "TXFIFO,Transmit FIFO Size" group.long 0x10++0x17 line.long 0x0 "CR,Control" bitfld.long 0x0 9. "RRF,Reset Receive FIFO" "0: No effect,1: Reset" bitfld.long 0x0 8. "RTF,Reset Transmit FIFO" "0: No effect,1: Reset" newline bitfld.long 0x0 3. "DBGEN,Debug Enable" "0: Disable,1: Enable" bitfld.long 0x0 1. "RST,Software Reset" "0: Not reset,1: Reset" newline bitfld.long 0x0 0. "MEN,Module Enable" "0: Disable,1: Enable" line.long 0x4 "SR,Status" rbitfld.long 0x4 24. "MBF,Module Busy Flag" "0: LPSPI is idle,1: LPSPI is busy" eventfld.long 0x4 13. "DMF,Data Match Flag" "0: No match,1: Match" newline eventfld.long 0x4 12. "REF,Receive Error Flag" "0: No overflow,1: Overflow" eventfld.long 0x4 11. "TEF,Transmit Error Flag" "0: No underrun,1: Underrun" newline eventfld.long 0x4 10. "TCF,Transfer Complete Flag" "0: Not complete,1: Complete" eventfld.long 0x4 9. "FCF,Frame Complete Flag" "0: Not complete,1: Complete" newline eventfld.long 0x4 8. "WCF,Word Complete Flag" "0: Not complete,1: Complete" rbitfld.long 0x4 1. "RDF,Receive Data Flag" "0: Receive data not ready,1: Receive data is ready" newline rbitfld.long 0x4 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested" line.long 0x8 "IER,Interrupt Enable" bitfld.long 0x8 13. "DMIE,Data Match Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 12. "REIE,Receive Error Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x8 11. "TEIE,Transmit Error Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 10. "TCIE,Transfer Complete Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x8 9. "FCIE,Frame Complete Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 8. "WCIE,Word Complete Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x8 1. "RDIE,Receive Data Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 0. "TDIE,Transmit Data Interrupt Enable" "0: Disable,1: Enable" line.long 0xC "DER,DMA Enable" bitfld.long 0xC 1. "RDDE,Receive Data DMA Enable" "0: Disable,1: Enable" bitfld.long 0xC 0. "TDDE,Transmit Data DMA Enable" "0: Disable,1: Enable" line.long 0x10 "CFGR0,Configuration 0" bitfld.long 0x10 9. "RDMO,Receive Data Match Only" "0: Disable,1: Enable" bitfld.long 0x10 8. "CIRFIFO,Circular FIFO Enable" "0: Disable,1: Enable" newline bitfld.long 0x10 3. "HRDIR,Host Request Direction" "0: Input,1: Output" bitfld.long 0x10 2. "HRSEL,Host Request Select" "0: HREQ pin,1: Input trigger" newline bitfld.long 0x10 1. "HRPOL,Host Request Polarity" "0: Active high,1: Active low" bitfld.long 0x10 0. "HREN,Host Request Enable" "0: Disable,1: Enable" line.long 0x14 "CFGR1,Configuration 1" bitfld.long 0x14 27. "PCSCFG,Peripheral Chip Select Configuration" "0: PCS[3:2] are configured for chip select function,1: PCS[3:2] are configured for half-duplex 4-bit.." bitfld.long 0x14 26. "OUTCFG,Output Configuration" "0: Output data retains last value.,1: Output data is 3-stated." newline bitfld.long 0x14 24.--25. "PINCFG,Pin Configuration" "0: SIN is used for input data; SOUT is used for..,1: SIN is used for both input and output data. Only..,2: SOUT is used for both input and output data.,3: SOUT is used for input data; SIN is used for.." bitfld.long 0x14 16.--18. "MATCFG,Match Configuration" "0: Match is disabled,?,2: Match first data word with compare word,3: Match any data word with compare word,4: Sequential match first data word,5: Sequential match any data word,6: Match first data word (masked) with compare word..,7: Match any data word (masked) with compare word.." newline hexmask.long.byte 0x14 8.--11. 1. "PCSPOL,Peripheral Chip Select Polarity" bitfld.long 0x14 4. "PARTIAL,Partial Enable" "0: Discard,1: Store" newline bitfld.long 0x14 3. "NOSTALL,No Stall" "0: Disable,1: Enable" bitfld.long 0x14 2. "AUTOPCS,Automatic PCS" "0: Disable,1: Enable" newline bitfld.long 0x14 1. "SAMPLE,Sample Point" "0: SCK edge,1: Delayed SCK edge" bitfld.long 0x14 0. "MASTER,Master Mode" "0: Slave mode,1: Master mode" group.long 0x30++0x7 line.long 0x0 "DMR0,Data Match 0" hexmask.long 0x0 0.--31. 1. "MATCH0,Match 0 Value" line.long 0x4 "DMR1,Data Match 1" hexmask.long 0x4 0.--31. 1. "MATCH1,Match 1 Value" group.long 0x40++0x7 line.long 0x0 "CCR,Clock Configuration" hexmask.long.byte 0x0 24.--31. 1. "SCKPCS,SCK-to-PCS Delay" hexmask.long.byte 0x0 16.--23. 1. "PCSSCK,PCS-to-SCK Delay" newline hexmask.long.byte 0x0 8.--15. 1. "DBT,Delay Between Transfers" hexmask.long.byte 0x0 0.--7. 1. "SCKDIV,SCK Divider" line.long 0x4 "CCR1,Clock Configuration 1" hexmask.long.byte 0x4 24.--31. 1. "SCKSCK,SCK Inter-Frame Delay" hexmask.long.byte 0x4 16.--23. 1. "PCSPCS,PCS to PCS delay" newline hexmask.long.byte 0x4 8.--15. 1. "SCKHLD,SCK Hold" hexmask.long.byte 0x4 0.--7. 1. "SCKSET,SCK Setup" group.long 0x58++0x3 line.long 0x0 "FCR,FIFO Control" bitfld.long 0x0 16.--17. "RXWATER,Receive FIFO Watermark" "0,1,2,3" bitfld.long 0x0 0.--1. "TXWATER,Transmit FIFO Watermark" "0,1,2,3" rgroup.long 0x5C++0x3 line.long 0x0 "FSR,FIFO Status" bitfld.long 0x0 16.--18. "RXCOUNT,Receive FIFO Count" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "TXCOUNT,Transmit FIFO Count" "0,1,2,3,4,5,6,7" group.long 0x60++0x3 line.long 0x0 "TCR,Transmit Command" bitfld.long 0x0 31. "CPOL,Clock Polarity" "0: Inactive low,1: Inactive high" bitfld.long 0x0 30. "CPHA,Clock Phase" "0: Captured,1: Changed" newline bitfld.long 0x0 27.--29. "PRESCALE,Prescaler Value" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128" bitfld.long 0x0 24.--25. "PCS,Peripheral Chip Select" "0: Transfer using PCS[0],1: Transfer using PCS[1],2: Transfer using PCS[2],3: Transfer using PCS[3]" newline bitfld.long 0x0 23. "LSBF,LSB First" "0: Data is transferred MSB first,1: Data is transferred LSB first" bitfld.long 0x0 22. "BYSW,Byte Swap" "0: Disabled,1: Enabled" newline bitfld.long 0x0 21. "CONT,Continuous Transfer" "0: Continuous transfer is disabled,1: Continuous transfer is enabled" bitfld.long 0x0 20. "CONTC,Continuing Command" "0: Command word for start of new transfer,1: Command word for continuing transfer" newline bitfld.long 0x0 19. "RXMSK,Receive Data Mask" "0: Normal transfer,1: Receive data is masked" bitfld.long 0x0 18. "TXMSK,Transmit Data Mask" "0: Normal transfer,1: Mask transmit data" newline bitfld.long 0x0 16.--17. "WIDTH,Transfer Width" "0: 1-bit transfer,1: 2-bit transfer,2: 4-bit transfer,?" hexmask.long.word 0x0 0.--11. 1. "FRAMESZ,Frame Size" wgroup.long 0x64++0x3 line.long 0x0 "TDR,Transmit Data" hexmask.long 0x0 0.--31. 1. "DATA,Transmit Data" rgroup.long 0x70++0xB line.long 0x0 "RSR,Receive Status" bitfld.long 0x0 1. "RXEMPTY,RX FIFO Empty" "0: Not empty,1: Empty" bitfld.long 0x0 0. "SOF,Start Of Frame" "0: Subsequent data word,1: First data word" line.long 0x4 "RDR,Receive Data" hexmask.long 0x4 0.--31. 1. "DATA,Receive Data" line.long 0x8 "RDROR,Receive Data Read Only" hexmask.long 0x8 0.--31. 1. "DATA,Receive Data" wgroup.long 0x3FC++0x3 line.long 0x0 "TCBR,Transmit Command Burst" hexmask.long 0x0 0.--31. 1. "DATA,Command Data" repeat 128. (increment 0x0 0x1)(increment 0x0 0x4) wgroup.long ($2+0x400)++0x3 line.long 0x0 "TDBR[$1],Transmit Data Burst" hexmask.long 0x0 0.--31. 1. "DATA,Data" repeat.end repeat 128. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x600)++0x3 line.long 0x0 "RDBR[$1],Receive Data Burst" hexmask.long 0x0 0.--31. 1. "DATA,Data" repeat.end tree.end tree "LPSPI_4" base ad:0x404BC000 rgroup.long 0x0++0x7 line.long 0x0 "VERID,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Module Identification Number" line.long 0x4 "PARAM,Parameter" hexmask.long.byte 0x4 16.--23. 1. "PCSNUM,PCS Number" hexmask.long.byte 0x4 8.--15. 1. "RXFIFO,Receive FIFO Size" newline hexmask.long.byte 0x4 0.--7. 1. "TXFIFO,Transmit FIFO Size" group.long 0x10++0x17 line.long 0x0 "CR,Control" bitfld.long 0x0 9. "RRF,Reset Receive FIFO" "0: No effect,1: Reset" bitfld.long 0x0 8. "RTF,Reset Transmit FIFO" "0: No effect,1: Reset" newline bitfld.long 0x0 3. "DBGEN,Debug Enable" "0: Disable,1: Enable" bitfld.long 0x0 1. "RST,Software Reset" "0: Not reset,1: Reset" newline bitfld.long 0x0 0. "MEN,Module Enable" "0: Disable,1: Enable" line.long 0x4 "SR,Status" rbitfld.long 0x4 24. "MBF,Module Busy Flag" "0: LPSPI is idle,1: LPSPI is busy" eventfld.long 0x4 13. "DMF,Data Match Flag" "0: No match,1: Match" newline eventfld.long 0x4 12. "REF,Receive Error Flag" "0: No overflow,1: Overflow" eventfld.long 0x4 11. "TEF,Transmit Error Flag" "0: No underrun,1: Underrun" newline eventfld.long 0x4 10. "TCF,Transfer Complete Flag" "0: Not complete,1: Complete" eventfld.long 0x4 9. "FCF,Frame Complete Flag" "0: Not complete,1: Complete" newline eventfld.long 0x4 8. "WCF,Word Complete Flag" "0: Not complete,1: Complete" rbitfld.long 0x4 1. "RDF,Receive Data Flag" "0: Receive data not ready,1: Receive data is ready" newline rbitfld.long 0x4 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested" line.long 0x8 "IER,Interrupt Enable" bitfld.long 0x8 13. "DMIE,Data Match Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 12. "REIE,Receive Error Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x8 11. "TEIE,Transmit Error Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 10. "TCIE,Transfer Complete Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x8 9. "FCIE,Frame Complete Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 8. "WCIE,Word Complete Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x8 1. "RDIE,Receive Data Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 0. "TDIE,Transmit Data Interrupt Enable" "0: Disable,1: Enable" line.long 0xC "DER,DMA Enable" bitfld.long 0xC 1. "RDDE,Receive Data DMA Enable" "0: Disable,1: Enable" bitfld.long 0xC 0. "TDDE,Transmit Data DMA Enable" "0: Disable,1: Enable" line.long 0x10 "CFGR0,Configuration 0" bitfld.long 0x10 9. "RDMO,Receive Data Match Only" "0: Disable,1: Enable" bitfld.long 0x10 8. "CIRFIFO,Circular FIFO Enable" "0: Disable,1: Enable" newline bitfld.long 0x10 3. "HRDIR,Host Request Direction" "0: Input,1: Output" bitfld.long 0x10 2. "HRSEL,Host Request Select" "0: HREQ pin,1: Input trigger" newline bitfld.long 0x10 1. "HRPOL,Host Request Polarity" "0: Active high,1: Active low" bitfld.long 0x10 0. "HREN,Host Request Enable" "0: Disable,1: Enable" line.long 0x14 "CFGR1,Configuration 1" bitfld.long 0x14 27. "PCSCFG,Peripheral Chip Select Configuration" "0: PCS[3:2] are configured for chip select function,1: PCS[3:2] are configured for half-duplex 4-bit.." bitfld.long 0x14 26. "OUTCFG,Output Configuration" "0: Output data retains last value.,1: Output data is 3-stated." newline bitfld.long 0x14 24.--25. "PINCFG,Pin Configuration" "0: SIN is used for input data; SOUT is used for..,1: SIN is used for both input and output data. Only..,2: SOUT is used for both input and output data.,3: SOUT is used for input data; SIN is used for.." bitfld.long 0x14 16.--18. "MATCFG,Match Configuration" "0: Match is disabled,?,2: Match first data word with compare word,3: Match any data word with compare word,4: Sequential match first data word,5: Sequential match any data word,6: Match first data word (masked) with compare word..,7: Match any data word (masked) with compare word.." newline hexmask.long.byte 0x14 8.--11. 1. "PCSPOL,Peripheral Chip Select Polarity" bitfld.long 0x14 4. "PARTIAL,Partial Enable" "0: Discard,1: Store" newline bitfld.long 0x14 3. "NOSTALL,No Stall" "0: Disable,1: Enable" bitfld.long 0x14 2. "AUTOPCS,Automatic PCS" "0: Disable,1: Enable" newline bitfld.long 0x14 1. "SAMPLE,Sample Point" "0: SCK edge,1: Delayed SCK edge" bitfld.long 0x14 0. "MASTER,Master Mode" "0: Slave mode,1: Master mode" group.long 0x30++0x7 line.long 0x0 "DMR0,Data Match 0" hexmask.long 0x0 0.--31. 1. "MATCH0,Match 0 Value" line.long 0x4 "DMR1,Data Match 1" hexmask.long 0x4 0.--31. 1. "MATCH1,Match 1 Value" group.long 0x40++0x7 line.long 0x0 "CCR,Clock Configuration" hexmask.long.byte 0x0 24.--31. 1. "SCKPCS,SCK-to-PCS Delay" hexmask.long.byte 0x0 16.--23. 1. "PCSSCK,PCS-to-SCK Delay" newline hexmask.long.byte 0x0 8.--15. 1. "DBT,Delay Between Transfers" hexmask.long.byte 0x0 0.--7. 1. "SCKDIV,SCK Divider" line.long 0x4 "CCR1,Clock Configuration 1" hexmask.long.byte 0x4 24.--31. 1. "SCKSCK,SCK Inter-Frame Delay" hexmask.long.byte 0x4 16.--23. 1. "PCSPCS,PCS to PCS delay" newline hexmask.long.byte 0x4 8.--15. 1. "SCKHLD,SCK Hold" hexmask.long.byte 0x4 0.--7. 1. "SCKSET,SCK Setup" group.long 0x58++0x3 line.long 0x0 "FCR,FIFO Control" bitfld.long 0x0 16.--17. "RXWATER,Receive FIFO Watermark" "0,1,2,3" bitfld.long 0x0 0.--1. "TXWATER,Transmit FIFO Watermark" "0,1,2,3" rgroup.long 0x5C++0x3 line.long 0x0 "FSR,FIFO Status" bitfld.long 0x0 16.--18. "RXCOUNT,Receive FIFO Count" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "TXCOUNT,Transmit FIFO Count" "0,1,2,3,4,5,6,7" group.long 0x60++0x3 line.long 0x0 "TCR,Transmit Command" bitfld.long 0x0 31. "CPOL,Clock Polarity" "0: Inactive low,1: Inactive high" bitfld.long 0x0 30. "CPHA,Clock Phase" "0: Captured,1: Changed" newline bitfld.long 0x0 27.--29. "PRESCALE,Prescaler Value" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128" bitfld.long 0x0 24.--25. "PCS,Peripheral Chip Select" "0: Transfer using PCS[0],1: Transfer using PCS[1],2: Transfer using PCS[2],3: Transfer using PCS[3]" newline bitfld.long 0x0 23. "LSBF,LSB First" "0: Data is transferred MSB first,1: Data is transferred LSB first" bitfld.long 0x0 22. "BYSW,Byte Swap" "0: Disabled,1: Enabled" newline bitfld.long 0x0 21. "CONT,Continuous Transfer" "0: Continuous transfer is disabled,1: Continuous transfer is enabled" bitfld.long 0x0 20. "CONTC,Continuing Command" "0: Command word for start of new transfer,1: Command word for continuing transfer" newline bitfld.long 0x0 19. "RXMSK,Receive Data Mask" "0: Normal transfer,1: Receive data is masked" bitfld.long 0x0 18. "TXMSK,Transmit Data Mask" "0: Normal transfer,1: Mask transmit data" newline bitfld.long 0x0 16.--17. "WIDTH,Transfer Width" "0: 1-bit transfer,1: 2-bit transfer,2: 4-bit transfer,?" hexmask.long.word 0x0 0.--11. 1. "FRAMESZ,Frame Size" wgroup.long 0x64++0x3 line.long 0x0 "TDR,Transmit Data" hexmask.long 0x0 0.--31. 1. "DATA,Transmit Data" rgroup.long 0x70++0xB line.long 0x0 "RSR,Receive Status" bitfld.long 0x0 1. "RXEMPTY,RX FIFO Empty" "0: Not empty,1: Empty" bitfld.long 0x0 0. "SOF,Start Of Frame" "0: Subsequent data word,1: First data word" line.long 0x4 "RDR,Receive Data" hexmask.long 0x4 0.--31. 1. "DATA,Receive Data" line.long 0x8 "RDROR,Receive Data Read Only" hexmask.long 0x8 0.--31. 1. "DATA,Receive Data" wgroup.long 0x3FC++0x3 line.long 0x0 "TCBR,Transmit Command Burst" hexmask.long 0x0 0.--31. 1. "DATA,Command Data" repeat 128. (increment 0x0 0x1)(increment 0x0 0x4) wgroup.long ($2+0x400)++0x3 line.long 0x0 "TDBR[$1],Transmit Data Burst" hexmask.long 0x0 0.--31. 1. "DATA,Data" repeat.end repeat 128. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x600)++0x3 line.long 0x0 "RDBR[$1],Receive Data Burst" hexmask.long 0x0 0.--31. 1. "DATA,Data" repeat.end tree.end tree "LPSPI_5" base ad:0x404C0000 rgroup.long 0x0++0x7 line.long 0x0 "VERID,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Module Identification Number" line.long 0x4 "PARAM,Parameter" hexmask.long.byte 0x4 16.--23. 1. "PCSNUM,PCS Number" hexmask.long.byte 0x4 8.--15. 1. "RXFIFO,Receive FIFO Size" newline hexmask.long.byte 0x4 0.--7. 1. "TXFIFO,Transmit FIFO Size" group.long 0x10++0x17 line.long 0x0 "CR,Control" bitfld.long 0x0 9. "RRF,Reset Receive FIFO" "0: No effect,1: Reset" bitfld.long 0x0 8. "RTF,Reset Transmit FIFO" "0: No effect,1: Reset" newline bitfld.long 0x0 3. "DBGEN,Debug Enable" "0: Disable,1: Enable" bitfld.long 0x0 1. "RST,Software Reset" "0: Not reset,1: Reset" newline bitfld.long 0x0 0. "MEN,Module Enable" "0: Disable,1: Enable" line.long 0x4 "SR,Status" rbitfld.long 0x4 24. "MBF,Module Busy Flag" "0: LPSPI is idle,1: LPSPI is busy" eventfld.long 0x4 13. "DMF,Data Match Flag" "0: No match,1: Match" newline eventfld.long 0x4 12. "REF,Receive Error Flag" "0: No overflow,1: Overflow" eventfld.long 0x4 11. "TEF,Transmit Error Flag" "0: No underrun,1: Underrun" newline eventfld.long 0x4 10. "TCF,Transfer Complete Flag" "0: Not complete,1: Complete" eventfld.long 0x4 9. "FCF,Frame Complete Flag" "0: Not complete,1: Complete" newline eventfld.long 0x4 8. "WCF,Word Complete Flag" "0: Not complete,1: Complete" rbitfld.long 0x4 1. "RDF,Receive Data Flag" "0: Receive data not ready,1: Receive data is ready" newline rbitfld.long 0x4 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested" line.long 0x8 "IER,Interrupt Enable" bitfld.long 0x8 13. "DMIE,Data Match Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 12. "REIE,Receive Error Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x8 11. "TEIE,Transmit Error Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 10. "TCIE,Transfer Complete Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x8 9. "FCIE,Frame Complete Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 8. "WCIE,Word Complete Interrupt Enable" "0: Disable,1: Enable" newline bitfld.long 0x8 1. "RDIE,Receive Data Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x8 0. "TDIE,Transmit Data Interrupt Enable" "0: Disable,1: Enable" line.long 0xC "DER,DMA Enable" bitfld.long 0xC 1. "RDDE,Receive Data DMA Enable" "0: Disable,1: Enable" bitfld.long 0xC 0. "TDDE,Transmit Data DMA Enable" "0: Disable,1: Enable" line.long 0x10 "CFGR0,Configuration 0" bitfld.long 0x10 9. "RDMO,Receive Data Match Only" "0: Disable,1: Enable" bitfld.long 0x10 8. "CIRFIFO,Circular FIFO Enable" "0: Disable,1: Enable" newline bitfld.long 0x10 3. "HRDIR,Host Request Direction" "0: Input,1: Output" bitfld.long 0x10 2. "HRSEL,Host Request Select" "0: HREQ pin,1: Input trigger" newline bitfld.long 0x10 1. "HRPOL,Host Request Polarity" "0: Active high,1: Active low" bitfld.long 0x10 0. "HREN,Host Request Enable" "0: Disable,1: Enable" line.long 0x14 "CFGR1,Configuration 1" bitfld.long 0x14 27. "PCSCFG,Peripheral Chip Select Configuration" "0: PCS[3:2] are configured for chip select function,1: PCS[3:2] are configured for half-duplex 4-bit.." bitfld.long 0x14 26. "OUTCFG,Output Configuration" "0: Output data retains last value.,1: Output data is 3-stated." newline bitfld.long 0x14 24.--25. "PINCFG,Pin Configuration" "0: SIN is used for input data; SOUT is used for..,1: SIN is used for both input and output data. Only..,2: SOUT is used for both input and output data.,3: SOUT is used for input data; SIN is used for.." bitfld.long 0x14 16.--18. "MATCFG,Match Configuration" "0: Match is disabled,?,2: Match first data word with compare word,3: Match any data word with compare word,4: Sequential match first data word,5: Sequential match any data word,6: Match first data word (masked) with compare word..,7: Match any data word (masked) with compare word.." newline hexmask.long.byte 0x14 8.--11. 1. "PCSPOL,Peripheral Chip Select Polarity" bitfld.long 0x14 4. "PARTIAL,Partial Enable" "0: Discard,1: Store" newline bitfld.long 0x14 3. "NOSTALL,No Stall" "0: Disable,1: Enable" bitfld.long 0x14 2. "AUTOPCS,Automatic PCS" "0: Disable,1: Enable" newline bitfld.long 0x14 1. "SAMPLE,Sample Point" "0: SCK edge,1: Delayed SCK edge" bitfld.long 0x14 0. "MASTER,Master Mode" "0: Slave mode,1: Master mode" group.long 0x30++0x7 line.long 0x0 "DMR0,Data Match 0" hexmask.long 0x0 0.--31. 1. "MATCH0,Match 0 Value" line.long 0x4 "DMR1,Data Match 1" hexmask.long 0x4 0.--31. 1. "MATCH1,Match 1 Value" group.long 0x40++0x7 line.long 0x0 "CCR,Clock Configuration" hexmask.long.byte 0x0 24.--31. 1. "SCKPCS,SCK-to-PCS Delay" hexmask.long.byte 0x0 16.--23. 1. "PCSSCK,PCS-to-SCK Delay" newline hexmask.long.byte 0x0 8.--15. 1. "DBT,Delay Between Transfers" hexmask.long.byte 0x0 0.--7. 1. "SCKDIV,SCK Divider" line.long 0x4 "CCR1,Clock Configuration 1" hexmask.long.byte 0x4 24.--31. 1. "SCKSCK,SCK Inter-Frame Delay" hexmask.long.byte 0x4 16.--23. 1. "PCSPCS,PCS to PCS delay" newline hexmask.long.byte 0x4 8.--15. 1. "SCKHLD,SCK Hold" hexmask.long.byte 0x4 0.--7. 1. "SCKSET,SCK Setup" group.long 0x58++0x3 line.long 0x0 "FCR,FIFO Control" bitfld.long 0x0 16.--17. "RXWATER,Receive FIFO Watermark" "0,1,2,3" bitfld.long 0x0 0.--1. "TXWATER,Transmit FIFO Watermark" "0,1,2,3" rgroup.long 0x5C++0x3 line.long 0x0 "FSR,FIFO Status" bitfld.long 0x0 16.--18. "RXCOUNT,Receive FIFO Count" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "TXCOUNT,Transmit FIFO Count" "0,1,2,3,4,5,6,7" group.long 0x60++0x3 line.long 0x0 "TCR,Transmit Command" bitfld.long 0x0 31. "CPOL,Clock Polarity" "0: Inactive low,1: Inactive high" bitfld.long 0x0 30. "CPHA,Clock Phase" "0: Captured,1: Changed" newline bitfld.long 0x0 27.--29. "PRESCALE,Prescaler Value" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128" bitfld.long 0x0 24.--25. "PCS,Peripheral Chip Select" "0: Transfer using PCS[0],1: Transfer using PCS[1],2: Transfer using PCS[2],3: Transfer using PCS[3]" newline bitfld.long 0x0 23. "LSBF,LSB First" "0: Data is transferred MSB first,1: Data is transferred LSB first" bitfld.long 0x0 22. "BYSW,Byte Swap" "0: Disabled,1: Enabled" newline bitfld.long 0x0 21. "CONT,Continuous Transfer" "0: Continuous transfer is disabled,1: Continuous transfer is enabled" bitfld.long 0x0 20. "CONTC,Continuing Command" "0: Command word for start of new transfer,1: Command word for continuing transfer" newline bitfld.long 0x0 19. "RXMSK,Receive Data Mask" "0: Normal transfer,1: Receive data is masked" bitfld.long 0x0 18. "TXMSK,Transmit Data Mask" "0: Normal transfer,1: Mask transmit data" newline bitfld.long 0x0 16.--17. "WIDTH,Transfer Width" "0: 1-bit transfer,1: 2-bit transfer,2: 4-bit transfer,?" hexmask.long.word 0x0 0.--11. 1. "FRAMESZ,Frame Size" wgroup.long 0x64++0x3 line.long 0x0 "TDR,Transmit Data" hexmask.long 0x0 0.--31. 1. "DATA,Transmit Data" rgroup.long 0x70++0xB line.long 0x0 "RSR,Receive Status" bitfld.long 0x0 1. "RXEMPTY,RX FIFO Empty" "0: Not empty,1: Empty" bitfld.long 0x0 0. "SOF,Start Of Frame" "0: Subsequent data word,1: First data word" line.long 0x4 "RDR,Receive Data" hexmask.long 0x4 0.--31. 1. "DATA,Receive Data" line.long 0x8 "RDROR,Receive Data Read Only" hexmask.long 0x8 0.--31. 1. "DATA,Receive Data" wgroup.long 0x3FC++0x3 line.long 0x0 "TCBR,Transmit Command Burst" hexmask.long 0x0 0.--31. 1. "DATA,Command Data" repeat 128. (increment 0x0 0x1)(increment 0x0 0x4) wgroup.long ($2+0x400)++0x3 line.long 0x0 "TDBR[$1],Transmit Data Burst" hexmask.long 0x0 0.--31. 1. "DATA,Data" repeat.end repeat 128. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x600)++0x3 line.long 0x0 "RDBR[$1],Receive Data Burst" hexmask.long 0x0 0.--31. 1. "DATA,Data" repeat.end tree.end tree.end tree "LPUART (Low Power Universal Asynchronous Receiver/Transmitter)" base ad:0x0 tree "LPUART_0" base ad:0x40328000 rgroup.long 0x0++0x7 line.long 0x0 "VERID,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Identification Number" line.long 0x4 "PARAM,Parameter" hexmask.long.byte 0x4 8.--15. 1. "RXFIFO,Receive FIFO Size" hexmask.long.byte 0x4 0.--7. 1. "TXFIFO,Transmit FIFO Size" group.long 0x8++0x27 line.long 0x0 "GLOBAL,Global" bitfld.long 0x0 1. "RST,Software Reset" "0: Not reset,1: Reset" line.long 0x4 "PINCFG,Pin Configuration" bitfld.long 0x4 0.--1. "TRGSEL,Trigger Select" "0: Input trigger disabled,1: Input trigger used instead of the RXD pin input,2: Input trigger used instead of the CTS_B pin input,3: Input trigger used to modulate the TXD pin.." line.long 0x8 "BAUD,Baud Rate" bitfld.long 0x8 31. "MAEN1,Match Address Mode Enable 1" "0: Disables,1: Enables" bitfld.long 0x8 30. "MAEN2,Match Address Mode Enable 2" "0: Disables,1: Enables" newline bitfld.long 0x8 29. "M10,10-Bit Mode Select" "0: Receiver and transmitter use 7-bit to 9-bit data..,1: Receiver and transmitter use 10-bit data.." hexmask.long.byte 0x8 24.--28. 1. "OSR,Oversampling Ratio (OSR)" newline bitfld.long 0x8 23. "TDMAE,Transmitter DMA Enable" "0: Disables DMA request,1: Enables DMA request" bitfld.long 0x8 21. "RDMAE,Receiver Full DMA Enable" "0: Disables DMA request,1: Enables DMA request" newline bitfld.long 0x8 18.--19. "MATCFG,Match Configuration" "0: Address match wakeup,1: Idle match wakeup,2: Match on and match off,3: Enables RWU on data match and match on/off for.." bitfld.long 0x8 17. "BOTHEDGE,Both Edge Sampling" "0: Receiver samples input data using the rising..,1: Receiver samples input data using the rising and.." newline bitfld.long 0x8 16. "RESYNCDIS,Resynchronization Disable" "0: Enables resynchronization,1: Disables resynchronization" bitfld.long 0x8 15. "LBKDIE,LIN Break Detect Interrupt Enable" "0: Disables hardware interrupts from STAT[LBKDIF]..,1: Requests hardware interrupt when STAT[LBKDIF] is 1" newline bitfld.long 0x8 14. "RXEDGIE,RX Input Active Edge Interrupt Enable" "0: Disables hardware interrupts from STAT[RXEDGIF],1: Requests hardware interrupts when STAT[RXEDGIF].." bitfld.long 0x8 13. "SBNS,Stop Bit Number Select" "0: One stop bit,1: Two stop bits" newline hexmask.long.word 0x8 0.--12. 1. "SBR,Baud Rate Modulo Divisor" line.long 0xC "STAT,Status" eventfld.long 0xC 31. "LBKDIF,LIN Break Detect Interrupt Flag" "0: Not detected,1: Detected" eventfld.long 0xC 30. "RXEDGIF,RXD Pin Active Edge Interrupt Flag" "0: Not occurred,1: Occurred" newline bitfld.long 0xC 29. "MSBF,MSB First" "0: LSB,1: MSB" bitfld.long 0xC 28. "RXINV,Receive Data Inversion" "0: Inverted,1: Not inverted" newline bitfld.long 0xC 27. "RWUID,Receive Wake Up Idle Detect" "0: STAT[IDLE] does not become 1,1: STAT[IDLE] becomes 1" bitfld.long 0xC 26. "BRK13,Break Character Generation Length" "0: 9 to 13 bit times,1: 12 to 15 bit times" newline bitfld.long 0xC 25. "LBKDE,LIN Break Detection Enable" "0: Disables,1: Enables" rbitfld.long 0xC 24. "RAF,Receiver Active Flag" "0: Idle waiting for a start bit,1: Receiver active (RXD pin input not idle)" newline rbitfld.long 0xC 23. "TDRE,Transmit Data Register Empty Flag" "0: Greater than watermark,1: Equal to or less than watermark" rbitfld.long 0xC 22. "TC,Transmission Complete Flag" "0: Transmitter active (sending data a preamble or a..,1: Transmitter idle (transmission activity complete)" newline rbitfld.long 0xC 21. "RDRF,Receive Data Register Full Flag" "0: Equal to or less than watermark,1: Greater than watermark" eventfld.long 0xC 20. "IDLE,Idle Line Flag" "0: No idle line detected,1: Idle line detected" newline eventfld.long 0xC 19. "OR,Receiver Overrun Flag" "0: No overrun,1: Receive overrun (new LPUART data lost)" eventfld.long 0xC 18. "NF,Noise Flag (NF)" "0: No noise detected,1: Noise detected" newline eventfld.long 0xC 17. "FE,Framing Error Flag (FE)" "0: No framing error detected (this does not..,1: Framing error detected" eventfld.long 0xC 16. "PF,Parity Error Flag (PF)" "0: No parity error detected,1: Parity error detected" newline eventfld.long 0xC 15. "MA1F,Match 1 Flag" "0: Not equal to MA1,1: Equal to MA1" eventfld.long 0xC 14. "MA2F,Match 2 Flag" "0: Not equal to MA2,1: Equal to MA2" newline rbitfld.long 0xC 9. "TSF,Timeout Status Flag" "0: Field is 0,1: Field is 1" rbitfld.long 0xC 8. "MSF,MODEM Status Flag" "0: Field is 0,1: Field is 1" newline bitfld.long 0xC 1. "AME,Address Mark Enable" "0: Address mark in character is MSB,1: Address mark in character is the last bit before.." bitfld.long 0xC 0. "LBKFE,LIN Break Flag Enable" "0: Disables LIN break detect,1: Enables LIN break detect" line.long 0x10 "CTRL,Control" bitfld.long 0x10 31. "R8T9,Receive Bit 8 Transmit Bit 9" "0,1" bitfld.long 0x10 30. "R9T8,Receive Bit 9 Transmit Bit 8" "0,1" newline bitfld.long 0x10 29. "TXDIR,TXD Pin Direction in Single-Wire Mode" "0: TXD pin is an input in Single-Wire mode,1: TXD pin is an output in Single-Wire mode" bitfld.long 0x10 28. "TXINV,Transmit Data Inversion" "0: Not inverted,1: Inverted" newline bitfld.long 0x10 27. "ORIE,Overrun Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 26. "NEIE,Noise Error Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 25. "FEIE,Framing Error Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 24. "PEIE,Parity Error Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 23. "TIE,Transmit Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 22. "TCIE,Transmission Complete Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 21. "RIE,Receiver Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 20. "ILIE,Idle Line Interrupt Enable" "0: Disables hardware interrupts from STAT[IDLE];..,1: Enables hardware interrupts when STAT[IDLE] = 1" newline bitfld.long 0x10 19. "TE,Transmitter Enable" "0: Disables,1: Enables" bitfld.long 0x10 18. "RE,Receiver Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 17. "RWU,Receiver Wakeup Control" "0: Normal receiver operation,1: LPUART receiver in standby waiting for a wakeup.." bitfld.long 0x10 16. "SBK,Send Break" "0: Normal transmitter operation,1: Queue break character(s) to be sent" newline bitfld.long 0x10 15. "MA1IE,Match 1 (MA1F) Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 14. "MA2IE,Match 2 (MA2F) Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 11. "M7,7-Bit Mode Select" "0: 8-bit to 10-bit data characters,1: 7-bit data characters" bitfld.long 0x10 8.--10. "IDLECFG,Idle Configuration" "0: 1,1: 2,2: 4,3: 8,4: 16,5: 32,6: 64,7: 128" newline bitfld.long 0x10 7. "LOOPS,Loop Mode Select" "0: Normal operation: RXD and TXD use separate pins,1: Loop mode or Single-Wire mode" bitfld.long 0x10 6. "DOZEEN,Enables LPUART in Doze mode." "0: Enables,1: Disables" newline bitfld.long 0x10 5. "RSRC,Receiver Source Select" "0: Internal Loopback mode,1: Single-wire mode" bitfld.long 0x10 4. "M,9-Bit Or 8-Bit Mode Select" "0: 8-bit data characters,1: 9-bit data characters" newline bitfld.long 0x10 3. "WAKE,Receiver Wakeup Method Select" "0: Configures CTRL[RWU] for idle-line wakeup,1: Configures CTRL[RWU] with address-mark wakeup" bitfld.long 0x10 2. "ILT,Idle Line Type Select" "0: After the start bit,1: After the stop bit" newline bitfld.long 0x10 1. "PE,Parity Enable" "0: Disables,1: Enables" bitfld.long 0x10 0. "PT,Parity Type" "0: Even parity,1: Odd parity" line.long 0x14 "DATA,Data" rbitfld.long 0x14 15. "NOISY,Noisy Data Received" "0: Received without noise,1: Received with noise" rbitfld.long 0x14 14. "PARITYE,Parity Error" "0: Received without a parity error,1: Received with a parity error" newline bitfld.long 0x14 13. "FRETSC,Frame Error Transmit Special Character" "0: Received without a frame error on reads or..,1: Received with a frame error on reads or.." rbitfld.long 0x14 12. "RXEMPT,Receive Buffer Empty" "0: Contains valid data,1: Contains invalid data and is empty" newline rbitfld.long 0x14 11. "IDLINE,Idle Line" "0: Received was not idle,1: Receiver was idle" rbitfld.long 0x14 10. "LINBRK,LIN Break" "0: LIN break not detected or LIN break detect..,1: LIN break detected" newline bitfld.long 0x14 9. "R9T9,Read Receive FIFO Bit 9 Or Write Transmit FIFO Bit 9" "0,1" bitfld.long 0x14 8. "R8T8,Read Receive FIFO Bit 8 Or Write Transmit FIFO Bit 8" "0,1" newline bitfld.long 0x14 7. "R7T7,Read Receive FIFO Bit 7 Or Write Transmit FIFO Bit 7" "0,1" bitfld.long 0x14 6. "R6T6,Read Receive FIFO Bit 6 Or Write Transmit FIFO Bit 6" "0,1" newline bitfld.long 0x14 5. "R5T5,Read Receive FIFO Bit 5 Or Write Transmit FIFO Bit 5" "0,1" bitfld.long 0x14 4. "R4T4,Read Receive FIFO Bit 4 Or Write Transmit FIFO Bit 4" "0,1" newline bitfld.long 0x14 3. "R3T3,Read Receive FIFO Bit 3 Or Write Transmit FIFO Bit 3" "0,1" bitfld.long 0x14 2. "R2T2,Read Receive FIFO Bit 2 Or Write Transmit FIFO Bit 2" "0,1" newline bitfld.long 0x14 1. "R1T1,Read Receive FIFO Bit 1 Or Write Transmit FIFO Bit 1" "0,1" bitfld.long 0x14 0. "R0T0,Read Receive FIFO Bit 0 Or Write Transmit FIFO Bit 0" "0,1" line.long 0x18 "MATCH,Match Address" hexmask.long.word 0x18 16.--25. 1. "MA2,Match Address 2" hexmask.long.word 0x18 0.--9. 1. "MA1,Match Address 1" line.long 0x1C "MODIR,MODEM IrDA" bitfld.long 0x1C 18. "IREN,IR Enable" "0: Disables,1: Enables" bitfld.long 0x1C 16.--17. "TNP,Transmitter Narrow Pulse" "0: 1 / OSR,1: 2 / OSR,2: 3 / OSR,3: 4 / OSR" newline hexmask.long.byte 0x1C 8.--11. 1. "RTSWATER,Receive RTS Configuration" bitfld.long 0x1C 5. "TXCTSSRC,Transmit CTS Source" "0: The CTS_B pin,1: An internal connection to the receiver address.." newline bitfld.long 0x1C 4. "TXCTSC,Transmit CTS Configuration" "0: Sampled at the start of each character,1: Sampled when the transmitter is idle" bitfld.long 0x1C 3. "RXRTSE,Receiver RTS Enable" "0: Disables,1: Enables" newline bitfld.long 0x1C 2. "TXRTSPOL,Transmitter RTS Polarity" "0: Transmitter RTS is active low,1: Transmitter RTS is active high" bitfld.long 0x1C 1. "TXRTSE,Transmitter RTS Enable" "0: Disables,1: Enables" newline bitfld.long 0x1C 0. "TXCTSE,Transmitter CTS Enable" "0: Disables,1: Enables" line.long 0x20 "FIFO,FIFO" rbitfld.long 0x20 23. "TXEMPT,Transmit FIFO Or Buffer Empty" "0: Not empty,1: Empty" rbitfld.long 0x20 22. "RXEMPT,Receive FIFO Or Buffer Empty" "0: Not empty,1: Empty" newline eventfld.long 0x20 17. "TXOF,Transmitter FIFO Overflow Flag" "0: No overflow,1: Overflow" eventfld.long 0x20 16. "RXUF,Receiver FIFO Underflow Flag" "0: No underflow,1: Underflow" newline bitfld.long 0x20 15. "TXFLUSH,Transmit FIFO Flush" "0: No effect,1: All data is flushed out" bitfld.long 0x20 14. "RXFLUSH,Receive FIFO Flush" "0: No effect,1: All data is flushed out" newline bitfld.long 0x20 10.--12. "RXIDEN,Receiver Idle Empty Enable" "0: Disables STAT[RDRF] to become 1 because of..,1: Enables STAT[RDRF] to become 1 because of..,2: Enables STAT[RDRF] to become 1 because of..,3: Enables STAT[RDRF] to become 1 because of..,4: Enables STAT[RDRF] to become 1 because of..,5: Enables STAT[RDRF] to become 1 because of..,6: Enables STAT[RDRF] to become 1 because of..,7: Enables STAT[RDRF] to become 1 because of.." bitfld.long 0x20 9. "TXOFE,Transmit FIFO Overflow Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x20 8. "RXUFE,Receive FIFO Underflow Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x20 7. "TXFE,Transmit FIFO Enable" "0: Disables; buffer depth is 1,1: Enables; FIFO[TXFIFOSIZE] indicates the buffer.." newline rbitfld.long 0x20 4.--6. "TXFIFOSIZE,Transmit FIFO Buffer Depth" "0: Transmit FIFO buffer depth = 1 dataword,1: Transmit FIFO buffer depth = 4 datawords,2: Transmit FIFO buffer depth = 8 datawords,3: Transmit FIFO buffer depth = 16 datawords,4: Transmit FIFO buffer depth = 32 datawords,5: Transmit FIFO buffer depth = 64 datawords,6: Transmit FIFO buffer depth = 128 datawords,7: Transmit FIFO buffer depth = 256 datawords" bitfld.long 0x20 3. "RXFE,Receive FIFO Enable" "0: Disables; buffer depth is 1,1: Enables; FIFO[RXFIFOSIZE] indicates the buffer.." newline rbitfld.long 0x20 0.--2. "RXFIFOSIZE,Receive FIFO Buffer Depth" "0: Receive FIFO buffer depth = 1 dataword,1: Receive FIFO buffer depth = 4 datawords,2: Receive FIFO buffer depth = 8 datawords,3: Receive FIFO buffer depth = 16 datawords,4: Receive FIFO buffer depth = 32 datawords,5: Receive FIFO buffer depth = 64 datawords,6: Receive FIFO buffer depth = 128 datawords,7: Receive FIFO buffer depth = 256 datawords" line.long 0x24 "WATER,Watermark" hexmask.long.byte 0x24 24.--28. 1. "RXCOUNT,Receive Counter" hexmask.long.byte 0x24 16.--19. 1. "RXWATER,Receive Watermark" newline hexmask.long.byte 0x24 8.--12. 1. "TXCOUNT,Transmit Counter" hexmask.long.byte 0x24 0.--3. 1. "TXWATER,Transmit Watermark" rgroup.long 0x30++0x3 line.long 0x0 "DATARO,Data Read-Only" hexmask.long.word 0x0 0.--15. 1. "DATA,Receive Data" group.long 0x40++0x13 line.long 0x0 "MCR,MODEM Control" bitfld.long 0x0 9. "RTS,Request To Send" "0: Default state is logic one,1: Default state is logic zero" bitfld.long 0x0 8. "DTR,Data Terminal Ready" "0: Default state is logic one,1: Default state is logic zero" newline bitfld.long 0x0 3. "DCD,Data Carrier Detect" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x0 2. "RIN,Ring Indicator" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x0 1. "DSR,Data Set Ready" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x0 0. "CTS,Clear To Send" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x4 "MSR,MODEM Status" rbitfld.long 0x4 7. "DCD,Data Carrier Detect" "0: The DCD_B pin is logic one,1: The DCD_B pin is logic zero" rbitfld.long 0x4 6. "RIN,Ring Indicator" "0: The RIN_B pin is logic one,1: The RIN_B pin is logic zero" newline rbitfld.long 0x4 5. "DSR,Data Set Ready" "0: The DSR_B pin is logic one,1: The DSR_B pin is logic zero" rbitfld.long 0x4 4. "CTS,Clear To Send" "0: The CTS_B pin is logic one,1: The CTS_B pin is logic zero" newline eventfld.long 0x4 3. "DDCD,Delta Data Carrier Detect" "0: Did not change state,1: Changed state" eventfld.long 0x4 2. "DRI,Delta Ring Indicator" "0: Did not change state,1: Changed state" newline eventfld.long 0x4 1. "DDSR,Delta Data Set Ready" "0: Did not change state,1: Changed state" eventfld.long 0x4 0. "DCTS,Delta Clear To Send" "0: Did not change state,1: Changed state" line.long 0x8 "REIR,Receiver Extended Idle" hexmask.long.word 0x8 0.--13. 1. "IDTIME,Idle Time" line.long 0xC "TEIR,Transmitter Extended Idle" hexmask.long.word 0xC 0.--13. 1. "IDTIME,Idle Time" line.long 0x10 "HDCR,Half Duplex Control" hexmask.long.byte 0x10 8.--15. 1. "RTSEXT,RTS Extended" bitfld.long 0x10 3. "RXMSK,Receive Mask" "0: Does not mask,1: Masks" newline bitfld.long 0x10 2. "RXWRMSK,Receive FIFO Write Mask" "0: Does not mask,1: Masks" bitfld.long 0x10 1. "RXSEL,Receive Select" "0: RXD,1: TXD" newline bitfld.long 0x10 0. "TXSTALL,Transmit Stall" "0: No effect,1: Does not become busy" group.long 0x58++0x7 line.long 0x0 "TOCR,Timeout Control" hexmask.long.byte 0x0 8.--11. 1. "TOIE,Timeout Interrupt Enable" hexmask.long.byte 0x0 0.--3. 1. "TOEN,Timeout Enable" line.long 0x4 "TOSR,Timeout Status" hexmask.long.byte 0x4 8.--11. 1. "TOF,Timeout Flag" hexmask.long.byte 0x4 0.--3. 1. "TOZ,Timeout Zero" repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x60)++0x3 line.long 0x0 "TIMEOUT[$1],Timeout N" bitfld.long 0x0 30.--31. "CFG,Idle Configuration" "0: Becomes 1 after timeout characters are received,1: Becomes 1 when idle for timeout bit clocks,2: Becomes 1 when idle for timeout bit clocks..,3: Becomes 1 when idle for at least timeout bit.." hexmask.long.word 0x0 0.--13. 1. "TIMEOUT,Timeout Value" repeat.end repeat 128. (increment 0x0 0x1)(increment 0x0 0x4) wgroup.long ($2+0x200)++0x3 line.long 0x0 "TCBR[$1],Transmit Command Burst" hexmask.long.word 0x0 0.--15. 1. "DATA,Data" repeat.end repeat 256. (increment 0x0 0x1)(increment 0x0 0x4) wgroup.long ($2+0x400)++0x3 line.long 0x0 "TDBR[$1],Transmit Data Burst" hexmask.long.byte 0x0 24.--31. 1. "DATA3,Data3" hexmask.long.byte 0x0 16.--23. 1. "DATA2,Data2" newline hexmask.long.byte 0x0 8.--15. 1. "DATA1,Data1" hexmask.long.byte 0x0 0.--7. 1. "DATA0,Data0" repeat.end tree.end tree "LPUART_1" base ad:0x4032C000 rgroup.long 0x0++0x7 line.long 0x0 "VERID,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Identification Number" line.long 0x4 "PARAM,Parameter" hexmask.long.byte 0x4 8.--15. 1. "RXFIFO,Receive FIFO Size" hexmask.long.byte 0x4 0.--7. 1. "TXFIFO,Transmit FIFO Size" group.long 0x8++0x27 line.long 0x0 "GLOBAL,Global" bitfld.long 0x0 1. "RST,Software Reset" "0: Not reset,1: Reset" line.long 0x4 "PINCFG,Pin Configuration" bitfld.long 0x4 0.--1. "TRGSEL,Trigger Select" "0: Input trigger disabled,1: Input trigger used instead of the RXD pin input,2: Input trigger used instead of the CTS_B pin input,3: Input trigger used to modulate the TXD pin.." line.long 0x8 "BAUD,Baud Rate" bitfld.long 0x8 31. "MAEN1,Match Address Mode Enable 1" "0: Disables,1: Enables" bitfld.long 0x8 30. "MAEN2,Match Address Mode Enable 2" "0: Disables,1: Enables" newline bitfld.long 0x8 29. "M10,10-Bit Mode Select" "0: Receiver and transmitter use 7-bit to 9-bit data..,1: Receiver and transmitter use 10-bit data.." hexmask.long.byte 0x8 24.--28. 1. "OSR,Oversampling Ratio (OSR)" newline bitfld.long 0x8 23. "TDMAE,Transmitter DMA Enable" "0: Disables DMA request,1: Enables DMA request" bitfld.long 0x8 21. "RDMAE,Receiver Full DMA Enable" "0: Disables DMA request,1: Enables DMA request" newline bitfld.long 0x8 18.--19. "MATCFG,Match Configuration" "0: Address match wakeup,1: Idle match wakeup,2: Match on and match off,3: Enables RWU on data match and match on/off for.." bitfld.long 0x8 17. "BOTHEDGE,Both Edge Sampling" "0: Receiver samples input data using the rising..,1: Receiver samples input data using the rising and.." newline bitfld.long 0x8 16. "RESYNCDIS,Resynchronization Disable" "0: Enables resynchronization,1: Disables resynchronization" bitfld.long 0x8 15. "LBKDIE,LIN Break Detect Interrupt Enable" "0: Disables hardware interrupts from STAT[LBKDIF]..,1: Requests hardware interrupt when STAT[LBKDIF] is 1" newline bitfld.long 0x8 14. "RXEDGIE,RX Input Active Edge Interrupt Enable" "0: Disables hardware interrupts from STAT[RXEDGIF],1: Requests hardware interrupts when STAT[RXEDGIF].." bitfld.long 0x8 13. "SBNS,Stop Bit Number Select" "0: One stop bit,1: Two stop bits" newline hexmask.long.word 0x8 0.--12. 1. "SBR,Baud Rate Modulo Divisor" line.long 0xC "STAT,Status" eventfld.long 0xC 31. "LBKDIF,LIN Break Detect Interrupt Flag" "0: Not detected,1: Detected" eventfld.long 0xC 30. "RXEDGIF,RXD Pin Active Edge Interrupt Flag" "0: Not occurred,1: Occurred" newline bitfld.long 0xC 29. "MSBF,MSB First" "0: LSB,1: MSB" bitfld.long 0xC 28. "RXINV,Receive Data Inversion" "0: Inverted,1: Not inverted" newline bitfld.long 0xC 27. "RWUID,Receive Wake Up Idle Detect" "0: STAT[IDLE] does not become 1,1: STAT[IDLE] becomes 1" bitfld.long 0xC 26. "BRK13,Break Character Generation Length" "0: 9 to 13 bit times,1: 12 to 15 bit times" newline bitfld.long 0xC 25. "LBKDE,LIN Break Detection Enable" "0: Disables,1: Enables" rbitfld.long 0xC 24. "RAF,Receiver Active Flag" "0: Idle waiting for a start bit,1: Receiver active (RXD pin input not idle)" newline rbitfld.long 0xC 23. "TDRE,Transmit Data Register Empty Flag" "0: Greater than watermark,1: Equal to or less than watermark" rbitfld.long 0xC 22. "TC,Transmission Complete Flag" "0: Transmitter active (sending data a preamble or a..,1: Transmitter idle (transmission activity complete)" newline rbitfld.long 0xC 21. "RDRF,Receive Data Register Full Flag" "0: Equal to or less than watermark,1: Greater than watermark" eventfld.long 0xC 20. "IDLE,Idle Line Flag" "0: No idle line detected,1: Idle line detected" newline eventfld.long 0xC 19. "OR,Receiver Overrun Flag" "0: No overrun,1: Receive overrun (new LPUART data lost)" eventfld.long 0xC 18. "NF,Noise Flag (NF)" "0: No noise detected,1: Noise detected" newline eventfld.long 0xC 17. "FE,Framing Error Flag (FE)" "0: No framing error detected (this does not..,1: Framing error detected" eventfld.long 0xC 16. "PF,Parity Error Flag (PF)" "0: No parity error detected,1: Parity error detected" newline eventfld.long 0xC 15. "MA1F,Match 1 Flag" "0: Not equal to MA1,1: Equal to MA1" eventfld.long 0xC 14. "MA2F,Match 2 Flag" "0: Not equal to MA2,1: Equal to MA2" newline rbitfld.long 0xC 9. "TSF,Timeout Status Flag" "0: Field is 0,1: Field is 1" rbitfld.long 0xC 8. "MSF,MODEM Status Flag" "0: Field is 0,1: Field is 1" newline bitfld.long 0xC 1. "AME,Address Mark Enable" "0: Address mark in character is MSB,1: Address mark in character is the last bit before.." bitfld.long 0xC 0. "LBKFE,LIN Break Flag Enable" "0: Disables LIN break detect,1: Enables LIN break detect" line.long 0x10 "CTRL,Control" bitfld.long 0x10 31. "R8T9,Receive Bit 8 Transmit Bit 9" "0,1" bitfld.long 0x10 30. "R9T8,Receive Bit 9 Transmit Bit 8" "0,1" newline bitfld.long 0x10 29. "TXDIR,TXD Pin Direction in Single-Wire Mode" "0: TXD pin is an input in Single-Wire mode,1: TXD pin is an output in Single-Wire mode" bitfld.long 0x10 28. "TXINV,Transmit Data Inversion" "0: Not inverted,1: Inverted" newline bitfld.long 0x10 27. "ORIE,Overrun Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 26. "NEIE,Noise Error Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 25. "FEIE,Framing Error Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 24. "PEIE,Parity Error Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 23. "TIE,Transmit Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 22. "TCIE,Transmission Complete Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 21. "RIE,Receiver Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 20. "ILIE,Idle Line Interrupt Enable" "0: Disables hardware interrupts from STAT[IDLE];..,1: Enables hardware interrupts when STAT[IDLE] = 1" newline bitfld.long 0x10 19. "TE,Transmitter Enable" "0: Disables,1: Enables" bitfld.long 0x10 18. "RE,Receiver Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 17. "RWU,Receiver Wakeup Control" "0: Normal receiver operation,1: LPUART receiver in standby waiting for a wakeup.." bitfld.long 0x10 16. "SBK,Send Break" "0: Normal transmitter operation,1: Queue break character(s) to be sent" newline bitfld.long 0x10 15. "MA1IE,Match 1 (MA1F) Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 14. "MA2IE,Match 2 (MA2F) Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 11. "M7,7-Bit Mode Select" "0: 8-bit to 10-bit data characters,1: 7-bit data characters" bitfld.long 0x10 8.--10. "IDLECFG,Idle Configuration" "0: 1,1: 2,2: 4,3: 8,4: 16,5: 32,6: 64,7: 128" newline bitfld.long 0x10 7. "LOOPS,Loop Mode Select" "0: Normal operation: RXD and TXD use separate pins,1: Loop mode or Single-Wire mode" bitfld.long 0x10 6. "DOZEEN,Enables LPUART in Doze mode." "0: Enables,1: Disables" newline bitfld.long 0x10 5. "RSRC,Receiver Source Select" "0: Internal Loopback mode,1: Single-wire mode" bitfld.long 0x10 4. "M,9-Bit Or 8-Bit Mode Select" "0: 8-bit data characters,1: 9-bit data characters" newline bitfld.long 0x10 3. "WAKE,Receiver Wakeup Method Select" "0: Configures CTRL[RWU] for idle-line wakeup,1: Configures CTRL[RWU] with address-mark wakeup" bitfld.long 0x10 2. "ILT,Idle Line Type Select" "0: After the start bit,1: After the stop bit" newline bitfld.long 0x10 1. "PE,Parity Enable" "0: Disables,1: Enables" bitfld.long 0x10 0. "PT,Parity Type" "0: Even parity,1: Odd parity" line.long 0x14 "DATA,Data" rbitfld.long 0x14 15. "NOISY,Noisy Data Received" "0: Received without noise,1: Received with noise" rbitfld.long 0x14 14. "PARITYE,Parity Error" "0: Received without a parity error,1: Received with a parity error" newline bitfld.long 0x14 13. "FRETSC,Frame Error Transmit Special Character" "0: Received without a frame error on reads or..,1: Received with a frame error on reads or.." rbitfld.long 0x14 12. "RXEMPT,Receive Buffer Empty" "0: Contains valid data,1: Contains invalid data and is empty" newline rbitfld.long 0x14 11. "IDLINE,Idle Line" "0: Received was not idle,1: Receiver was idle" rbitfld.long 0x14 10. "LINBRK,LIN Break" "0: LIN break not detected or LIN break detect..,1: LIN break detected" newline bitfld.long 0x14 9. "R9T9,Read Receive FIFO Bit 9 Or Write Transmit FIFO Bit 9" "0,1" bitfld.long 0x14 8. "R8T8,Read Receive FIFO Bit 8 Or Write Transmit FIFO Bit 8" "0,1" newline bitfld.long 0x14 7. "R7T7,Read Receive FIFO Bit 7 Or Write Transmit FIFO Bit 7" "0,1" bitfld.long 0x14 6. "R6T6,Read Receive FIFO Bit 6 Or Write Transmit FIFO Bit 6" "0,1" newline bitfld.long 0x14 5. "R5T5,Read Receive FIFO Bit 5 Or Write Transmit FIFO Bit 5" "0,1" bitfld.long 0x14 4. "R4T4,Read Receive FIFO Bit 4 Or Write Transmit FIFO Bit 4" "0,1" newline bitfld.long 0x14 3. "R3T3,Read Receive FIFO Bit 3 Or Write Transmit FIFO Bit 3" "0,1" bitfld.long 0x14 2. "R2T2,Read Receive FIFO Bit 2 Or Write Transmit FIFO Bit 2" "0,1" newline bitfld.long 0x14 1. "R1T1,Read Receive FIFO Bit 1 Or Write Transmit FIFO Bit 1" "0,1" bitfld.long 0x14 0. "R0T0,Read Receive FIFO Bit 0 Or Write Transmit FIFO Bit 0" "0,1" line.long 0x18 "MATCH,Match Address" hexmask.long.word 0x18 16.--25. 1. "MA2,Match Address 2" hexmask.long.word 0x18 0.--9. 1. "MA1,Match Address 1" line.long 0x1C "MODIR,MODEM IrDA" bitfld.long 0x1C 18. "IREN,IR Enable" "0: Disables,1: Enables" bitfld.long 0x1C 16.--17. "TNP,Transmitter Narrow Pulse" "0: 1 / OSR,1: 2 / OSR,2: 3 / OSR,3: 4 / OSR" newline hexmask.long.byte 0x1C 8.--11. 1. "RTSWATER,Receive RTS Configuration" bitfld.long 0x1C 5. "TXCTSSRC,Transmit CTS Source" "0: The CTS_B pin,1: An internal connection to the receiver address.." newline bitfld.long 0x1C 4. "TXCTSC,Transmit CTS Configuration" "0: Sampled at the start of each character,1: Sampled when the transmitter is idle" bitfld.long 0x1C 3. "RXRTSE,Receiver RTS Enable" "0: Disables,1: Enables" newline bitfld.long 0x1C 2. "TXRTSPOL,Transmitter RTS Polarity" "0: Transmitter RTS is active low,1: Transmitter RTS is active high" bitfld.long 0x1C 1. "TXRTSE,Transmitter RTS Enable" "0: Disables,1: Enables" newline bitfld.long 0x1C 0. "TXCTSE,Transmitter CTS Enable" "0: Disables,1: Enables" line.long 0x20 "FIFO,FIFO" rbitfld.long 0x20 23. "TXEMPT,Transmit FIFO Or Buffer Empty" "0: Not empty,1: Empty" rbitfld.long 0x20 22. "RXEMPT,Receive FIFO Or Buffer Empty" "0: Not empty,1: Empty" newline eventfld.long 0x20 17. "TXOF,Transmitter FIFO Overflow Flag" "0: No overflow,1: Overflow" eventfld.long 0x20 16. "RXUF,Receiver FIFO Underflow Flag" "0: No underflow,1: Underflow" newline bitfld.long 0x20 15. "TXFLUSH,Transmit FIFO Flush" "0: No effect,1: All data is flushed out" bitfld.long 0x20 14. "RXFLUSH,Receive FIFO Flush" "0: No effect,1: All data is flushed out" newline bitfld.long 0x20 10.--12. "RXIDEN,Receiver Idle Empty Enable" "0: Disables STAT[RDRF] to become 1 because of..,1: Enables STAT[RDRF] to become 1 because of..,2: Enables STAT[RDRF] to become 1 because of..,3: Enables STAT[RDRF] to become 1 because of..,4: Enables STAT[RDRF] to become 1 because of..,5: Enables STAT[RDRF] to become 1 because of..,6: Enables STAT[RDRF] to become 1 because of..,7: Enables STAT[RDRF] to become 1 because of.." bitfld.long 0x20 9. "TXOFE,Transmit FIFO Overflow Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x20 8. "RXUFE,Receive FIFO Underflow Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x20 7. "TXFE,Transmit FIFO Enable" "0: Disables; buffer depth is 1,1: Enables; FIFO[TXFIFOSIZE] indicates the buffer.." newline rbitfld.long 0x20 4.--6. "TXFIFOSIZE,Transmit FIFO Buffer Depth" "0: Transmit FIFO buffer depth = 1 dataword,1: Transmit FIFO buffer depth = 4 datawords,2: Transmit FIFO buffer depth = 8 datawords,3: Transmit FIFO buffer depth = 16 datawords,4: Transmit FIFO buffer depth = 32 datawords,5: Transmit FIFO buffer depth = 64 datawords,6: Transmit FIFO buffer depth = 128 datawords,7: Transmit FIFO buffer depth = 256 datawords" bitfld.long 0x20 3. "RXFE,Receive FIFO Enable" "0: Disables; buffer depth is 1,1: Enables; FIFO[RXFIFOSIZE] indicates the buffer.." newline rbitfld.long 0x20 0.--2. "RXFIFOSIZE,Receive FIFO Buffer Depth" "0: Receive FIFO buffer depth = 1 dataword,1: Receive FIFO buffer depth = 4 datawords,2: Receive FIFO buffer depth = 8 datawords,3: Receive FIFO buffer depth = 16 datawords,4: Receive FIFO buffer depth = 32 datawords,5: Receive FIFO buffer depth = 64 datawords,6: Receive FIFO buffer depth = 128 datawords,7: Receive FIFO buffer depth = 256 datawords" line.long 0x24 "WATER,Watermark" hexmask.long.byte 0x24 24.--28. 1. "RXCOUNT,Receive Counter" hexmask.long.byte 0x24 16.--19. 1. "RXWATER,Receive Watermark" newline hexmask.long.byte 0x24 8.--12. 1. "TXCOUNT,Transmit Counter" hexmask.long.byte 0x24 0.--3. 1. "TXWATER,Transmit Watermark" rgroup.long 0x30++0x3 line.long 0x0 "DATARO,Data Read-Only" hexmask.long.word 0x0 0.--15. 1. "DATA,Receive Data" group.long 0x40++0x13 line.long 0x0 "MCR,MODEM Control" bitfld.long 0x0 9. "RTS,Request To Send" "0: Default state is logic one,1: Default state is logic zero" bitfld.long 0x0 8. "DTR,Data Terminal Ready" "0: Default state is logic one,1: Default state is logic zero" newline bitfld.long 0x0 3. "DCD,Data Carrier Detect" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x0 2. "RIN,Ring Indicator" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x0 1. "DSR,Data Set Ready" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x0 0. "CTS,Clear To Send" "0: Interrupt disabled,1: Interrupt enabled" line.long 0x4 "MSR,MODEM Status" rbitfld.long 0x4 7. "DCD,Data Carrier Detect" "0: The DCD_B pin is logic one,1: The DCD_B pin is logic zero" rbitfld.long 0x4 6. "RIN,Ring Indicator" "0: The RIN_B pin is logic one,1: The RIN_B pin is logic zero" newline rbitfld.long 0x4 5. "DSR,Data Set Ready" "0: The DSR_B pin is logic one,1: The DSR_B pin is logic zero" rbitfld.long 0x4 4. "CTS,Clear To Send" "0: The CTS_B pin is logic one,1: The CTS_B pin is logic zero" newline eventfld.long 0x4 3. "DDCD,Delta Data Carrier Detect" "0: Did not change state,1: Changed state" eventfld.long 0x4 2. "DRI,Delta Ring Indicator" "0: Did not change state,1: Changed state" newline eventfld.long 0x4 1. "DDSR,Delta Data Set Ready" "0: Did not change state,1: Changed state" eventfld.long 0x4 0. "DCTS,Delta Clear To Send" "0: Did not change state,1: Changed state" line.long 0x8 "REIR,Receiver Extended Idle" hexmask.long.word 0x8 0.--13. 1. "IDTIME,Idle Time" line.long 0xC "TEIR,Transmitter Extended Idle" hexmask.long.word 0xC 0.--13. 1. "IDTIME,Idle Time" line.long 0x10 "HDCR,Half Duplex Control" hexmask.long.byte 0x10 8.--15. 1. "RTSEXT,RTS Extended" bitfld.long 0x10 3. "RXMSK,Receive Mask" "0: Does not mask,1: Masks" newline bitfld.long 0x10 2. "RXWRMSK,Receive FIFO Write Mask" "0: Does not mask,1: Masks" bitfld.long 0x10 1. "RXSEL,Receive Select" "0: RXD,1: TXD" newline bitfld.long 0x10 0. "TXSTALL,Transmit Stall" "0: No effect,1: Does not become busy" group.long 0x58++0x7 line.long 0x0 "TOCR,Timeout Control" hexmask.long.byte 0x0 8.--11. 1. "TOIE,Timeout Interrupt Enable" hexmask.long.byte 0x0 0.--3. 1. "TOEN,Timeout Enable" line.long 0x4 "TOSR,Timeout Status" hexmask.long.byte 0x4 8.--11. 1. "TOF,Timeout Flag" hexmask.long.byte 0x4 0.--3. 1. "TOZ,Timeout Zero" repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x60)++0x3 line.long 0x0 "TIMEOUT[$1],Timeout N" bitfld.long 0x0 30.--31. "CFG,Idle Configuration" "0: Becomes 1 after timeout characters are received,1: Becomes 1 when idle for timeout bit clocks,2: Becomes 1 when idle for timeout bit clocks..,3: Becomes 1 when idle for at least timeout bit.." hexmask.long.word 0x0 0.--13. 1. "TIMEOUT,Timeout Value" repeat.end repeat 128. (increment 0x0 0x1)(increment 0x0 0x4) wgroup.long ($2+0x200)++0x3 line.long 0x0 "TCBR[$1],Transmit Command Burst" hexmask.long.word 0x0 0.--15. 1. "DATA,Data" repeat.end repeat 256. (increment 0x0 0x1)(increment 0x0 0x4) wgroup.long ($2+0x400)++0x3 line.long 0x0 "TDBR[$1],Transmit Data Burst" hexmask.long.byte 0x0 24.--31. 1. "DATA3,Data3" hexmask.long.byte 0x0 16.--23. 1. "DATA2,Data2" newline hexmask.long.byte 0x0 8.--15. 1. "DATA1,Data1" hexmask.long.byte 0x0 0.--7. 1. "DATA0,Data0" repeat.end tree.end tree "LPUART_2" base ad:0x40330000 rgroup.long 0x0++0x7 line.long 0x0 "VERID,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Identification Number" line.long 0x4 "PARAM,Parameter" hexmask.long.byte 0x4 8.--15. 1. "RXFIFO,Receive FIFO Size" hexmask.long.byte 0x4 0.--7. 1. "TXFIFO,Transmit FIFO Size" group.long 0x8++0x27 line.long 0x0 "GLOBAL,Global" bitfld.long 0x0 1. "RST,Software Reset" "0: Not reset,1: Reset" line.long 0x4 "PINCFG,Pin Configuration" bitfld.long 0x4 0.--1. "TRGSEL,Trigger Select" "0: Input trigger disabled,1: Input trigger used instead of the RXD pin input,2: Input trigger used instead of the CTS_B pin input,3: Input trigger used to modulate the TXD pin.." line.long 0x8 "BAUD,Baud Rate" bitfld.long 0x8 31. "MAEN1,Match Address Mode Enable 1" "0: Disables,1: Enables" bitfld.long 0x8 30. "MAEN2,Match Address Mode Enable 2" "0: Disables,1: Enables" newline bitfld.long 0x8 29. "M10,10-Bit Mode Select" "0: Receiver and transmitter use 7-bit to 9-bit data..,1: Receiver and transmitter use 10-bit data.." hexmask.long.byte 0x8 24.--28. 1. "OSR,Oversampling Ratio (OSR)" newline bitfld.long 0x8 23. "TDMAE,Transmitter DMA Enable" "0: Disables DMA request,1: Enables DMA request" bitfld.long 0x8 21. "RDMAE,Receiver Full DMA Enable" "0: Disables DMA request,1: Enables DMA request" newline bitfld.long 0x8 18.--19. "MATCFG,Match Configuration" "0: Address match wakeup,1: Idle match wakeup,2: Match on and match off,3: Enables RWU on data match and match on/off for.." bitfld.long 0x8 17. "BOTHEDGE,Both Edge Sampling" "0: Receiver samples input data using the rising..,1: Receiver samples input data using the rising and.." newline bitfld.long 0x8 16. "RESYNCDIS,Resynchronization Disable" "0: Enables resynchronization,1: Disables resynchronization" bitfld.long 0x8 15. "LBKDIE,LIN Break Detect Interrupt Enable" "0: Disables hardware interrupts from STAT[LBKDIF]..,1: Requests hardware interrupt when STAT[LBKDIF] is 1" newline bitfld.long 0x8 14. "RXEDGIE,RX Input Active Edge Interrupt Enable" "0: Disables hardware interrupts from STAT[RXEDGIF],1: Requests hardware interrupts when STAT[RXEDGIF].." bitfld.long 0x8 13. "SBNS,Stop Bit Number Select" "0: One stop bit,1: Two stop bits" newline hexmask.long.word 0x8 0.--12. 1. "SBR,Baud Rate Modulo Divisor" line.long 0xC "STAT,Status" eventfld.long 0xC 31. "LBKDIF,LIN Break Detect Interrupt Flag" "0: Not detected,1: Detected" eventfld.long 0xC 30. "RXEDGIF,RXD Pin Active Edge Interrupt Flag" "0: Not occurred,1: Occurred" newline bitfld.long 0xC 29. "MSBF,MSB First" "0: LSB,1: MSB" bitfld.long 0xC 28. "RXINV,Receive Data Inversion" "0: Inverted,1: Not inverted" newline bitfld.long 0xC 27. "RWUID,Receive Wake Up Idle Detect" "0: STAT[IDLE] does not become 1,1: STAT[IDLE] becomes 1" bitfld.long 0xC 26. "BRK13,Break Character Generation Length" "0: 9 to 13 bit times,1: 12 to 15 bit times" newline bitfld.long 0xC 25. "LBKDE,LIN Break Detection Enable" "0: Disables,1: Enables" rbitfld.long 0xC 24. "RAF,Receiver Active Flag" "0: Idle waiting for a start bit,1: Receiver active (RXD pin input not idle)" newline rbitfld.long 0xC 23. "TDRE,Transmit Data Register Empty Flag" "0: Greater than watermark,1: Equal to or less than watermark" rbitfld.long 0xC 22. "TC,Transmission Complete Flag" "0: Transmitter active (sending data a preamble or a..,1: Transmitter idle (transmission activity complete)" newline rbitfld.long 0xC 21. "RDRF,Receive Data Register Full Flag" "0: Equal to or less than watermark,1: Greater than watermark" eventfld.long 0xC 20. "IDLE,Idle Line Flag" "0: No idle line detected,1: Idle line detected" newline eventfld.long 0xC 19. "OR,Receiver Overrun Flag" "0: No overrun,1: Receive overrun (new LPUART data lost)" eventfld.long 0xC 18. "NF,Noise Flag (NF)" "0: No noise detected,1: Noise detected" newline eventfld.long 0xC 17. "FE,Framing Error Flag (FE)" "0: No framing error detected (this does not..,1: Framing error detected" eventfld.long 0xC 16. "PF,Parity Error Flag (PF)" "0: No parity error detected,1: Parity error detected" newline eventfld.long 0xC 15. "MA1F,Match 1 Flag" "0: Not equal to MA1,1: Equal to MA1" eventfld.long 0xC 14. "MA2F,Match 2 Flag" "0: Not equal to MA2,1: Equal to MA2" newline bitfld.long 0xC 1. "AME,Address Mark Enable" "0: Address mark in character is MSB,1: Address mark in character is the last bit before.." bitfld.long 0xC 0. "LBKFE,LIN Break Flag Enable" "0: Disables LIN break detect,1: Enables LIN break detect" line.long 0x10 "CTRL,Control" bitfld.long 0x10 31. "R8T9,Receive Bit 8 Transmit Bit 9" "0,1" bitfld.long 0x10 30. "R9T8,Receive Bit 9 Transmit Bit 8" "0,1" newline bitfld.long 0x10 29. "TXDIR,TXD Pin Direction in Single-Wire Mode" "0: TXD pin is an input in Single-Wire mode,1: TXD pin is an output in Single-Wire mode" bitfld.long 0x10 28. "TXINV,Transmit Data Inversion" "0: Not inverted,1: Inverted" newline bitfld.long 0x10 27. "ORIE,Overrun Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 26. "NEIE,Noise Error Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 25. "FEIE,Framing Error Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 24. "PEIE,Parity Error Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 23. "TIE,Transmit Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 22. "TCIE,Transmission Complete Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 21. "RIE,Receiver Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 20. "ILIE,Idle Line Interrupt Enable" "0: Disables hardware interrupts from STAT[IDLE];..,1: Enables hardware interrupts when STAT[IDLE] = 1" newline bitfld.long 0x10 19. "TE,Transmitter Enable" "0: Disables,1: Enables" bitfld.long 0x10 18. "RE,Receiver Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 17. "RWU,Receiver Wakeup Control" "0: Normal receiver operation,1: LPUART receiver in standby waiting for a wakeup.." bitfld.long 0x10 16. "SBK,Send Break" "0: Normal transmitter operation,1: Queue break character(s) to be sent" newline bitfld.long 0x10 15. "MA1IE,Match 1 (MA1F) Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 14. "MA2IE,Match 2 (MA2F) Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 11. "M7,7-Bit Mode Select" "0: 8-bit to 10-bit data characters,1: 7-bit data characters" bitfld.long 0x10 8.--10. "IDLECFG,Idle Configuration" "0: 1,1: 2,2: 4,3: 8,4: 16,5: 32,6: 64,7: 128" newline bitfld.long 0x10 7. "LOOPS,Loop Mode Select" "0: Normal operation: RXD and TXD use separate pins,1: Loop mode or Single-Wire mode" bitfld.long 0x10 6. "DOZEEN,Enables LPUART in Doze mode." "0: Enables,1: Disables" newline bitfld.long 0x10 5. "RSRC,Receiver Source Select" "0: Internal Loopback mode,1: Single-wire mode" bitfld.long 0x10 4. "M,9-Bit Or 8-Bit Mode Select" "0: 8-bit data characters,1: 9-bit data characters" newline bitfld.long 0x10 3. "WAKE,Receiver Wakeup Method Select" "0: Configures CTRL[RWU] for idle-line wakeup,1: Configures CTRL[RWU] with address-mark wakeup" bitfld.long 0x10 2. "ILT,Idle Line Type Select" "0: After the start bit,1: After the stop bit" newline bitfld.long 0x10 1. "PE,Parity Enable" "0: Disables,1: Enables" bitfld.long 0x10 0. "PT,Parity Type" "0: Even parity,1: Odd parity" line.long 0x14 "DATA,Data" rbitfld.long 0x14 15. "NOISY,Noisy Data Received" "0: Received without noise,1: Received with noise" rbitfld.long 0x14 14. "PARITYE,Parity Error" "0: Received without a parity error,1: Received with a parity error" newline bitfld.long 0x14 13. "FRETSC,Frame Error Transmit Special Character" "0: Received without a frame error on reads or..,1: Received with a frame error on reads or.." rbitfld.long 0x14 12. "RXEMPT,Receive Buffer Empty" "0: Contains valid data,1: Contains invalid data and is empty" newline rbitfld.long 0x14 11. "IDLINE,Idle Line" "0: Received was not idle,1: Receiver was idle" rbitfld.long 0x14 10. "LINBRK,LIN Break" "0: LIN break not detected or LIN break detect..,1: LIN break detected" newline bitfld.long 0x14 9. "R9T9,Read Receive FIFO Bit 9 Or Write Transmit FIFO Bit 9" "0,1" bitfld.long 0x14 8. "R8T8,Read Receive FIFO Bit 8 Or Write Transmit FIFO Bit 8" "0,1" newline bitfld.long 0x14 7. "R7T7,Read Receive FIFO Bit 7 Or Write Transmit FIFO Bit 7" "0,1" bitfld.long 0x14 6. "R6T6,Read Receive FIFO Bit 6 Or Write Transmit FIFO Bit 6" "0,1" newline bitfld.long 0x14 5. "R5T5,Read Receive FIFO Bit 5 Or Write Transmit FIFO Bit 5" "0,1" bitfld.long 0x14 4. "R4T4,Read Receive FIFO Bit 4 Or Write Transmit FIFO Bit 4" "0,1" newline bitfld.long 0x14 3. "R3T3,Read Receive FIFO Bit 3 Or Write Transmit FIFO Bit 3" "0,1" bitfld.long 0x14 2. "R2T2,Read Receive FIFO Bit 2 Or Write Transmit FIFO Bit 2" "0,1" newline bitfld.long 0x14 1. "R1T1,Read Receive FIFO Bit 1 Or Write Transmit FIFO Bit 1" "0,1" bitfld.long 0x14 0. "R0T0,Read Receive FIFO Bit 0 Or Write Transmit FIFO Bit 0" "0,1" line.long 0x18 "MATCH,Match Address" hexmask.long.word 0x18 16.--25. 1. "MA2,Match Address 2" hexmask.long.word 0x18 0.--9. 1. "MA1,Match Address 1" line.long 0x1C "MODIR,MODEM IrDA" bitfld.long 0x1C 18. "IREN,IR Enable" "0: Disables,1: Enables" bitfld.long 0x1C 16.--17. "TNP,Transmitter Narrow Pulse" "0: 1 / OSR,1: 2 / OSR,2: 3 / OSR,3: 4 / OSR" newline bitfld.long 0x1C 8.--9. "RTSWATER,Receive RTS Configuration" "0,1,2,3" bitfld.long 0x1C 5. "TXCTSSRC,Transmit CTS Source" "0: The CTS_B pin,1: An internal connection to the receiver address.." newline bitfld.long 0x1C 4. "TXCTSC,Transmit CTS Configuration" "0: Sampled at the start of each character,1: Sampled when the transmitter is idle" bitfld.long 0x1C 3. "RXRTSE,Receiver RTS Enable" "0: Disables,1: Enables" newline bitfld.long 0x1C 2. "TXRTSPOL,Transmitter RTS Polarity" "0: Transmitter RTS is active low,1: Transmitter RTS is active high" bitfld.long 0x1C 1. "TXRTSE,Transmitter RTS Enable" "0: Disables,1: Enables" newline bitfld.long 0x1C 0. "TXCTSE,Transmitter CTS Enable" "0: Disables,1: Enables" line.long 0x20 "FIFO,FIFO" rbitfld.long 0x20 23. "TXEMPT,Transmit FIFO Or Buffer Empty" "0: Not empty,1: Empty" rbitfld.long 0x20 22. "RXEMPT,Receive FIFO Or Buffer Empty" "0: Not empty,1: Empty" newline eventfld.long 0x20 17. "TXOF,Transmitter FIFO Overflow Flag" "0: No overflow,1: Overflow" eventfld.long 0x20 16. "RXUF,Receiver FIFO Underflow Flag" "0: No underflow,1: Underflow" newline bitfld.long 0x20 15. "TXFLUSH,Transmit FIFO Flush" "0: No effect,1: All data is flushed out" bitfld.long 0x20 14. "RXFLUSH,Receive FIFO Flush" "0: No effect,1: All data is flushed out" newline bitfld.long 0x20 10.--12. "RXIDEN,Receiver Idle Empty Enable" "0: Disables STAT[RDRF] to become 1 because of..,1: Enables STAT[RDRF] to become 1 because of..,2: Enables STAT[RDRF] to become 1 because of..,3: Enables STAT[RDRF] to become 1 because of..,4: Enables STAT[RDRF] to become 1 because of..,5: Enables STAT[RDRF] to become 1 because of..,6: Enables STAT[RDRF] to become 1 because of..,7: Enables STAT[RDRF] to become 1 because of.." bitfld.long 0x20 9. "TXOFE,Transmit FIFO Overflow Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x20 8. "RXUFE,Receive FIFO Underflow Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x20 7. "TXFE,Transmit FIFO Enable" "0: Disables; buffer depth is 1,1: Enables; FIFO[TXFIFOSIZE] indicates the buffer.." newline rbitfld.long 0x20 4.--6. "TXFIFOSIZE,Transmit FIFO Buffer Depth" "0: Transmit FIFO buffer depth = 1 dataword,1: Transmit FIFO buffer depth = 4 datawords,2: Transmit FIFO buffer depth = 8 datawords,3: Transmit FIFO buffer depth = 16 datawords,4: Transmit FIFO buffer depth = 32 datawords,5: Transmit FIFO buffer depth = 64 datawords,6: Transmit FIFO buffer depth = 128 datawords,7: Transmit FIFO buffer depth = 256 datawords" bitfld.long 0x20 3. "RXFE,Receive FIFO Enable" "0: Disables; buffer depth is 1,1: Enables; FIFO[RXFIFOSIZE] indicates the buffer.." newline rbitfld.long 0x20 0.--2. "RXFIFOSIZE,Receive FIFO Buffer Depth" "0: Receive FIFO buffer depth = 1 dataword,1: Receive FIFO buffer depth = 4 datawords,2: Receive FIFO buffer depth = 8 datawords,3: Receive FIFO buffer depth = 16 datawords,4: Receive FIFO buffer depth = 32 datawords,5: Receive FIFO buffer depth = 64 datawords,6: Receive FIFO buffer depth = 128 datawords,7: Receive FIFO buffer depth = 256 datawords" line.long 0x24 "WATER,Watermark" rbitfld.long 0x24 24.--26. "RXCOUNT,Receive Counter" "0,1,2,3,4,5,6,7" bitfld.long 0x24 16.--17. "RXWATER,Receive Watermark" "0,1,2,3" newline rbitfld.long 0x24 8.--10. "TXCOUNT,Transmit Counter" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0.--1. "TXWATER,Transmit Watermark" "0,1,2,3" rgroup.long 0x30++0x3 line.long 0x0 "DATARO,Data Read-Only" hexmask.long.word 0x0 0.--15. 1. "DATA,Receive Data" tree.end tree "LPUART_3" base ad:0x40334000 rgroup.long 0x0++0x7 line.long 0x0 "VERID,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Identification Number" line.long 0x4 "PARAM,Parameter" hexmask.long.byte 0x4 8.--15. 1. "RXFIFO,Receive FIFO Size" hexmask.long.byte 0x4 0.--7. 1. "TXFIFO,Transmit FIFO Size" group.long 0x8++0x27 line.long 0x0 "GLOBAL,Global" bitfld.long 0x0 1. "RST,Software Reset" "0: Not reset,1: Reset" line.long 0x4 "PINCFG,Pin Configuration" bitfld.long 0x4 0.--1. "TRGSEL,Trigger Select" "0: Input trigger disabled,1: Input trigger used instead of the RXD pin input,2: Input trigger used instead of the CTS_B pin input,3: Input trigger used to modulate the TXD pin.." line.long 0x8 "BAUD,Baud Rate" bitfld.long 0x8 31. "MAEN1,Match Address Mode Enable 1" "0: Disables,1: Enables" bitfld.long 0x8 30. "MAEN2,Match Address Mode Enable 2" "0: Disables,1: Enables" newline bitfld.long 0x8 29. "M10,10-Bit Mode Select" "0: Receiver and transmitter use 7-bit to 9-bit data..,1: Receiver and transmitter use 10-bit data.." hexmask.long.byte 0x8 24.--28. 1. "OSR,Oversampling Ratio (OSR)" newline bitfld.long 0x8 23. "TDMAE,Transmitter DMA Enable" "0: Disables DMA request,1: Enables DMA request" bitfld.long 0x8 21. "RDMAE,Receiver Full DMA Enable" "0: Disables DMA request,1: Enables DMA request" newline bitfld.long 0x8 18.--19. "MATCFG,Match Configuration" "0: Address match wakeup,1: Idle match wakeup,2: Match on and match off,3: Enables RWU on data match and match on/off for.." bitfld.long 0x8 17. "BOTHEDGE,Both Edge Sampling" "0: Receiver samples input data using the rising..,1: Receiver samples input data using the rising and.." newline bitfld.long 0x8 16. "RESYNCDIS,Resynchronization Disable" "0: Enables resynchronization,1: Disables resynchronization" bitfld.long 0x8 15. "LBKDIE,LIN Break Detect Interrupt Enable" "0: Disables hardware interrupts from STAT[LBKDIF]..,1: Requests hardware interrupt when STAT[LBKDIF] is 1" newline bitfld.long 0x8 14. "RXEDGIE,RX Input Active Edge Interrupt Enable" "0: Disables hardware interrupts from STAT[RXEDGIF],1: Requests hardware interrupts when STAT[RXEDGIF].." bitfld.long 0x8 13. "SBNS,Stop Bit Number Select" "0: One stop bit,1: Two stop bits" newline hexmask.long.word 0x8 0.--12. 1. "SBR,Baud Rate Modulo Divisor" line.long 0xC "STAT,Status" eventfld.long 0xC 31. "LBKDIF,LIN Break Detect Interrupt Flag" "0: Not detected,1: Detected" eventfld.long 0xC 30. "RXEDGIF,RXD Pin Active Edge Interrupt Flag" "0: Not occurred,1: Occurred" newline bitfld.long 0xC 29. "MSBF,MSB First" "0: LSB,1: MSB" bitfld.long 0xC 28. "RXINV,Receive Data Inversion" "0: Inverted,1: Not inverted" newline bitfld.long 0xC 27. "RWUID,Receive Wake Up Idle Detect" "0: STAT[IDLE] does not become 1,1: STAT[IDLE] becomes 1" bitfld.long 0xC 26. "BRK13,Break Character Generation Length" "0: 9 to 13 bit times,1: 12 to 15 bit times" newline bitfld.long 0xC 25. "LBKDE,LIN Break Detection Enable" "0: Disables,1: Enables" rbitfld.long 0xC 24. "RAF,Receiver Active Flag" "0: Idle waiting for a start bit,1: Receiver active (RXD pin input not idle)" newline rbitfld.long 0xC 23. "TDRE,Transmit Data Register Empty Flag" "0: Greater than watermark,1: Equal to or less than watermark" rbitfld.long 0xC 22. "TC,Transmission Complete Flag" "0: Transmitter active (sending data a preamble or a..,1: Transmitter idle (transmission activity complete)" newline rbitfld.long 0xC 21. "RDRF,Receive Data Register Full Flag" "0: Equal to or less than watermark,1: Greater than watermark" eventfld.long 0xC 20. "IDLE,Idle Line Flag" "0: No idle line detected,1: Idle line detected" newline eventfld.long 0xC 19. "OR,Receiver Overrun Flag" "0: No overrun,1: Receive overrun (new LPUART data lost)" eventfld.long 0xC 18. "NF,Noise Flag (NF)" "0: No noise detected,1: Noise detected" newline eventfld.long 0xC 17. "FE,Framing Error Flag (FE)" "0: No framing error detected (this does not..,1: Framing error detected" eventfld.long 0xC 16. "PF,Parity Error Flag (PF)" "0: No parity error detected,1: Parity error detected" newline eventfld.long 0xC 15. "MA1F,Match 1 Flag" "0: Not equal to MA1,1: Equal to MA1" eventfld.long 0xC 14. "MA2F,Match 2 Flag" "0: Not equal to MA2,1: Equal to MA2" newline bitfld.long 0xC 1. "AME,Address Mark Enable" "0: Address mark in character is MSB,1: Address mark in character is the last bit before.." bitfld.long 0xC 0. "LBKFE,LIN Break Flag Enable" "0: Disables LIN break detect,1: Enables LIN break detect" line.long 0x10 "CTRL,Control" bitfld.long 0x10 31. "R8T9,Receive Bit 8 Transmit Bit 9" "0,1" bitfld.long 0x10 30. "R9T8,Receive Bit 9 Transmit Bit 8" "0,1" newline bitfld.long 0x10 29. "TXDIR,TXD Pin Direction in Single-Wire Mode" "0: TXD pin is an input in Single-Wire mode,1: TXD pin is an output in Single-Wire mode" bitfld.long 0x10 28. "TXINV,Transmit Data Inversion" "0: Not inverted,1: Inverted" newline bitfld.long 0x10 27. "ORIE,Overrun Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 26. "NEIE,Noise Error Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 25. "FEIE,Framing Error Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 24. "PEIE,Parity Error Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 23. "TIE,Transmit Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 22. "TCIE,Transmission Complete Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 21. "RIE,Receiver Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 20. "ILIE,Idle Line Interrupt Enable" "0: Disables hardware interrupts from STAT[IDLE];..,1: Enables hardware interrupts when STAT[IDLE] = 1" newline bitfld.long 0x10 19. "TE,Transmitter Enable" "0: Disables,1: Enables" bitfld.long 0x10 18. "RE,Receiver Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 17. "RWU,Receiver Wakeup Control" "0: Normal receiver operation,1: LPUART receiver in standby waiting for a wakeup.." bitfld.long 0x10 16. "SBK,Send Break" "0: Normal transmitter operation,1: Queue break character(s) to be sent" newline bitfld.long 0x10 15. "MA1IE,Match 1 (MA1F) Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 14. "MA2IE,Match 2 (MA2F) Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 11. "M7,7-Bit Mode Select" "0: 8-bit to 10-bit data characters,1: 7-bit data characters" bitfld.long 0x10 8.--10. "IDLECFG,Idle Configuration" "0: 1,1: 2,2: 4,3: 8,4: 16,5: 32,6: 64,7: 128" newline bitfld.long 0x10 7. "LOOPS,Loop Mode Select" "0: Normal operation: RXD and TXD use separate pins,1: Loop mode or Single-Wire mode" bitfld.long 0x10 6. "DOZEEN,Enables LPUART in Doze mode." "0: Enables,1: Disables" newline bitfld.long 0x10 5. "RSRC,Receiver Source Select" "0: Internal Loopback mode,1: Single-wire mode" bitfld.long 0x10 4. "M,9-Bit Or 8-Bit Mode Select" "0: 8-bit data characters,1: 9-bit data characters" newline bitfld.long 0x10 3. "WAKE,Receiver Wakeup Method Select" "0: Configures CTRL[RWU] for idle-line wakeup,1: Configures CTRL[RWU] with address-mark wakeup" bitfld.long 0x10 2. "ILT,Idle Line Type Select" "0: After the start bit,1: After the stop bit" newline bitfld.long 0x10 1. "PE,Parity Enable" "0: Disables,1: Enables" bitfld.long 0x10 0. "PT,Parity Type" "0: Even parity,1: Odd parity" line.long 0x14 "DATA,Data" rbitfld.long 0x14 15. "NOISY,Noisy Data Received" "0: Received without noise,1: Received with noise" rbitfld.long 0x14 14. "PARITYE,Parity Error" "0: Received without a parity error,1: Received with a parity error" newline bitfld.long 0x14 13. "FRETSC,Frame Error Transmit Special Character" "0: Received without a frame error on reads or..,1: Received with a frame error on reads or.." rbitfld.long 0x14 12. "RXEMPT,Receive Buffer Empty" "0: Contains valid data,1: Contains invalid data and is empty" newline rbitfld.long 0x14 11. "IDLINE,Idle Line" "0: Received was not idle,1: Receiver was idle" rbitfld.long 0x14 10. "LINBRK,LIN Break" "0: LIN break not detected or LIN break detect..,1: LIN break detected" newline bitfld.long 0x14 9. "R9T9,Read Receive FIFO Bit 9 Or Write Transmit FIFO Bit 9" "0,1" bitfld.long 0x14 8. "R8T8,Read Receive FIFO Bit 8 Or Write Transmit FIFO Bit 8" "0,1" newline bitfld.long 0x14 7. "R7T7,Read Receive FIFO Bit 7 Or Write Transmit FIFO Bit 7" "0,1" bitfld.long 0x14 6. "R6T6,Read Receive FIFO Bit 6 Or Write Transmit FIFO Bit 6" "0,1" newline bitfld.long 0x14 5. "R5T5,Read Receive FIFO Bit 5 Or Write Transmit FIFO Bit 5" "0,1" bitfld.long 0x14 4. "R4T4,Read Receive FIFO Bit 4 Or Write Transmit FIFO Bit 4" "0,1" newline bitfld.long 0x14 3. "R3T3,Read Receive FIFO Bit 3 Or Write Transmit FIFO Bit 3" "0,1" bitfld.long 0x14 2. "R2T2,Read Receive FIFO Bit 2 Or Write Transmit FIFO Bit 2" "0,1" newline bitfld.long 0x14 1. "R1T1,Read Receive FIFO Bit 1 Or Write Transmit FIFO Bit 1" "0,1" bitfld.long 0x14 0. "R0T0,Read Receive FIFO Bit 0 Or Write Transmit FIFO Bit 0" "0,1" line.long 0x18 "MATCH,Match Address" hexmask.long.word 0x18 16.--25. 1. "MA2,Match Address 2" hexmask.long.word 0x18 0.--9. 1. "MA1,Match Address 1" line.long 0x1C "MODIR,MODEM IrDA" bitfld.long 0x1C 18. "IREN,IR Enable" "0: Disables,1: Enables" bitfld.long 0x1C 16.--17. "TNP,Transmitter Narrow Pulse" "0: 1 / OSR,1: 2 / OSR,2: 3 / OSR,3: 4 / OSR" newline bitfld.long 0x1C 8.--9. "RTSWATER,Receive RTS Configuration" "0,1,2,3" bitfld.long 0x1C 5. "TXCTSSRC,Transmit CTS Source" "0: The CTS_B pin,1: An internal connection to the receiver address.." newline bitfld.long 0x1C 4. "TXCTSC,Transmit CTS Configuration" "0: Sampled at the start of each character,1: Sampled when the transmitter is idle" bitfld.long 0x1C 3. "RXRTSE,Receiver RTS Enable" "0: Disables,1: Enables" newline bitfld.long 0x1C 2. "TXRTSPOL,Transmitter RTS Polarity" "0: Transmitter RTS is active low,1: Transmitter RTS is active high" bitfld.long 0x1C 1. "TXRTSE,Transmitter RTS Enable" "0: Disables,1: Enables" newline bitfld.long 0x1C 0. "TXCTSE,Transmitter CTS Enable" "0: Disables,1: Enables" line.long 0x20 "FIFO,FIFO" rbitfld.long 0x20 23. "TXEMPT,Transmit FIFO Or Buffer Empty" "0: Not empty,1: Empty" rbitfld.long 0x20 22. "RXEMPT,Receive FIFO Or Buffer Empty" "0: Not empty,1: Empty" newline eventfld.long 0x20 17. "TXOF,Transmitter FIFO Overflow Flag" "0: No overflow,1: Overflow" eventfld.long 0x20 16. "RXUF,Receiver FIFO Underflow Flag" "0: No underflow,1: Underflow" newline bitfld.long 0x20 15. "TXFLUSH,Transmit FIFO Flush" "0: No effect,1: All data is flushed out" bitfld.long 0x20 14. "RXFLUSH,Receive FIFO Flush" "0: No effect,1: All data is flushed out" newline bitfld.long 0x20 10.--12. "RXIDEN,Receiver Idle Empty Enable" "0: Disables STAT[RDRF] to become 1 because of..,1: Enables STAT[RDRF] to become 1 because of..,2: Enables STAT[RDRF] to become 1 because of..,3: Enables STAT[RDRF] to become 1 because of..,4: Enables STAT[RDRF] to become 1 because of..,5: Enables STAT[RDRF] to become 1 because of..,6: Enables STAT[RDRF] to become 1 because of..,7: Enables STAT[RDRF] to become 1 because of.." bitfld.long 0x20 9. "TXOFE,Transmit FIFO Overflow Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x20 8. "RXUFE,Receive FIFO Underflow Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x20 7. "TXFE,Transmit FIFO Enable" "0: Disables; buffer depth is 1,1: Enables; FIFO[TXFIFOSIZE] indicates the buffer.." newline rbitfld.long 0x20 4.--6. "TXFIFOSIZE,Transmit FIFO Buffer Depth" "0: Transmit FIFO buffer depth = 1 dataword,1: Transmit FIFO buffer depth = 4 datawords,2: Transmit FIFO buffer depth = 8 datawords,3: Transmit FIFO buffer depth = 16 datawords,4: Transmit FIFO buffer depth = 32 datawords,5: Transmit FIFO buffer depth = 64 datawords,6: Transmit FIFO buffer depth = 128 datawords,7: Transmit FIFO buffer depth = 256 datawords" bitfld.long 0x20 3. "RXFE,Receive FIFO Enable" "0: Disables; buffer depth is 1,1: Enables; FIFO[RXFIFOSIZE] indicates the buffer.." newline rbitfld.long 0x20 0.--2. "RXFIFOSIZE,Receive FIFO Buffer Depth" "0: Receive FIFO buffer depth = 1 dataword,1: Receive FIFO buffer depth = 4 datawords,2: Receive FIFO buffer depth = 8 datawords,3: Receive FIFO buffer depth = 16 datawords,4: Receive FIFO buffer depth = 32 datawords,5: Receive FIFO buffer depth = 64 datawords,6: Receive FIFO buffer depth = 128 datawords,7: Receive FIFO buffer depth = 256 datawords" line.long 0x24 "WATER,Watermark" rbitfld.long 0x24 24.--26. "RXCOUNT,Receive Counter" "0,1,2,3,4,5,6,7" bitfld.long 0x24 16.--17. "RXWATER,Receive Watermark" "0,1,2,3" newline rbitfld.long 0x24 8.--10. "TXCOUNT,Transmit Counter" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0.--1. "TXWATER,Transmit Watermark" "0,1,2,3" rgroup.long 0x30++0x3 line.long 0x0 "DATARO,Data Read-Only" hexmask.long.word 0x0 0.--15. 1. "DATA,Receive Data" tree.end tree "LPUART_4" base ad:0x40338000 rgroup.long 0x0++0x7 line.long 0x0 "VERID,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Identification Number" line.long 0x4 "PARAM,Parameter" hexmask.long.byte 0x4 8.--15. 1. "RXFIFO,Receive FIFO Size" hexmask.long.byte 0x4 0.--7. 1. "TXFIFO,Transmit FIFO Size" group.long 0x8++0x27 line.long 0x0 "GLOBAL,Global" bitfld.long 0x0 1. "RST,Software Reset" "0: Not reset,1: Reset" line.long 0x4 "PINCFG,Pin Configuration" bitfld.long 0x4 0.--1. "TRGSEL,Trigger Select" "0: Input trigger disabled,1: Input trigger used instead of the RXD pin input,2: Input trigger used instead of the CTS_B pin input,3: Input trigger used to modulate the TXD pin.." line.long 0x8 "BAUD,Baud Rate" bitfld.long 0x8 31. "MAEN1,Match Address Mode Enable 1" "0: Disables,1: Enables" bitfld.long 0x8 30. "MAEN2,Match Address Mode Enable 2" "0: Disables,1: Enables" newline bitfld.long 0x8 29. "M10,10-Bit Mode Select" "0: Receiver and transmitter use 7-bit to 9-bit data..,1: Receiver and transmitter use 10-bit data.." hexmask.long.byte 0x8 24.--28. 1. "OSR,Oversampling Ratio (OSR)" newline bitfld.long 0x8 23. "TDMAE,Transmitter DMA Enable" "0: Disables DMA request,1: Enables DMA request" bitfld.long 0x8 21. "RDMAE,Receiver Full DMA Enable" "0: Disables DMA request,1: Enables DMA request" newline bitfld.long 0x8 18.--19. "MATCFG,Match Configuration" "0: Address match wakeup,1: Idle match wakeup,2: Match on and match off,3: Enables RWU on data match and match on/off for.." bitfld.long 0x8 17. "BOTHEDGE,Both Edge Sampling" "0: Receiver samples input data using the rising..,1: Receiver samples input data using the rising and.." newline bitfld.long 0x8 16. "RESYNCDIS,Resynchronization Disable" "0: Enables resynchronization,1: Disables resynchronization" bitfld.long 0x8 15. "LBKDIE,LIN Break Detect Interrupt Enable" "0: Disables hardware interrupts from STAT[LBKDIF]..,1: Requests hardware interrupt when STAT[LBKDIF] is 1" newline bitfld.long 0x8 14. "RXEDGIE,RX Input Active Edge Interrupt Enable" "0: Disables hardware interrupts from STAT[RXEDGIF],1: Requests hardware interrupts when STAT[RXEDGIF].." bitfld.long 0x8 13. "SBNS,Stop Bit Number Select" "0: One stop bit,1: Two stop bits" newline hexmask.long.word 0x8 0.--12. 1. "SBR,Baud Rate Modulo Divisor" line.long 0xC "STAT,Status" eventfld.long 0xC 31. "LBKDIF,LIN Break Detect Interrupt Flag" "0: Not detected,1: Detected" eventfld.long 0xC 30. "RXEDGIF,RXD Pin Active Edge Interrupt Flag" "0: Not occurred,1: Occurred" newline bitfld.long 0xC 29. "MSBF,MSB First" "0: LSB,1: MSB" bitfld.long 0xC 28. "RXINV,Receive Data Inversion" "0: Inverted,1: Not inverted" newline bitfld.long 0xC 27. "RWUID,Receive Wake Up Idle Detect" "0: STAT[IDLE] does not become 1,1: STAT[IDLE] becomes 1" bitfld.long 0xC 26. "BRK13,Break Character Generation Length" "0: 9 to 13 bit times,1: 12 to 15 bit times" newline bitfld.long 0xC 25. "LBKDE,LIN Break Detection Enable" "0: Disables,1: Enables" rbitfld.long 0xC 24. "RAF,Receiver Active Flag" "0: Idle waiting for a start bit,1: Receiver active (RXD pin input not idle)" newline rbitfld.long 0xC 23. "TDRE,Transmit Data Register Empty Flag" "0: Greater than watermark,1: Equal to or less than watermark" rbitfld.long 0xC 22. "TC,Transmission Complete Flag" "0: Transmitter active (sending data a preamble or a..,1: Transmitter idle (transmission activity complete)" newline rbitfld.long 0xC 21. "RDRF,Receive Data Register Full Flag" "0: Equal to or less than watermark,1: Greater than watermark" eventfld.long 0xC 20. "IDLE,Idle Line Flag" "0: No idle line detected,1: Idle line detected" newline eventfld.long 0xC 19. "OR,Receiver Overrun Flag" "0: No overrun,1: Receive overrun (new LPUART data lost)" eventfld.long 0xC 18. "NF,Noise Flag (NF)" "0: No noise detected,1: Noise detected" newline eventfld.long 0xC 17. "FE,Framing Error Flag (FE)" "0: No framing error detected (this does not..,1: Framing error detected" eventfld.long 0xC 16. "PF,Parity Error Flag (PF)" "0: No parity error detected,1: Parity error detected" newline eventfld.long 0xC 15. "MA1F,Match 1 Flag" "0: Not equal to MA1,1: Equal to MA1" eventfld.long 0xC 14. "MA2F,Match 2 Flag" "0: Not equal to MA2,1: Equal to MA2" newline bitfld.long 0xC 1. "AME,Address Mark Enable" "0: Address mark in character is MSB,1: Address mark in character is the last bit before.." bitfld.long 0xC 0. "LBKFE,LIN Break Flag Enable" "0: Disables LIN break detect,1: Enables LIN break detect" line.long 0x10 "CTRL,Control" bitfld.long 0x10 31. "R8T9,Receive Bit 8 Transmit Bit 9" "0,1" bitfld.long 0x10 30. "R9T8,Receive Bit 9 Transmit Bit 8" "0,1" newline bitfld.long 0x10 29. "TXDIR,TXD Pin Direction in Single-Wire Mode" "0: TXD pin is an input in Single-Wire mode,1: TXD pin is an output in Single-Wire mode" bitfld.long 0x10 28. "TXINV,Transmit Data Inversion" "0: Not inverted,1: Inverted" newline bitfld.long 0x10 27. "ORIE,Overrun Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 26. "NEIE,Noise Error Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 25. "FEIE,Framing Error Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 24. "PEIE,Parity Error Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 23. "TIE,Transmit Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 22. "TCIE,Transmission Complete Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 21. "RIE,Receiver Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 20. "ILIE,Idle Line Interrupt Enable" "0: Disables hardware interrupts from STAT[IDLE];..,1: Enables hardware interrupts when STAT[IDLE] = 1" newline bitfld.long 0x10 19. "TE,Transmitter Enable" "0: Disables,1: Enables" bitfld.long 0x10 18. "RE,Receiver Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 17. "RWU,Receiver Wakeup Control" "0: Normal receiver operation,1: LPUART receiver in standby waiting for a wakeup.." bitfld.long 0x10 16. "SBK,Send Break" "0: Normal transmitter operation,1: Queue break character(s) to be sent" newline bitfld.long 0x10 15. "MA1IE,Match 1 (MA1F) Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 14. "MA2IE,Match 2 (MA2F) Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 11. "M7,7-Bit Mode Select" "0: 8-bit to 10-bit data characters,1: 7-bit data characters" bitfld.long 0x10 8.--10. "IDLECFG,Idle Configuration" "0: 1,1: 2,2: 4,3: 8,4: 16,5: 32,6: 64,7: 128" newline bitfld.long 0x10 7. "LOOPS,Loop Mode Select" "0: Normal operation: RXD and TXD use separate pins,1: Loop mode or Single-Wire mode" bitfld.long 0x10 6. "DOZEEN,Enables LPUART in Doze mode." "0: Enables,1: Disables" newline bitfld.long 0x10 5. "RSRC,Receiver Source Select" "0: Internal Loopback mode,1: Single-wire mode" bitfld.long 0x10 4. "M,9-Bit Or 8-Bit Mode Select" "0: 8-bit data characters,1: 9-bit data characters" newline bitfld.long 0x10 3. "WAKE,Receiver Wakeup Method Select" "0: Configures CTRL[RWU] for idle-line wakeup,1: Configures CTRL[RWU] with address-mark wakeup" bitfld.long 0x10 2. "ILT,Idle Line Type Select" "0: After the start bit,1: After the stop bit" newline bitfld.long 0x10 1. "PE,Parity Enable" "0: Disables,1: Enables" bitfld.long 0x10 0. "PT,Parity Type" "0: Even parity,1: Odd parity" line.long 0x14 "DATA,Data" rbitfld.long 0x14 15. "NOISY,Noisy Data Received" "0: Received without noise,1: Received with noise" rbitfld.long 0x14 14. "PARITYE,Parity Error" "0: Received without a parity error,1: Received with a parity error" newline bitfld.long 0x14 13. "FRETSC,Frame Error Transmit Special Character" "0: Received without a frame error on reads or..,1: Received with a frame error on reads or.." rbitfld.long 0x14 12. "RXEMPT,Receive Buffer Empty" "0: Contains valid data,1: Contains invalid data and is empty" newline rbitfld.long 0x14 11. "IDLINE,Idle Line" "0: Received was not idle,1: Receiver was idle" rbitfld.long 0x14 10. "LINBRK,LIN Break" "0: LIN break not detected or LIN break detect..,1: LIN break detected" newline bitfld.long 0x14 9. "R9T9,Read Receive FIFO Bit 9 Or Write Transmit FIFO Bit 9" "0,1" bitfld.long 0x14 8. "R8T8,Read Receive FIFO Bit 8 Or Write Transmit FIFO Bit 8" "0,1" newline bitfld.long 0x14 7. "R7T7,Read Receive FIFO Bit 7 Or Write Transmit FIFO Bit 7" "0,1" bitfld.long 0x14 6. "R6T6,Read Receive FIFO Bit 6 Or Write Transmit FIFO Bit 6" "0,1" newline bitfld.long 0x14 5. "R5T5,Read Receive FIFO Bit 5 Or Write Transmit FIFO Bit 5" "0,1" bitfld.long 0x14 4. "R4T4,Read Receive FIFO Bit 4 Or Write Transmit FIFO Bit 4" "0,1" newline bitfld.long 0x14 3. "R3T3,Read Receive FIFO Bit 3 Or Write Transmit FIFO Bit 3" "0,1" bitfld.long 0x14 2. "R2T2,Read Receive FIFO Bit 2 Or Write Transmit FIFO Bit 2" "0,1" newline bitfld.long 0x14 1. "R1T1,Read Receive FIFO Bit 1 Or Write Transmit FIFO Bit 1" "0,1" bitfld.long 0x14 0. "R0T0,Read Receive FIFO Bit 0 Or Write Transmit FIFO Bit 0" "0,1" line.long 0x18 "MATCH,Match Address" hexmask.long.word 0x18 16.--25. 1. "MA2,Match Address 2" hexmask.long.word 0x18 0.--9. 1. "MA1,Match Address 1" line.long 0x1C "MODIR,MODEM IrDA" bitfld.long 0x1C 18. "IREN,IR Enable" "0: Disables,1: Enables" bitfld.long 0x1C 16.--17. "TNP,Transmitter Narrow Pulse" "0: 1 / OSR,1: 2 / OSR,2: 3 / OSR,3: 4 / OSR" newline bitfld.long 0x1C 8.--9. "RTSWATER,Receive RTS Configuration" "0,1,2,3" bitfld.long 0x1C 5. "TXCTSSRC,Transmit CTS Source" "0: The CTS_B pin,1: An internal connection to the receiver address.." newline bitfld.long 0x1C 4. "TXCTSC,Transmit CTS Configuration" "0: Sampled at the start of each character,1: Sampled when the transmitter is idle" bitfld.long 0x1C 3. "RXRTSE,Receiver RTS Enable" "0: Disables,1: Enables" newline bitfld.long 0x1C 2. "TXRTSPOL,Transmitter RTS Polarity" "0: Transmitter RTS is active low,1: Transmitter RTS is active high" bitfld.long 0x1C 1. "TXRTSE,Transmitter RTS Enable" "0: Disables,1: Enables" newline bitfld.long 0x1C 0. "TXCTSE,Transmitter CTS Enable" "0: Disables,1: Enables" line.long 0x20 "FIFO,FIFO" rbitfld.long 0x20 23. "TXEMPT,Transmit FIFO Or Buffer Empty" "0: Not empty,1: Empty" rbitfld.long 0x20 22. "RXEMPT,Receive FIFO Or Buffer Empty" "0: Not empty,1: Empty" newline eventfld.long 0x20 17. "TXOF,Transmitter FIFO Overflow Flag" "0: No overflow,1: Overflow" eventfld.long 0x20 16. "RXUF,Receiver FIFO Underflow Flag" "0: No underflow,1: Underflow" newline bitfld.long 0x20 15. "TXFLUSH,Transmit FIFO Flush" "0: No effect,1: All data is flushed out" bitfld.long 0x20 14. "RXFLUSH,Receive FIFO Flush" "0: No effect,1: All data is flushed out" newline bitfld.long 0x20 10.--12. "RXIDEN,Receiver Idle Empty Enable" "0: Disables STAT[RDRF] to become 1 because of..,1: Enables STAT[RDRF] to become 1 because of..,2: Enables STAT[RDRF] to become 1 because of..,3: Enables STAT[RDRF] to become 1 because of..,4: Enables STAT[RDRF] to become 1 because of..,5: Enables STAT[RDRF] to become 1 because of..,6: Enables STAT[RDRF] to become 1 because of..,7: Enables STAT[RDRF] to become 1 because of.." bitfld.long 0x20 9. "TXOFE,Transmit FIFO Overflow Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x20 8. "RXUFE,Receive FIFO Underflow Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x20 7. "TXFE,Transmit FIFO Enable" "0: Disables; buffer depth is 1,1: Enables; FIFO[TXFIFOSIZE] indicates the buffer.." newline rbitfld.long 0x20 4.--6. "TXFIFOSIZE,Transmit FIFO Buffer Depth" "0: Transmit FIFO buffer depth = 1 dataword,1: Transmit FIFO buffer depth = 4 datawords,2: Transmit FIFO buffer depth = 8 datawords,3: Transmit FIFO buffer depth = 16 datawords,4: Transmit FIFO buffer depth = 32 datawords,5: Transmit FIFO buffer depth = 64 datawords,6: Transmit FIFO buffer depth = 128 datawords,7: Transmit FIFO buffer depth = 256 datawords" bitfld.long 0x20 3. "RXFE,Receive FIFO Enable" "0: Disables; buffer depth is 1,1: Enables; FIFO[RXFIFOSIZE] indicates the buffer.." newline rbitfld.long 0x20 0.--2. "RXFIFOSIZE,Receive FIFO Buffer Depth" "0: Receive FIFO buffer depth = 1 dataword,1: Receive FIFO buffer depth = 4 datawords,2: Receive FIFO buffer depth = 8 datawords,3: Receive FIFO buffer depth = 16 datawords,4: Receive FIFO buffer depth = 32 datawords,5: Receive FIFO buffer depth = 64 datawords,6: Receive FIFO buffer depth = 128 datawords,7: Receive FIFO buffer depth = 256 datawords" line.long 0x24 "WATER,Watermark" rbitfld.long 0x24 24.--26. "RXCOUNT,Receive Counter" "0,1,2,3,4,5,6,7" bitfld.long 0x24 16.--17. "RXWATER,Receive Watermark" "0,1,2,3" newline rbitfld.long 0x24 8.--10. "TXCOUNT,Transmit Counter" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0.--1. "TXWATER,Transmit Watermark" "0,1,2,3" rgroup.long 0x30++0x3 line.long 0x0 "DATARO,Data Read-Only" hexmask.long.word 0x0 0.--15. 1. "DATA,Receive Data" tree.end tree "LPUART_5" base ad:0x4033C000 rgroup.long 0x0++0x7 line.long 0x0 "VERID,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Identification Number" line.long 0x4 "PARAM,Parameter" hexmask.long.byte 0x4 8.--15. 1. "RXFIFO,Receive FIFO Size" hexmask.long.byte 0x4 0.--7. 1. "TXFIFO,Transmit FIFO Size" group.long 0x8++0x27 line.long 0x0 "GLOBAL,Global" bitfld.long 0x0 1. "RST,Software Reset" "0: Not reset,1: Reset" line.long 0x4 "PINCFG,Pin Configuration" bitfld.long 0x4 0.--1. "TRGSEL,Trigger Select" "0: Input trigger disabled,1: Input trigger used instead of the RXD pin input,2: Input trigger used instead of the CTS_B pin input,3: Input trigger used to modulate the TXD pin.." line.long 0x8 "BAUD,Baud Rate" bitfld.long 0x8 31. "MAEN1,Match Address Mode Enable 1" "0: Disables,1: Enables" bitfld.long 0x8 30. "MAEN2,Match Address Mode Enable 2" "0: Disables,1: Enables" newline bitfld.long 0x8 29. "M10,10-Bit Mode Select" "0: Receiver and transmitter use 7-bit to 9-bit data..,1: Receiver and transmitter use 10-bit data.." hexmask.long.byte 0x8 24.--28. 1. "OSR,Oversampling Ratio (OSR)" newline bitfld.long 0x8 23. "TDMAE,Transmitter DMA Enable" "0: Disables DMA request,1: Enables DMA request" bitfld.long 0x8 21. "RDMAE,Receiver Full DMA Enable" "0: Disables DMA request,1: Enables DMA request" newline bitfld.long 0x8 18.--19. "MATCFG,Match Configuration" "0: Address match wakeup,1: Idle match wakeup,2: Match on and match off,3: Enables RWU on data match and match on/off for.." bitfld.long 0x8 17. "BOTHEDGE,Both Edge Sampling" "0: Receiver samples input data using the rising..,1: Receiver samples input data using the rising and.." newline bitfld.long 0x8 16. "RESYNCDIS,Resynchronization Disable" "0: Enables resynchronization,1: Disables resynchronization" bitfld.long 0x8 15. "LBKDIE,LIN Break Detect Interrupt Enable" "0: Disables hardware interrupts from STAT[LBKDIF]..,1: Requests hardware interrupt when STAT[LBKDIF] is 1" newline bitfld.long 0x8 14. "RXEDGIE,RX Input Active Edge Interrupt Enable" "0: Disables hardware interrupts from STAT[RXEDGIF],1: Requests hardware interrupts when STAT[RXEDGIF].." bitfld.long 0x8 13. "SBNS,Stop Bit Number Select" "0: One stop bit,1: Two stop bits" newline hexmask.long.word 0x8 0.--12. 1. "SBR,Baud Rate Modulo Divisor" line.long 0xC "STAT,Status" eventfld.long 0xC 31. "LBKDIF,LIN Break Detect Interrupt Flag" "0: Not detected,1: Detected" eventfld.long 0xC 30. "RXEDGIF,RXD Pin Active Edge Interrupt Flag" "0: Not occurred,1: Occurred" newline bitfld.long 0xC 29. "MSBF,MSB First" "0: LSB,1: MSB" bitfld.long 0xC 28. "RXINV,Receive Data Inversion" "0: Inverted,1: Not inverted" newline bitfld.long 0xC 27. "RWUID,Receive Wake Up Idle Detect" "0: STAT[IDLE] does not become 1,1: STAT[IDLE] becomes 1" bitfld.long 0xC 26. "BRK13,Break Character Generation Length" "0: 9 to 13 bit times,1: 12 to 15 bit times" newline bitfld.long 0xC 25. "LBKDE,LIN Break Detection Enable" "0: Disables,1: Enables" rbitfld.long 0xC 24. "RAF,Receiver Active Flag" "0: Idle waiting for a start bit,1: Receiver active (RXD pin input not idle)" newline rbitfld.long 0xC 23. "TDRE,Transmit Data Register Empty Flag" "0: Greater than watermark,1: Equal to or less than watermark" rbitfld.long 0xC 22. "TC,Transmission Complete Flag" "0: Transmitter active (sending data a preamble or a..,1: Transmitter idle (transmission activity complete)" newline rbitfld.long 0xC 21. "RDRF,Receive Data Register Full Flag" "0: Equal to or less than watermark,1: Greater than watermark" eventfld.long 0xC 20. "IDLE,Idle Line Flag" "0: No idle line detected,1: Idle line detected" newline eventfld.long 0xC 19. "OR,Receiver Overrun Flag" "0: No overrun,1: Receive overrun (new LPUART data lost)" eventfld.long 0xC 18. "NF,Noise Flag (NF)" "0: No noise detected,1: Noise detected" newline eventfld.long 0xC 17. "FE,Framing Error Flag (FE)" "0: No framing error detected (this does not..,1: Framing error detected" eventfld.long 0xC 16. "PF,Parity Error Flag (PF)" "0: No parity error detected,1: Parity error detected" newline eventfld.long 0xC 15. "MA1F,Match 1 Flag" "0: Not equal to MA1,1: Equal to MA1" eventfld.long 0xC 14. "MA2F,Match 2 Flag" "0: Not equal to MA2,1: Equal to MA2" newline bitfld.long 0xC 1. "AME,Address Mark Enable" "0: Address mark in character is MSB,1: Address mark in character is the last bit before.." bitfld.long 0xC 0. "LBKFE,LIN Break Flag Enable" "0: Disables LIN break detect,1: Enables LIN break detect" line.long 0x10 "CTRL,Control" bitfld.long 0x10 31. "R8T9,Receive Bit 8 Transmit Bit 9" "0,1" bitfld.long 0x10 30. "R9T8,Receive Bit 9 Transmit Bit 8" "0,1" newline bitfld.long 0x10 29. "TXDIR,TXD Pin Direction in Single-Wire Mode" "0: TXD pin is an input in Single-Wire mode,1: TXD pin is an output in Single-Wire mode" bitfld.long 0x10 28. "TXINV,Transmit Data Inversion" "0: Not inverted,1: Inverted" newline bitfld.long 0x10 27. "ORIE,Overrun Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 26. "NEIE,Noise Error Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 25. "FEIE,Framing Error Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 24. "PEIE,Parity Error Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 23. "TIE,Transmit Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 22. "TCIE,Transmission Complete Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 21. "RIE,Receiver Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 20. "ILIE,Idle Line Interrupt Enable" "0: Disables hardware interrupts from STAT[IDLE];..,1: Enables hardware interrupts when STAT[IDLE] = 1" newline bitfld.long 0x10 19. "TE,Transmitter Enable" "0: Disables,1: Enables" bitfld.long 0x10 18. "RE,Receiver Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 17. "RWU,Receiver Wakeup Control" "0: Normal receiver operation,1: LPUART receiver in standby waiting for a wakeup.." bitfld.long 0x10 16. "SBK,Send Break" "0: Normal transmitter operation,1: Queue break character(s) to be sent" newline bitfld.long 0x10 15. "MA1IE,Match 1 (MA1F) Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 14. "MA2IE,Match 2 (MA2F) Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 11. "M7,7-Bit Mode Select" "0: 8-bit to 10-bit data characters,1: 7-bit data characters" bitfld.long 0x10 8.--10. "IDLECFG,Idle Configuration" "0: 1,1: 2,2: 4,3: 8,4: 16,5: 32,6: 64,7: 128" newline bitfld.long 0x10 7. "LOOPS,Loop Mode Select" "0: Normal operation: RXD and TXD use separate pins,1: Loop mode or Single-Wire mode" bitfld.long 0x10 6. "DOZEEN,Enables LPUART in Doze mode." "0: Enables,1: Disables" newline bitfld.long 0x10 5. "RSRC,Receiver Source Select" "0: Internal Loopback mode,1: Single-wire mode" bitfld.long 0x10 4. "M,9-Bit Or 8-Bit Mode Select" "0: 8-bit data characters,1: 9-bit data characters" newline bitfld.long 0x10 3. "WAKE,Receiver Wakeup Method Select" "0: Configures CTRL[RWU] for idle-line wakeup,1: Configures CTRL[RWU] with address-mark wakeup" bitfld.long 0x10 2. "ILT,Idle Line Type Select" "0: After the start bit,1: After the stop bit" newline bitfld.long 0x10 1. "PE,Parity Enable" "0: Disables,1: Enables" bitfld.long 0x10 0. "PT,Parity Type" "0: Even parity,1: Odd parity" line.long 0x14 "DATA,Data" rbitfld.long 0x14 15. "NOISY,Noisy Data Received" "0: Received without noise,1: Received with noise" rbitfld.long 0x14 14. "PARITYE,Parity Error" "0: Received without a parity error,1: Received with a parity error" newline bitfld.long 0x14 13. "FRETSC,Frame Error Transmit Special Character" "0: Received without a frame error on reads or..,1: Received with a frame error on reads or.." rbitfld.long 0x14 12. "RXEMPT,Receive Buffer Empty" "0: Contains valid data,1: Contains invalid data and is empty" newline rbitfld.long 0x14 11. "IDLINE,Idle Line" "0: Received was not idle,1: Receiver was idle" rbitfld.long 0x14 10. "LINBRK,LIN Break" "0: LIN break not detected or LIN break detect..,1: LIN break detected" newline bitfld.long 0x14 9. "R9T9,Read Receive FIFO Bit 9 Or Write Transmit FIFO Bit 9" "0,1" bitfld.long 0x14 8. "R8T8,Read Receive FIFO Bit 8 Or Write Transmit FIFO Bit 8" "0,1" newline bitfld.long 0x14 7. "R7T7,Read Receive FIFO Bit 7 Or Write Transmit FIFO Bit 7" "0,1" bitfld.long 0x14 6. "R6T6,Read Receive FIFO Bit 6 Or Write Transmit FIFO Bit 6" "0,1" newline bitfld.long 0x14 5. "R5T5,Read Receive FIFO Bit 5 Or Write Transmit FIFO Bit 5" "0,1" bitfld.long 0x14 4. "R4T4,Read Receive FIFO Bit 4 Or Write Transmit FIFO Bit 4" "0,1" newline bitfld.long 0x14 3. "R3T3,Read Receive FIFO Bit 3 Or Write Transmit FIFO Bit 3" "0,1" bitfld.long 0x14 2. "R2T2,Read Receive FIFO Bit 2 Or Write Transmit FIFO Bit 2" "0,1" newline bitfld.long 0x14 1. "R1T1,Read Receive FIFO Bit 1 Or Write Transmit FIFO Bit 1" "0,1" bitfld.long 0x14 0. "R0T0,Read Receive FIFO Bit 0 Or Write Transmit FIFO Bit 0" "0,1" line.long 0x18 "MATCH,Match Address" hexmask.long.word 0x18 16.--25. 1. "MA2,Match Address 2" hexmask.long.word 0x18 0.--9. 1. "MA1,Match Address 1" line.long 0x1C "MODIR,MODEM IrDA" bitfld.long 0x1C 18. "IREN,IR Enable" "0: Disables,1: Enables" bitfld.long 0x1C 16.--17. "TNP,Transmitter Narrow Pulse" "0: 1 / OSR,1: 2 / OSR,2: 3 / OSR,3: 4 / OSR" newline bitfld.long 0x1C 8.--9. "RTSWATER,Receive RTS Configuration" "0,1,2,3" bitfld.long 0x1C 5. "TXCTSSRC,Transmit CTS Source" "0: The CTS_B pin,1: An internal connection to the receiver address.." newline bitfld.long 0x1C 4. "TXCTSC,Transmit CTS Configuration" "0: Sampled at the start of each character,1: Sampled when the transmitter is idle" bitfld.long 0x1C 3. "RXRTSE,Receiver RTS Enable" "0: Disables,1: Enables" newline bitfld.long 0x1C 2. "TXRTSPOL,Transmitter RTS Polarity" "0: Transmitter RTS is active low,1: Transmitter RTS is active high" bitfld.long 0x1C 1. "TXRTSE,Transmitter RTS Enable" "0: Disables,1: Enables" newline bitfld.long 0x1C 0. "TXCTSE,Transmitter CTS Enable" "0: Disables,1: Enables" line.long 0x20 "FIFO,FIFO" rbitfld.long 0x20 23. "TXEMPT,Transmit FIFO Or Buffer Empty" "0: Not empty,1: Empty" rbitfld.long 0x20 22. "RXEMPT,Receive FIFO Or Buffer Empty" "0: Not empty,1: Empty" newline eventfld.long 0x20 17. "TXOF,Transmitter FIFO Overflow Flag" "0: No overflow,1: Overflow" eventfld.long 0x20 16. "RXUF,Receiver FIFO Underflow Flag" "0: No underflow,1: Underflow" newline bitfld.long 0x20 15. "TXFLUSH,Transmit FIFO Flush" "0: No effect,1: All data is flushed out" bitfld.long 0x20 14. "RXFLUSH,Receive FIFO Flush" "0: No effect,1: All data is flushed out" newline bitfld.long 0x20 10.--12. "RXIDEN,Receiver Idle Empty Enable" "0: Disables STAT[RDRF] to become 1 because of..,1: Enables STAT[RDRF] to become 1 because of..,2: Enables STAT[RDRF] to become 1 because of..,3: Enables STAT[RDRF] to become 1 because of..,4: Enables STAT[RDRF] to become 1 because of..,5: Enables STAT[RDRF] to become 1 because of..,6: Enables STAT[RDRF] to become 1 because of..,7: Enables STAT[RDRF] to become 1 because of.." bitfld.long 0x20 9. "TXOFE,Transmit FIFO Overflow Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x20 8. "RXUFE,Receive FIFO Underflow Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x20 7. "TXFE,Transmit FIFO Enable" "0: Disables; buffer depth is 1,1: Enables; FIFO[TXFIFOSIZE] indicates the buffer.." newline rbitfld.long 0x20 4.--6. "TXFIFOSIZE,Transmit FIFO Buffer Depth" "0: Transmit FIFO buffer depth = 1 dataword,1: Transmit FIFO buffer depth = 4 datawords,2: Transmit FIFO buffer depth = 8 datawords,3: Transmit FIFO buffer depth = 16 datawords,4: Transmit FIFO buffer depth = 32 datawords,5: Transmit FIFO buffer depth = 64 datawords,6: Transmit FIFO buffer depth = 128 datawords,7: Transmit FIFO buffer depth = 256 datawords" bitfld.long 0x20 3. "RXFE,Receive FIFO Enable" "0: Disables; buffer depth is 1,1: Enables; FIFO[RXFIFOSIZE] indicates the buffer.." newline rbitfld.long 0x20 0.--2. "RXFIFOSIZE,Receive FIFO Buffer Depth" "0: Receive FIFO buffer depth = 1 dataword,1: Receive FIFO buffer depth = 4 datawords,2: Receive FIFO buffer depth = 8 datawords,3: Receive FIFO buffer depth = 16 datawords,4: Receive FIFO buffer depth = 32 datawords,5: Receive FIFO buffer depth = 64 datawords,6: Receive FIFO buffer depth = 128 datawords,7: Receive FIFO buffer depth = 256 datawords" line.long 0x24 "WATER,Watermark" rbitfld.long 0x24 24.--26. "RXCOUNT,Receive Counter" "0,1,2,3,4,5,6,7" bitfld.long 0x24 16.--17. "RXWATER,Receive Watermark" "0,1,2,3" newline rbitfld.long 0x24 8.--10. "TXCOUNT,Transmit Counter" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0.--1. "TXWATER,Transmit Watermark" "0,1,2,3" rgroup.long 0x30++0x3 line.long 0x0 "DATARO,Data Read-Only" hexmask.long.word 0x0 0.--15. 1. "DATA,Receive Data" tree.end tree "LPUART_6" base ad:0x40340000 rgroup.long 0x0++0x7 line.long 0x0 "VERID,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Identification Number" line.long 0x4 "PARAM,Parameter" hexmask.long.byte 0x4 8.--15. 1. "RXFIFO,Receive FIFO Size" hexmask.long.byte 0x4 0.--7. 1. "TXFIFO,Transmit FIFO Size" group.long 0x8++0x27 line.long 0x0 "GLOBAL,Global" bitfld.long 0x0 1. "RST,Software Reset" "0: Not reset,1: Reset" line.long 0x4 "PINCFG,Pin Configuration" bitfld.long 0x4 0.--1. "TRGSEL,Trigger Select" "0: Input trigger disabled,1: Input trigger used instead of the RXD pin input,2: Input trigger used instead of the CTS_B pin input,3: Input trigger used to modulate the TXD pin.." line.long 0x8 "BAUD,Baud Rate" bitfld.long 0x8 31. "MAEN1,Match Address Mode Enable 1" "0: Disables,1: Enables" bitfld.long 0x8 30. "MAEN2,Match Address Mode Enable 2" "0: Disables,1: Enables" newline bitfld.long 0x8 29. "M10,10-Bit Mode Select" "0: Receiver and transmitter use 7-bit to 9-bit data..,1: Receiver and transmitter use 10-bit data.." hexmask.long.byte 0x8 24.--28. 1. "OSR,Oversampling Ratio (OSR)" newline bitfld.long 0x8 23. "TDMAE,Transmitter DMA Enable" "0: Disables DMA request,1: Enables DMA request" bitfld.long 0x8 21. "RDMAE,Receiver Full DMA Enable" "0: Disables DMA request,1: Enables DMA request" newline bitfld.long 0x8 18.--19. "MATCFG,Match Configuration" "0: Address match wakeup,1: Idle match wakeup,2: Match on and match off,3: Enables RWU on data match and match on/off for.." bitfld.long 0x8 17. "BOTHEDGE,Both Edge Sampling" "0: Receiver samples input data using the rising..,1: Receiver samples input data using the rising and.." newline bitfld.long 0x8 16. "RESYNCDIS,Resynchronization Disable" "0: Enables resynchronization,1: Disables resynchronization" bitfld.long 0x8 15. "LBKDIE,LIN Break Detect Interrupt Enable" "0: Disables hardware interrupts from STAT[LBKDIF]..,1: Requests hardware interrupt when STAT[LBKDIF] is 1" newline bitfld.long 0x8 14. "RXEDGIE,RX Input Active Edge Interrupt Enable" "0: Disables hardware interrupts from STAT[RXEDGIF],1: Requests hardware interrupts when STAT[RXEDGIF].." bitfld.long 0x8 13. "SBNS,Stop Bit Number Select" "0: One stop bit,1: Two stop bits" newline hexmask.long.word 0x8 0.--12. 1. "SBR,Baud Rate Modulo Divisor" line.long 0xC "STAT,Status" eventfld.long 0xC 31. "LBKDIF,LIN Break Detect Interrupt Flag" "0: Not detected,1: Detected" eventfld.long 0xC 30. "RXEDGIF,RXD Pin Active Edge Interrupt Flag" "0: Not occurred,1: Occurred" newline bitfld.long 0xC 29. "MSBF,MSB First" "0: LSB,1: MSB" bitfld.long 0xC 28. "RXINV,Receive Data Inversion" "0: Inverted,1: Not inverted" newline bitfld.long 0xC 27. "RWUID,Receive Wake Up Idle Detect" "0: STAT[IDLE] does not become 1,1: STAT[IDLE] becomes 1" bitfld.long 0xC 26. "BRK13,Break Character Generation Length" "0: 9 to 13 bit times,1: 12 to 15 bit times" newline bitfld.long 0xC 25. "LBKDE,LIN Break Detection Enable" "0: Disables,1: Enables" rbitfld.long 0xC 24. "RAF,Receiver Active Flag" "0: Idle waiting for a start bit,1: Receiver active (RXD pin input not idle)" newline rbitfld.long 0xC 23. "TDRE,Transmit Data Register Empty Flag" "0: Greater than watermark,1: Equal to or less than watermark" rbitfld.long 0xC 22. "TC,Transmission Complete Flag" "0: Transmitter active (sending data a preamble or a..,1: Transmitter idle (transmission activity complete)" newline rbitfld.long 0xC 21. "RDRF,Receive Data Register Full Flag" "0: Equal to or less than watermark,1: Greater than watermark" eventfld.long 0xC 20. "IDLE,Idle Line Flag" "0: No idle line detected,1: Idle line detected" newline eventfld.long 0xC 19. "OR,Receiver Overrun Flag" "0: No overrun,1: Receive overrun (new LPUART data lost)" eventfld.long 0xC 18. "NF,Noise Flag (NF)" "0: No noise detected,1: Noise detected" newline eventfld.long 0xC 17. "FE,Framing Error Flag (FE)" "0: No framing error detected (this does not..,1: Framing error detected" eventfld.long 0xC 16. "PF,Parity Error Flag (PF)" "0: No parity error detected,1: Parity error detected" newline eventfld.long 0xC 15. "MA1F,Match 1 Flag" "0: Not equal to MA1,1: Equal to MA1" eventfld.long 0xC 14. "MA2F,Match 2 Flag" "0: Not equal to MA2,1: Equal to MA2" newline bitfld.long 0xC 1. "AME,Address Mark Enable" "0: Address mark in character is MSB,1: Address mark in character is the last bit before.." bitfld.long 0xC 0. "LBKFE,LIN Break Flag Enable" "0: Disables LIN break detect,1: Enables LIN break detect" line.long 0x10 "CTRL,Control" bitfld.long 0x10 31. "R8T9,Receive Bit 8 Transmit Bit 9" "0,1" bitfld.long 0x10 30. "R9T8,Receive Bit 9 Transmit Bit 8" "0,1" newline bitfld.long 0x10 29. "TXDIR,TXD Pin Direction in Single-Wire Mode" "0: TXD pin is an input in Single-Wire mode,1: TXD pin is an output in Single-Wire mode" bitfld.long 0x10 28. "TXINV,Transmit Data Inversion" "0: Not inverted,1: Inverted" newline bitfld.long 0x10 27. "ORIE,Overrun Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 26. "NEIE,Noise Error Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 25. "FEIE,Framing Error Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 24. "PEIE,Parity Error Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 23. "TIE,Transmit Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 22. "TCIE,Transmission Complete Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 21. "RIE,Receiver Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 20. "ILIE,Idle Line Interrupt Enable" "0: Disables hardware interrupts from STAT[IDLE];..,1: Enables hardware interrupts when STAT[IDLE] = 1" newline bitfld.long 0x10 19. "TE,Transmitter Enable" "0: Disables,1: Enables" bitfld.long 0x10 18. "RE,Receiver Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 17. "RWU,Receiver Wakeup Control" "0: Normal receiver operation,1: LPUART receiver in standby waiting for a wakeup.." bitfld.long 0x10 16. "SBK,Send Break" "0: Normal transmitter operation,1: Queue break character(s) to be sent" newline bitfld.long 0x10 15. "MA1IE,Match 1 (MA1F) Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 14. "MA2IE,Match 2 (MA2F) Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 11. "M7,7-Bit Mode Select" "0: 8-bit to 10-bit data characters,1: 7-bit data characters" bitfld.long 0x10 8.--10. "IDLECFG,Idle Configuration" "0: 1,1: 2,2: 4,3: 8,4: 16,5: 32,6: 64,7: 128" newline bitfld.long 0x10 7. "LOOPS,Loop Mode Select" "0: Normal operation: RXD and TXD use separate pins,1: Loop mode or Single-Wire mode" bitfld.long 0x10 6. "DOZEEN,Enables LPUART in Doze mode." "0: Enables,1: Disables" newline bitfld.long 0x10 5. "RSRC,Receiver Source Select" "0: Internal Loopback mode,1: Single-wire mode" bitfld.long 0x10 4. "M,9-Bit Or 8-Bit Mode Select" "0: 8-bit data characters,1: 9-bit data characters" newline bitfld.long 0x10 3. "WAKE,Receiver Wakeup Method Select" "0: Configures CTRL[RWU] for idle-line wakeup,1: Configures CTRL[RWU] with address-mark wakeup" bitfld.long 0x10 2. "ILT,Idle Line Type Select" "0: After the start bit,1: After the stop bit" newline bitfld.long 0x10 1. "PE,Parity Enable" "0: Disables,1: Enables" bitfld.long 0x10 0. "PT,Parity Type" "0: Even parity,1: Odd parity" line.long 0x14 "DATA,Data" rbitfld.long 0x14 15. "NOISY,Noisy Data Received" "0: Received without noise,1: Received with noise" rbitfld.long 0x14 14. "PARITYE,Parity Error" "0: Received without a parity error,1: Received with a parity error" newline bitfld.long 0x14 13. "FRETSC,Frame Error Transmit Special Character" "0: Received without a frame error on reads or..,1: Received with a frame error on reads or.." rbitfld.long 0x14 12. "RXEMPT,Receive Buffer Empty" "0: Contains valid data,1: Contains invalid data and is empty" newline rbitfld.long 0x14 11. "IDLINE,Idle Line" "0: Received was not idle,1: Receiver was idle" rbitfld.long 0x14 10. "LINBRK,LIN Break" "0: LIN break not detected or LIN break detect..,1: LIN break detected" newline bitfld.long 0x14 9. "R9T9,Read Receive FIFO Bit 9 Or Write Transmit FIFO Bit 9" "0,1" bitfld.long 0x14 8. "R8T8,Read Receive FIFO Bit 8 Or Write Transmit FIFO Bit 8" "0,1" newline bitfld.long 0x14 7. "R7T7,Read Receive FIFO Bit 7 Or Write Transmit FIFO Bit 7" "0,1" bitfld.long 0x14 6. "R6T6,Read Receive FIFO Bit 6 Or Write Transmit FIFO Bit 6" "0,1" newline bitfld.long 0x14 5. "R5T5,Read Receive FIFO Bit 5 Or Write Transmit FIFO Bit 5" "0,1" bitfld.long 0x14 4. "R4T4,Read Receive FIFO Bit 4 Or Write Transmit FIFO Bit 4" "0,1" newline bitfld.long 0x14 3. "R3T3,Read Receive FIFO Bit 3 Or Write Transmit FIFO Bit 3" "0,1" bitfld.long 0x14 2. "R2T2,Read Receive FIFO Bit 2 Or Write Transmit FIFO Bit 2" "0,1" newline bitfld.long 0x14 1. "R1T1,Read Receive FIFO Bit 1 Or Write Transmit FIFO Bit 1" "0,1" bitfld.long 0x14 0. "R0T0,Read Receive FIFO Bit 0 Or Write Transmit FIFO Bit 0" "0,1" line.long 0x18 "MATCH,Match Address" hexmask.long.word 0x18 16.--25. 1. "MA2,Match Address 2" hexmask.long.word 0x18 0.--9. 1. "MA1,Match Address 1" line.long 0x1C "MODIR,MODEM IrDA" bitfld.long 0x1C 18. "IREN,IR Enable" "0: Disables,1: Enables" bitfld.long 0x1C 16.--17. "TNP,Transmitter Narrow Pulse" "0: 1 / OSR,1: 2 / OSR,2: 3 / OSR,3: 4 / OSR" newline bitfld.long 0x1C 8.--9. "RTSWATER,Receive RTS Configuration" "0,1,2,3" bitfld.long 0x1C 5. "TXCTSSRC,Transmit CTS Source" "0: The CTS_B pin,1: An internal connection to the receiver address.." newline bitfld.long 0x1C 4. "TXCTSC,Transmit CTS Configuration" "0: Sampled at the start of each character,1: Sampled when the transmitter is idle" bitfld.long 0x1C 3. "RXRTSE,Receiver RTS Enable" "0: Disables,1: Enables" newline bitfld.long 0x1C 2. "TXRTSPOL,Transmitter RTS Polarity" "0: Transmitter RTS is active low,1: Transmitter RTS is active high" bitfld.long 0x1C 1. "TXRTSE,Transmitter RTS Enable" "0: Disables,1: Enables" newline bitfld.long 0x1C 0. "TXCTSE,Transmitter CTS Enable" "0: Disables,1: Enables" line.long 0x20 "FIFO,FIFO" rbitfld.long 0x20 23. "TXEMPT,Transmit FIFO Or Buffer Empty" "0: Not empty,1: Empty" rbitfld.long 0x20 22. "RXEMPT,Receive FIFO Or Buffer Empty" "0: Not empty,1: Empty" newline eventfld.long 0x20 17. "TXOF,Transmitter FIFO Overflow Flag" "0: No overflow,1: Overflow" eventfld.long 0x20 16. "RXUF,Receiver FIFO Underflow Flag" "0: No underflow,1: Underflow" newline bitfld.long 0x20 15. "TXFLUSH,Transmit FIFO Flush" "0: No effect,1: All data is flushed out" bitfld.long 0x20 14. "RXFLUSH,Receive FIFO Flush" "0: No effect,1: All data is flushed out" newline bitfld.long 0x20 10.--12. "RXIDEN,Receiver Idle Empty Enable" "0: Disables STAT[RDRF] to become 1 because of..,1: Enables STAT[RDRF] to become 1 because of..,2: Enables STAT[RDRF] to become 1 because of..,3: Enables STAT[RDRF] to become 1 because of..,4: Enables STAT[RDRF] to become 1 because of..,5: Enables STAT[RDRF] to become 1 because of..,6: Enables STAT[RDRF] to become 1 because of..,7: Enables STAT[RDRF] to become 1 because of.." bitfld.long 0x20 9. "TXOFE,Transmit FIFO Overflow Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x20 8. "RXUFE,Receive FIFO Underflow Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x20 7. "TXFE,Transmit FIFO Enable" "0: Disables; buffer depth is 1,1: Enables; FIFO[TXFIFOSIZE] indicates the buffer.." newline rbitfld.long 0x20 4.--6. "TXFIFOSIZE,Transmit FIFO Buffer Depth" "0: Transmit FIFO buffer depth = 1 dataword,1: Transmit FIFO buffer depth = 4 datawords,2: Transmit FIFO buffer depth = 8 datawords,3: Transmit FIFO buffer depth = 16 datawords,4: Transmit FIFO buffer depth = 32 datawords,5: Transmit FIFO buffer depth = 64 datawords,6: Transmit FIFO buffer depth = 128 datawords,7: Transmit FIFO buffer depth = 256 datawords" bitfld.long 0x20 3. "RXFE,Receive FIFO Enable" "0: Disables; buffer depth is 1,1: Enables; FIFO[RXFIFOSIZE] indicates the buffer.." newline rbitfld.long 0x20 0.--2. "RXFIFOSIZE,Receive FIFO Buffer Depth" "0: Receive FIFO buffer depth = 1 dataword,1: Receive FIFO buffer depth = 4 datawords,2: Receive FIFO buffer depth = 8 datawords,3: Receive FIFO buffer depth = 16 datawords,4: Receive FIFO buffer depth = 32 datawords,5: Receive FIFO buffer depth = 64 datawords,6: Receive FIFO buffer depth = 128 datawords,7: Receive FIFO buffer depth = 256 datawords" line.long 0x24 "WATER,Watermark" rbitfld.long 0x24 24.--26. "RXCOUNT,Receive Counter" "0,1,2,3,4,5,6,7" bitfld.long 0x24 16.--17. "RXWATER,Receive Watermark" "0,1,2,3" newline rbitfld.long 0x24 8.--10. "TXCOUNT,Transmit Counter" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0.--1. "TXWATER,Transmit Watermark" "0,1,2,3" rgroup.long 0x30++0x3 line.long 0x0 "DATARO,Data Read-Only" hexmask.long.word 0x0 0.--15. 1. "DATA,Receive Data" tree.end tree "LPUART_7" base ad:0x40344000 rgroup.long 0x0++0x7 line.long 0x0 "VERID,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Identification Number" line.long 0x4 "PARAM,Parameter" hexmask.long.byte 0x4 8.--15. 1. "RXFIFO,Receive FIFO Size" hexmask.long.byte 0x4 0.--7. 1. "TXFIFO,Transmit FIFO Size" group.long 0x8++0x27 line.long 0x0 "GLOBAL,Global" bitfld.long 0x0 1. "RST,Software Reset" "0: Not reset,1: Reset" line.long 0x4 "PINCFG,Pin Configuration" bitfld.long 0x4 0.--1. "TRGSEL,Trigger Select" "0: Input trigger disabled,1: Input trigger used instead of the RXD pin input,2: Input trigger used instead of the CTS_B pin input,3: Input trigger used to modulate the TXD pin.." line.long 0x8 "BAUD,Baud Rate" bitfld.long 0x8 31. "MAEN1,Match Address Mode Enable 1" "0: Disables,1: Enables" bitfld.long 0x8 30. "MAEN2,Match Address Mode Enable 2" "0: Disables,1: Enables" newline bitfld.long 0x8 29. "M10,10-Bit Mode Select" "0: Receiver and transmitter use 7-bit to 9-bit data..,1: Receiver and transmitter use 10-bit data.." hexmask.long.byte 0x8 24.--28. 1. "OSR,Oversampling Ratio (OSR)" newline bitfld.long 0x8 23. "TDMAE,Transmitter DMA Enable" "0: Disables DMA request,1: Enables DMA request" bitfld.long 0x8 21. "RDMAE,Receiver Full DMA Enable" "0: Disables DMA request,1: Enables DMA request" newline bitfld.long 0x8 18.--19. "MATCFG,Match Configuration" "0: Address match wakeup,1: Idle match wakeup,2: Match on and match off,3: Enables RWU on data match and match on/off for.." bitfld.long 0x8 17. "BOTHEDGE,Both Edge Sampling" "0: Receiver samples input data using the rising..,1: Receiver samples input data using the rising and.." newline bitfld.long 0x8 16. "RESYNCDIS,Resynchronization Disable" "0: Enables resynchronization,1: Disables resynchronization" bitfld.long 0x8 15. "LBKDIE,LIN Break Detect Interrupt Enable" "0: Disables hardware interrupts from STAT[LBKDIF]..,1: Requests hardware interrupt when STAT[LBKDIF] is 1" newline bitfld.long 0x8 14. "RXEDGIE,RX Input Active Edge Interrupt Enable" "0: Disables hardware interrupts from STAT[RXEDGIF],1: Requests hardware interrupts when STAT[RXEDGIF].." bitfld.long 0x8 13. "SBNS,Stop Bit Number Select" "0: One stop bit,1: Two stop bits" newline hexmask.long.word 0x8 0.--12. 1. "SBR,Baud Rate Modulo Divisor" line.long 0xC "STAT,Status" eventfld.long 0xC 31. "LBKDIF,LIN Break Detect Interrupt Flag" "0: Not detected,1: Detected" eventfld.long 0xC 30. "RXEDGIF,RXD Pin Active Edge Interrupt Flag" "0: Not occurred,1: Occurred" newline bitfld.long 0xC 29. "MSBF,MSB First" "0: LSB,1: MSB" bitfld.long 0xC 28. "RXINV,Receive Data Inversion" "0: Inverted,1: Not inverted" newline bitfld.long 0xC 27. "RWUID,Receive Wake Up Idle Detect" "0: STAT[IDLE] does not become 1,1: STAT[IDLE] becomes 1" bitfld.long 0xC 26. "BRK13,Break Character Generation Length" "0: 9 to 13 bit times,1: 12 to 15 bit times" newline bitfld.long 0xC 25. "LBKDE,LIN Break Detection Enable" "0: Disables,1: Enables" rbitfld.long 0xC 24. "RAF,Receiver Active Flag" "0: Idle waiting for a start bit,1: Receiver active (RXD pin input not idle)" newline rbitfld.long 0xC 23. "TDRE,Transmit Data Register Empty Flag" "0: Greater than watermark,1: Equal to or less than watermark" rbitfld.long 0xC 22. "TC,Transmission Complete Flag" "0: Transmitter active (sending data a preamble or a..,1: Transmitter idle (transmission activity complete)" newline rbitfld.long 0xC 21. "RDRF,Receive Data Register Full Flag" "0: Equal to or less than watermark,1: Greater than watermark" eventfld.long 0xC 20. "IDLE,Idle Line Flag" "0: No idle line detected,1: Idle line detected" newline eventfld.long 0xC 19. "OR,Receiver Overrun Flag" "0: No overrun,1: Receive overrun (new LPUART data lost)" eventfld.long 0xC 18. "NF,Noise Flag (NF)" "0: No noise detected,1: Noise detected" newline eventfld.long 0xC 17. "FE,Framing Error Flag (FE)" "0: No framing error detected (this does not..,1: Framing error detected" eventfld.long 0xC 16. "PF,Parity Error Flag (PF)" "0: No parity error detected,1: Parity error detected" newline eventfld.long 0xC 15. "MA1F,Match 1 Flag" "0: Not equal to MA1,1: Equal to MA1" eventfld.long 0xC 14. "MA2F,Match 2 Flag" "0: Not equal to MA2,1: Equal to MA2" newline bitfld.long 0xC 1. "AME,Address Mark Enable" "0: Address mark in character is MSB,1: Address mark in character is the last bit before.." bitfld.long 0xC 0. "LBKFE,LIN Break Flag Enable" "0: Disables LIN break detect,1: Enables LIN break detect" line.long 0x10 "CTRL,Control" bitfld.long 0x10 31. "R8T9,Receive Bit 8 Transmit Bit 9" "0,1" bitfld.long 0x10 30. "R9T8,Receive Bit 9 Transmit Bit 8" "0,1" newline bitfld.long 0x10 29. "TXDIR,TXD Pin Direction in Single-Wire Mode" "0: TXD pin is an input in Single-Wire mode,1: TXD pin is an output in Single-Wire mode" bitfld.long 0x10 28. "TXINV,Transmit Data Inversion" "0: Not inverted,1: Inverted" newline bitfld.long 0x10 27. "ORIE,Overrun Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 26. "NEIE,Noise Error Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 25. "FEIE,Framing Error Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 24. "PEIE,Parity Error Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 23. "TIE,Transmit Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 22. "TCIE,Transmission Complete Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 21. "RIE,Receiver Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 20. "ILIE,Idle Line Interrupt Enable" "0: Disables hardware interrupts from STAT[IDLE];..,1: Enables hardware interrupts when STAT[IDLE] = 1" newline bitfld.long 0x10 19. "TE,Transmitter Enable" "0: Disables,1: Enables" bitfld.long 0x10 18. "RE,Receiver Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 17. "RWU,Receiver Wakeup Control" "0: Normal receiver operation,1: LPUART receiver in standby waiting for a wakeup.." bitfld.long 0x10 16. "SBK,Send Break" "0: Normal transmitter operation,1: Queue break character(s) to be sent" newline bitfld.long 0x10 15. "MA1IE,Match 1 (MA1F) Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 14. "MA2IE,Match 2 (MA2F) Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 11. "M7,7-Bit Mode Select" "0: 8-bit to 10-bit data characters,1: 7-bit data characters" bitfld.long 0x10 8.--10. "IDLECFG,Idle Configuration" "0: 1,1: 2,2: 4,3: 8,4: 16,5: 32,6: 64,7: 128" newline bitfld.long 0x10 7. "LOOPS,Loop Mode Select" "0: Normal operation: RXD and TXD use separate pins,1: Loop mode or Single-Wire mode" bitfld.long 0x10 6. "DOZEEN,Enables LPUART in Doze mode." "0: Enables,1: Disables" newline bitfld.long 0x10 5. "RSRC,Receiver Source Select" "0: Internal Loopback mode,1: Single-wire mode" bitfld.long 0x10 4. "M,9-Bit Or 8-Bit Mode Select" "0: 8-bit data characters,1: 9-bit data characters" newline bitfld.long 0x10 3. "WAKE,Receiver Wakeup Method Select" "0: Configures CTRL[RWU] for idle-line wakeup,1: Configures CTRL[RWU] with address-mark wakeup" bitfld.long 0x10 2. "ILT,Idle Line Type Select" "0: After the start bit,1: After the stop bit" newline bitfld.long 0x10 1. "PE,Parity Enable" "0: Disables,1: Enables" bitfld.long 0x10 0. "PT,Parity Type" "0: Even parity,1: Odd parity" line.long 0x14 "DATA,Data" rbitfld.long 0x14 15. "NOISY,Noisy Data Received" "0: Received without noise,1: Received with noise" rbitfld.long 0x14 14. "PARITYE,Parity Error" "0: Received without a parity error,1: Received with a parity error" newline bitfld.long 0x14 13. "FRETSC,Frame Error Transmit Special Character" "0: Received without a frame error on reads or..,1: Received with a frame error on reads or.." rbitfld.long 0x14 12. "RXEMPT,Receive Buffer Empty" "0: Contains valid data,1: Contains invalid data and is empty" newline rbitfld.long 0x14 11. "IDLINE,Idle Line" "0: Received was not idle,1: Receiver was idle" rbitfld.long 0x14 10. "LINBRK,LIN Break" "0: LIN break not detected or LIN break detect..,1: LIN break detected" newline bitfld.long 0x14 9. "R9T9,Read Receive FIFO Bit 9 Or Write Transmit FIFO Bit 9" "0,1" bitfld.long 0x14 8. "R8T8,Read Receive FIFO Bit 8 Or Write Transmit FIFO Bit 8" "0,1" newline bitfld.long 0x14 7. "R7T7,Read Receive FIFO Bit 7 Or Write Transmit FIFO Bit 7" "0,1" bitfld.long 0x14 6. "R6T6,Read Receive FIFO Bit 6 Or Write Transmit FIFO Bit 6" "0,1" newline bitfld.long 0x14 5. "R5T5,Read Receive FIFO Bit 5 Or Write Transmit FIFO Bit 5" "0,1" bitfld.long 0x14 4. "R4T4,Read Receive FIFO Bit 4 Or Write Transmit FIFO Bit 4" "0,1" newline bitfld.long 0x14 3. "R3T3,Read Receive FIFO Bit 3 Or Write Transmit FIFO Bit 3" "0,1" bitfld.long 0x14 2. "R2T2,Read Receive FIFO Bit 2 Or Write Transmit FIFO Bit 2" "0,1" newline bitfld.long 0x14 1. "R1T1,Read Receive FIFO Bit 1 Or Write Transmit FIFO Bit 1" "0,1" bitfld.long 0x14 0. "R0T0,Read Receive FIFO Bit 0 Or Write Transmit FIFO Bit 0" "0,1" line.long 0x18 "MATCH,Match Address" hexmask.long.word 0x18 16.--25. 1. "MA2,Match Address 2" hexmask.long.word 0x18 0.--9. 1. "MA1,Match Address 1" line.long 0x1C "MODIR,MODEM IrDA" bitfld.long 0x1C 18. "IREN,IR Enable" "0: Disables,1: Enables" bitfld.long 0x1C 16.--17. "TNP,Transmitter Narrow Pulse" "0: 1 / OSR,1: 2 / OSR,2: 3 / OSR,3: 4 / OSR" newline bitfld.long 0x1C 8.--9. "RTSWATER,Receive RTS Configuration" "0,1,2,3" bitfld.long 0x1C 5. "TXCTSSRC,Transmit CTS Source" "0: The CTS_B pin,1: An internal connection to the receiver address.." newline bitfld.long 0x1C 4. "TXCTSC,Transmit CTS Configuration" "0: Sampled at the start of each character,1: Sampled when the transmitter is idle" bitfld.long 0x1C 3. "RXRTSE,Receiver RTS Enable" "0: Disables,1: Enables" newline bitfld.long 0x1C 2. "TXRTSPOL,Transmitter RTS Polarity" "0: Transmitter RTS is active low,1: Transmitter RTS is active high" bitfld.long 0x1C 1. "TXRTSE,Transmitter RTS Enable" "0: Disables,1: Enables" newline bitfld.long 0x1C 0. "TXCTSE,Transmitter CTS Enable" "0: Disables,1: Enables" line.long 0x20 "FIFO,FIFO" rbitfld.long 0x20 23. "TXEMPT,Transmit FIFO Or Buffer Empty" "0: Not empty,1: Empty" rbitfld.long 0x20 22. "RXEMPT,Receive FIFO Or Buffer Empty" "0: Not empty,1: Empty" newline eventfld.long 0x20 17. "TXOF,Transmitter FIFO Overflow Flag" "0: No overflow,1: Overflow" eventfld.long 0x20 16. "RXUF,Receiver FIFO Underflow Flag" "0: No underflow,1: Underflow" newline bitfld.long 0x20 15. "TXFLUSH,Transmit FIFO Flush" "0: No effect,1: All data is flushed out" bitfld.long 0x20 14. "RXFLUSH,Receive FIFO Flush" "0: No effect,1: All data is flushed out" newline bitfld.long 0x20 10.--12. "RXIDEN,Receiver Idle Empty Enable" "0: Disables STAT[RDRF] to become 1 because of..,1: Enables STAT[RDRF] to become 1 because of..,2: Enables STAT[RDRF] to become 1 because of..,3: Enables STAT[RDRF] to become 1 because of..,4: Enables STAT[RDRF] to become 1 because of..,5: Enables STAT[RDRF] to become 1 because of..,6: Enables STAT[RDRF] to become 1 because of..,7: Enables STAT[RDRF] to become 1 because of.." bitfld.long 0x20 9. "TXOFE,Transmit FIFO Overflow Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x20 8. "RXUFE,Receive FIFO Underflow Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x20 7. "TXFE,Transmit FIFO Enable" "0: Disables; buffer depth is 1,1: Enables; FIFO[TXFIFOSIZE] indicates the buffer.." newline rbitfld.long 0x20 4.--6. "TXFIFOSIZE,Transmit FIFO Buffer Depth" "0: Transmit FIFO buffer depth = 1 dataword,1: Transmit FIFO buffer depth = 4 datawords,2: Transmit FIFO buffer depth = 8 datawords,3: Transmit FIFO buffer depth = 16 datawords,4: Transmit FIFO buffer depth = 32 datawords,5: Transmit FIFO buffer depth = 64 datawords,6: Transmit FIFO buffer depth = 128 datawords,7: Transmit FIFO buffer depth = 256 datawords" bitfld.long 0x20 3. "RXFE,Receive FIFO Enable" "0: Disables; buffer depth is 1,1: Enables; FIFO[RXFIFOSIZE] indicates the buffer.." newline rbitfld.long 0x20 0.--2. "RXFIFOSIZE,Receive FIFO Buffer Depth" "0: Receive FIFO buffer depth = 1 dataword,1: Receive FIFO buffer depth = 4 datawords,2: Receive FIFO buffer depth = 8 datawords,3: Receive FIFO buffer depth = 16 datawords,4: Receive FIFO buffer depth = 32 datawords,5: Receive FIFO buffer depth = 64 datawords,6: Receive FIFO buffer depth = 128 datawords,7: Receive FIFO buffer depth = 256 datawords" line.long 0x24 "WATER,Watermark" rbitfld.long 0x24 24.--26. "RXCOUNT,Receive Counter" "0,1,2,3,4,5,6,7" bitfld.long 0x24 16.--17. "RXWATER,Receive Watermark" "0,1,2,3" newline rbitfld.long 0x24 8.--10. "TXCOUNT,Transmit Counter" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0.--1. "TXWATER,Transmit Watermark" "0,1,2,3" rgroup.long 0x30++0x3 line.long 0x0 "DATARO,Data Read-Only" hexmask.long.word 0x0 0.--15. 1. "DATA,Receive Data" tree.end tree "LPUART_8" base ad:0x4048C000 rgroup.long 0x0++0x7 line.long 0x0 "VERID,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Identification Number" line.long 0x4 "PARAM,Parameter" hexmask.long.byte 0x4 8.--15. 1. "RXFIFO,Receive FIFO Size" hexmask.long.byte 0x4 0.--7. 1. "TXFIFO,Transmit FIFO Size" group.long 0x8++0x27 line.long 0x0 "GLOBAL,Global" bitfld.long 0x0 1. "RST,Software Reset" "0: Not reset,1: Reset" line.long 0x4 "PINCFG,Pin Configuration" bitfld.long 0x4 0.--1. "TRGSEL,Trigger Select" "0: Input trigger disabled,1: Input trigger used instead of the RXD pin input,2: Input trigger used instead of the CTS_B pin input,3: Input trigger used to modulate the TXD pin.." line.long 0x8 "BAUD,Baud Rate" bitfld.long 0x8 31. "MAEN1,Match Address Mode Enable 1" "0: Disables,1: Enables" bitfld.long 0x8 30. "MAEN2,Match Address Mode Enable 2" "0: Disables,1: Enables" newline bitfld.long 0x8 29. "M10,10-Bit Mode Select" "0: Receiver and transmitter use 7-bit to 9-bit data..,1: Receiver and transmitter use 10-bit data.." hexmask.long.byte 0x8 24.--28. 1. "OSR,Oversampling Ratio (OSR)" newline bitfld.long 0x8 23. "TDMAE,Transmitter DMA Enable" "0: Disables DMA request,1: Enables DMA request" bitfld.long 0x8 21. "RDMAE,Receiver Full DMA Enable" "0: Disables DMA request,1: Enables DMA request" newline bitfld.long 0x8 18.--19. "MATCFG,Match Configuration" "0: Address match wakeup,1: Idle match wakeup,2: Match on and match off,3: Enables RWU on data match and match on/off for.." bitfld.long 0x8 17. "BOTHEDGE,Both Edge Sampling" "0: Receiver samples input data using the rising..,1: Receiver samples input data using the rising and.." newline bitfld.long 0x8 16. "RESYNCDIS,Resynchronization Disable" "0: Enables resynchronization,1: Disables resynchronization" bitfld.long 0x8 15. "LBKDIE,LIN Break Detect Interrupt Enable" "0: Disables hardware interrupts from STAT[LBKDIF]..,1: Requests hardware interrupt when STAT[LBKDIF] is 1" newline bitfld.long 0x8 14. "RXEDGIE,RX Input Active Edge Interrupt Enable" "0: Disables hardware interrupts from STAT[RXEDGIF],1: Requests hardware interrupts when STAT[RXEDGIF].." bitfld.long 0x8 13. "SBNS,Stop Bit Number Select" "0: One stop bit,1: Two stop bits" newline hexmask.long.word 0x8 0.--12. 1. "SBR,Baud Rate Modulo Divisor" line.long 0xC "STAT,Status" eventfld.long 0xC 31. "LBKDIF,LIN Break Detect Interrupt Flag" "0: Not detected,1: Detected" eventfld.long 0xC 30. "RXEDGIF,RXD Pin Active Edge Interrupt Flag" "0: Not occurred,1: Occurred" newline bitfld.long 0xC 29. "MSBF,MSB First" "0: LSB,1: MSB" bitfld.long 0xC 28. "RXINV,Receive Data Inversion" "0: Inverted,1: Not inverted" newline bitfld.long 0xC 27. "RWUID,Receive Wake Up Idle Detect" "0: STAT[IDLE] does not become 1,1: STAT[IDLE] becomes 1" bitfld.long 0xC 26. "BRK13,Break Character Generation Length" "0: 9 to 13 bit times,1: 12 to 15 bit times" newline bitfld.long 0xC 25. "LBKDE,LIN Break Detection Enable" "0: Disables,1: Enables" rbitfld.long 0xC 24. "RAF,Receiver Active Flag" "0: Idle waiting for a start bit,1: Receiver active (RXD pin input not idle)" newline rbitfld.long 0xC 23. "TDRE,Transmit Data Register Empty Flag" "0: Greater than watermark,1: Equal to or less than watermark" rbitfld.long 0xC 22. "TC,Transmission Complete Flag" "0: Transmitter active (sending data a preamble or a..,1: Transmitter idle (transmission activity complete)" newline rbitfld.long 0xC 21. "RDRF,Receive Data Register Full Flag" "0: Equal to or less than watermark,1: Greater than watermark" eventfld.long 0xC 20. "IDLE,Idle Line Flag" "0: No idle line detected,1: Idle line detected" newline eventfld.long 0xC 19. "OR,Receiver Overrun Flag" "0: No overrun,1: Receive overrun (new LPUART data lost)" eventfld.long 0xC 18. "NF,Noise Flag (NF)" "0: No noise detected,1: Noise detected" newline eventfld.long 0xC 17. "FE,Framing Error Flag (FE)" "0: No framing error detected (this does not..,1: Framing error detected" eventfld.long 0xC 16. "PF,Parity Error Flag (PF)" "0: No parity error detected,1: Parity error detected" newline eventfld.long 0xC 15. "MA1F,Match 1 Flag" "0: Not equal to MA1,1: Equal to MA1" eventfld.long 0xC 14. "MA2F,Match 2 Flag" "0: Not equal to MA2,1: Equal to MA2" newline bitfld.long 0xC 1. "AME,Address Mark Enable" "0: Address mark in character is MSB,1: Address mark in character is the last bit before.." bitfld.long 0xC 0. "LBKFE,LIN Break Flag Enable" "0: Disables LIN break detect,1: Enables LIN break detect" line.long 0x10 "CTRL,Control" bitfld.long 0x10 31. "R8T9,Receive Bit 8 Transmit Bit 9" "0,1" bitfld.long 0x10 30. "R9T8,Receive Bit 9 Transmit Bit 8" "0,1" newline bitfld.long 0x10 29. "TXDIR,TXD Pin Direction in Single-Wire Mode" "0: TXD pin is an input in Single-Wire mode,1: TXD pin is an output in Single-Wire mode" bitfld.long 0x10 28. "TXINV,Transmit Data Inversion" "0: Not inverted,1: Inverted" newline bitfld.long 0x10 27. "ORIE,Overrun Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 26. "NEIE,Noise Error Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 25. "FEIE,Framing Error Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 24. "PEIE,Parity Error Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 23. "TIE,Transmit Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 22. "TCIE,Transmission Complete Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 21. "RIE,Receiver Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 20. "ILIE,Idle Line Interrupt Enable" "0: Disables hardware interrupts from STAT[IDLE];..,1: Enables hardware interrupts when STAT[IDLE] = 1" newline bitfld.long 0x10 19. "TE,Transmitter Enable" "0: Disables,1: Enables" bitfld.long 0x10 18. "RE,Receiver Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 17. "RWU,Receiver Wakeup Control" "0: Normal receiver operation,1: LPUART receiver in standby waiting for a wakeup.." bitfld.long 0x10 16. "SBK,Send Break" "0: Normal transmitter operation,1: Queue break character(s) to be sent" newline bitfld.long 0x10 15. "MA1IE,Match 1 (MA1F) Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 14. "MA2IE,Match 2 (MA2F) Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 11. "M7,7-Bit Mode Select" "0: 8-bit to 10-bit data characters,1: 7-bit data characters" bitfld.long 0x10 8.--10. "IDLECFG,Idle Configuration" "0: 1,1: 2,2: 4,3: 8,4: 16,5: 32,6: 64,7: 128" newline bitfld.long 0x10 7. "LOOPS,Loop Mode Select" "0: Normal operation: RXD and TXD use separate pins,1: Loop mode or Single-Wire mode" bitfld.long 0x10 6. "DOZEEN,Enables LPUART in Doze mode." "0: Enables,1: Disables" newline bitfld.long 0x10 5. "RSRC,Receiver Source Select" "0: Internal Loopback mode,1: Single-wire mode" bitfld.long 0x10 4. "M,9-Bit Or 8-Bit Mode Select" "0: 8-bit data characters,1: 9-bit data characters" newline bitfld.long 0x10 3. "WAKE,Receiver Wakeup Method Select" "0: Configures CTRL[RWU] for idle-line wakeup,1: Configures CTRL[RWU] with address-mark wakeup" bitfld.long 0x10 2. "ILT,Idle Line Type Select" "0: After the start bit,1: After the stop bit" newline bitfld.long 0x10 1. "PE,Parity Enable" "0: Disables,1: Enables" bitfld.long 0x10 0. "PT,Parity Type" "0: Even parity,1: Odd parity" line.long 0x14 "DATA,Data" rbitfld.long 0x14 15. "NOISY,Noisy Data Received" "0: Received without noise,1: Received with noise" rbitfld.long 0x14 14. "PARITYE,Parity Error" "0: Received without a parity error,1: Received with a parity error" newline bitfld.long 0x14 13. "FRETSC,Frame Error Transmit Special Character" "0: Received without a frame error on reads or..,1: Received with a frame error on reads or.." rbitfld.long 0x14 12. "RXEMPT,Receive Buffer Empty" "0: Contains valid data,1: Contains invalid data and is empty" newline rbitfld.long 0x14 11. "IDLINE,Idle Line" "0: Received was not idle,1: Receiver was idle" rbitfld.long 0x14 10. "LINBRK,LIN Break" "0: LIN break not detected or LIN break detect..,1: LIN break detected" newline bitfld.long 0x14 9. "R9T9,Read Receive FIFO Bit 9 Or Write Transmit FIFO Bit 9" "0,1" bitfld.long 0x14 8. "R8T8,Read Receive FIFO Bit 8 Or Write Transmit FIFO Bit 8" "0,1" newline bitfld.long 0x14 7. "R7T7,Read Receive FIFO Bit 7 Or Write Transmit FIFO Bit 7" "0,1" bitfld.long 0x14 6. "R6T6,Read Receive FIFO Bit 6 Or Write Transmit FIFO Bit 6" "0,1" newline bitfld.long 0x14 5. "R5T5,Read Receive FIFO Bit 5 Or Write Transmit FIFO Bit 5" "0,1" bitfld.long 0x14 4. "R4T4,Read Receive FIFO Bit 4 Or Write Transmit FIFO Bit 4" "0,1" newline bitfld.long 0x14 3. "R3T3,Read Receive FIFO Bit 3 Or Write Transmit FIFO Bit 3" "0,1" bitfld.long 0x14 2. "R2T2,Read Receive FIFO Bit 2 Or Write Transmit FIFO Bit 2" "0,1" newline bitfld.long 0x14 1. "R1T1,Read Receive FIFO Bit 1 Or Write Transmit FIFO Bit 1" "0,1" bitfld.long 0x14 0. "R0T0,Read Receive FIFO Bit 0 Or Write Transmit FIFO Bit 0" "0,1" line.long 0x18 "MATCH,Match Address" hexmask.long.word 0x18 16.--25. 1. "MA2,Match Address 2" hexmask.long.word 0x18 0.--9. 1. "MA1,Match Address 1" line.long 0x1C "MODIR,MODEM IrDA" bitfld.long 0x1C 18. "IREN,IR Enable" "0: Disables,1: Enables" bitfld.long 0x1C 16.--17. "TNP,Transmitter Narrow Pulse" "0: 1 / OSR,1: 2 / OSR,2: 3 / OSR,3: 4 / OSR" newline bitfld.long 0x1C 8.--9. "RTSWATER,Receive RTS Configuration" "0,1,2,3" bitfld.long 0x1C 5. "TXCTSSRC,Transmit CTS Source" "0: The CTS_B pin,1: An internal connection to the receiver address.." newline bitfld.long 0x1C 4. "TXCTSC,Transmit CTS Configuration" "0: Sampled at the start of each character,1: Sampled when the transmitter is idle" bitfld.long 0x1C 3. "RXRTSE,Receiver RTS Enable" "0: Disables,1: Enables" newline bitfld.long 0x1C 2. "TXRTSPOL,Transmitter RTS Polarity" "0: Transmitter RTS is active low,1: Transmitter RTS is active high" bitfld.long 0x1C 1. "TXRTSE,Transmitter RTS Enable" "0: Disables,1: Enables" newline bitfld.long 0x1C 0. "TXCTSE,Transmitter CTS Enable" "0: Disables,1: Enables" line.long 0x20 "FIFO,FIFO" rbitfld.long 0x20 23. "TXEMPT,Transmit FIFO Or Buffer Empty" "0: Not empty,1: Empty" rbitfld.long 0x20 22. "RXEMPT,Receive FIFO Or Buffer Empty" "0: Not empty,1: Empty" newline eventfld.long 0x20 17. "TXOF,Transmitter FIFO Overflow Flag" "0: No overflow,1: Overflow" eventfld.long 0x20 16. "RXUF,Receiver FIFO Underflow Flag" "0: No underflow,1: Underflow" newline bitfld.long 0x20 15. "TXFLUSH,Transmit FIFO Flush" "0: No effect,1: All data is flushed out" bitfld.long 0x20 14. "RXFLUSH,Receive FIFO Flush" "0: No effect,1: All data is flushed out" newline bitfld.long 0x20 10.--12. "RXIDEN,Receiver Idle Empty Enable" "0: Disables STAT[RDRF] to become 1 because of..,1: Enables STAT[RDRF] to become 1 because of..,2: Enables STAT[RDRF] to become 1 because of..,3: Enables STAT[RDRF] to become 1 because of..,4: Enables STAT[RDRF] to become 1 because of..,5: Enables STAT[RDRF] to become 1 because of..,6: Enables STAT[RDRF] to become 1 because of..,7: Enables STAT[RDRF] to become 1 because of.." bitfld.long 0x20 9. "TXOFE,Transmit FIFO Overflow Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x20 8. "RXUFE,Receive FIFO Underflow Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x20 7. "TXFE,Transmit FIFO Enable" "0: Disables; buffer depth is 1,1: Enables; FIFO[TXFIFOSIZE] indicates the buffer.." newline rbitfld.long 0x20 4.--6. "TXFIFOSIZE,Transmit FIFO Buffer Depth" "0: Transmit FIFO buffer depth = 1 dataword,1: Transmit FIFO buffer depth = 4 datawords,2: Transmit FIFO buffer depth = 8 datawords,3: Transmit FIFO buffer depth = 16 datawords,4: Transmit FIFO buffer depth = 32 datawords,5: Transmit FIFO buffer depth = 64 datawords,6: Transmit FIFO buffer depth = 128 datawords,7: Transmit FIFO buffer depth = 256 datawords" bitfld.long 0x20 3. "RXFE,Receive FIFO Enable" "0: Disables; buffer depth is 1,1: Enables; FIFO[RXFIFOSIZE] indicates the buffer.." newline rbitfld.long 0x20 0.--2. "RXFIFOSIZE,Receive FIFO Buffer Depth" "0: Receive FIFO buffer depth = 1 dataword,1: Receive FIFO buffer depth = 4 datawords,2: Receive FIFO buffer depth = 8 datawords,3: Receive FIFO buffer depth = 16 datawords,4: Receive FIFO buffer depth = 32 datawords,5: Receive FIFO buffer depth = 64 datawords,6: Receive FIFO buffer depth = 128 datawords,7: Receive FIFO buffer depth = 256 datawords" line.long 0x24 "WATER,Watermark" rbitfld.long 0x24 24.--26. "RXCOUNT,Receive Counter" "0,1,2,3,4,5,6,7" bitfld.long 0x24 16.--17. "RXWATER,Receive Watermark" "0,1,2,3" newline rbitfld.long 0x24 8.--10. "TXCOUNT,Transmit Counter" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0.--1. "TXWATER,Transmit Watermark" "0,1,2,3" rgroup.long 0x30++0x3 line.long 0x0 "DATARO,Data Read-Only" hexmask.long.word 0x0 0.--15. 1. "DATA,Receive Data" tree.end tree "LPUART_9" base ad:0x40490000 rgroup.long 0x0++0x7 line.long 0x0 "VERID,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Identification Number" line.long 0x4 "PARAM,Parameter" hexmask.long.byte 0x4 8.--15. 1. "RXFIFO,Receive FIFO Size" hexmask.long.byte 0x4 0.--7. 1. "TXFIFO,Transmit FIFO Size" group.long 0x8++0x27 line.long 0x0 "GLOBAL,Global" bitfld.long 0x0 1. "RST,Software Reset" "0: Not reset,1: Reset" line.long 0x4 "PINCFG,Pin Configuration" bitfld.long 0x4 0.--1. "TRGSEL,Trigger Select" "0: Input trigger disabled,1: Input trigger used instead of the RXD pin input,2: Input trigger used instead of the CTS_B pin input,3: Input trigger used to modulate the TXD pin.." line.long 0x8 "BAUD,Baud Rate" bitfld.long 0x8 31. "MAEN1,Match Address Mode Enable 1" "0: Disables,1: Enables" bitfld.long 0x8 30. "MAEN2,Match Address Mode Enable 2" "0: Disables,1: Enables" newline bitfld.long 0x8 29. "M10,10-Bit Mode Select" "0: Receiver and transmitter use 7-bit to 9-bit data..,1: Receiver and transmitter use 10-bit data.." hexmask.long.byte 0x8 24.--28. 1. "OSR,Oversampling Ratio (OSR)" newline bitfld.long 0x8 23. "TDMAE,Transmitter DMA Enable" "0: Disables DMA request,1: Enables DMA request" bitfld.long 0x8 21. "RDMAE,Receiver Full DMA Enable" "0: Disables DMA request,1: Enables DMA request" newline bitfld.long 0x8 18.--19. "MATCFG,Match Configuration" "0: Address match wakeup,1: Idle match wakeup,2: Match on and match off,3: Enables RWU on data match and match on/off for.." bitfld.long 0x8 17. "BOTHEDGE,Both Edge Sampling" "0: Receiver samples input data using the rising..,1: Receiver samples input data using the rising and.." newline bitfld.long 0x8 16. "RESYNCDIS,Resynchronization Disable" "0: Enables resynchronization,1: Disables resynchronization" bitfld.long 0x8 15. "LBKDIE,LIN Break Detect Interrupt Enable" "0: Disables hardware interrupts from STAT[LBKDIF]..,1: Requests hardware interrupt when STAT[LBKDIF] is 1" newline bitfld.long 0x8 14. "RXEDGIE,RX Input Active Edge Interrupt Enable" "0: Disables hardware interrupts from STAT[RXEDGIF],1: Requests hardware interrupts when STAT[RXEDGIF].." bitfld.long 0x8 13. "SBNS,Stop Bit Number Select" "0: One stop bit,1: Two stop bits" newline hexmask.long.word 0x8 0.--12. 1. "SBR,Baud Rate Modulo Divisor" line.long 0xC "STAT,Status" eventfld.long 0xC 31. "LBKDIF,LIN Break Detect Interrupt Flag" "0: Not detected,1: Detected" eventfld.long 0xC 30. "RXEDGIF,RXD Pin Active Edge Interrupt Flag" "0: Not occurred,1: Occurred" newline bitfld.long 0xC 29. "MSBF,MSB First" "0: LSB,1: MSB" bitfld.long 0xC 28. "RXINV,Receive Data Inversion" "0: Inverted,1: Not inverted" newline bitfld.long 0xC 27. "RWUID,Receive Wake Up Idle Detect" "0: STAT[IDLE] does not become 1,1: STAT[IDLE] becomes 1" bitfld.long 0xC 26. "BRK13,Break Character Generation Length" "0: 9 to 13 bit times,1: 12 to 15 bit times" newline bitfld.long 0xC 25. "LBKDE,LIN Break Detection Enable" "0: Disables,1: Enables" rbitfld.long 0xC 24. "RAF,Receiver Active Flag" "0: Idle waiting for a start bit,1: Receiver active (RXD pin input not idle)" newline rbitfld.long 0xC 23. "TDRE,Transmit Data Register Empty Flag" "0: Greater than watermark,1: Equal to or less than watermark" rbitfld.long 0xC 22. "TC,Transmission Complete Flag" "0: Transmitter active (sending data a preamble or a..,1: Transmitter idle (transmission activity complete)" newline rbitfld.long 0xC 21. "RDRF,Receive Data Register Full Flag" "0: Equal to or less than watermark,1: Greater than watermark" eventfld.long 0xC 20. "IDLE,Idle Line Flag" "0: No idle line detected,1: Idle line detected" newline eventfld.long 0xC 19. "OR,Receiver Overrun Flag" "0: No overrun,1: Receive overrun (new LPUART data lost)" eventfld.long 0xC 18. "NF,Noise Flag (NF)" "0: No noise detected,1: Noise detected" newline eventfld.long 0xC 17. "FE,Framing Error Flag (FE)" "0: No framing error detected (this does not..,1: Framing error detected" eventfld.long 0xC 16. "PF,Parity Error Flag (PF)" "0: No parity error detected,1: Parity error detected" newline eventfld.long 0xC 15. "MA1F,Match 1 Flag" "0: Not equal to MA1,1: Equal to MA1" eventfld.long 0xC 14. "MA2F,Match 2 Flag" "0: Not equal to MA2,1: Equal to MA2" newline bitfld.long 0xC 1. "AME,Address Mark Enable" "0: Address mark in character is MSB,1: Address mark in character is the last bit before.." bitfld.long 0xC 0. "LBKFE,LIN Break Flag Enable" "0: Disables LIN break detect,1: Enables LIN break detect" line.long 0x10 "CTRL,Control" bitfld.long 0x10 31. "R8T9,Receive Bit 8 Transmit Bit 9" "0,1" bitfld.long 0x10 30. "R9T8,Receive Bit 9 Transmit Bit 8" "0,1" newline bitfld.long 0x10 29. "TXDIR,TXD Pin Direction in Single-Wire Mode" "0: TXD pin is an input in Single-Wire mode,1: TXD pin is an output in Single-Wire mode" bitfld.long 0x10 28. "TXINV,Transmit Data Inversion" "0: Not inverted,1: Inverted" newline bitfld.long 0x10 27. "ORIE,Overrun Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 26. "NEIE,Noise Error Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 25. "FEIE,Framing Error Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 24. "PEIE,Parity Error Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 23. "TIE,Transmit Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 22. "TCIE,Transmission Complete Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 21. "RIE,Receiver Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 20. "ILIE,Idle Line Interrupt Enable" "0: Disables hardware interrupts from STAT[IDLE];..,1: Enables hardware interrupts when STAT[IDLE] = 1" newline bitfld.long 0x10 19. "TE,Transmitter Enable" "0: Disables,1: Enables" bitfld.long 0x10 18. "RE,Receiver Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 17. "RWU,Receiver Wakeup Control" "0: Normal receiver operation,1: LPUART receiver in standby waiting for a wakeup.." bitfld.long 0x10 16. "SBK,Send Break" "0: Normal transmitter operation,1: Queue break character(s) to be sent" newline bitfld.long 0x10 15. "MA1IE,Match 1 (MA1F) Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 14. "MA2IE,Match 2 (MA2F) Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 11. "M7,7-Bit Mode Select" "0: 8-bit to 10-bit data characters,1: 7-bit data characters" bitfld.long 0x10 8.--10. "IDLECFG,Idle Configuration" "0: 1,1: 2,2: 4,3: 8,4: 16,5: 32,6: 64,7: 128" newline bitfld.long 0x10 7. "LOOPS,Loop Mode Select" "0: Normal operation: RXD and TXD use separate pins,1: Loop mode or Single-Wire mode" bitfld.long 0x10 6. "DOZEEN,Enables LPUART in Doze mode." "0: Enables,1: Disables" newline bitfld.long 0x10 5. "RSRC,Receiver Source Select" "0: Internal Loopback mode,1: Single-wire mode" bitfld.long 0x10 4. "M,9-Bit Or 8-Bit Mode Select" "0: 8-bit data characters,1: 9-bit data characters" newline bitfld.long 0x10 3. "WAKE,Receiver Wakeup Method Select" "0: Configures CTRL[RWU] for idle-line wakeup,1: Configures CTRL[RWU] with address-mark wakeup" bitfld.long 0x10 2. "ILT,Idle Line Type Select" "0: After the start bit,1: After the stop bit" newline bitfld.long 0x10 1. "PE,Parity Enable" "0: Disables,1: Enables" bitfld.long 0x10 0. "PT,Parity Type" "0: Even parity,1: Odd parity" line.long 0x14 "DATA,Data" rbitfld.long 0x14 15. "NOISY,Noisy Data Received" "0: Received without noise,1: Received with noise" rbitfld.long 0x14 14. "PARITYE,Parity Error" "0: Received without a parity error,1: Received with a parity error" newline bitfld.long 0x14 13. "FRETSC,Frame Error Transmit Special Character" "0: Received without a frame error on reads or..,1: Received with a frame error on reads or.." rbitfld.long 0x14 12. "RXEMPT,Receive Buffer Empty" "0: Contains valid data,1: Contains invalid data and is empty" newline rbitfld.long 0x14 11. "IDLINE,Idle Line" "0: Received was not idle,1: Receiver was idle" rbitfld.long 0x14 10. "LINBRK,LIN Break" "0: LIN break not detected or LIN break detect..,1: LIN break detected" newline bitfld.long 0x14 9. "R9T9,Read Receive FIFO Bit 9 Or Write Transmit FIFO Bit 9" "0,1" bitfld.long 0x14 8. "R8T8,Read Receive FIFO Bit 8 Or Write Transmit FIFO Bit 8" "0,1" newline bitfld.long 0x14 7. "R7T7,Read Receive FIFO Bit 7 Or Write Transmit FIFO Bit 7" "0,1" bitfld.long 0x14 6. "R6T6,Read Receive FIFO Bit 6 Or Write Transmit FIFO Bit 6" "0,1" newline bitfld.long 0x14 5. "R5T5,Read Receive FIFO Bit 5 Or Write Transmit FIFO Bit 5" "0,1" bitfld.long 0x14 4. "R4T4,Read Receive FIFO Bit 4 Or Write Transmit FIFO Bit 4" "0,1" newline bitfld.long 0x14 3. "R3T3,Read Receive FIFO Bit 3 Or Write Transmit FIFO Bit 3" "0,1" bitfld.long 0x14 2. "R2T2,Read Receive FIFO Bit 2 Or Write Transmit FIFO Bit 2" "0,1" newline bitfld.long 0x14 1. "R1T1,Read Receive FIFO Bit 1 Or Write Transmit FIFO Bit 1" "0,1" bitfld.long 0x14 0. "R0T0,Read Receive FIFO Bit 0 Or Write Transmit FIFO Bit 0" "0,1" line.long 0x18 "MATCH,Match Address" hexmask.long.word 0x18 16.--25. 1. "MA2,Match Address 2" hexmask.long.word 0x18 0.--9. 1. "MA1,Match Address 1" line.long 0x1C "MODIR,MODEM IrDA" bitfld.long 0x1C 18. "IREN,IR Enable" "0: Disables,1: Enables" bitfld.long 0x1C 16.--17. "TNP,Transmitter Narrow Pulse" "0: 1 / OSR,1: 2 / OSR,2: 3 / OSR,3: 4 / OSR" newline bitfld.long 0x1C 8.--9. "RTSWATER,Receive RTS Configuration" "0,1,2,3" bitfld.long 0x1C 5. "TXCTSSRC,Transmit CTS Source" "0: The CTS_B pin,1: An internal connection to the receiver address.." newline bitfld.long 0x1C 4. "TXCTSC,Transmit CTS Configuration" "0: Sampled at the start of each character,1: Sampled when the transmitter is idle" bitfld.long 0x1C 3. "RXRTSE,Receiver RTS Enable" "0: Disables,1: Enables" newline bitfld.long 0x1C 2. "TXRTSPOL,Transmitter RTS Polarity" "0: Transmitter RTS is active low,1: Transmitter RTS is active high" bitfld.long 0x1C 1. "TXRTSE,Transmitter RTS Enable" "0: Disables,1: Enables" newline bitfld.long 0x1C 0. "TXCTSE,Transmitter CTS Enable" "0: Disables,1: Enables" line.long 0x20 "FIFO,FIFO" rbitfld.long 0x20 23. "TXEMPT,Transmit FIFO Or Buffer Empty" "0: Not empty,1: Empty" rbitfld.long 0x20 22. "RXEMPT,Receive FIFO Or Buffer Empty" "0: Not empty,1: Empty" newline eventfld.long 0x20 17. "TXOF,Transmitter FIFO Overflow Flag" "0: No overflow,1: Overflow" eventfld.long 0x20 16. "RXUF,Receiver FIFO Underflow Flag" "0: No underflow,1: Underflow" newline bitfld.long 0x20 15. "TXFLUSH,Transmit FIFO Flush" "0: No effect,1: All data is flushed out" bitfld.long 0x20 14. "RXFLUSH,Receive FIFO Flush" "0: No effect,1: All data is flushed out" newline bitfld.long 0x20 10.--12. "RXIDEN,Receiver Idle Empty Enable" "0: Disables STAT[RDRF] to become 1 because of..,1: Enables STAT[RDRF] to become 1 because of..,2: Enables STAT[RDRF] to become 1 because of..,3: Enables STAT[RDRF] to become 1 because of..,4: Enables STAT[RDRF] to become 1 because of..,5: Enables STAT[RDRF] to become 1 because of..,6: Enables STAT[RDRF] to become 1 because of..,7: Enables STAT[RDRF] to become 1 because of.." bitfld.long 0x20 9. "TXOFE,Transmit FIFO Overflow Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x20 8. "RXUFE,Receive FIFO Underflow Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x20 7. "TXFE,Transmit FIFO Enable" "0: Disables; buffer depth is 1,1: Enables; FIFO[TXFIFOSIZE] indicates the buffer.." newline rbitfld.long 0x20 4.--6. "TXFIFOSIZE,Transmit FIFO Buffer Depth" "0: Transmit FIFO buffer depth = 1 dataword,1: Transmit FIFO buffer depth = 4 datawords,2: Transmit FIFO buffer depth = 8 datawords,3: Transmit FIFO buffer depth = 16 datawords,4: Transmit FIFO buffer depth = 32 datawords,5: Transmit FIFO buffer depth = 64 datawords,6: Transmit FIFO buffer depth = 128 datawords,7: Transmit FIFO buffer depth = 256 datawords" bitfld.long 0x20 3. "RXFE,Receive FIFO Enable" "0: Disables; buffer depth is 1,1: Enables; FIFO[RXFIFOSIZE] indicates the buffer.." newline rbitfld.long 0x20 0.--2. "RXFIFOSIZE,Receive FIFO Buffer Depth" "0: Receive FIFO buffer depth = 1 dataword,1: Receive FIFO buffer depth = 4 datawords,2: Receive FIFO buffer depth = 8 datawords,3: Receive FIFO buffer depth = 16 datawords,4: Receive FIFO buffer depth = 32 datawords,5: Receive FIFO buffer depth = 64 datawords,6: Receive FIFO buffer depth = 128 datawords,7: Receive FIFO buffer depth = 256 datawords" line.long 0x24 "WATER,Watermark" rbitfld.long 0x24 24.--26. "RXCOUNT,Receive Counter" "0,1,2,3,4,5,6,7" bitfld.long 0x24 16.--17. "RXWATER,Receive Watermark" "0,1,2,3" newline rbitfld.long 0x24 8.--10. "TXCOUNT,Transmit Counter" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0.--1. "TXWATER,Transmit Watermark" "0,1,2,3" rgroup.long 0x30++0x3 line.long 0x0 "DATARO,Data Read-Only" hexmask.long.word 0x0 0.--15. 1. "DATA,Receive Data" tree.end tree "LPUART_10" base ad:0x40494000 rgroup.long 0x0++0x7 line.long 0x0 "VERID,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Identification Number" line.long 0x4 "PARAM,Parameter" hexmask.long.byte 0x4 8.--15. 1. "RXFIFO,Receive FIFO Size" hexmask.long.byte 0x4 0.--7. 1. "TXFIFO,Transmit FIFO Size" group.long 0x8++0x27 line.long 0x0 "GLOBAL,Global" bitfld.long 0x0 1. "RST,Software Reset" "0: Not reset,1: Reset" line.long 0x4 "PINCFG,Pin Configuration" bitfld.long 0x4 0.--1. "TRGSEL,Trigger Select" "0: Input trigger disabled,1: Input trigger used instead of the RXD pin input,2: Input trigger used instead of the CTS_B pin input,3: Input trigger used to modulate the TXD pin.." line.long 0x8 "BAUD,Baud Rate" bitfld.long 0x8 31. "MAEN1,Match Address Mode Enable 1" "0: Disables,1: Enables" bitfld.long 0x8 30. "MAEN2,Match Address Mode Enable 2" "0: Disables,1: Enables" newline bitfld.long 0x8 29. "M10,10-Bit Mode Select" "0: Receiver and transmitter use 7-bit to 9-bit data..,1: Receiver and transmitter use 10-bit data.." hexmask.long.byte 0x8 24.--28. 1. "OSR,Oversampling Ratio (OSR)" newline bitfld.long 0x8 23. "TDMAE,Transmitter DMA Enable" "0: Disables DMA request,1: Enables DMA request" bitfld.long 0x8 21. "RDMAE,Receiver Full DMA Enable" "0: Disables DMA request,1: Enables DMA request" newline bitfld.long 0x8 18.--19. "MATCFG,Match Configuration" "0: Address match wakeup,1: Idle match wakeup,2: Match on and match off,3: Enables RWU on data match and match on/off for.." bitfld.long 0x8 17. "BOTHEDGE,Both Edge Sampling" "0: Receiver samples input data using the rising..,1: Receiver samples input data using the rising and.." newline bitfld.long 0x8 16. "RESYNCDIS,Resynchronization Disable" "0: Enables resynchronization,1: Disables resynchronization" bitfld.long 0x8 15. "LBKDIE,LIN Break Detect Interrupt Enable" "0: Disables hardware interrupts from STAT[LBKDIF]..,1: Requests hardware interrupt when STAT[LBKDIF] is 1" newline bitfld.long 0x8 14. "RXEDGIE,RX Input Active Edge Interrupt Enable" "0: Disables hardware interrupts from STAT[RXEDGIF],1: Requests hardware interrupts when STAT[RXEDGIF].." bitfld.long 0x8 13. "SBNS,Stop Bit Number Select" "0: One stop bit,1: Two stop bits" newline hexmask.long.word 0x8 0.--12. 1. "SBR,Baud Rate Modulo Divisor" line.long 0xC "STAT,Status" eventfld.long 0xC 31. "LBKDIF,LIN Break Detect Interrupt Flag" "0: Not detected,1: Detected" eventfld.long 0xC 30. "RXEDGIF,RXD Pin Active Edge Interrupt Flag" "0: Not occurred,1: Occurred" newline bitfld.long 0xC 29. "MSBF,MSB First" "0: LSB,1: MSB" bitfld.long 0xC 28. "RXINV,Receive Data Inversion" "0: Inverted,1: Not inverted" newline bitfld.long 0xC 27. "RWUID,Receive Wake Up Idle Detect" "0: STAT[IDLE] does not become 1,1: STAT[IDLE] becomes 1" bitfld.long 0xC 26. "BRK13,Break Character Generation Length" "0: 9 to 13 bit times,1: 12 to 15 bit times" newline bitfld.long 0xC 25. "LBKDE,LIN Break Detection Enable" "0: Disables,1: Enables" rbitfld.long 0xC 24. "RAF,Receiver Active Flag" "0: Idle waiting for a start bit,1: Receiver active (RXD pin input not idle)" newline rbitfld.long 0xC 23. "TDRE,Transmit Data Register Empty Flag" "0: Greater than watermark,1: Equal to or less than watermark" rbitfld.long 0xC 22. "TC,Transmission Complete Flag" "0: Transmitter active (sending data a preamble or a..,1: Transmitter idle (transmission activity complete)" newline rbitfld.long 0xC 21. "RDRF,Receive Data Register Full Flag" "0: Equal to or less than watermark,1: Greater than watermark" eventfld.long 0xC 20. "IDLE,Idle Line Flag" "0: No idle line detected,1: Idle line detected" newline eventfld.long 0xC 19. "OR,Receiver Overrun Flag" "0: No overrun,1: Receive overrun (new LPUART data lost)" eventfld.long 0xC 18. "NF,Noise Flag (NF)" "0: No noise detected,1: Noise detected" newline eventfld.long 0xC 17. "FE,Framing Error Flag (FE)" "0: No framing error detected (this does not..,1: Framing error detected" eventfld.long 0xC 16. "PF,Parity Error Flag (PF)" "0: No parity error detected,1: Parity error detected" newline eventfld.long 0xC 15. "MA1F,Match 1 Flag" "0: Not equal to MA1,1: Equal to MA1" eventfld.long 0xC 14. "MA2F,Match 2 Flag" "0: Not equal to MA2,1: Equal to MA2" newline bitfld.long 0xC 1. "AME,Address Mark Enable" "0: Address mark in character is MSB,1: Address mark in character is the last bit before.." bitfld.long 0xC 0. "LBKFE,LIN Break Flag Enable" "0: Disables LIN break detect,1: Enables LIN break detect" line.long 0x10 "CTRL,Control" bitfld.long 0x10 31. "R8T9,Receive Bit 8 Transmit Bit 9" "0,1" bitfld.long 0x10 30. "R9T8,Receive Bit 9 Transmit Bit 8" "0,1" newline bitfld.long 0x10 29. "TXDIR,TXD Pin Direction in Single-Wire Mode" "0: TXD pin is an input in Single-Wire mode,1: TXD pin is an output in Single-Wire mode" bitfld.long 0x10 28. "TXINV,Transmit Data Inversion" "0: Not inverted,1: Inverted" newline bitfld.long 0x10 27. "ORIE,Overrun Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 26. "NEIE,Noise Error Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 25. "FEIE,Framing Error Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 24. "PEIE,Parity Error Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 23. "TIE,Transmit Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 22. "TCIE,Transmission Complete Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 21. "RIE,Receiver Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 20. "ILIE,Idle Line Interrupt Enable" "0: Disables hardware interrupts from STAT[IDLE];..,1: Enables hardware interrupts when STAT[IDLE] = 1" newline bitfld.long 0x10 19. "TE,Transmitter Enable" "0: Disables,1: Enables" bitfld.long 0x10 18. "RE,Receiver Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 17. "RWU,Receiver Wakeup Control" "0: Normal receiver operation,1: LPUART receiver in standby waiting for a wakeup.." bitfld.long 0x10 16. "SBK,Send Break" "0: Normal transmitter operation,1: Queue break character(s) to be sent" newline bitfld.long 0x10 15. "MA1IE,Match 1 (MA1F) Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 14. "MA2IE,Match 2 (MA2F) Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 11. "M7,7-Bit Mode Select" "0: 8-bit to 10-bit data characters,1: 7-bit data characters" bitfld.long 0x10 8.--10. "IDLECFG,Idle Configuration" "0: 1,1: 2,2: 4,3: 8,4: 16,5: 32,6: 64,7: 128" newline bitfld.long 0x10 7. "LOOPS,Loop Mode Select" "0: Normal operation: RXD and TXD use separate pins,1: Loop mode or Single-Wire mode" bitfld.long 0x10 6. "DOZEEN,Enables LPUART in Doze mode." "0: Enables,1: Disables" newline bitfld.long 0x10 5. "RSRC,Receiver Source Select" "0: Internal Loopback mode,1: Single-wire mode" bitfld.long 0x10 4. "M,9-Bit Or 8-Bit Mode Select" "0: 8-bit data characters,1: 9-bit data characters" newline bitfld.long 0x10 3. "WAKE,Receiver Wakeup Method Select" "0: Configures CTRL[RWU] for idle-line wakeup,1: Configures CTRL[RWU] with address-mark wakeup" bitfld.long 0x10 2. "ILT,Idle Line Type Select" "0: After the start bit,1: After the stop bit" newline bitfld.long 0x10 1. "PE,Parity Enable" "0: Disables,1: Enables" bitfld.long 0x10 0. "PT,Parity Type" "0: Even parity,1: Odd parity" line.long 0x14 "DATA,Data" rbitfld.long 0x14 15. "NOISY,Noisy Data Received" "0: Received without noise,1: Received with noise" rbitfld.long 0x14 14. "PARITYE,Parity Error" "0: Received without a parity error,1: Received with a parity error" newline bitfld.long 0x14 13. "FRETSC,Frame Error Transmit Special Character" "0: Received without a frame error on reads or..,1: Received with a frame error on reads or.." rbitfld.long 0x14 12. "RXEMPT,Receive Buffer Empty" "0: Contains valid data,1: Contains invalid data and is empty" newline rbitfld.long 0x14 11. "IDLINE,Idle Line" "0: Received was not idle,1: Receiver was idle" rbitfld.long 0x14 10. "LINBRK,LIN Break" "0: LIN break not detected or LIN break detect..,1: LIN break detected" newline bitfld.long 0x14 9. "R9T9,Read Receive FIFO Bit 9 Or Write Transmit FIFO Bit 9" "0,1" bitfld.long 0x14 8. "R8T8,Read Receive FIFO Bit 8 Or Write Transmit FIFO Bit 8" "0,1" newline bitfld.long 0x14 7. "R7T7,Read Receive FIFO Bit 7 Or Write Transmit FIFO Bit 7" "0,1" bitfld.long 0x14 6. "R6T6,Read Receive FIFO Bit 6 Or Write Transmit FIFO Bit 6" "0,1" newline bitfld.long 0x14 5. "R5T5,Read Receive FIFO Bit 5 Or Write Transmit FIFO Bit 5" "0,1" bitfld.long 0x14 4. "R4T4,Read Receive FIFO Bit 4 Or Write Transmit FIFO Bit 4" "0,1" newline bitfld.long 0x14 3. "R3T3,Read Receive FIFO Bit 3 Or Write Transmit FIFO Bit 3" "0,1" bitfld.long 0x14 2. "R2T2,Read Receive FIFO Bit 2 Or Write Transmit FIFO Bit 2" "0,1" newline bitfld.long 0x14 1. "R1T1,Read Receive FIFO Bit 1 Or Write Transmit FIFO Bit 1" "0,1" bitfld.long 0x14 0. "R0T0,Read Receive FIFO Bit 0 Or Write Transmit FIFO Bit 0" "0,1" line.long 0x18 "MATCH,Match Address" hexmask.long.word 0x18 16.--25. 1. "MA2,Match Address 2" hexmask.long.word 0x18 0.--9. 1. "MA1,Match Address 1" line.long 0x1C "MODIR,MODEM IrDA" bitfld.long 0x1C 18. "IREN,IR Enable" "0: Disables,1: Enables" bitfld.long 0x1C 16.--17. "TNP,Transmitter Narrow Pulse" "0: 1 / OSR,1: 2 / OSR,2: 3 / OSR,3: 4 / OSR" newline bitfld.long 0x1C 8.--9. "RTSWATER,Receive RTS Configuration" "0,1,2,3" bitfld.long 0x1C 5. "TXCTSSRC,Transmit CTS Source" "0: The CTS_B pin,1: An internal connection to the receiver address.." newline bitfld.long 0x1C 4. "TXCTSC,Transmit CTS Configuration" "0: Sampled at the start of each character,1: Sampled when the transmitter is idle" bitfld.long 0x1C 3. "RXRTSE,Receiver RTS Enable" "0: Disables,1: Enables" newline bitfld.long 0x1C 2. "TXRTSPOL,Transmitter RTS Polarity" "0: Transmitter RTS is active low,1: Transmitter RTS is active high" bitfld.long 0x1C 1. "TXRTSE,Transmitter RTS Enable" "0: Disables,1: Enables" newline bitfld.long 0x1C 0. "TXCTSE,Transmitter CTS Enable" "0: Disables,1: Enables" line.long 0x20 "FIFO,FIFO" rbitfld.long 0x20 23. "TXEMPT,Transmit FIFO Or Buffer Empty" "0: Not empty,1: Empty" rbitfld.long 0x20 22. "RXEMPT,Receive FIFO Or Buffer Empty" "0: Not empty,1: Empty" newline eventfld.long 0x20 17. "TXOF,Transmitter FIFO Overflow Flag" "0: No overflow,1: Overflow" eventfld.long 0x20 16. "RXUF,Receiver FIFO Underflow Flag" "0: No underflow,1: Underflow" newline bitfld.long 0x20 15. "TXFLUSH,Transmit FIFO Flush" "0: No effect,1: All data is flushed out" bitfld.long 0x20 14. "RXFLUSH,Receive FIFO Flush" "0: No effect,1: All data is flushed out" newline bitfld.long 0x20 10.--12. "RXIDEN,Receiver Idle Empty Enable" "0: Disables STAT[RDRF] to become 1 because of..,1: Enables STAT[RDRF] to become 1 because of..,2: Enables STAT[RDRF] to become 1 because of..,3: Enables STAT[RDRF] to become 1 because of..,4: Enables STAT[RDRF] to become 1 because of..,5: Enables STAT[RDRF] to become 1 because of..,6: Enables STAT[RDRF] to become 1 because of..,7: Enables STAT[RDRF] to become 1 because of.." bitfld.long 0x20 9. "TXOFE,Transmit FIFO Overflow Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x20 8. "RXUFE,Receive FIFO Underflow Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x20 7. "TXFE,Transmit FIFO Enable" "0: Disables; buffer depth is 1,1: Enables; FIFO[TXFIFOSIZE] indicates the buffer.." newline rbitfld.long 0x20 4.--6. "TXFIFOSIZE,Transmit FIFO Buffer Depth" "0: Transmit FIFO buffer depth = 1 dataword,1: Transmit FIFO buffer depth = 4 datawords,2: Transmit FIFO buffer depth = 8 datawords,3: Transmit FIFO buffer depth = 16 datawords,4: Transmit FIFO buffer depth = 32 datawords,5: Transmit FIFO buffer depth = 64 datawords,6: Transmit FIFO buffer depth = 128 datawords,7: Transmit FIFO buffer depth = 256 datawords" bitfld.long 0x20 3. "RXFE,Receive FIFO Enable" "0: Disables; buffer depth is 1,1: Enables; FIFO[RXFIFOSIZE] indicates the buffer.." newline rbitfld.long 0x20 0.--2. "RXFIFOSIZE,Receive FIFO Buffer Depth" "0: Receive FIFO buffer depth = 1 dataword,1: Receive FIFO buffer depth = 4 datawords,2: Receive FIFO buffer depth = 8 datawords,3: Receive FIFO buffer depth = 16 datawords,4: Receive FIFO buffer depth = 32 datawords,5: Receive FIFO buffer depth = 64 datawords,6: Receive FIFO buffer depth = 128 datawords,7: Receive FIFO buffer depth = 256 datawords" line.long 0x24 "WATER,Watermark" rbitfld.long 0x24 24.--26. "RXCOUNT,Receive Counter" "0,1,2,3,4,5,6,7" bitfld.long 0x24 16.--17. "RXWATER,Receive Watermark" "0,1,2,3" newline rbitfld.long 0x24 8.--10. "TXCOUNT,Transmit Counter" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0.--1. "TXWATER,Transmit Watermark" "0,1,2,3" rgroup.long 0x30++0x3 line.long 0x0 "DATARO,Data Read-Only" hexmask.long.word 0x0 0.--15. 1. "DATA,Receive Data" tree.end tree "LPUART_11" base ad:0x40498000 rgroup.long 0x0++0x7 line.long 0x0 "VERID,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Identification Number" line.long 0x4 "PARAM,Parameter" hexmask.long.byte 0x4 8.--15. 1. "RXFIFO,Receive FIFO Size" hexmask.long.byte 0x4 0.--7. 1. "TXFIFO,Transmit FIFO Size" group.long 0x8++0x27 line.long 0x0 "GLOBAL,Global" bitfld.long 0x0 1. "RST,Software Reset" "0: Not reset,1: Reset" line.long 0x4 "PINCFG,Pin Configuration" bitfld.long 0x4 0.--1. "TRGSEL,Trigger Select" "0: Input trigger disabled,1: Input trigger used instead of the RXD pin input,2: Input trigger used instead of the CTS_B pin input,3: Input trigger used to modulate the TXD pin.." line.long 0x8 "BAUD,Baud Rate" bitfld.long 0x8 31. "MAEN1,Match Address Mode Enable 1" "0: Disables,1: Enables" bitfld.long 0x8 30. "MAEN2,Match Address Mode Enable 2" "0: Disables,1: Enables" newline bitfld.long 0x8 29. "M10,10-Bit Mode Select" "0: Receiver and transmitter use 7-bit to 9-bit data..,1: Receiver and transmitter use 10-bit data.." hexmask.long.byte 0x8 24.--28. 1. "OSR,Oversampling Ratio (OSR)" newline bitfld.long 0x8 23. "TDMAE,Transmitter DMA Enable" "0: Disables DMA request,1: Enables DMA request" bitfld.long 0x8 21. "RDMAE,Receiver Full DMA Enable" "0: Disables DMA request,1: Enables DMA request" newline bitfld.long 0x8 18.--19. "MATCFG,Match Configuration" "0: Address match wakeup,1: Idle match wakeup,2: Match on and match off,3: Enables RWU on data match and match on/off for.." bitfld.long 0x8 17. "BOTHEDGE,Both Edge Sampling" "0: Receiver samples input data using the rising..,1: Receiver samples input data using the rising and.." newline bitfld.long 0x8 16. "RESYNCDIS,Resynchronization Disable" "0: Enables resynchronization,1: Disables resynchronization" bitfld.long 0x8 15. "LBKDIE,LIN Break Detect Interrupt Enable" "0: Disables hardware interrupts from STAT[LBKDIF]..,1: Requests hardware interrupt when STAT[LBKDIF] is 1" newline bitfld.long 0x8 14. "RXEDGIE,RX Input Active Edge Interrupt Enable" "0: Disables hardware interrupts from STAT[RXEDGIF],1: Requests hardware interrupts when STAT[RXEDGIF].." bitfld.long 0x8 13. "SBNS,Stop Bit Number Select" "0: One stop bit,1: Two stop bits" newline hexmask.long.word 0x8 0.--12. 1. "SBR,Baud Rate Modulo Divisor" line.long 0xC "STAT,Status" eventfld.long 0xC 31. "LBKDIF,LIN Break Detect Interrupt Flag" "0: Not detected,1: Detected" eventfld.long 0xC 30. "RXEDGIF,RXD Pin Active Edge Interrupt Flag" "0: Not occurred,1: Occurred" newline bitfld.long 0xC 29. "MSBF,MSB First" "0: LSB,1: MSB" bitfld.long 0xC 28. "RXINV,Receive Data Inversion" "0: Inverted,1: Not inverted" newline bitfld.long 0xC 27. "RWUID,Receive Wake Up Idle Detect" "0: STAT[IDLE] does not become 1,1: STAT[IDLE] becomes 1" bitfld.long 0xC 26. "BRK13,Break Character Generation Length" "0: 9 to 13 bit times,1: 12 to 15 bit times" newline bitfld.long 0xC 25. "LBKDE,LIN Break Detection Enable" "0: Disables,1: Enables" rbitfld.long 0xC 24. "RAF,Receiver Active Flag" "0: Idle waiting for a start bit,1: Receiver active (RXD pin input not idle)" newline rbitfld.long 0xC 23. "TDRE,Transmit Data Register Empty Flag" "0: Greater than watermark,1: Equal to or less than watermark" rbitfld.long 0xC 22. "TC,Transmission Complete Flag" "0: Transmitter active (sending data a preamble or a..,1: Transmitter idle (transmission activity complete)" newline rbitfld.long 0xC 21. "RDRF,Receive Data Register Full Flag" "0: Equal to or less than watermark,1: Greater than watermark" eventfld.long 0xC 20. "IDLE,Idle Line Flag" "0: No idle line detected,1: Idle line detected" newline eventfld.long 0xC 19. "OR,Receiver Overrun Flag" "0: No overrun,1: Receive overrun (new LPUART data lost)" eventfld.long 0xC 18. "NF,Noise Flag (NF)" "0: No noise detected,1: Noise detected" newline eventfld.long 0xC 17. "FE,Framing Error Flag (FE)" "0: No framing error detected (this does not..,1: Framing error detected" eventfld.long 0xC 16. "PF,Parity Error Flag (PF)" "0: No parity error detected,1: Parity error detected" newline eventfld.long 0xC 15. "MA1F,Match 1 Flag" "0: Not equal to MA1,1: Equal to MA1" eventfld.long 0xC 14. "MA2F,Match 2 Flag" "0: Not equal to MA2,1: Equal to MA2" newline bitfld.long 0xC 1. "AME,Address Mark Enable" "0: Address mark in character is MSB,1: Address mark in character is the last bit before.." bitfld.long 0xC 0. "LBKFE,LIN Break Flag Enable" "0: Disables LIN break detect,1: Enables LIN break detect" line.long 0x10 "CTRL,Control" bitfld.long 0x10 31. "R8T9,Receive Bit 8 Transmit Bit 9" "0,1" bitfld.long 0x10 30. "R9T8,Receive Bit 9 Transmit Bit 8" "0,1" newline bitfld.long 0x10 29. "TXDIR,TXD Pin Direction in Single-Wire Mode" "0: TXD pin is an input in Single-Wire mode,1: TXD pin is an output in Single-Wire mode" bitfld.long 0x10 28. "TXINV,Transmit Data Inversion" "0: Not inverted,1: Inverted" newline bitfld.long 0x10 27. "ORIE,Overrun Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 26. "NEIE,Noise Error Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 25. "FEIE,Framing Error Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 24. "PEIE,Parity Error Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 23. "TIE,Transmit Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 22. "TCIE,Transmission Complete Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 21. "RIE,Receiver Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 20. "ILIE,Idle Line Interrupt Enable" "0: Disables hardware interrupts from STAT[IDLE];..,1: Enables hardware interrupts when STAT[IDLE] = 1" newline bitfld.long 0x10 19. "TE,Transmitter Enable" "0: Disables,1: Enables" bitfld.long 0x10 18. "RE,Receiver Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 17. "RWU,Receiver Wakeup Control" "0: Normal receiver operation,1: LPUART receiver in standby waiting for a wakeup.." bitfld.long 0x10 16. "SBK,Send Break" "0: Normal transmitter operation,1: Queue break character(s) to be sent" newline bitfld.long 0x10 15. "MA1IE,Match 1 (MA1F) Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 14. "MA2IE,Match 2 (MA2F) Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 11. "M7,7-Bit Mode Select" "0: 8-bit to 10-bit data characters,1: 7-bit data characters" bitfld.long 0x10 8.--10. "IDLECFG,Idle Configuration" "0: 1,1: 2,2: 4,3: 8,4: 16,5: 32,6: 64,7: 128" newline bitfld.long 0x10 7. "LOOPS,Loop Mode Select" "0: Normal operation: RXD and TXD use separate pins,1: Loop mode or Single-Wire mode" bitfld.long 0x10 6. "DOZEEN,Enables LPUART in Doze mode." "0: Enables,1: Disables" newline bitfld.long 0x10 5. "RSRC,Receiver Source Select" "0: Internal Loopback mode,1: Single-wire mode" bitfld.long 0x10 4. "M,9-Bit Or 8-Bit Mode Select" "0: 8-bit data characters,1: 9-bit data characters" newline bitfld.long 0x10 3. "WAKE,Receiver Wakeup Method Select" "0: Configures CTRL[RWU] for idle-line wakeup,1: Configures CTRL[RWU] with address-mark wakeup" bitfld.long 0x10 2. "ILT,Idle Line Type Select" "0: After the start bit,1: After the stop bit" newline bitfld.long 0x10 1. "PE,Parity Enable" "0: Disables,1: Enables" bitfld.long 0x10 0. "PT,Parity Type" "0: Even parity,1: Odd parity" line.long 0x14 "DATA,Data" rbitfld.long 0x14 15. "NOISY,Noisy Data Received" "0: Received without noise,1: Received with noise" rbitfld.long 0x14 14. "PARITYE,Parity Error" "0: Received without a parity error,1: Received with a parity error" newline bitfld.long 0x14 13. "FRETSC,Frame Error Transmit Special Character" "0: Received without a frame error on reads or..,1: Received with a frame error on reads or.." rbitfld.long 0x14 12. "RXEMPT,Receive Buffer Empty" "0: Contains valid data,1: Contains invalid data and is empty" newline rbitfld.long 0x14 11. "IDLINE,Idle Line" "0: Received was not idle,1: Receiver was idle" rbitfld.long 0x14 10. "LINBRK,LIN Break" "0: LIN break not detected or LIN break detect..,1: LIN break detected" newline bitfld.long 0x14 9. "R9T9,Read Receive FIFO Bit 9 Or Write Transmit FIFO Bit 9" "0,1" bitfld.long 0x14 8. "R8T8,Read Receive FIFO Bit 8 Or Write Transmit FIFO Bit 8" "0,1" newline bitfld.long 0x14 7. "R7T7,Read Receive FIFO Bit 7 Or Write Transmit FIFO Bit 7" "0,1" bitfld.long 0x14 6. "R6T6,Read Receive FIFO Bit 6 Or Write Transmit FIFO Bit 6" "0,1" newline bitfld.long 0x14 5. "R5T5,Read Receive FIFO Bit 5 Or Write Transmit FIFO Bit 5" "0,1" bitfld.long 0x14 4. "R4T4,Read Receive FIFO Bit 4 Or Write Transmit FIFO Bit 4" "0,1" newline bitfld.long 0x14 3. "R3T3,Read Receive FIFO Bit 3 Or Write Transmit FIFO Bit 3" "0,1" bitfld.long 0x14 2. "R2T2,Read Receive FIFO Bit 2 Or Write Transmit FIFO Bit 2" "0,1" newline bitfld.long 0x14 1. "R1T1,Read Receive FIFO Bit 1 Or Write Transmit FIFO Bit 1" "0,1" bitfld.long 0x14 0. "R0T0,Read Receive FIFO Bit 0 Or Write Transmit FIFO Bit 0" "0,1" line.long 0x18 "MATCH,Match Address" hexmask.long.word 0x18 16.--25. 1. "MA2,Match Address 2" hexmask.long.word 0x18 0.--9. 1. "MA1,Match Address 1" line.long 0x1C "MODIR,MODEM IrDA" bitfld.long 0x1C 18. "IREN,IR Enable" "0: Disables,1: Enables" bitfld.long 0x1C 16.--17. "TNP,Transmitter Narrow Pulse" "0: 1 / OSR,1: 2 / OSR,2: 3 / OSR,3: 4 / OSR" newline bitfld.long 0x1C 8.--9. "RTSWATER,Receive RTS Configuration" "0,1,2,3" bitfld.long 0x1C 5. "TXCTSSRC,Transmit CTS Source" "0: The CTS_B pin,1: An internal connection to the receiver address.." newline bitfld.long 0x1C 4. "TXCTSC,Transmit CTS Configuration" "0: Sampled at the start of each character,1: Sampled when the transmitter is idle" bitfld.long 0x1C 3. "RXRTSE,Receiver RTS Enable" "0: Disables,1: Enables" newline bitfld.long 0x1C 2. "TXRTSPOL,Transmitter RTS Polarity" "0: Transmitter RTS is active low,1: Transmitter RTS is active high" bitfld.long 0x1C 1. "TXRTSE,Transmitter RTS Enable" "0: Disables,1: Enables" newline bitfld.long 0x1C 0. "TXCTSE,Transmitter CTS Enable" "0: Disables,1: Enables" line.long 0x20 "FIFO,FIFO" rbitfld.long 0x20 23. "TXEMPT,Transmit FIFO Or Buffer Empty" "0: Not empty,1: Empty" rbitfld.long 0x20 22. "RXEMPT,Receive FIFO Or Buffer Empty" "0: Not empty,1: Empty" newline eventfld.long 0x20 17. "TXOF,Transmitter FIFO Overflow Flag" "0: No overflow,1: Overflow" eventfld.long 0x20 16. "RXUF,Receiver FIFO Underflow Flag" "0: No underflow,1: Underflow" newline bitfld.long 0x20 15. "TXFLUSH,Transmit FIFO Flush" "0: No effect,1: All data is flushed out" bitfld.long 0x20 14. "RXFLUSH,Receive FIFO Flush" "0: No effect,1: All data is flushed out" newline bitfld.long 0x20 10.--12. "RXIDEN,Receiver Idle Empty Enable" "0: Disables STAT[RDRF] to become 1 because of..,1: Enables STAT[RDRF] to become 1 because of..,2: Enables STAT[RDRF] to become 1 because of..,3: Enables STAT[RDRF] to become 1 because of..,4: Enables STAT[RDRF] to become 1 because of..,5: Enables STAT[RDRF] to become 1 because of..,6: Enables STAT[RDRF] to become 1 because of..,7: Enables STAT[RDRF] to become 1 because of.." bitfld.long 0x20 9. "TXOFE,Transmit FIFO Overflow Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x20 8. "RXUFE,Receive FIFO Underflow Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x20 7. "TXFE,Transmit FIFO Enable" "0: Disables; buffer depth is 1,1: Enables; FIFO[TXFIFOSIZE] indicates the buffer.." newline rbitfld.long 0x20 4.--6. "TXFIFOSIZE,Transmit FIFO Buffer Depth" "0: Transmit FIFO buffer depth = 1 dataword,1: Transmit FIFO buffer depth = 4 datawords,2: Transmit FIFO buffer depth = 8 datawords,3: Transmit FIFO buffer depth = 16 datawords,4: Transmit FIFO buffer depth = 32 datawords,5: Transmit FIFO buffer depth = 64 datawords,6: Transmit FIFO buffer depth = 128 datawords,7: Transmit FIFO buffer depth = 256 datawords" bitfld.long 0x20 3. "RXFE,Receive FIFO Enable" "0: Disables; buffer depth is 1,1: Enables; FIFO[RXFIFOSIZE] indicates the buffer.." newline rbitfld.long 0x20 0.--2. "RXFIFOSIZE,Receive FIFO Buffer Depth" "0: Receive FIFO buffer depth = 1 dataword,1: Receive FIFO buffer depth = 4 datawords,2: Receive FIFO buffer depth = 8 datawords,3: Receive FIFO buffer depth = 16 datawords,4: Receive FIFO buffer depth = 32 datawords,5: Receive FIFO buffer depth = 64 datawords,6: Receive FIFO buffer depth = 128 datawords,7: Receive FIFO buffer depth = 256 datawords" line.long 0x24 "WATER,Watermark" rbitfld.long 0x24 24.--26. "RXCOUNT,Receive Counter" "0,1,2,3,4,5,6,7" bitfld.long 0x24 16.--17. "RXWATER,Receive Watermark" "0,1,2,3" newline rbitfld.long 0x24 8.--10. "TXCOUNT,Transmit Counter" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0.--1. "TXWATER,Transmit Watermark" "0,1,2,3" rgroup.long 0x30++0x3 line.long 0x0 "DATARO,Data Read-Only" hexmask.long.word 0x0 0.--15. 1. "DATA,Receive Data" tree.end tree "LPUART_12" base ad:0x4049C000 rgroup.long 0x0++0x7 line.long 0x0 "VERID,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Identification Number" line.long 0x4 "PARAM,Parameter" hexmask.long.byte 0x4 8.--15. 1. "RXFIFO,Receive FIFO Size" hexmask.long.byte 0x4 0.--7. 1. "TXFIFO,Transmit FIFO Size" group.long 0x8++0x27 line.long 0x0 "GLOBAL,Global" bitfld.long 0x0 1. "RST,Software Reset" "0: Not reset,1: Reset" line.long 0x4 "PINCFG,Pin Configuration" bitfld.long 0x4 0.--1. "TRGSEL,Trigger Select" "0: Input trigger disabled,1: Input trigger used instead of the RXD pin input,2: Input trigger used instead of the CTS_B pin input,3: Input trigger used to modulate the TXD pin.." line.long 0x8 "BAUD,Baud Rate" bitfld.long 0x8 31. "MAEN1,Match Address Mode Enable 1" "0: Disables,1: Enables" bitfld.long 0x8 30. "MAEN2,Match Address Mode Enable 2" "0: Disables,1: Enables" newline bitfld.long 0x8 29. "M10,10-Bit Mode Select" "0: Receiver and transmitter use 7-bit to 9-bit data..,1: Receiver and transmitter use 10-bit data.." hexmask.long.byte 0x8 24.--28. 1. "OSR,Oversampling Ratio (OSR)" newline bitfld.long 0x8 23. "TDMAE,Transmitter DMA Enable" "0: Disables DMA request,1: Enables DMA request" bitfld.long 0x8 21. "RDMAE,Receiver Full DMA Enable" "0: Disables DMA request,1: Enables DMA request" newline bitfld.long 0x8 18.--19. "MATCFG,Match Configuration" "0: Address match wakeup,1: Idle match wakeup,2: Match on and match off,3: Enables RWU on data match and match on/off for.." bitfld.long 0x8 17. "BOTHEDGE,Both Edge Sampling" "0: Receiver samples input data using the rising..,1: Receiver samples input data using the rising and.." newline bitfld.long 0x8 16. "RESYNCDIS,Resynchronization Disable" "0: Enables resynchronization,1: Disables resynchronization" bitfld.long 0x8 15. "LBKDIE,LIN Break Detect Interrupt Enable" "0: Disables hardware interrupts from STAT[LBKDIF]..,1: Requests hardware interrupt when STAT[LBKDIF] is 1" newline bitfld.long 0x8 14. "RXEDGIE,RX Input Active Edge Interrupt Enable" "0: Disables hardware interrupts from STAT[RXEDGIF],1: Requests hardware interrupts when STAT[RXEDGIF].." bitfld.long 0x8 13. "SBNS,Stop Bit Number Select" "0: One stop bit,1: Two stop bits" newline hexmask.long.word 0x8 0.--12. 1. "SBR,Baud Rate Modulo Divisor" line.long 0xC "STAT,Status" eventfld.long 0xC 31. "LBKDIF,LIN Break Detect Interrupt Flag" "0: Not detected,1: Detected" eventfld.long 0xC 30. "RXEDGIF,RXD Pin Active Edge Interrupt Flag" "0: Not occurred,1: Occurred" newline bitfld.long 0xC 29. "MSBF,MSB First" "0: LSB,1: MSB" bitfld.long 0xC 28. "RXINV,Receive Data Inversion" "0: Inverted,1: Not inverted" newline bitfld.long 0xC 27. "RWUID,Receive Wake Up Idle Detect" "0: STAT[IDLE] does not become 1,1: STAT[IDLE] becomes 1" bitfld.long 0xC 26. "BRK13,Break Character Generation Length" "0: 9 to 13 bit times,1: 12 to 15 bit times" newline bitfld.long 0xC 25. "LBKDE,LIN Break Detection Enable" "0: Disables,1: Enables" rbitfld.long 0xC 24. "RAF,Receiver Active Flag" "0: Idle waiting for a start bit,1: Receiver active (RXD pin input not idle)" newline rbitfld.long 0xC 23. "TDRE,Transmit Data Register Empty Flag" "0: Greater than watermark,1: Equal to or less than watermark" rbitfld.long 0xC 22. "TC,Transmission Complete Flag" "0: Transmitter active (sending data a preamble or a..,1: Transmitter idle (transmission activity complete)" newline rbitfld.long 0xC 21. "RDRF,Receive Data Register Full Flag" "0: Equal to or less than watermark,1: Greater than watermark" eventfld.long 0xC 20. "IDLE,Idle Line Flag" "0: No idle line detected,1: Idle line detected" newline eventfld.long 0xC 19. "OR,Receiver Overrun Flag" "0: No overrun,1: Receive overrun (new LPUART data lost)" eventfld.long 0xC 18. "NF,Noise Flag (NF)" "0: No noise detected,1: Noise detected" newline eventfld.long 0xC 17. "FE,Framing Error Flag (FE)" "0: No framing error detected (this does not..,1: Framing error detected" eventfld.long 0xC 16. "PF,Parity Error Flag (PF)" "0: No parity error detected,1: Parity error detected" newline eventfld.long 0xC 15. "MA1F,Match 1 Flag" "0: Not equal to MA1,1: Equal to MA1" eventfld.long 0xC 14. "MA2F,Match 2 Flag" "0: Not equal to MA2,1: Equal to MA2" newline bitfld.long 0xC 1. "AME,Address Mark Enable" "0: Address mark in character is MSB,1: Address mark in character is the last bit before.." bitfld.long 0xC 0. "LBKFE,LIN Break Flag Enable" "0: Disables LIN break detect,1: Enables LIN break detect" line.long 0x10 "CTRL,Control" bitfld.long 0x10 31. "R8T9,Receive Bit 8 Transmit Bit 9" "0,1" bitfld.long 0x10 30. "R9T8,Receive Bit 9 Transmit Bit 8" "0,1" newline bitfld.long 0x10 29. "TXDIR,TXD Pin Direction in Single-Wire Mode" "0: TXD pin is an input in Single-Wire mode,1: TXD pin is an output in Single-Wire mode" bitfld.long 0x10 28. "TXINV,Transmit Data Inversion" "0: Not inverted,1: Inverted" newline bitfld.long 0x10 27. "ORIE,Overrun Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 26. "NEIE,Noise Error Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 25. "FEIE,Framing Error Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 24. "PEIE,Parity Error Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 23. "TIE,Transmit Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 22. "TCIE,Transmission Complete Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 21. "RIE,Receiver Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 20. "ILIE,Idle Line Interrupt Enable" "0: Disables hardware interrupts from STAT[IDLE];..,1: Enables hardware interrupts when STAT[IDLE] = 1" newline bitfld.long 0x10 19. "TE,Transmitter Enable" "0: Disables,1: Enables" bitfld.long 0x10 18. "RE,Receiver Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 17. "RWU,Receiver Wakeup Control" "0: Normal receiver operation,1: LPUART receiver in standby waiting for a wakeup.." bitfld.long 0x10 16. "SBK,Send Break" "0: Normal transmitter operation,1: Queue break character(s) to be sent" newline bitfld.long 0x10 15. "MA1IE,Match 1 (MA1F) Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 14. "MA2IE,Match 2 (MA2F) Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 11. "M7,7-Bit Mode Select" "0: 8-bit to 10-bit data characters,1: 7-bit data characters" bitfld.long 0x10 8.--10. "IDLECFG,Idle Configuration" "0: 1,1: 2,2: 4,3: 8,4: 16,5: 32,6: 64,7: 128" newline bitfld.long 0x10 7. "LOOPS,Loop Mode Select" "0: Normal operation: RXD and TXD use separate pins,1: Loop mode or Single-Wire mode" bitfld.long 0x10 6. "DOZEEN,Enables LPUART in Doze mode." "0: Enables,1: Disables" newline bitfld.long 0x10 5. "RSRC,Receiver Source Select" "0: Internal Loopback mode,1: Single-wire mode" bitfld.long 0x10 4. "M,9-Bit Or 8-Bit Mode Select" "0: 8-bit data characters,1: 9-bit data characters" newline bitfld.long 0x10 3. "WAKE,Receiver Wakeup Method Select" "0: Configures CTRL[RWU] for idle-line wakeup,1: Configures CTRL[RWU] with address-mark wakeup" bitfld.long 0x10 2. "ILT,Idle Line Type Select" "0: After the start bit,1: After the stop bit" newline bitfld.long 0x10 1. "PE,Parity Enable" "0: Disables,1: Enables" bitfld.long 0x10 0. "PT,Parity Type" "0: Even parity,1: Odd parity" line.long 0x14 "DATA,Data" rbitfld.long 0x14 15. "NOISY,Noisy Data Received" "0: Received without noise,1: Received with noise" rbitfld.long 0x14 14. "PARITYE,Parity Error" "0: Received without a parity error,1: Received with a parity error" newline bitfld.long 0x14 13. "FRETSC,Frame Error Transmit Special Character" "0: Received without a frame error on reads or..,1: Received with a frame error on reads or.." rbitfld.long 0x14 12. "RXEMPT,Receive Buffer Empty" "0: Contains valid data,1: Contains invalid data and is empty" newline rbitfld.long 0x14 11. "IDLINE,Idle Line" "0: Received was not idle,1: Receiver was idle" rbitfld.long 0x14 10. "LINBRK,LIN Break" "0: LIN break not detected or LIN break detect..,1: LIN break detected" newline bitfld.long 0x14 9. "R9T9,Read Receive FIFO Bit 9 Or Write Transmit FIFO Bit 9" "0,1" bitfld.long 0x14 8. "R8T8,Read Receive FIFO Bit 8 Or Write Transmit FIFO Bit 8" "0,1" newline bitfld.long 0x14 7. "R7T7,Read Receive FIFO Bit 7 Or Write Transmit FIFO Bit 7" "0,1" bitfld.long 0x14 6. "R6T6,Read Receive FIFO Bit 6 Or Write Transmit FIFO Bit 6" "0,1" newline bitfld.long 0x14 5. "R5T5,Read Receive FIFO Bit 5 Or Write Transmit FIFO Bit 5" "0,1" bitfld.long 0x14 4. "R4T4,Read Receive FIFO Bit 4 Or Write Transmit FIFO Bit 4" "0,1" newline bitfld.long 0x14 3. "R3T3,Read Receive FIFO Bit 3 Or Write Transmit FIFO Bit 3" "0,1" bitfld.long 0x14 2. "R2T2,Read Receive FIFO Bit 2 Or Write Transmit FIFO Bit 2" "0,1" newline bitfld.long 0x14 1. "R1T1,Read Receive FIFO Bit 1 Or Write Transmit FIFO Bit 1" "0,1" bitfld.long 0x14 0. "R0T0,Read Receive FIFO Bit 0 Or Write Transmit FIFO Bit 0" "0,1" line.long 0x18 "MATCH,Match Address" hexmask.long.word 0x18 16.--25. 1. "MA2,Match Address 2" hexmask.long.word 0x18 0.--9. 1. "MA1,Match Address 1" line.long 0x1C "MODIR,MODEM IrDA" bitfld.long 0x1C 18. "IREN,IR Enable" "0: Disables,1: Enables" bitfld.long 0x1C 16.--17. "TNP,Transmitter Narrow Pulse" "0: 1 / OSR,1: 2 / OSR,2: 3 / OSR,3: 4 / OSR" newline bitfld.long 0x1C 8.--9. "RTSWATER,Receive RTS Configuration" "0,1,2,3" bitfld.long 0x1C 5. "TXCTSSRC,Transmit CTS Source" "0: The CTS_B pin,1: An internal connection to the receiver address.." newline bitfld.long 0x1C 4. "TXCTSC,Transmit CTS Configuration" "0: Sampled at the start of each character,1: Sampled when the transmitter is idle" bitfld.long 0x1C 3. "RXRTSE,Receiver RTS Enable" "0: Disables,1: Enables" newline bitfld.long 0x1C 2. "TXRTSPOL,Transmitter RTS Polarity" "0: Transmitter RTS is active low,1: Transmitter RTS is active high" bitfld.long 0x1C 1. "TXRTSE,Transmitter RTS Enable" "0: Disables,1: Enables" newline bitfld.long 0x1C 0. "TXCTSE,Transmitter CTS Enable" "0: Disables,1: Enables" line.long 0x20 "FIFO,FIFO" rbitfld.long 0x20 23. "TXEMPT,Transmit FIFO Or Buffer Empty" "0: Not empty,1: Empty" rbitfld.long 0x20 22. "RXEMPT,Receive FIFO Or Buffer Empty" "0: Not empty,1: Empty" newline eventfld.long 0x20 17. "TXOF,Transmitter FIFO Overflow Flag" "0: No overflow,1: Overflow" eventfld.long 0x20 16. "RXUF,Receiver FIFO Underflow Flag" "0: No underflow,1: Underflow" newline bitfld.long 0x20 15. "TXFLUSH,Transmit FIFO Flush" "0: No effect,1: All data is flushed out" bitfld.long 0x20 14. "RXFLUSH,Receive FIFO Flush" "0: No effect,1: All data is flushed out" newline bitfld.long 0x20 10.--12. "RXIDEN,Receiver Idle Empty Enable" "0: Disables STAT[RDRF] to become 1 because of..,1: Enables STAT[RDRF] to become 1 because of..,2: Enables STAT[RDRF] to become 1 because of..,3: Enables STAT[RDRF] to become 1 because of..,4: Enables STAT[RDRF] to become 1 because of..,5: Enables STAT[RDRF] to become 1 because of..,6: Enables STAT[RDRF] to become 1 because of..,7: Enables STAT[RDRF] to become 1 because of.." bitfld.long 0x20 9. "TXOFE,Transmit FIFO Overflow Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x20 8. "RXUFE,Receive FIFO Underflow Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x20 7. "TXFE,Transmit FIFO Enable" "0: Disables; buffer depth is 1,1: Enables; FIFO[TXFIFOSIZE] indicates the buffer.." newline rbitfld.long 0x20 4.--6. "TXFIFOSIZE,Transmit FIFO Buffer Depth" "0: Transmit FIFO buffer depth = 1 dataword,1: Transmit FIFO buffer depth = 4 datawords,2: Transmit FIFO buffer depth = 8 datawords,3: Transmit FIFO buffer depth = 16 datawords,4: Transmit FIFO buffer depth = 32 datawords,5: Transmit FIFO buffer depth = 64 datawords,6: Transmit FIFO buffer depth = 128 datawords,7: Transmit FIFO buffer depth = 256 datawords" bitfld.long 0x20 3. "RXFE,Receive FIFO Enable" "0: Disables; buffer depth is 1,1: Enables; FIFO[RXFIFOSIZE] indicates the buffer.." newline rbitfld.long 0x20 0.--2. "RXFIFOSIZE,Receive FIFO Buffer Depth" "0: Receive FIFO buffer depth = 1 dataword,1: Receive FIFO buffer depth = 4 datawords,2: Receive FIFO buffer depth = 8 datawords,3: Receive FIFO buffer depth = 16 datawords,4: Receive FIFO buffer depth = 32 datawords,5: Receive FIFO buffer depth = 64 datawords,6: Receive FIFO buffer depth = 128 datawords,7: Receive FIFO buffer depth = 256 datawords" line.long 0x24 "WATER,Watermark" rbitfld.long 0x24 24.--26. "RXCOUNT,Receive Counter" "0,1,2,3,4,5,6,7" bitfld.long 0x24 16.--17. "RXWATER,Receive Watermark" "0,1,2,3" newline rbitfld.long 0x24 8.--10. "TXCOUNT,Transmit Counter" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0.--1. "TXWATER,Transmit Watermark" "0,1,2,3" rgroup.long 0x30++0x3 line.long 0x0 "DATARO,Data Read-Only" hexmask.long.word 0x0 0.--15. 1. "DATA,Receive Data" tree.end tree "LPUART_13" base ad:0x404A0000 rgroup.long 0x0++0x7 line.long 0x0 "VERID,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Identification Number" line.long 0x4 "PARAM,Parameter" hexmask.long.byte 0x4 8.--15. 1. "RXFIFO,Receive FIFO Size" hexmask.long.byte 0x4 0.--7. 1. "TXFIFO,Transmit FIFO Size" group.long 0x8++0x27 line.long 0x0 "GLOBAL,Global" bitfld.long 0x0 1. "RST,Software Reset" "0: Not reset,1: Reset" line.long 0x4 "PINCFG,Pin Configuration" bitfld.long 0x4 0.--1. "TRGSEL,Trigger Select" "0: Input trigger disabled,1: Input trigger used instead of the RXD pin input,2: Input trigger used instead of the CTS_B pin input,3: Input trigger used to modulate the TXD pin.." line.long 0x8 "BAUD,Baud Rate" bitfld.long 0x8 31. "MAEN1,Match Address Mode Enable 1" "0: Disables,1: Enables" bitfld.long 0x8 30. "MAEN2,Match Address Mode Enable 2" "0: Disables,1: Enables" newline bitfld.long 0x8 29. "M10,10-Bit Mode Select" "0: Receiver and transmitter use 7-bit to 9-bit data..,1: Receiver and transmitter use 10-bit data.." hexmask.long.byte 0x8 24.--28. 1. "OSR,Oversampling Ratio (OSR)" newline bitfld.long 0x8 23. "TDMAE,Transmitter DMA Enable" "0: Disables DMA request,1: Enables DMA request" bitfld.long 0x8 21. "RDMAE,Receiver Full DMA Enable" "0: Disables DMA request,1: Enables DMA request" newline bitfld.long 0x8 18.--19. "MATCFG,Match Configuration" "0: Address match wakeup,1: Idle match wakeup,2: Match on and match off,3: Enables RWU on data match and match on/off for.." bitfld.long 0x8 17. "BOTHEDGE,Both Edge Sampling" "0: Receiver samples input data using the rising..,1: Receiver samples input data using the rising and.." newline bitfld.long 0x8 16. "RESYNCDIS,Resynchronization Disable" "0: Enables resynchronization,1: Disables resynchronization" bitfld.long 0x8 15. "LBKDIE,LIN Break Detect Interrupt Enable" "0: Disables hardware interrupts from STAT[LBKDIF]..,1: Requests hardware interrupt when STAT[LBKDIF] is 1" newline bitfld.long 0x8 14. "RXEDGIE,RX Input Active Edge Interrupt Enable" "0: Disables hardware interrupts from STAT[RXEDGIF],1: Requests hardware interrupts when STAT[RXEDGIF].." bitfld.long 0x8 13. "SBNS,Stop Bit Number Select" "0: One stop bit,1: Two stop bits" newline hexmask.long.word 0x8 0.--12. 1. "SBR,Baud Rate Modulo Divisor" line.long 0xC "STAT,Status" eventfld.long 0xC 31. "LBKDIF,LIN Break Detect Interrupt Flag" "0: Not detected,1: Detected" eventfld.long 0xC 30. "RXEDGIF,RXD Pin Active Edge Interrupt Flag" "0: Not occurred,1: Occurred" newline bitfld.long 0xC 29. "MSBF,MSB First" "0: LSB,1: MSB" bitfld.long 0xC 28. "RXINV,Receive Data Inversion" "0: Inverted,1: Not inverted" newline bitfld.long 0xC 27. "RWUID,Receive Wake Up Idle Detect" "0: STAT[IDLE] does not become 1,1: STAT[IDLE] becomes 1" bitfld.long 0xC 26. "BRK13,Break Character Generation Length" "0: 9 to 13 bit times,1: 12 to 15 bit times" newline bitfld.long 0xC 25. "LBKDE,LIN Break Detection Enable" "0: Disables,1: Enables" rbitfld.long 0xC 24. "RAF,Receiver Active Flag" "0: Idle waiting for a start bit,1: Receiver active (RXD pin input not idle)" newline rbitfld.long 0xC 23. "TDRE,Transmit Data Register Empty Flag" "0: Greater than watermark,1: Equal to or less than watermark" rbitfld.long 0xC 22. "TC,Transmission Complete Flag" "0: Transmitter active (sending data a preamble or a..,1: Transmitter idle (transmission activity complete)" newline rbitfld.long 0xC 21. "RDRF,Receive Data Register Full Flag" "0: Equal to or less than watermark,1: Greater than watermark" eventfld.long 0xC 20. "IDLE,Idle Line Flag" "0: No idle line detected,1: Idle line detected" newline eventfld.long 0xC 19. "OR,Receiver Overrun Flag" "0: No overrun,1: Receive overrun (new LPUART data lost)" eventfld.long 0xC 18. "NF,Noise Flag (NF)" "0: No noise detected,1: Noise detected" newline eventfld.long 0xC 17. "FE,Framing Error Flag (FE)" "0: No framing error detected (this does not..,1: Framing error detected" eventfld.long 0xC 16. "PF,Parity Error Flag (PF)" "0: No parity error detected,1: Parity error detected" newline eventfld.long 0xC 15. "MA1F,Match 1 Flag" "0: Not equal to MA1,1: Equal to MA1" eventfld.long 0xC 14. "MA2F,Match 2 Flag" "0: Not equal to MA2,1: Equal to MA2" newline bitfld.long 0xC 1. "AME,Address Mark Enable" "0: Address mark in character is MSB,1: Address mark in character is the last bit before.." bitfld.long 0xC 0. "LBKFE,LIN Break Flag Enable" "0: Disables LIN break detect,1: Enables LIN break detect" line.long 0x10 "CTRL,Control" bitfld.long 0x10 31. "R8T9,Receive Bit 8 Transmit Bit 9" "0,1" bitfld.long 0x10 30. "R9T8,Receive Bit 9 Transmit Bit 8" "0,1" newline bitfld.long 0x10 29. "TXDIR,TXD Pin Direction in Single-Wire Mode" "0: TXD pin is an input in Single-Wire mode,1: TXD pin is an output in Single-Wire mode" bitfld.long 0x10 28. "TXINV,Transmit Data Inversion" "0: Not inverted,1: Inverted" newline bitfld.long 0x10 27. "ORIE,Overrun Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 26. "NEIE,Noise Error Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 25. "FEIE,Framing Error Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 24. "PEIE,Parity Error Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 23. "TIE,Transmit Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 22. "TCIE,Transmission Complete Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 21. "RIE,Receiver Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 20. "ILIE,Idle Line Interrupt Enable" "0: Disables hardware interrupts from STAT[IDLE];..,1: Enables hardware interrupts when STAT[IDLE] = 1" newline bitfld.long 0x10 19. "TE,Transmitter Enable" "0: Disables,1: Enables" bitfld.long 0x10 18. "RE,Receiver Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 17. "RWU,Receiver Wakeup Control" "0: Normal receiver operation,1: LPUART receiver in standby waiting for a wakeup.." bitfld.long 0x10 16. "SBK,Send Break" "0: Normal transmitter operation,1: Queue break character(s) to be sent" newline bitfld.long 0x10 15. "MA1IE,Match 1 (MA1F) Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 14. "MA2IE,Match 2 (MA2F) Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 11. "M7,7-Bit Mode Select" "0: 8-bit to 10-bit data characters,1: 7-bit data characters" bitfld.long 0x10 8.--10. "IDLECFG,Idle Configuration" "0: 1,1: 2,2: 4,3: 8,4: 16,5: 32,6: 64,7: 128" newline bitfld.long 0x10 7. "LOOPS,Loop Mode Select" "0: Normal operation: RXD and TXD use separate pins,1: Loop mode or Single-Wire mode" bitfld.long 0x10 6. "DOZEEN,Enables LPUART in Doze mode." "0: Enables,1: Disables" newline bitfld.long 0x10 5. "RSRC,Receiver Source Select" "0: Internal Loopback mode,1: Single-wire mode" bitfld.long 0x10 4. "M,9-Bit Or 8-Bit Mode Select" "0: 8-bit data characters,1: 9-bit data characters" newline bitfld.long 0x10 3. "WAKE,Receiver Wakeup Method Select" "0: Configures CTRL[RWU] for idle-line wakeup,1: Configures CTRL[RWU] with address-mark wakeup" bitfld.long 0x10 2. "ILT,Idle Line Type Select" "0: After the start bit,1: After the stop bit" newline bitfld.long 0x10 1. "PE,Parity Enable" "0: Disables,1: Enables" bitfld.long 0x10 0. "PT,Parity Type" "0: Even parity,1: Odd parity" line.long 0x14 "DATA,Data" rbitfld.long 0x14 15. "NOISY,Noisy Data Received" "0: Received without noise,1: Received with noise" rbitfld.long 0x14 14. "PARITYE,Parity Error" "0: Received without a parity error,1: Received with a parity error" newline bitfld.long 0x14 13. "FRETSC,Frame Error Transmit Special Character" "0: Received without a frame error on reads or..,1: Received with a frame error on reads or.." rbitfld.long 0x14 12. "RXEMPT,Receive Buffer Empty" "0: Contains valid data,1: Contains invalid data and is empty" newline rbitfld.long 0x14 11. "IDLINE,Idle Line" "0: Received was not idle,1: Receiver was idle" rbitfld.long 0x14 10. "LINBRK,LIN Break" "0: LIN break not detected or LIN break detect..,1: LIN break detected" newline bitfld.long 0x14 9. "R9T9,Read Receive FIFO Bit 9 Or Write Transmit FIFO Bit 9" "0,1" bitfld.long 0x14 8. "R8T8,Read Receive FIFO Bit 8 Or Write Transmit FIFO Bit 8" "0,1" newline bitfld.long 0x14 7. "R7T7,Read Receive FIFO Bit 7 Or Write Transmit FIFO Bit 7" "0,1" bitfld.long 0x14 6. "R6T6,Read Receive FIFO Bit 6 Or Write Transmit FIFO Bit 6" "0,1" newline bitfld.long 0x14 5. "R5T5,Read Receive FIFO Bit 5 Or Write Transmit FIFO Bit 5" "0,1" bitfld.long 0x14 4. "R4T4,Read Receive FIFO Bit 4 Or Write Transmit FIFO Bit 4" "0,1" newline bitfld.long 0x14 3. "R3T3,Read Receive FIFO Bit 3 Or Write Transmit FIFO Bit 3" "0,1" bitfld.long 0x14 2. "R2T2,Read Receive FIFO Bit 2 Or Write Transmit FIFO Bit 2" "0,1" newline bitfld.long 0x14 1. "R1T1,Read Receive FIFO Bit 1 Or Write Transmit FIFO Bit 1" "0,1" bitfld.long 0x14 0. "R0T0,Read Receive FIFO Bit 0 Or Write Transmit FIFO Bit 0" "0,1" line.long 0x18 "MATCH,Match Address" hexmask.long.word 0x18 16.--25. 1. "MA2,Match Address 2" hexmask.long.word 0x18 0.--9. 1. "MA1,Match Address 1" line.long 0x1C "MODIR,MODEM IrDA" bitfld.long 0x1C 18. "IREN,IR Enable" "0: Disables,1: Enables" bitfld.long 0x1C 16.--17. "TNP,Transmitter Narrow Pulse" "0: 1 / OSR,1: 2 / OSR,2: 3 / OSR,3: 4 / OSR" newline bitfld.long 0x1C 8.--9. "RTSWATER,Receive RTS Configuration" "0,1,2,3" bitfld.long 0x1C 5. "TXCTSSRC,Transmit CTS Source" "0: The CTS_B pin,1: An internal connection to the receiver address.." newline bitfld.long 0x1C 4. "TXCTSC,Transmit CTS Configuration" "0: Sampled at the start of each character,1: Sampled when the transmitter is idle" bitfld.long 0x1C 3. "RXRTSE,Receiver RTS Enable" "0: Disables,1: Enables" newline bitfld.long 0x1C 2. "TXRTSPOL,Transmitter RTS Polarity" "0: Transmitter RTS is active low,1: Transmitter RTS is active high" bitfld.long 0x1C 1. "TXRTSE,Transmitter RTS Enable" "0: Disables,1: Enables" newline bitfld.long 0x1C 0. "TXCTSE,Transmitter CTS Enable" "0: Disables,1: Enables" line.long 0x20 "FIFO,FIFO" rbitfld.long 0x20 23. "TXEMPT,Transmit FIFO Or Buffer Empty" "0: Not empty,1: Empty" rbitfld.long 0x20 22. "RXEMPT,Receive FIFO Or Buffer Empty" "0: Not empty,1: Empty" newline eventfld.long 0x20 17. "TXOF,Transmitter FIFO Overflow Flag" "0: No overflow,1: Overflow" eventfld.long 0x20 16. "RXUF,Receiver FIFO Underflow Flag" "0: No underflow,1: Underflow" newline bitfld.long 0x20 15. "TXFLUSH,Transmit FIFO Flush" "0: No effect,1: All data is flushed out" bitfld.long 0x20 14. "RXFLUSH,Receive FIFO Flush" "0: No effect,1: All data is flushed out" newline bitfld.long 0x20 10.--12. "RXIDEN,Receiver Idle Empty Enable" "0: Disables STAT[RDRF] to become 1 because of..,1: Enables STAT[RDRF] to become 1 because of..,2: Enables STAT[RDRF] to become 1 because of..,3: Enables STAT[RDRF] to become 1 because of..,4: Enables STAT[RDRF] to become 1 because of..,5: Enables STAT[RDRF] to become 1 because of..,6: Enables STAT[RDRF] to become 1 because of..,7: Enables STAT[RDRF] to become 1 because of.." bitfld.long 0x20 9. "TXOFE,Transmit FIFO Overflow Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x20 8. "RXUFE,Receive FIFO Underflow Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x20 7. "TXFE,Transmit FIFO Enable" "0: Disables; buffer depth is 1,1: Enables; FIFO[TXFIFOSIZE] indicates the buffer.." newline rbitfld.long 0x20 4.--6. "TXFIFOSIZE,Transmit FIFO Buffer Depth" "0: Transmit FIFO buffer depth = 1 dataword,1: Transmit FIFO buffer depth = 4 datawords,2: Transmit FIFO buffer depth = 8 datawords,3: Transmit FIFO buffer depth = 16 datawords,4: Transmit FIFO buffer depth = 32 datawords,5: Transmit FIFO buffer depth = 64 datawords,6: Transmit FIFO buffer depth = 128 datawords,7: Transmit FIFO buffer depth = 256 datawords" bitfld.long 0x20 3. "RXFE,Receive FIFO Enable" "0: Disables; buffer depth is 1,1: Enables; FIFO[RXFIFOSIZE] indicates the buffer.." newline rbitfld.long 0x20 0.--2. "RXFIFOSIZE,Receive FIFO Buffer Depth" "0: Receive FIFO buffer depth = 1 dataword,1: Receive FIFO buffer depth = 4 datawords,2: Receive FIFO buffer depth = 8 datawords,3: Receive FIFO buffer depth = 16 datawords,4: Receive FIFO buffer depth = 32 datawords,5: Receive FIFO buffer depth = 64 datawords,6: Receive FIFO buffer depth = 128 datawords,7: Receive FIFO buffer depth = 256 datawords" line.long 0x24 "WATER,Watermark" rbitfld.long 0x24 24.--26. "RXCOUNT,Receive Counter" "0,1,2,3,4,5,6,7" bitfld.long 0x24 16.--17. "RXWATER,Receive Watermark" "0,1,2,3" newline rbitfld.long 0x24 8.--10. "TXCOUNT,Transmit Counter" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0.--1. "TXWATER,Transmit Watermark" "0,1,2,3" rgroup.long 0x30++0x3 line.long 0x0 "DATARO,Data Read-Only" hexmask.long.word 0x0 0.--15. 1. "DATA,Receive Data" tree.end tree "LPUART_14" base ad:0x404A4000 rgroup.long 0x0++0x7 line.long 0x0 "VERID,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Identification Number" line.long 0x4 "PARAM,Parameter" hexmask.long.byte 0x4 8.--15. 1. "RXFIFO,Receive FIFO Size" hexmask.long.byte 0x4 0.--7. 1. "TXFIFO,Transmit FIFO Size" group.long 0x8++0x27 line.long 0x0 "GLOBAL,Global" bitfld.long 0x0 1. "RST,Software Reset" "0: Not reset,1: Reset" line.long 0x4 "PINCFG,Pin Configuration" bitfld.long 0x4 0.--1. "TRGSEL,Trigger Select" "0: Input trigger disabled,1: Input trigger used instead of the RXD pin input,2: Input trigger used instead of the CTS_B pin input,3: Input trigger used to modulate the TXD pin.." line.long 0x8 "BAUD,Baud Rate" bitfld.long 0x8 31. "MAEN1,Match Address Mode Enable 1" "0: Disables,1: Enables" bitfld.long 0x8 30. "MAEN2,Match Address Mode Enable 2" "0: Disables,1: Enables" newline bitfld.long 0x8 29. "M10,10-Bit Mode Select" "0: Receiver and transmitter use 7-bit to 9-bit data..,1: Receiver and transmitter use 10-bit data.." hexmask.long.byte 0x8 24.--28. 1. "OSR,Oversampling Ratio (OSR)" newline bitfld.long 0x8 23. "TDMAE,Transmitter DMA Enable" "0: Disables DMA request,1: Enables DMA request" bitfld.long 0x8 21. "RDMAE,Receiver Full DMA Enable" "0: Disables DMA request,1: Enables DMA request" newline bitfld.long 0x8 18.--19. "MATCFG,Match Configuration" "0: Address match wakeup,1: Idle match wakeup,2: Match on and match off,3: Enables RWU on data match and match on/off for.." bitfld.long 0x8 17. "BOTHEDGE,Both Edge Sampling" "0: Receiver samples input data using the rising..,1: Receiver samples input data using the rising and.." newline bitfld.long 0x8 16. "RESYNCDIS,Resynchronization Disable" "0: Enables resynchronization,1: Disables resynchronization" bitfld.long 0x8 15. "LBKDIE,LIN Break Detect Interrupt Enable" "0: Disables hardware interrupts from STAT[LBKDIF]..,1: Requests hardware interrupt when STAT[LBKDIF] is 1" newline bitfld.long 0x8 14. "RXEDGIE,RX Input Active Edge Interrupt Enable" "0: Disables hardware interrupts from STAT[RXEDGIF],1: Requests hardware interrupts when STAT[RXEDGIF].." bitfld.long 0x8 13. "SBNS,Stop Bit Number Select" "0: One stop bit,1: Two stop bits" newline hexmask.long.word 0x8 0.--12. 1. "SBR,Baud Rate Modulo Divisor" line.long 0xC "STAT,Status" eventfld.long 0xC 31. "LBKDIF,LIN Break Detect Interrupt Flag" "0: Not detected,1: Detected" eventfld.long 0xC 30. "RXEDGIF,RXD Pin Active Edge Interrupt Flag" "0: Not occurred,1: Occurred" newline bitfld.long 0xC 29. "MSBF,MSB First" "0: LSB,1: MSB" bitfld.long 0xC 28. "RXINV,Receive Data Inversion" "0: Inverted,1: Not inverted" newline bitfld.long 0xC 27. "RWUID,Receive Wake Up Idle Detect" "0: STAT[IDLE] does not become 1,1: STAT[IDLE] becomes 1" bitfld.long 0xC 26. "BRK13,Break Character Generation Length" "0: 9 to 13 bit times,1: 12 to 15 bit times" newline bitfld.long 0xC 25. "LBKDE,LIN Break Detection Enable" "0: Disables,1: Enables" rbitfld.long 0xC 24. "RAF,Receiver Active Flag" "0: Idle waiting for a start bit,1: Receiver active (RXD pin input not idle)" newline rbitfld.long 0xC 23. "TDRE,Transmit Data Register Empty Flag" "0: Greater than watermark,1: Equal to or less than watermark" rbitfld.long 0xC 22. "TC,Transmission Complete Flag" "0: Transmitter active (sending data a preamble or a..,1: Transmitter idle (transmission activity complete)" newline rbitfld.long 0xC 21. "RDRF,Receive Data Register Full Flag" "0: Equal to or less than watermark,1: Greater than watermark" eventfld.long 0xC 20. "IDLE,Idle Line Flag" "0: No idle line detected,1: Idle line detected" newline eventfld.long 0xC 19. "OR,Receiver Overrun Flag" "0: No overrun,1: Receive overrun (new LPUART data lost)" eventfld.long 0xC 18. "NF,Noise Flag (NF)" "0: No noise detected,1: Noise detected" newline eventfld.long 0xC 17. "FE,Framing Error Flag (FE)" "0: No framing error detected (this does not..,1: Framing error detected" eventfld.long 0xC 16. "PF,Parity Error Flag (PF)" "0: No parity error detected,1: Parity error detected" newline eventfld.long 0xC 15. "MA1F,Match 1 Flag" "0: Not equal to MA1,1: Equal to MA1" eventfld.long 0xC 14. "MA2F,Match 2 Flag" "0: Not equal to MA2,1: Equal to MA2" newline bitfld.long 0xC 1. "AME,Address Mark Enable" "0: Address mark in character is MSB,1: Address mark in character is the last bit before.." bitfld.long 0xC 0. "LBKFE,LIN Break Flag Enable" "0: Disables LIN break detect,1: Enables LIN break detect" line.long 0x10 "CTRL,Control" bitfld.long 0x10 31. "R8T9,Receive Bit 8 Transmit Bit 9" "0,1" bitfld.long 0x10 30. "R9T8,Receive Bit 9 Transmit Bit 8" "0,1" newline bitfld.long 0x10 29. "TXDIR,TXD Pin Direction in Single-Wire Mode" "0: TXD pin is an input in Single-Wire mode,1: TXD pin is an output in Single-Wire mode" bitfld.long 0x10 28. "TXINV,Transmit Data Inversion" "0: Not inverted,1: Inverted" newline bitfld.long 0x10 27. "ORIE,Overrun Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 26. "NEIE,Noise Error Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 25. "FEIE,Framing Error Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 24. "PEIE,Parity Error Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 23. "TIE,Transmit Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 22. "TCIE,Transmission Complete Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 21. "RIE,Receiver Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 20. "ILIE,Idle Line Interrupt Enable" "0: Disables hardware interrupts from STAT[IDLE];..,1: Enables hardware interrupts when STAT[IDLE] = 1" newline bitfld.long 0x10 19. "TE,Transmitter Enable" "0: Disables,1: Enables" bitfld.long 0x10 18. "RE,Receiver Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 17. "RWU,Receiver Wakeup Control" "0: Normal receiver operation,1: LPUART receiver in standby waiting for a wakeup.." bitfld.long 0x10 16. "SBK,Send Break" "0: Normal transmitter operation,1: Queue break character(s) to be sent" newline bitfld.long 0x10 15. "MA1IE,Match 1 (MA1F) Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 14. "MA2IE,Match 2 (MA2F) Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 11. "M7,7-Bit Mode Select" "0: 8-bit to 10-bit data characters,1: 7-bit data characters" bitfld.long 0x10 8.--10. "IDLECFG,Idle Configuration" "0: 1,1: 2,2: 4,3: 8,4: 16,5: 32,6: 64,7: 128" newline bitfld.long 0x10 7. "LOOPS,Loop Mode Select" "0: Normal operation: RXD and TXD use separate pins,1: Loop mode or Single-Wire mode" bitfld.long 0x10 6. "DOZEEN,Enables LPUART in Doze mode." "0: Enables,1: Disables" newline bitfld.long 0x10 5. "RSRC,Receiver Source Select" "0: Internal Loopback mode,1: Single-wire mode" bitfld.long 0x10 4. "M,9-Bit Or 8-Bit Mode Select" "0: 8-bit data characters,1: 9-bit data characters" newline bitfld.long 0x10 3. "WAKE,Receiver Wakeup Method Select" "0: Configures CTRL[RWU] for idle-line wakeup,1: Configures CTRL[RWU] with address-mark wakeup" bitfld.long 0x10 2. "ILT,Idle Line Type Select" "0: After the start bit,1: After the stop bit" newline bitfld.long 0x10 1. "PE,Parity Enable" "0: Disables,1: Enables" bitfld.long 0x10 0. "PT,Parity Type" "0: Even parity,1: Odd parity" line.long 0x14 "DATA,Data" rbitfld.long 0x14 15. "NOISY,Noisy Data Received" "0: Received without noise,1: Received with noise" rbitfld.long 0x14 14. "PARITYE,Parity Error" "0: Received without a parity error,1: Received with a parity error" newline bitfld.long 0x14 13. "FRETSC,Frame Error Transmit Special Character" "0: Received without a frame error on reads or..,1: Received with a frame error on reads or.." rbitfld.long 0x14 12. "RXEMPT,Receive Buffer Empty" "0: Contains valid data,1: Contains invalid data and is empty" newline rbitfld.long 0x14 11. "IDLINE,Idle Line" "0: Received was not idle,1: Receiver was idle" rbitfld.long 0x14 10. "LINBRK,LIN Break" "0: LIN break not detected or LIN break detect..,1: LIN break detected" newline bitfld.long 0x14 9. "R9T9,Read Receive FIFO Bit 9 Or Write Transmit FIFO Bit 9" "0,1" bitfld.long 0x14 8. "R8T8,Read Receive FIFO Bit 8 Or Write Transmit FIFO Bit 8" "0,1" newline bitfld.long 0x14 7. "R7T7,Read Receive FIFO Bit 7 Or Write Transmit FIFO Bit 7" "0,1" bitfld.long 0x14 6. "R6T6,Read Receive FIFO Bit 6 Or Write Transmit FIFO Bit 6" "0,1" newline bitfld.long 0x14 5. "R5T5,Read Receive FIFO Bit 5 Or Write Transmit FIFO Bit 5" "0,1" bitfld.long 0x14 4. "R4T4,Read Receive FIFO Bit 4 Or Write Transmit FIFO Bit 4" "0,1" newline bitfld.long 0x14 3. "R3T3,Read Receive FIFO Bit 3 Or Write Transmit FIFO Bit 3" "0,1" bitfld.long 0x14 2. "R2T2,Read Receive FIFO Bit 2 Or Write Transmit FIFO Bit 2" "0,1" newline bitfld.long 0x14 1. "R1T1,Read Receive FIFO Bit 1 Or Write Transmit FIFO Bit 1" "0,1" bitfld.long 0x14 0. "R0T0,Read Receive FIFO Bit 0 Or Write Transmit FIFO Bit 0" "0,1" line.long 0x18 "MATCH,Match Address" hexmask.long.word 0x18 16.--25. 1. "MA2,Match Address 2" hexmask.long.word 0x18 0.--9. 1. "MA1,Match Address 1" line.long 0x1C "MODIR,MODEM IrDA" bitfld.long 0x1C 18. "IREN,IR Enable" "0: Disables,1: Enables" bitfld.long 0x1C 16.--17. "TNP,Transmitter Narrow Pulse" "0: 1 / OSR,1: 2 / OSR,2: 3 / OSR,3: 4 / OSR" newline bitfld.long 0x1C 8.--9. "RTSWATER,Receive RTS Configuration" "0,1,2,3" bitfld.long 0x1C 5. "TXCTSSRC,Transmit CTS Source" "0: The CTS_B pin,1: An internal connection to the receiver address.." newline bitfld.long 0x1C 4. "TXCTSC,Transmit CTS Configuration" "0: Sampled at the start of each character,1: Sampled when the transmitter is idle" bitfld.long 0x1C 3. "RXRTSE,Receiver RTS Enable" "0: Disables,1: Enables" newline bitfld.long 0x1C 2. "TXRTSPOL,Transmitter RTS Polarity" "0: Transmitter RTS is active low,1: Transmitter RTS is active high" bitfld.long 0x1C 1. "TXRTSE,Transmitter RTS Enable" "0: Disables,1: Enables" newline bitfld.long 0x1C 0. "TXCTSE,Transmitter CTS Enable" "0: Disables,1: Enables" line.long 0x20 "FIFO,FIFO" rbitfld.long 0x20 23. "TXEMPT,Transmit FIFO Or Buffer Empty" "0: Not empty,1: Empty" rbitfld.long 0x20 22. "RXEMPT,Receive FIFO Or Buffer Empty" "0: Not empty,1: Empty" newline eventfld.long 0x20 17. "TXOF,Transmitter FIFO Overflow Flag" "0: No overflow,1: Overflow" eventfld.long 0x20 16. "RXUF,Receiver FIFO Underflow Flag" "0: No underflow,1: Underflow" newline bitfld.long 0x20 15. "TXFLUSH,Transmit FIFO Flush" "0: No effect,1: All data is flushed out" bitfld.long 0x20 14. "RXFLUSH,Receive FIFO Flush" "0: No effect,1: All data is flushed out" newline bitfld.long 0x20 10.--12. "RXIDEN,Receiver Idle Empty Enable" "0: Disables STAT[RDRF] to become 1 because of..,1: Enables STAT[RDRF] to become 1 because of..,2: Enables STAT[RDRF] to become 1 because of..,3: Enables STAT[RDRF] to become 1 because of..,4: Enables STAT[RDRF] to become 1 because of..,5: Enables STAT[RDRF] to become 1 because of..,6: Enables STAT[RDRF] to become 1 because of..,7: Enables STAT[RDRF] to become 1 because of.." bitfld.long 0x20 9. "TXOFE,Transmit FIFO Overflow Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x20 8. "RXUFE,Receive FIFO Underflow Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x20 7. "TXFE,Transmit FIFO Enable" "0: Disables; buffer depth is 1,1: Enables; FIFO[TXFIFOSIZE] indicates the buffer.." newline rbitfld.long 0x20 4.--6. "TXFIFOSIZE,Transmit FIFO Buffer Depth" "0: Transmit FIFO buffer depth = 1 dataword,1: Transmit FIFO buffer depth = 4 datawords,2: Transmit FIFO buffer depth = 8 datawords,3: Transmit FIFO buffer depth = 16 datawords,4: Transmit FIFO buffer depth = 32 datawords,5: Transmit FIFO buffer depth = 64 datawords,6: Transmit FIFO buffer depth = 128 datawords,7: Transmit FIFO buffer depth = 256 datawords" bitfld.long 0x20 3. "RXFE,Receive FIFO Enable" "0: Disables; buffer depth is 1,1: Enables; FIFO[RXFIFOSIZE] indicates the buffer.." newline rbitfld.long 0x20 0.--2. "RXFIFOSIZE,Receive FIFO Buffer Depth" "0: Receive FIFO buffer depth = 1 dataword,1: Receive FIFO buffer depth = 4 datawords,2: Receive FIFO buffer depth = 8 datawords,3: Receive FIFO buffer depth = 16 datawords,4: Receive FIFO buffer depth = 32 datawords,5: Receive FIFO buffer depth = 64 datawords,6: Receive FIFO buffer depth = 128 datawords,7: Receive FIFO buffer depth = 256 datawords" line.long 0x24 "WATER,Watermark" rbitfld.long 0x24 24.--26. "RXCOUNT,Receive Counter" "0,1,2,3,4,5,6,7" bitfld.long 0x24 16.--17. "RXWATER,Receive Watermark" "0,1,2,3" newline rbitfld.long 0x24 8.--10. "TXCOUNT,Transmit Counter" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0.--1. "TXWATER,Transmit Watermark" "0,1,2,3" rgroup.long 0x30++0x3 line.long 0x0 "DATARO,Data Read-Only" hexmask.long.word 0x0 0.--15. 1. "DATA,Receive Data" tree.end tree "LPUART_15" base ad:0x404A8000 rgroup.long 0x0++0x7 line.long 0x0 "VERID,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Identification Number" line.long 0x4 "PARAM,Parameter" hexmask.long.byte 0x4 8.--15. 1. "RXFIFO,Receive FIFO Size" hexmask.long.byte 0x4 0.--7. 1. "TXFIFO,Transmit FIFO Size" group.long 0x8++0x27 line.long 0x0 "GLOBAL,Global" bitfld.long 0x0 1. "RST,Software Reset" "0: Not reset,1: Reset" line.long 0x4 "PINCFG,Pin Configuration" bitfld.long 0x4 0.--1. "TRGSEL,Trigger Select" "0: Input trigger disabled,1: Input trigger used instead of the RXD pin input,2: Input trigger used instead of the CTS_B pin input,3: Input trigger used to modulate the TXD pin.." line.long 0x8 "BAUD,Baud Rate" bitfld.long 0x8 31. "MAEN1,Match Address Mode Enable 1" "0: Disables,1: Enables" bitfld.long 0x8 30. "MAEN2,Match Address Mode Enable 2" "0: Disables,1: Enables" newline bitfld.long 0x8 29. "M10,10-Bit Mode Select" "0: Receiver and transmitter use 7-bit to 9-bit data..,1: Receiver and transmitter use 10-bit data.." hexmask.long.byte 0x8 24.--28. 1. "OSR,Oversampling Ratio (OSR)" newline bitfld.long 0x8 23. "TDMAE,Transmitter DMA Enable" "0: Disables DMA request,1: Enables DMA request" bitfld.long 0x8 21. "RDMAE,Receiver Full DMA Enable" "0: Disables DMA request,1: Enables DMA request" newline bitfld.long 0x8 18.--19. "MATCFG,Match Configuration" "0: Address match wakeup,1: Idle match wakeup,2: Match on and match off,3: Enables RWU on data match and match on/off for.." bitfld.long 0x8 17. "BOTHEDGE,Both Edge Sampling" "0: Receiver samples input data using the rising..,1: Receiver samples input data using the rising and.." newline bitfld.long 0x8 16. "RESYNCDIS,Resynchronization Disable" "0: Enables resynchronization,1: Disables resynchronization" bitfld.long 0x8 15. "LBKDIE,LIN Break Detect Interrupt Enable" "0: Disables hardware interrupts from STAT[LBKDIF]..,1: Requests hardware interrupt when STAT[LBKDIF] is 1" newline bitfld.long 0x8 14. "RXEDGIE,RX Input Active Edge Interrupt Enable" "0: Disables hardware interrupts from STAT[RXEDGIF],1: Requests hardware interrupts when STAT[RXEDGIF].." bitfld.long 0x8 13. "SBNS,Stop Bit Number Select" "0: One stop bit,1: Two stop bits" newline hexmask.long.word 0x8 0.--12. 1. "SBR,Baud Rate Modulo Divisor" line.long 0xC "STAT,Status" eventfld.long 0xC 31. "LBKDIF,LIN Break Detect Interrupt Flag" "0: Not detected,1: Detected" eventfld.long 0xC 30. "RXEDGIF,RXD Pin Active Edge Interrupt Flag" "0: Not occurred,1: Occurred" newline bitfld.long 0xC 29. "MSBF,MSB First" "0: LSB,1: MSB" bitfld.long 0xC 28. "RXINV,Receive Data Inversion" "0: Inverted,1: Not inverted" newline bitfld.long 0xC 27. "RWUID,Receive Wake Up Idle Detect" "0: STAT[IDLE] does not become 1,1: STAT[IDLE] becomes 1" bitfld.long 0xC 26. "BRK13,Break Character Generation Length" "0: 9 to 13 bit times,1: 12 to 15 bit times" newline bitfld.long 0xC 25. "LBKDE,LIN Break Detection Enable" "0: Disables,1: Enables" rbitfld.long 0xC 24. "RAF,Receiver Active Flag" "0: Idle waiting for a start bit,1: Receiver active (RXD pin input not idle)" newline rbitfld.long 0xC 23. "TDRE,Transmit Data Register Empty Flag" "0: Greater than watermark,1: Equal to or less than watermark" rbitfld.long 0xC 22. "TC,Transmission Complete Flag" "0: Transmitter active (sending data a preamble or a..,1: Transmitter idle (transmission activity complete)" newline rbitfld.long 0xC 21. "RDRF,Receive Data Register Full Flag" "0: Equal to or less than watermark,1: Greater than watermark" eventfld.long 0xC 20. "IDLE,Idle Line Flag" "0: No idle line detected,1: Idle line detected" newline eventfld.long 0xC 19. "OR,Receiver Overrun Flag" "0: No overrun,1: Receive overrun (new LPUART data lost)" eventfld.long 0xC 18. "NF,Noise Flag (NF)" "0: No noise detected,1: Noise detected" newline eventfld.long 0xC 17. "FE,Framing Error Flag (FE)" "0: No framing error detected (this does not..,1: Framing error detected" eventfld.long 0xC 16. "PF,Parity Error Flag (PF)" "0: No parity error detected,1: Parity error detected" newline eventfld.long 0xC 15. "MA1F,Match 1 Flag" "0: Not equal to MA1,1: Equal to MA1" eventfld.long 0xC 14. "MA2F,Match 2 Flag" "0: Not equal to MA2,1: Equal to MA2" newline bitfld.long 0xC 1. "AME,Address Mark Enable" "0: Address mark in character is MSB,1: Address mark in character is the last bit before.." bitfld.long 0xC 0. "LBKFE,LIN Break Flag Enable" "0: Disables LIN break detect,1: Enables LIN break detect" line.long 0x10 "CTRL,Control" bitfld.long 0x10 31. "R8T9,Receive Bit 8 Transmit Bit 9" "0,1" bitfld.long 0x10 30. "R9T8,Receive Bit 9 Transmit Bit 8" "0,1" newline bitfld.long 0x10 29. "TXDIR,TXD Pin Direction in Single-Wire Mode" "0: TXD pin is an input in Single-Wire mode,1: TXD pin is an output in Single-Wire mode" bitfld.long 0x10 28. "TXINV,Transmit Data Inversion" "0: Not inverted,1: Inverted" newline bitfld.long 0x10 27. "ORIE,Overrun Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 26. "NEIE,Noise Error Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 25. "FEIE,Framing Error Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 24. "PEIE,Parity Error Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 23. "TIE,Transmit Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 22. "TCIE,Transmission Complete Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 21. "RIE,Receiver Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 20. "ILIE,Idle Line Interrupt Enable" "0: Disables hardware interrupts from STAT[IDLE];..,1: Enables hardware interrupts when STAT[IDLE] = 1" newline bitfld.long 0x10 19. "TE,Transmitter Enable" "0: Disables,1: Enables" bitfld.long 0x10 18. "RE,Receiver Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 17. "RWU,Receiver Wakeup Control" "0: Normal receiver operation,1: LPUART receiver in standby waiting for a wakeup.." bitfld.long 0x10 16. "SBK,Send Break" "0: Normal transmitter operation,1: Queue break character(s) to be sent" newline bitfld.long 0x10 15. "MA1IE,Match 1 (MA1F) Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x10 14. "MA2IE,Match 2 (MA2F) Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x10 11. "M7,7-Bit Mode Select" "0: 8-bit to 10-bit data characters,1: 7-bit data characters" bitfld.long 0x10 8.--10. "IDLECFG,Idle Configuration" "0: 1,1: 2,2: 4,3: 8,4: 16,5: 32,6: 64,7: 128" newline bitfld.long 0x10 7. "LOOPS,Loop Mode Select" "0: Normal operation: RXD and TXD use separate pins,1: Loop mode or Single-Wire mode" bitfld.long 0x10 6. "DOZEEN,Enables LPUART in Doze mode." "0: Enables,1: Disables" newline bitfld.long 0x10 5. "RSRC,Receiver Source Select" "0: Internal Loopback mode,1: Single-wire mode" bitfld.long 0x10 4. "M,9-Bit Or 8-Bit Mode Select" "0: 8-bit data characters,1: 9-bit data characters" newline bitfld.long 0x10 3. "WAKE,Receiver Wakeup Method Select" "0: Configures CTRL[RWU] for idle-line wakeup,1: Configures CTRL[RWU] with address-mark wakeup" bitfld.long 0x10 2. "ILT,Idle Line Type Select" "0: After the start bit,1: After the stop bit" newline bitfld.long 0x10 1. "PE,Parity Enable" "0: Disables,1: Enables" bitfld.long 0x10 0. "PT,Parity Type" "0: Even parity,1: Odd parity" line.long 0x14 "DATA,Data" rbitfld.long 0x14 15. "NOISY,Noisy Data Received" "0: Received without noise,1: Received with noise" rbitfld.long 0x14 14. "PARITYE,Parity Error" "0: Received without a parity error,1: Received with a parity error" newline bitfld.long 0x14 13. "FRETSC,Frame Error Transmit Special Character" "0: Received without a frame error on reads or..,1: Received with a frame error on reads or.." rbitfld.long 0x14 12. "RXEMPT,Receive Buffer Empty" "0: Contains valid data,1: Contains invalid data and is empty" newline rbitfld.long 0x14 11. "IDLINE,Idle Line" "0: Received was not idle,1: Receiver was idle" rbitfld.long 0x14 10. "LINBRK,LIN Break" "0: LIN break not detected or LIN break detect..,1: LIN break detected" newline bitfld.long 0x14 9. "R9T9,Read Receive FIFO Bit 9 Or Write Transmit FIFO Bit 9" "0,1" bitfld.long 0x14 8. "R8T8,Read Receive FIFO Bit 8 Or Write Transmit FIFO Bit 8" "0,1" newline bitfld.long 0x14 7. "R7T7,Read Receive FIFO Bit 7 Or Write Transmit FIFO Bit 7" "0,1" bitfld.long 0x14 6. "R6T6,Read Receive FIFO Bit 6 Or Write Transmit FIFO Bit 6" "0,1" newline bitfld.long 0x14 5. "R5T5,Read Receive FIFO Bit 5 Or Write Transmit FIFO Bit 5" "0,1" bitfld.long 0x14 4. "R4T4,Read Receive FIFO Bit 4 Or Write Transmit FIFO Bit 4" "0,1" newline bitfld.long 0x14 3. "R3T3,Read Receive FIFO Bit 3 Or Write Transmit FIFO Bit 3" "0,1" bitfld.long 0x14 2. "R2T2,Read Receive FIFO Bit 2 Or Write Transmit FIFO Bit 2" "0,1" newline bitfld.long 0x14 1. "R1T1,Read Receive FIFO Bit 1 Or Write Transmit FIFO Bit 1" "0,1" bitfld.long 0x14 0. "R0T0,Read Receive FIFO Bit 0 Or Write Transmit FIFO Bit 0" "0,1" line.long 0x18 "MATCH,Match Address" hexmask.long.word 0x18 16.--25. 1. "MA2,Match Address 2" hexmask.long.word 0x18 0.--9. 1. "MA1,Match Address 1" line.long 0x1C "MODIR,MODEM IrDA" bitfld.long 0x1C 18. "IREN,IR Enable" "0: Disables,1: Enables" bitfld.long 0x1C 16.--17. "TNP,Transmitter Narrow Pulse" "0: 1 / OSR,1: 2 / OSR,2: 3 / OSR,3: 4 / OSR" newline bitfld.long 0x1C 8.--9. "RTSWATER,Receive RTS Configuration" "0,1,2,3" bitfld.long 0x1C 5. "TXCTSSRC,Transmit CTS Source" "0: The CTS_B pin,1: An internal connection to the receiver address.." newline bitfld.long 0x1C 4. "TXCTSC,Transmit CTS Configuration" "0: Sampled at the start of each character,1: Sampled when the transmitter is idle" bitfld.long 0x1C 3. "RXRTSE,Receiver RTS Enable" "0: Disables,1: Enables" newline bitfld.long 0x1C 2. "TXRTSPOL,Transmitter RTS Polarity" "0: Transmitter RTS is active low,1: Transmitter RTS is active high" bitfld.long 0x1C 1. "TXRTSE,Transmitter RTS Enable" "0: Disables,1: Enables" newline bitfld.long 0x1C 0. "TXCTSE,Transmitter CTS Enable" "0: Disables,1: Enables" line.long 0x20 "FIFO,FIFO" rbitfld.long 0x20 23. "TXEMPT,Transmit FIFO Or Buffer Empty" "0: Not empty,1: Empty" rbitfld.long 0x20 22. "RXEMPT,Receive FIFO Or Buffer Empty" "0: Not empty,1: Empty" newline eventfld.long 0x20 17. "TXOF,Transmitter FIFO Overflow Flag" "0: No overflow,1: Overflow" eventfld.long 0x20 16. "RXUF,Receiver FIFO Underflow Flag" "0: No underflow,1: Underflow" newline bitfld.long 0x20 15. "TXFLUSH,Transmit FIFO Flush" "0: No effect,1: All data is flushed out" bitfld.long 0x20 14. "RXFLUSH,Receive FIFO Flush" "0: No effect,1: All data is flushed out" newline bitfld.long 0x20 10.--12. "RXIDEN,Receiver Idle Empty Enable" "0: Disables STAT[RDRF] to become 1 because of..,1: Enables STAT[RDRF] to become 1 because of..,2: Enables STAT[RDRF] to become 1 because of..,3: Enables STAT[RDRF] to become 1 because of..,4: Enables STAT[RDRF] to become 1 because of..,5: Enables STAT[RDRF] to become 1 because of..,6: Enables STAT[RDRF] to become 1 because of..,7: Enables STAT[RDRF] to become 1 because of.." bitfld.long 0x20 9. "TXOFE,Transmit FIFO Overflow Interrupt Enable" "0: Disables,1: Enables" newline bitfld.long 0x20 8. "RXUFE,Receive FIFO Underflow Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x20 7. "TXFE,Transmit FIFO Enable" "0: Disables; buffer depth is 1,1: Enables; FIFO[TXFIFOSIZE] indicates the buffer.." newline rbitfld.long 0x20 4.--6. "TXFIFOSIZE,Transmit FIFO Buffer Depth" "0: Transmit FIFO buffer depth = 1 dataword,1: Transmit FIFO buffer depth = 4 datawords,2: Transmit FIFO buffer depth = 8 datawords,3: Transmit FIFO buffer depth = 16 datawords,4: Transmit FIFO buffer depth = 32 datawords,5: Transmit FIFO buffer depth = 64 datawords,6: Transmit FIFO buffer depth = 128 datawords,7: Transmit FIFO buffer depth = 256 datawords" bitfld.long 0x20 3. "RXFE,Receive FIFO Enable" "0: Disables; buffer depth is 1,1: Enables; FIFO[RXFIFOSIZE] indicates the buffer.." newline rbitfld.long 0x20 0.--2. "RXFIFOSIZE,Receive FIFO Buffer Depth" "0: Receive FIFO buffer depth = 1 dataword,1: Receive FIFO buffer depth = 4 datawords,2: Receive FIFO buffer depth = 8 datawords,3: Receive FIFO buffer depth = 16 datawords,4: Receive FIFO buffer depth = 32 datawords,5: Receive FIFO buffer depth = 64 datawords,6: Receive FIFO buffer depth = 128 datawords,7: Receive FIFO buffer depth = 256 datawords" line.long 0x24 "WATER,Watermark" rbitfld.long 0x24 24.--26. "RXCOUNT,Receive Counter" "0,1,2,3,4,5,6,7" bitfld.long 0x24 16.--17. "RXWATER,Receive Watermark" "0,1,2,3" newline rbitfld.long 0x24 8.--10. "TXCOUNT,Transmit Counter" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0.--1. "TXWATER,Transmit Watermark" "0,1,2,3" rgroup.long 0x30++0x3 line.long 0x0 "DATARO,Data Read-Only" hexmask.long.word 0x0 0.--15. 1. "DATA,Receive Data" tree.end tree.end tree "MC_CGM (Clock Generation Module)" base ad:0x402D8000 group.long 0x0++0x3 line.long 0x0 "PCFS_SDUR,PCFS Step Duration" hexmask.long.word 0x0 0.--15. 1. "SDUR,Step duration" group.long 0x58++0xB line.long 0x0 "PCFS_DIVC8,PCFS Divider Change 8 Register" hexmask.long.word 0x0 16.--31. 1. "INIT,Divider change initial value" hexmask.long.byte 0x0 0.--7. 1. "RATE,Divider change rate" line.long 0x4 "PCFS_DIVE8,PCFS Divider End 8 Register" hexmask.long.tbyte 0x4 0.--19. 1. "DIVE,Divider end value" line.long 0x8 "PCFS_DIVS8,PCFS Divider Start 8 Register" hexmask.long.tbyte 0x8 0.--19. 1. "DIVS,Divider start value" group.long 0x300++0x3 line.long 0x0 "MUX_0_CSC,Clock Mux 0 Select Control Register" hexmask.long.byte 0x0 24.--27. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" bitfld.long 0x0 1. "RAMPDOWN,PCFS ramp-down" "0,1" newline bitfld.long 0x0 0. "RAMPUP,PCFS ramp-up" "0,1" rgroup.long 0x304++0x3 line.long 0x0 "MUX_0_CSS,Clock Mux 0 Select Status Register" hexmask.long.byte 0x0 24.--27. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to FIRC because of a safe clock request..,5: Switch to FIRC because of a safe clock request..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." bitfld.long 0x0 1. "RAMPDOWN,PCFS ramp-down" "0: No ramp-down operation was requested.,1: Ramp-down operation was requested." newline bitfld.long 0x0 0. "RAMPUP,PCFS ramp-up" "0: No ramp-up operation was requested.,1: Ramp-up operation was requested." group.long 0x308++0x1F line.long 0x0 "MUX_0_DC_0,Clock Mux 0 Divider 0 Control Register" rbitfld.long 0x0 31. "DE,Divider enable" "0: Unused,1: Divider is enabled." bitfld.long 0x0 16.--18. "DIV,Division value" "0,1,2,3,4,5,6,7" line.long 0x4 "MUX_0_DC_1,Clock Mux 0 Divider 1 Control Register" rbitfld.long 0x4 31. "DE,Divider enable" "0: Unused,1: Divider is enabled." bitfld.long 0x4 16.--18. "DIV,Division value" "0,1,2,3,4,5,6,7" line.long 0x8 "MUX_0_DC_2,Clock Mux 0 Divider 2 Control Register" rbitfld.long 0x8 31. "DE,Divider enable" "0: Unused,1: Divider is enabled." hexmask.long.byte 0x8 16.--19. 1. "DIV,Division value" line.long 0xC "MUX_0_DC_3,Clock Mux 0 Divider 3 Control Register" rbitfld.long 0xC 31. "DE,Divider enable" "0: Unused,1: Divider is enabled." bitfld.long 0xC 16.--18. "DIV,Division value" "0,1,2,3,4,5,6,7" line.long 0x10 "MUX_0_DC_4,Clock Mux 0 Divider 4 Control Register" rbitfld.long 0x10 31. "DE,Divider enable" "0: Unused,1: Divider is enabled." bitfld.long 0x10 16.--18. "DIV,Division value" "0,1,2,3,4,5,6,7" line.long 0x14 "MUX_0_DC_5,Clock Mux 0 Divider 5 Control Register" rbitfld.long 0x14 31. "DE,Divider enable" "0: Unused,1: Divider is enabled." bitfld.long 0x14 16.--18. "DIV,Division value" "0,1,2,3,4,5,6,7" line.long 0x18 "MUX_0_DC_6,Clock Mux 0 Divider 6 Control Register" rbitfld.long 0x18 31. "DE,Divider enable" "0: Unused,1: Divider is enabled." bitfld.long 0x18 16.--18. "DIV,Division value" "0,1,2,3,4,5,6,7" line.long 0x1C "MUX_0_DC_7,Clock Mux 0 Divider 7 Control Register" rbitfld.long 0x1C 31. "DE,Divider enable" "0: Unused,1: Divider is enabled." bitfld.long 0x1C 16.--17. "DIV,Division value" "0,1,2,3" group.long 0x334++0x7 line.long 0x0 "MUX_0_DIV_TRIG_CTRL,Clock Mux 0 Divider Trigger Control Register" bitfld.long 0x0 31. "HHEN,Halt handshake enable" "0: No halt handshake protocol is initiated.,1: Halt handshake protocol is initiated." bitfld.long 0x0 0. "TCTL,Trigger control" "0: Immediate divider update,1: Common trigger divider update" line.long 0x4 "MUX_0_DIV_TRIG,Clock Mux 0 Divider Trigger Register" hexmask.long 0x4 0.--31. 1. "TRIGGER,Trigger for divider update" rgroup.long 0x33C++0x3 line.long 0x0 "MUX_0_DIV_UPD_STAT,Clock Mux 0 Divider Update Status Register" bitfld.long 0x0 0. "DIV_STAT,Divider status for clock mux 0" "0: No divider configuration update is pending.,1: Divider configuration update on at least one.." group.long 0x340++0x3 line.long 0x0 "MUX_1_CSC,Clock Mux 1 Select Control Register" hexmask.long.byte 0x0 24.--28. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" rgroup.long 0x344++0x3 line.long 0x0 "MUX_1_CSS,Clock Mux 1 Select Status Register" hexmask.long.byte 0x0 24.--28. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to FIRC because of a safe clock request..,5: Switch to FIRC because of a safe clock request..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." group.long 0x348++0x3 line.long 0x0 "MUX_1_DC_0,Clock Mux 1 Divider 0 Control Register" bitfld.long 0x0 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." bitfld.long 0x0 16. "DIV,Division value" "0,1" rgroup.long 0x37C++0x3 line.long 0x0 "MUX_1_DIV_UPD_STAT,Clock Mux 1 Divider Update Status Register" bitfld.long 0x0 0. "DIV_STAT,Divider status for clock mux 1" "0: No divider configuration update is pending.,1: Divider configuration update on at least one.." group.long 0x380++0x3 line.long 0x0 "MUX_2_CSC,Clock Mux 2 Select Control Register" hexmask.long.byte 0x0 24.--28. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" rgroup.long 0x384++0x3 line.long 0x0 "MUX_2_CSS,Clock Mux 2 Select Status Register" hexmask.long.byte 0x0 24.--28. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to FIRC because of a safe clock request..,5: Switch to FIRC because of a safe clock request..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." group.long 0x388++0x3 line.long 0x0 "MUX_2_DC_0,Clock Mux 2 Divider 0 Control Register" bitfld.long 0x0 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." bitfld.long 0x0 16. "DIV,Division value" "0,1" rgroup.long 0x3BC++0x3 line.long 0x0 "MUX_2_DIV_UPD_STAT,Clock Mux 2 Divider Update Status Register" bitfld.long 0x0 0. "DIV_STAT,Divider status for clock mux 2" "0: No divider configuration update is pending.,1: Divider configuration update on at least one.." group.long 0x3C0++0x3 line.long 0x0 "MUX_3_CSC,Clock Mux 3 Select Control Register" hexmask.long.byte 0x0 24.--28. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" rgroup.long 0x3C4++0x3 line.long 0x0 "MUX_3_CSS,Clock Mux 3 Select Status Register" hexmask.long.byte 0x0 24.--28. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to FIRC because of a safe clock request..,5: Switch to FIRC because of a safe clock request..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." group.long 0x3C8++0x3 line.long 0x0 "MUX_3_DC_0,Clock Mux 3 Divider 0 Control Register" bitfld.long 0x0 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." bitfld.long 0x0 16.--17. "DIV,Division value" "0,1,2,3" rgroup.long 0x3FC++0x3 line.long 0x0 "MUX_3_DIV_UPD_STAT,Clock Mux 3 Divider Update Status Register" bitfld.long 0x0 0. "DIV_STAT,Divider status for clock mux 3" "0: No divider configuration update is pending.,1: Divider configuration update on at least one.." group.long 0x400++0x3 line.long 0x0 "MUX_4_CSC,Clock Mux 4 Select Control Register" hexmask.long.byte 0x0 24.--28. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" rgroup.long 0x404++0x3 line.long 0x0 "MUX_4_CSS,Clock Mux 4 Select Status Register" hexmask.long.byte 0x0 24.--28. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to FIRC because of a safe clock request..,5: Switch to FIRC because of a safe clock request..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." group.long 0x408++0x3 line.long 0x0 "MUX_4_DC_0,Clock Mux 4 Divider 0 Control Register" bitfld.long 0x0 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." bitfld.long 0x0 16.--17. "DIV,Division value" "0,1,2,3" rgroup.long 0x43C++0x3 line.long 0x0 "MUX_4_DIV_UPD_STAT,Clock Mux 4 Divider Update Status Register" bitfld.long 0x0 0. "DIV_STAT,Divider status for clock mux 4" "0: No divider configuration update is pending.,1: Divider configuration update on at least one.." group.long 0x440++0x3 line.long 0x0 "MUX_5_CSC,Clock Mux 5 Select Control Register" hexmask.long.byte 0x0 24.--29. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "FCG,Force clock gate" "0,1" newline bitfld.long 0x0 2. "CG,Clock gate" "0,1" rgroup.long 0x444++0x3 line.long 0x0 "MUX_5_CSS,Clock Mux 5 Select Status Register" hexmask.long.byte 0x0 24.--29. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17. "CS,Clock status" "0: Clock is gated to logic-0 at output of clock mux,1: Clock mux is transparent. Active clock pulses at.." newline bitfld.long 0x0 16. "GRIP,Gating request is in progress." "0: Clock source gating or ungating has completed.,1: Clock source gating or ungating is in progress." group.long 0x448++0x3 line.long 0x0 "MUX_5_DC_0,Clock Mux 5 Divider 0 Control Register" bitfld.long 0x0 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." hexmask.long.byte 0x0 16.--21. 1. "DIV,Division value" rgroup.long 0x47C++0x3 line.long 0x0 "MUX_5_DIV_UPD_STAT,Clock Mux 5 Divider Update Status Register" bitfld.long 0x0 0. "DIV_STAT,Divider status for clock mux 5" "0: No divider configuration update is pending.,1: Divider configuration update on at least one.." group.long 0x480++0x3 line.long 0x0 "MUX_6_CSC,Clock Mux 6 Select Control Register" hexmask.long.byte 0x0 24.--29. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "FCG,Force clock gate" "0,1" newline bitfld.long 0x0 2. "CG,Clock gate" "0,1" rgroup.long 0x484++0x3 line.long 0x0 "MUX_6_CSS,Clock Mux 6 Select Status Register" hexmask.long.byte 0x0 24.--29. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17. "CS,Clock status" "0: Clock is gated to logic-0 at output of clock mux,1: Clock mux is transparent. Active clock pulses at.." newline bitfld.long 0x0 16. "GRIP,Gating request is in progress." "0: Clock source gating or ungating has completed.,1: Clock source gating or ungating is in progress." group.long 0x488++0x3 line.long 0x0 "MUX_6_DC_0,Clock Mux 6 Divider 0 Control Register" bitfld.long 0x0 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." hexmask.long.byte 0x0 16.--21. 1. "DIV,Division value" rgroup.long 0x4BC++0x3 line.long 0x0 "MUX_6_DIV_UPD_STAT,Clock Mux 6 Divider Update Status Register" bitfld.long 0x0 0. "DIV_STAT,Divider status for clock mux 6" "0: No divider configuration update is pending.,1: Divider configuration update on at least one.." group.long 0x4C0++0x3 line.long 0x0 "MUX_7_CSC,Clock Mux 7 Select Control Register" hexmask.long.byte 0x0 24.--28. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" rgroup.long 0x4C4++0x3 line.long 0x0 "MUX_7_CSS,Clock Mux 7 Select Status Register" hexmask.long.byte 0x0 24.--28. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to FIRC because of a safe clock request..,5: Switch to FIRC because of a safe clock request..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." group.long 0x4C8++0x3 line.long 0x0 "MUX_7_DC_0,Clock Mux 7 Divider 0 Control Register" bitfld.long 0x0 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." hexmask.long.byte 0x0 16.--21. 1. "DIV,Division value" rgroup.long 0x4FC++0x3 line.long 0x0 "MUX_7_DIV_UPD_STAT,Clock Mux 7 Divider Update Status Register" bitfld.long 0x0 0. "DIV_STAT,Divider status for clock mux 7" "0: No divider configuration update is pending.,1: Divider configuration update on at least one.." group.long 0x500++0x3 line.long 0x0 "MUX_8_CSC,Clock Mux 8 Select Control Register" hexmask.long.byte 0x0 24.--28. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" rgroup.long 0x504++0x3 line.long 0x0 "MUX_8_CSS,Clock Mux 8 Select Status Register" hexmask.long.byte 0x0 24.--28. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to FIRC because of a safe clock request..,5: Switch to FIRC because of a safe clock request..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." group.long 0x508++0x3 line.long 0x0 "MUX_8_DC_0,Clock Mux 8 Divider 0 Control Register" bitfld.long 0x0 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." hexmask.long.byte 0x0 16.--21. 1. "DIV,Division value" rgroup.long 0x53C++0x3 line.long 0x0 "MUX_8_DIV_UPD_STAT,Clock Mux 8 Divider Update Status Register" bitfld.long 0x0 0. "DIV_STAT,Divider status for clock mux 8" "0: No divider configuration update is pending.,1: Divider configuration update on at least one.." group.long 0x540++0x3 line.long 0x0 "MUX_9_CSC,Clock Mux 9 Select Control Register" hexmask.long.byte 0x0 24.--28. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" rgroup.long 0x544++0x3 line.long 0x0 "MUX_9_CSS,Clock Mux 9 Select Status Register" hexmask.long.byte 0x0 24.--28. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to FIRC because of a safe clock request..,5: Switch to FIRC because of a safe clock request..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." group.long 0x548++0x3 line.long 0x0 "MUX_9_DC_0,Clock Mux 9 Divider 0 Control Register" bitfld.long 0x0 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." hexmask.long.byte 0x0 16.--21. 1. "DIV,Division value" rgroup.long 0x57C++0x3 line.long 0x0 "MUX_9_DIV_UPD_STAT,Clock Mux 9 Divider Update Status Register" bitfld.long 0x0 0. "DIV_STAT,Divider status for clock mux 9" "0: No divider configuration update is pending.,1: Divider configuration update on at least one.." group.long 0x580++0x3 line.long 0x0 "MUX_10_CSC,Clock Mux 10 Select Control Register" hexmask.long.byte 0x0 24.--27. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" rgroup.long 0x584++0x3 line.long 0x0 "MUX_10_CSS,Clock Mux 10 Select Status Register" hexmask.long.byte 0x0 24.--27. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to FIRC because of a safe clock request..,5: Switch to FIRC because of a safe clock request..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." group.long 0x588++0x3 line.long 0x0 "MUX_10_DC_0,Clock Mux 10 Divider 0 Control Register" bitfld.long 0x0 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." bitfld.long 0x0 16.--18. "DIV,Division value" "0,1,2,3,4,5,6,7" rgroup.long 0x5BC++0x3 line.long 0x0 "MUX_10_DIV_UPD_STAT,Clock Mux 10 Divider Update Status Register" bitfld.long 0x0 0. "DIV_STAT,Divider status for clock mux 10" "0: No divider configuration update is pending.,1: Divider configuration update on at least one.." group.long 0x5C0++0x3 line.long 0x0 "MUX_11_CSC,Clock Mux 11 Select Control Register" hexmask.long.byte 0x0 24.--27. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "FCG,Force clock gate" "0,1" newline bitfld.long 0x0 2. "CG,Clock gate" "0,1" rgroup.long 0x5C4++0x3 line.long 0x0 "MUX_11_CSS,Clock Mux 11 Select Status Register" hexmask.long.byte 0x0 24.--27. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17. "CS,Clock status" "0: Clock is gated to logic-0 at output of clock mux,1: Clock mux is transparent. Active clock pulses at.." newline bitfld.long 0x0 16. "GRIP,Gating request is in progress." "0: Clock source gating or ungating has completed.,1: Clock source gating or ungating is in progress." group.long 0x5C8++0x3 line.long 0x0 "MUX_11_DC_0,Clock Mux 11 Divider 0 Control Register" bitfld.long 0x0 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." hexmask.long.byte 0x0 16.--19. 1. "DIV,Division value" rgroup.long 0x5FC++0x3 line.long 0x0 "MUX_11_DIV_UPD_STAT,Clock Mux 11 Divider Update Status Register" bitfld.long 0x0 0. "DIV_STAT,Divider status for clock mux 11" "0: No divider configuration update is pending.,1: Divider configuration update on at least one.." group.long 0x640++0x3 line.long 0x0 "MUX_13_CSC,Clock Mux 13 Select Control Register" hexmask.long.byte 0x0 24.--28. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" rgroup.long 0x644++0x3 line.long 0x0 "MUX_13_CSS,Clock Mux 13 Select Status Register" hexmask.long.byte 0x0 24.--28. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to FIRC because of a safe clock request..,5: Switch to FIRC because of a safe clock request..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." group.long 0x648++0x3 line.long 0x0 "MUX_13_DC_0,Clock Mux 13 Divider 0 Control Register" bitfld.long 0x0 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." bitfld.long 0x0 16. "DIV,Division value" "0,1" rgroup.long 0x67C++0x3 line.long 0x0 "MUX_13_DIV_UPD_STAT,Clock Mux 13 Divider Update Status Register" bitfld.long 0x0 0. "DIV_STAT,Divider status for clock mux 13" "0: No divider configuration update is pending.,1: Divider configuration update on at least one.." group.long 0x680++0x3 line.long 0x0 "MUX_14_CSC,Clock Mux 14 Select Control Register" hexmask.long.byte 0x0 24.--27. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" rgroup.long 0x684++0x3 line.long 0x0 "MUX_14_CSS,Clock Mux 14 Select Status Register" hexmask.long.byte 0x0 24.--27. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to FIRC because of a safe clock request..,5: Switch to FIRC because of a safe clock request..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." group.long 0x688++0x3 line.long 0x0 "MUX_14_DC_0,Clock Mux 14 Divider 0 Control Register" bitfld.long 0x0 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." bitfld.long 0x0 16. "DIV,Division value" "0,1" rgroup.long 0x6BC++0x3 line.long 0x0 "MUX_14_DIV_UPD_STAT,Clock Mux 14 Divider Update Status Register" bitfld.long 0x0 0. "DIV_STAT,Divider status for clock mux 14" "0: No divider configuration update is pending.,1: Divider configuration update on at least one.." group.long 0x6C0++0x3 line.long 0x0 "MUX_15_CSC,Clock Mux 15 Select Control Register" hexmask.long.byte 0x0 24.--28. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" rgroup.long 0x6C4++0x3 line.long 0x0 "MUX_15_CSS,Clock Mux 15 Select Status Register" hexmask.long.byte 0x0 24.--28. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to FIRC because of a safe clock request..,5: Switch to FIRC because of a safe clock request..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." group.long 0x6C8++0x3 line.long 0x0 "MUX_15_DC_0,Clock Mux 15 Divider 0 Control Register" bitfld.long 0x0 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." hexmask.long.byte 0x0 16.--21. 1. "DIV,Division value" rgroup.long 0x6FC++0x3 line.long 0x0 "MUX_15_DIV_UPD_STAT,Clock Mux 15 Divider Update Status Register" bitfld.long 0x0 0. "DIV_STAT,Divider status for clock mux 15" "0: No divider configuration update is pending.,1: Divider configuration update on at least one.." group.long 0x700++0x3 line.long 0x0 "MUX_16_CSC,Clock Mux 16 Select Control Register" hexmask.long.byte 0x0 24.--28. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" rgroup.long 0x704++0x3 line.long 0x0 "MUX_16_CSS,Clock Mux 16 Select Status Register" hexmask.long.byte 0x0 24.--28. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to FIRC because of a safe clock request..,5: Switch to FIRC because of a safe clock request..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." group.long 0x708++0x3 line.long 0x0 "MUX_16_DC_0,Clock Mux 16 Divider 0 Control Register" bitfld.long 0x0 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." hexmask.long.byte 0x0 16.--21. 1. "DIV,Division value" rgroup.long 0x73C++0x3 line.long 0x0 "MUX_16_DIV_UPD_STAT,Clock Mux 16 Divider Update Status Register" bitfld.long 0x0 0. "DIV_STAT,Divider status for clock mux 16" "0: No divider configuration update is pending.,1: Divider configuration update on at least one.." group.long 0x780++0x3 line.long 0x0 "MUX_18_CSC,Clock Mux 18 Select Control Register" hexmask.long.byte 0x0 24.--28. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" rgroup.long 0x784++0x3 line.long 0x0 "MUX_18_CSS,Clock Mux 18 Select Status Register" hexmask.long.byte 0x0 24.--28. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to FIRC because of a safe clock request..,5: Switch to FIRC because of a safe clock request..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." group.long 0x788++0x3 line.long 0x0 "MUX_18_DC_0,Clock Mux 18 Divider 0 Control Register" bitfld.long 0x0 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." bitfld.long 0x0 16. "DIV,Division value" "0,1" rgroup.long 0x7BC++0x3 line.long 0x0 "MUX_18_DIV_UPD_STAT,Clock Mux 18 Divider Update Status Register" bitfld.long 0x0 0. "DIV_STAT,Divider status for clock mux 18" "0: No divider configuration update is pending.,1: Divider configuration update on at least one.." group.long 0x7C0++0x3 line.long 0x0 "MUX_19_CSC,Clock Mux 19 Select Control Register" hexmask.long.byte 0x0 24.--27. 1. "SELCTL,Clock source selection control" bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0,1" newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0,1" rgroup.long 0x7C4++0x3 line.long 0x0 "MUX_19_CSS,Clock Mux 19 Select Status Register" hexmask.long.byte 0x0 24.--27. 1. "SELSTAT,Clock source selection status" bitfld.long 0x0 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded.,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to FIRC because of a safe clock request..,5: Switch to FIRC because of a safe clock request..,?,?" newline bitfld.long 0x0 16. "SWIP,Switch in progress" "0: Clock source switching is complete.,1: Clock source switching is in progress." bitfld.long 0x0 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested.,1: Safe clock switch operation was requested." newline bitfld.long 0x0 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested.,1: Clock switch operation was requested." group.long 0x7C8++0x3 line.long 0x0 "MUX_19_DC_0,Clock Mux 19 Divider 0 Control Register" bitfld.long 0x0 31. "DE,Divider enable" "0: Divider is disabled.,1: Divider is enabled." hexmask.long.byte 0x0 16.--21. 1. "DIV,Division value" rgroup.long 0x7FC++0x3 line.long 0x0 "MUX_19_DIV_UPD_STAT,Clock Mux 19 Divider Update Status Register" bitfld.long 0x0 0. "DIV_STAT,Divider status for clock mux 19" "0: No divider configuration update is pending.,1: Divider configuration update on at least one.." tree.end tree "MC_ME (Mode Entry Module)" base ad:0x402DC000 group.long 0x0++0xB line.long 0x0 "CTL_KEY,Control Key Register" hexmask.long.word 0x0 0.--15. 1. "KEY,Control key" line.long 0x4 "MODE_CONF,Mode Configuration Register" bitfld.long 0x4 15. "STANDBY,Standby request" "0,1" bitfld.long 0x4 1. "FUNC_RST,Functional reset request" "0,1" bitfld.long 0x4 0. "DEST_RST,Destructive reset request" "0,1" line.long 0x8 "MODE_UPD,Mode Update Register" bitfld.long 0x8 0. "MODE_UPD,Mode update" "0,1" rgroup.long 0xC++0x3 line.long 0x0 "MODE_STAT,Mode Status Register" bitfld.long 0x0 0. "PREV_MODE,Previous mode" "0: The previous mode was reset (any reset).,1: The previous mode was standby." group.long 0x10++0x3 line.long 0x0 "MAIN_COREID,Main Core ID Register" hexmask.long.byte 0x0 8.--12. 1. "PIDX,Partition index" bitfld.long 0x0 0.--2. "CIDX,Core index" "0,1,2,3,4,5,6,7" group.long 0x100++0x7 line.long 0x0 "PRTN0_PCONF,Partition 0 Process Configuration Register" bitfld.long 0x0 0. "PCE,Partition clock enable" "0: Disable the clock to IPs,1: Enable the clock to IPs" line.long 0x4 "PRTN0_PUPD,Partition 0 Process Update Register" bitfld.long 0x4 0. "PCUD,Partition clock update" "0: Do not trigger the hardware process,1: Trigger the hardware process" rgroup.long 0x108++0x3 line.long 0x0 "PRTN0_STAT,Partition 0 Status Register" bitfld.long 0x0 0. "PCS,Partition clock status" "0: Clock is inactive,1: Clock is active" group.long 0x10C++0x3 line.long 0x0 "PRTN0_CORE_LOCKSTEP,Partition 0 Core Lockstep Control Register" bitfld.long 0x0 2. "LS2,Lockstep 2" "0: Lockstep disabled,1: Lockstep enabled" rgroup.long 0x110++0x7 line.long 0x0 "PRTN0_COFB0_STAT,Partition 0 COFB Set 0 Clock Status Register" bitfld.long 0x0 28. "BLOCK28,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 3. "BLOCK3,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 2. "BLOCK2,IP block status" "0: Clock is not running.,1: Clock is running." line.long 0x4 "PRTN0_COFB1_STAT,Partition 0 COFB Set 1 Clock Status Register" bitfld.long 0x4 20. "BLOCK52,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 19. "BLOCK51,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 18. "BLOCK50,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x4 17. "BLOCK49,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 15. "BLOCK47,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 14. "BLOCK46,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x4 13. "BLOCK45,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 12. "BLOCK44,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 10. "BLOCK42,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x4 9. "BLOCK41,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 8. "BLOCK40,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 7. "BLOCK39,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x4 6. "BLOCK38,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 4. "BLOCK36,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 3. "BLOCK35,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x4 2. "BLOCK34,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 1. "BLOCK33,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 0. "BLOCK32,IP block status" "0: Clock is not running.,1: Clock is running." group.long 0x130++0x7 line.long 0x0 "PRTN0_COFB0_CLKEN,Partition 0 COFB Set 0 Clock Enable Register" bitfld.long 0x0 28. "REQ28,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 3. "REQ3,Clock enable" "0: Clock is turned off.,1: Clock is turned on." line.long 0x4 "PRTN0_COFB1_CLKEN,Partition 0 COFB Set 1 Clock Enable Register" bitfld.long 0x4 20. "REQ52,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x4 19. "REQ51,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x4 18. "REQ50,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x4 17. "REQ49,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x4 15. "REQ47,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x4 14. "REQ46,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x4 13. "REQ45,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x4 12. "REQ44,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x4 10. "REQ42,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x4 9. "REQ41,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x4 8. "REQ40,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x4 7. "REQ39,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x4 6. "REQ38,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x4 4. "REQ36,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x4 3. "REQ35,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x4 2. "REQ34,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x4 1. "REQ33,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x4 0. "REQ32,Clock enable" "0: Clock is turned off.,1: Clock is turned on." group.long 0x140++0x7 line.long 0x0 "PRTN0_CORE0_PCONF,Partition 0 Core 0 Process Configuration Register" bitfld.long 0x0 0. "CCE,Core 0 clock enable" "0: Disable the core clock,1: Enable the core clock" line.long 0x4 "PRTN0_CORE0_PUPD,Partition 0 Core 0 Process Update Register" bitfld.long 0x4 0. "CCUPD,Core 0 clock update" "0: Do not trigger the hardware process,1: Trigger the hardware process" rgroup.long 0x148++0x3 line.long 0x0 "PRTN0_CORE0_STAT,Partition 0 Core 0 Status Register" bitfld.long 0x0 31. "WFI,Wait for interrupt status" "0: No WFI executed,1: WFI executed" bitfld.long 0x0 0. "CCS,Core 0 clock process status" "0: Clock is inactive.,1: Clock is active." group.long 0x14C++0x3 line.long 0x0 "PRTN0_CORE0_ADDR,Partition 0 Core 0 Address Register" hexmask.long 0x0 2.--31. 1. "ADDR,Address" group.long 0x160++0x7 line.long 0x0 "PRTN0_CORE1_PCONF,Partition 0 Core 1 Process Configuration Register" bitfld.long 0x0 0. "CCE,Core 1 clock enable" "0: Disable the core clock,1: Enable the core clock" line.long 0x4 "PRTN0_CORE1_PUPD,Partition 0 Core 1 Process Update Register" bitfld.long 0x4 0. "CCUPD,Core 1 clock update" "0: Do not trigger the hardware process,1: Trigger the hardware process" rgroup.long 0x168++0x3 line.long 0x0 "PRTN0_CORE1_STAT,Partition 0 Core 1 Status Register" bitfld.long 0x0 31. "WFI,Wait for interrupt status" "0: No WFI executed,1: WFI executed" bitfld.long 0x0 0. "CCS,Core 1 clock process status" "0: Clock is inactive.,1: Clock is active." group.long 0x16C++0x3 line.long 0x0 "PRTN0_CORE1_ADDR,Partition 0 Core 1 Address Register" hexmask.long 0x0 2.--31. 1. "ADDR,Address" rgroup.long 0x188++0x7 line.long 0x0 "PRTN0_CORE2_STAT,Partition 0 Core 2 Status Register" bitfld.long 0x0 31. "WFI,Wait for interrupt status" "0: No WFI executed,1: WFI executed" bitfld.long 0x0 0. "CCS,Core 2 clock process status" "?,1: Clock is active." line.long 0x4 "PRTN0_CORE2_ADDR,Partition 0 Core 2 Address Register" hexmask.long 0x4 2.--31. 1. "ADDR,Address" group.long 0x1A0++0x7 line.long 0x0 "PRTN0_CORE3_PCONF,Partition 0 Core 3 Process Configuration Register" bitfld.long 0x0 0. "CCE,Core 3 clock enable" "0: Disable the core clock,1: Enable the core clock" line.long 0x4 "PRTN0_CORE3_PUPD,Partition 0 Core 3 Process Update Register" bitfld.long 0x4 0. "CCUPD,Core 3 clock update" "0: Do not trigger the hardware process,1: Trigger the hardware process" rgroup.long 0x1A8++0x3 line.long 0x0 "PRTN0_CORE3_STAT,Partition 0 Core 3 Status Register" bitfld.long 0x0 31. "WFI,Wait for interrupt status" "0: No WFI executed,1: WFI executed" bitfld.long 0x0 0. "CCS,Core 3 clock process status" "0: Clock is inactive.,1: Clock is active." group.long 0x1AC++0x3 line.long 0x0 "PRTN0_CORE3_ADDR,Partition 0 Core 3 Address Register" hexmask.long 0x0 2.--31. 1. "ADDR,Address" group.long 0x1C0++0x7 line.long 0x0 "PRTN0_CORE4_PCONF,Partition 0 Core 4 Process Configuration Register" bitfld.long 0x0 0. "CCE,Core 4 clock enable" "0: Disable the core clock,1: Enable the core clock" line.long 0x4 "PRTN0_CORE4_PUPD,Partition 0 Core 4 Process Update Register" bitfld.long 0x4 0. "CCUPD,Core 4 clock update" "0: Do not trigger the hardware process,1: Trigger the hardware process" rgroup.long 0x1C8++0x3 line.long 0x0 "PRTN0_CORE4_STAT,Partition 0 Core 4 Status Register" bitfld.long 0x0 31. "WFI,Wait for interrupt status" "0: No WFI executed,1: WFI executed" bitfld.long 0x0 0. "CCS,Core 4 clock process status" "0: Clock is inactive.,1: Clock is active." group.long 0x1CC++0x3 line.long 0x0 "PRTN0_CORE4_ADDR,Partition 0 Core 4 Address Register" hexmask.long 0x0 2.--31. 1. "ADDR,Address" group.long 0x1E0++0x7 line.long 0x0 "PRTN0_CORE5_PCONF,Partition 0 Core 5 Process Configuration Register" bitfld.long 0x0 0. "CCE,Core 5 clock enable" "0: Disable the core clock,1: Enable the core clock" line.long 0x4 "PRTN0_CORE5_PUPD,Partition 0 Core 5 Process Update Register" bitfld.long 0x4 0. "CCUPD,Core 5 clock update" "0: Do not trigger the hardware process,1: Trigger the hardware process" rgroup.long 0x1E8++0x3 line.long 0x0 "PRTN0_CORE5_STAT,Partition 0 Core 5 Status Register" bitfld.long 0x0 31. "WFI,Wait for interrupt status" "0: No WFI executed,1: WFI executed" bitfld.long 0x0 0. "CCS,Core 5 clock process status" "0: Clock is inactive.,1: Clock is active." group.long 0x1EC++0x3 line.long 0x0 "PRTN0_CORE5_ADDR,Partition 0 Core 5 Address Register" hexmask.long 0x0 2.--31. 1. "ADDR,Address" group.long 0x300++0x7 line.long 0x0 "PRTN1_PCONF,Partition 1 Process Configuration Register" bitfld.long 0x0 0. "PCE,Partition clock enable" "0: Disable the clock to IPs,1: Enable the clock to IPs" line.long 0x4 "PRTN1_PUPD,Partition 1 Process Update Register" bitfld.long 0x4 0. "PCUD,Partition clock update" "0: Do not trigger the hardware process,1: Trigger the hardware process" rgroup.long 0x308++0x3 line.long 0x0 "PRTN1_STAT,Partition 1 Status Register" bitfld.long 0x0 0. "PCS,Partition clock status" "0: Clock is inactive,1: Clock is active" rgroup.long 0x310++0xF line.long 0x0 "PRTN1_COFB0_STAT,Partition 1 COFB Set 0 Clock Status Register" bitfld.long 0x0 31. "BLOCK31,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 30. "BLOCK30,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 29. "BLOCK29,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 28. "BLOCK28,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 27. "BLOCK27,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 26. "BLOCK26,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 25. "BLOCK25,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 24. "BLOCK24,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 23. "BLOCK23,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 21. "BLOCK21,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 20. "BLOCK20,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 19. "BLOCK19,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 18. "BLOCK18,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 17. "BLOCK17,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 16. "BLOCK16,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 15. "BLOCK15,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 14. "BLOCK14,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 13. "BLOCK13,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 12. "BLOCK12,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 11. "BLOCK11,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 10. "BLOCK10,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 9. "BLOCK9,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 8. "BLOCK8,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 7. "BLOCK7,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 6. "BLOCK6,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 5. "BLOCK5,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 4. "BLOCK4,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 3. "BLOCK3,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 2. "BLOCK2,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 1. "BLOCK1,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 0. "BLOCK0,IP block status" "0: Clock is not running.,1: Clock is running." line.long 0x4 "PRTN1_COFB1_STAT,Partition 1 COFB Set 1 Clock Status Register" bitfld.long 0x4 31. "BLOCK63,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 30. "BLOCK62,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 29. "BLOCK61,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x4 28. "BLOCK60,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 27. "BLOCK59,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 26. "BLOCK58,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x4 25. "BLOCK57,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 24. "BLOCK56,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 23. "BLOCK55,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x4 22. "BLOCK54,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 21. "BLOCK53,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 20. "BLOCK52,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x4 19. "BLOCK51,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 18. "BLOCK50,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 17. "BLOCK49,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x4 15. "BLOCK47,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 13. "BLOCK45,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 11. "BLOCK43,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x4 10. "BLOCK42,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 9. "BLOCK41,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 8. "BLOCK40,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x4 7. "BLOCK39,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 6. "BLOCK38,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 5. "BLOCK37,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x4 4. "BLOCK36,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 3. "BLOCK35,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 2. "BLOCK34,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x4 1. "BLOCK33,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 0. "BLOCK32,IP block status" "0: Clock is not running.,1: Clock is running." line.long 0x8 "PRTN1_COFB2_STAT,Partition 1 COFB Set 2 Clock Status Register" bitfld.long 0x8 31. "BLOCK95,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x8 29. "BLOCK93,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x8 28. "BLOCK92,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x8 27. "BLOCK91,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x8 25. "BLOCK89,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x8 24. "BLOCK88,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x8 23. "BLOCK87,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x8 22. "BLOCK86,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x8 21. "BLOCK85,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x8 20. "BLOCK84,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x8 19. "BLOCK83,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x8 18. "BLOCK82,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x8 17. "BLOCK81,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x8 16. "BLOCK80,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x8 15. "BLOCK79,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x8 14. "BLOCK78,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x8 13. "BLOCK77,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x8 12. "BLOCK76,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x8 11. "BLOCK75,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x8 10. "BLOCK74,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x8 9. "BLOCK73,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x8 8. "BLOCK72,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x8 7. "BLOCK71,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x8 6. "BLOCK70,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x8 5. "BLOCK69,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x8 4. "BLOCK68,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x8 3. "BLOCK67,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x8 2. "BLOCK66,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x8 1. "BLOCK65,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x8 0. "BLOCK64,IP block status" "0: Clock is not running.,1: Clock is running." line.long 0xC "PRTN1_COFB3_STAT,Partition 1 COFB Set 3 Clock Status Register" bitfld.long 0xC 31. "BLOCK127,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0xC 30. "BLOCK126,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0xC 29. "BLOCK125,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0xC 28. "BLOCK124,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0xC 27. "BLOCK123,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0xC 26. "BLOCK122,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0xC 25. "BLOCK121,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0xC 24. "BLOCK120,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0xC 23. "BLOCK119,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0xC 22. "BLOCK118,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0xC 21. "BLOCK117,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0xC 20. "BLOCK116,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0xC 19. "BLOCK115,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0xC 18. "BLOCK114,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0xC 17. "BLOCK113,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0xC 16. "BLOCK112,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0xC 14. "BLOCK110,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0xC 12. "BLOCK108,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0xC 11. "BLOCK107,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0xC 10. "BLOCK106,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0xC 9. "BLOCK105,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0xC 8. "BLOCK104,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0xC 7. "BLOCK103,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0xC 6. "BLOCK102,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0xC 5. "BLOCK101,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0xC 3. "BLOCK99,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0xC 2. "BLOCK98,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0xC 1. "BLOCK97,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0xC 0. "BLOCK96,IP block status" "0: Clock is not running.,1: Clock is running." group.long 0x330++0xF line.long 0x0 "PRTN1_COFB0_CLKEN,Partition 1 COFB Set 0 Clock Enable Register" bitfld.long 0x0 31. "REQ31,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 29. "REQ29,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 28. "REQ28,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 24. "REQ24,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 23. "REQ23,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 21. "REQ21,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 15. "REQ15,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 14. "REQ14,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 13. "REQ13,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 12. "REQ12,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 11. "REQ11,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 10. "REQ10,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 9. "REQ9,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 8. "REQ8,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 7. "REQ7,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 6. "REQ6,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 5. "REQ5,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 4. "REQ4,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 3. "REQ3,Clock enable" "0: Clock is turned off.,1: Clock is turned on." line.long 0x4 "PRTN1_COFB1_CLKEN,Partition 1 COFB Set 1 Clock Enable Register" bitfld.long 0x4 31. "REQ63,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x4 25. "REQ57,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x4 24. "REQ56,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x4 21. "REQ53,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x4 19. "REQ51,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x4 17. "REQ49,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x4 15. "REQ47,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x4 13. "REQ45,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x4 10. "REQ42,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x4 2. "REQ34,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x4 1. "REQ33,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x4 0. "REQ32,Clock enable" "0: Clock is turned off.,1: Clock is turned on." line.long 0x8 "PRTN1_COFB2_CLKEN,Partition 1 COFB Set 2 Clock Enable Register" bitfld.long 0x8 31. "REQ95,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x8 29. "REQ93,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x8 28. "REQ92,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x8 27. "REQ91,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x8 25. "REQ89,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x8 24. "REQ88,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x8 23. "REQ87,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x8 22. "REQ86,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x8 21. "REQ85,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x8 20. "REQ84,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x8 17. "REQ81,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x8 16. "REQ80,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x8 15. "REQ79,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x8 14. "REQ78,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x8 13. "REQ77,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x8 12. "REQ76,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x8 11. "REQ75,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x8 10. "REQ74,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x8 9. "REQ73,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x8 8. "REQ72,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x8 7. "REQ71,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x8 6. "REQ70,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x8 5. "REQ69,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x8 4. "REQ68,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x8 3. "REQ67,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x8 2. "REQ66,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x8 1. "REQ65,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x8 0. "REQ64,Clock enable" "0: Clock is turned off.,1: Clock is turned on." line.long 0xC "PRTN1_COFB3_CLKEN,Partition 1 COFB Set 3 Clock Enable Register" bitfld.long 0xC 31. "REQ127,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0xC 30. "REQ126,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0xC 29. "REQ125,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0xC 28. "REQ124,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0xC 27. "REQ123,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0xC 26. "REQ122,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0xC 25. "REQ121,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0xC 24. "REQ120,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0xC 23. "REQ119,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0xC 22. "REQ118,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0xC 21. "REQ117,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0xC 20. "REQ116,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0xC 19. "REQ115,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0xC 18. "REQ114,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0xC 17. "REQ113,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0xC 16. "REQ112,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0xC 8. "REQ104,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0xC 6. "REQ102,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0xC 0. "REQ96,Clock enable" "0: Clock is turned off.,1: Clock is turned on." group.long 0x500++0x7 line.long 0x0 "PRTN2_PCONF,Partition 2 Process Configuration Register" bitfld.long 0x0 0. "PCE,Partition clock enable" "0: Disable the clock to IPs,1: Enable the clock to IPs" line.long 0x4 "PRTN2_PUPD,Partition 2 Process Update Register" bitfld.long 0x4 0. "PCUD,Partition clock update" "0: Do not trigger the hardware process,1: Trigger the hardware process" rgroup.long 0x508++0x3 line.long 0x0 "PRTN2_STAT,Partition 2 Status Register" bitfld.long 0x0 0. "PCS,Partition clock status" "0: Clock is inactive,1: Clock is active" rgroup.long 0x510++0xB line.long 0x0 "PRTN2_COFB0_STAT,Partition 2 COFB Set 0 Clock Status Register" bitfld.long 0x0 31. "BLOCK31,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 30. "BLOCK30,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 29. "BLOCK29,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 28. "BLOCK28,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 27. "BLOCK27,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 26. "BLOCK26,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 25. "BLOCK25,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 24. "BLOCK24,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 23. "BLOCK23,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 22. "BLOCK22,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 21. "BLOCK21,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 20. "BLOCK20,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 19. "BLOCK19,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 18. "BLOCK18,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 17. "BLOCK17,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 16. "BLOCK16,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 15. "BLOCK15,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 14. "BLOCK14,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 13. "BLOCK13,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 12. "BLOCK12,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 11. "BLOCK11,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 10. "BLOCK10,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 9. "BLOCK9,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 8. "BLOCK8,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 7. "BLOCK7,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 6. "BLOCK6,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 5. "BLOCK5,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 4. "BLOCK4,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 3. "BLOCK3,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 2. "BLOCK2,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x0 1. "BLOCK1,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x0 0. "BLOCK0,IP block status" "0: Clock is not running.,1: Clock is running." line.long 0x4 "PRTN2_COFB1_STAT,Partition 2 COFB Set 1 Clock Status Register" bitfld.long 0x4 31. "BLOCK63,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 30. "BLOCK62,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 27. "BLOCK59,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x4 26. "BLOCK58,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 23. "BLOCK55,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 19. "BLOCK51,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x4 16. "BLOCK48,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 15. "BLOCK47,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 10. "BLOCK42,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x4 9. "BLOCK41,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 8. "BLOCK40,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 7. "BLOCK39,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x4 6. "BLOCK38,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 5. "BLOCK37,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 4. "BLOCK36,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x4 3. "BLOCK35,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 2. "BLOCK34,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x4 1. "BLOCK33,IP block status" "0: Clock is not running.,1: Clock is running." line.long 0x8 "PRTN2_COFB2_STAT,Partition 2 COFB Set 2 Clock Status Register" bitfld.long 0x8 27. "BLOCK91,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x8 26. "BLOCK90,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x8 25. "BLOCK89,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x8 24. "BLOCK88,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x8 23. "BLOCK87,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x8 22. "BLOCK86,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x8 21. "BLOCK85,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x8 20. "BLOCK84,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x8 19. "BLOCK83,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x8 18. "BLOCK82,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x8 17. "BLOCK81,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x8 16. "BLOCK80,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x8 15. "BLOCK79,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x8 14. "BLOCK78,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x8 13. "BLOCK77,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x8 12. "BLOCK76,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x8 11. "BLOCK75,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x8 10. "BLOCK74,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x8 9. "BLOCK73,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x8 8. "BLOCK72,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x8 6. "BLOCK70,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x8 5. "BLOCK69,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x8 4. "BLOCK68,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x8 3. "BLOCK67,IP block status" "0: Clock is not running.,1: Clock is running." newline bitfld.long 0x8 1. "BLOCK65,IP block status" "0: Clock is not running.,1: Clock is running." bitfld.long 0x8 0. "BLOCK64,IP block status" "0: Clock is not running.,1: Clock is running." group.long 0x530++0xB line.long 0x0 "PRTN2_COFB0_CLKEN,Partition 2 COFB Set 0 Clock Enable Register" bitfld.long 0x0 31. "REQ31,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 30. "REQ30,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 29. "REQ29,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 28. "REQ28,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 27. "REQ27,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 24. "REQ24,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 23. "REQ23,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 22. "REQ22,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 21. "REQ21,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 20. "REQ20,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 19. "REQ19,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 18. "REQ18,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 17. "REQ17,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 16. "REQ16,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 15. "REQ15,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 14. "REQ14,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 13. "REQ13,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 12. "REQ12,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 11. "REQ11,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 10. "REQ10,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 9. "REQ9,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 8. "REQ8,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 7. "REQ7,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 6. "REQ6,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x0 5. "REQ5,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x0 4. "REQ4,Clock enable" "0: Clock is turned off.,1: Clock is turned on." line.long 0x4 "PRTN2_COFB1_CLKEN,Partition 2 COFB Set 1 Clock Enable Register" bitfld.long 0x4 31. "REQ63,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x4 30. "REQ62,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x4 26. "REQ58,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x4 23. "REQ55,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x4 19. "REQ51,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x4 16. "REQ48,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x4 15. "REQ47,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x4 10. "REQ42,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x4 9. "REQ41,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x4 8. "REQ40,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x4 7. "REQ39,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x4 6. "REQ38,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x4 5. "REQ37,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x4 4. "REQ36,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x4 3. "REQ35,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x4 2. "REQ34,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x4 1. "REQ33,Clock enable" "0: Clock is turned off.,1: Clock is turned on." line.long 0x8 "PRTN2_COFB2_CLKEN,Partition 2 COFB Set 2 Clock Enable Register" bitfld.long 0x8 27. "REQ91,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x8 26. "REQ90,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x8 25. "REQ89,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x8 24. "REQ88,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x8 23. "REQ87,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x8 22. "REQ86,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x8 21. "REQ85,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x8 20. "REQ84,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x8 19. "REQ83,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x8 18. "REQ82,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x8 17. "REQ81,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x8 16. "REQ80,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x8 15. "REQ79,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x8 14. "REQ78,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x8 13. "REQ77,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x8 12. "REQ76,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x8 11. "REQ75,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x8 10. "REQ74,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x8 9. "REQ73,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x8 8. "REQ72,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x8 6. "REQ70,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x8 5. "REQ69,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x8 4. "REQ68,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x8 3. "REQ67,Clock enable" "0: Clock is turned off.,1: Clock is turned on." newline bitfld.long 0x8 1. "REQ65,Clock enable" "0: Clock is turned off.,1: Clock is turned on." bitfld.long 0x8 0. "REQ64,Clock enable" "0: Clock is turned off.,1: Clock is turned on." tree.end tree "MC_RGM (Reset Generation Module)" base ad:0x4028C000 group.long 0x0++0x3 line.long 0x0 "DES,Destructive Event Status Register" eventfld.long 0x0 30. "DEBUG_DEST,Flag for 'Destructive' Reset DEBUG_DEST" "0: 'Destructive' reset event DEBUG_DEST has not..,1: 'Destructive' reset event DEBUG_DEST has occurred." eventfld.long 0x0 29. "SW_DEST,Flag for 'Destructive' Reset SW_DEST" "0: 'Destructive' reset event SW_DEST has not..,1: 'Destructive' reset event SW_DEST has occurred." newline eventfld.long 0x0 18. "HSE_SNVS_RST,Flag for 'Destructive' Reset HSE_SNVS_RST" "0: 'Destructive' reset event HSE_SNVS_RST has not..,1: 'Destructive' reset event HSE_SNVS_RST has.." eventfld.long 0x0 17. "HSE_TMPR_RST,Flag for 'Destructive' Reset HSE_TMPR_RST" "0: 'Destructive' reset event HSE_TMPR_RST has not..,1: 'Destructive' reset event HSE_TMPR_RST has.." newline eventfld.long 0x0 16. "CM7_CORE_CLK_FAIL,Flag for 'Destructive' Reset CM7_CORE_CLK_FAIL" "0: 'Destructive' reset event CM7_CORE_CLK_FAIL has..,1: 'Destructive' reset event CM7_CORE_CLK_FAIL has.." eventfld.long 0x0 15. "SYS_DIV_FAIL,Flag for 'Destructive' Reset SYS_DIV_FAIL" "0: 'Destructive' reset event SYS_DIV_FAIL has not..,1: 'Destructive' reset event SYS_DIV_FAIL has.." newline eventfld.long 0x0 14. "HSE_CLK_FAIL,Flag for 'Destructive' Reset HSE_CLK_FAIL" "0: 'Destructive' reset event HSE_CLK_FAIL has not..,1: 'Destructive' reset event HSE_CLK_FAIL has.." eventfld.long 0x0 12. "AIPS_PLAT_CLK_FAIL,Flag for 'Destructive' Reset AIPS_PLAT_CLK_FAIL" "0: 'Destructive' reset event AIPS_PLAT_CLK_FAIL has..,1: 'Destructive' reset event AIPS_PLAT_CLK_FAIL has.." newline eventfld.long 0x0 10. "CORE_CLK_FAIL,Flag for 'Destructive' Reset CORE_CLK_FAIL" "0: 'Destructive' reset event CORE_CLK_FAIL has not..,1: 'Destructive' reset event CORE_CLK_FAIL has.." eventfld.long 0x0 9. "PLL_LOL,Flag for 'Destructive' Reset PLL_LOL" "0: 'Destructive' reset event PLL_LOL has not..,1: 'Destructive' reset event PLL_LOL has occurred." newline eventfld.long 0x0 8. "FXOSC_FAIL,Flag for 'Destructive' Reset FXOSC_FAIL" "0: 'Destructive' reset event FXOSC_FAIL has not..,1: 'Destructive' reset event FXOSC_FAIL has occurred." eventfld.long 0x0 6. "MC_RGM_FRE,Flag for 'Destructive' Reset MC_RGM_FRE" "0: 'Destructive' reset event MC_RGM_FRE has not..,1: 'Destructive' reset event MC_RGM_FRE has occurred." newline eventfld.long 0x0 4. "STCU_URF,Flag for 'Destructive' Reset STCU_URF" "0: 'Destructive' reset event STCU_URF has not..,1: 'Destructive' reset event STCU_URF has occurred." eventfld.long 0x0 3. "FCCU_FTR,Flag for 'Destructive' Reset FCCU_FTR" "0: 'Destructive' reset event FCCU_FTR has not..,1: 'Destructive' reset event FCCU_FTR has occurred." newline eventfld.long 0x0 0. "F_POR,Flag for power-on reset" "0: No power-on event has occurred since the last..,1: A power-on event has occurred." group.long 0x8++0x1F line.long 0x0 "FES,Functional /External Reset Status Register" eventfld.long 0x0 30. "DEBUG_FUNC,Flag for 'Functional' Reset DEBUG_FUNC" "0: 'Functional' reset event DEBUG_FUNC has not..,1: 'Functional' reset event DEBUG_FUNC has occurred." eventfld.long 0x0 29. "SW_FUNC,Flag for 'Functional' Reset SW_FUNC" "0: 'Functional' reset event SW_FUNC has not..,1: 'Functional' reset event SW_FUNC has occurred." newline eventfld.long 0x0 20. "HSE_BOOT_RST,Flag for 'Functional' Reset HSE_BOOT_RST" "0: 'Functional' reset event HSE_BOOT_RST has not..,1: 'Functional' reset event HSE_BOOT_RST has.." eventfld.long 0x0 16. "HSE_SWT_RST,Flag for 'Functional' Reset HSE_SWT_RST" "0: 'Functional' reset event HSE_SWT_RST has not..,1: 'Functional' reset event HSE_SWT_RST has occurred." newline eventfld.long 0x0 12. "PLL_AUX,Flag for 'Functional' Reset PLL_AUX" "0: 'Functional' reset event PLL_AUX has not..,1: 'Functional' reset event PLL_AUX has occurred." eventfld.long 0x0 10. "SWT3_RST,Flag for 'Functional' Reset SWT3_RST" "0: 'Functional' reset event SWT3_RST has not..,1: 'Functional' reset event SWT3_RST has occurred." newline eventfld.long 0x0 9. "JTAG_RST,Flag for 'Functional' Reset JTAG_RST" "0: 'Functional' reset event JTAG_RST has not..,1: 'Functional' reset event JTAG_RST has occurred." eventfld.long 0x0 8. "SWT2_RST,Flag for 'Functional' Reset SWT2_RST" "0: 'Functional' reset event SWT2_RST has not..,1: 'Functional' reset event SWT2_RST has occurred." newline eventfld.long 0x0 7. "SWT1_RST,Flag for 'Functional' Reset SWT1_RST" "0: 'Functional' reset event SWT1_RST has not..,1: 'Functional' reset event SWT1_RST has occurred." eventfld.long 0x0 6. "SWT0_RST,Flag for 'Functional' Reset SWT0_RST" "0: 'Functional' reset event SWT0_RST has not..,1: 'Functional' reset event SWT0_RST has occurred." newline eventfld.long 0x0 4. "ST_DONE,Flag for 'Functional' Reset ST_DONE" "0: 'Functional' reset event ST_DONE has not..,1: 'Functional' reset event ST_DONE has occurred." eventfld.long 0x0 3. "FCCU_RST,Flag for 'Functional' Reset FCCU_RST" "0: 'Functional' reset event FCCU_RST has not..,1: 'Functional' reset event FCCU_RST has occurred." newline eventfld.long 0x0 0. "F_EXR,Flag for External Reset" "0: No external reset event has occurred since..,1: An external reset event has occurred." line.long 0x4 "FERD,Functional Event Reset Disable Register" bitfld.long 0x4 30. "D_DEBUG_FUNC,DEBUG_FUNC Disable Control" "0: Functional reset event DEBUG_FUNC triggers a..,1: Functional reset event DEBUG_FUNC generates an.." bitfld.long 0x4 10. "D_SWT3_RST,SWT3_RST Disable Control" "0: Functional reset event SWT3_RST triggers a reset..,1: Functional reset event SWT3_RST generates an.." newline bitfld.long 0x4 9. "D_JTAG_RST,JTAG_RST Disable Control" "0: Functional reset event JTAG_RST triggers a reset..,1: Functional reset event JTAG_RST generates an.." bitfld.long 0x4 8. "D_SWT2_RST,SWT2_RST Disable Control" "0: Functional reset event SWT2_RST triggers a reset..,1: Functional reset event SWT2_RST generates an.." newline bitfld.long 0x4 7. "D_SWT1_RST,SWT1_RST Disable Control" "0: Functional reset event SWT1_RST triggers a reset..,1: Functional reset event SWT1_RST generates an.." bitfld.long 0x4 6. "D_SWT0_RST,SWT0_RST Disable Control" "0: Functional reset event SWT0_RST triggers a reset..,1: Functional reset event SWT0_RST generates an.." newline bitfld.long 0x4 3. "D_FCCU_RST,FCCU_RST Disable Control" "0: Functional reset event FCCU_RST triggers a reset..,1: Functional reset event FCCU_RST generates an.." line.long 0x8 "FBRE,Functional Bidirectional Reset Enable Register" rbitfld.long 0x8 30. "BE_DEBUG_FUNC,Bidirectional Reset Enables for 'Functional' Reset DEBUG_FUNC" "0: External reset pin is asserted on a 'Functional'..,1: External reset pin is not asserted on a.." rbitfld.long 0x8 29. "BE_SW_FUNC,Bidirectional Reset Enables for 'Functional' Reset SW_FUNC" "0: External reset pin is asserted on a 'Functional'..,1: External reset pin is not asserted on a.." newline rbitfld.long 0x8 20. "BE_HSE_BOOT_RST,Bidirectional Reset Enables for 'Functional' Reset HSE_BOOT_RST" "0: External reset pin is asserted on a 'Functional'..,1: External reset pin is not asserted on a.." rbitfld.long 0x8 16. "BE_HSE_SWT_RST,Bidirectional Reset Enables for 'Functional' Reset HSE_SWT_RST" "0: External reset pin is asserted on a 'Functional'..,1: External reset pin is not asserted on a.." newline rbitfld.long 0x8 12. "BE_PLL_AUX,Bidirectional Reset Enables for 'Functional' Reset PLL_AUX" "0: External reset pin is asserted on a 'Functional'..,1: External reset pin is not asserted on a.." bitfld.long 0x8 10. "BE_SWT3_RST,Bidirectional Reset Enables for 'Functional' Reset SWT3_RST" "0: External reset pin is asserted on a 'Functional'..,1: External reset pin is not asserted on a.." newline rbitfld.long 0x8 9. "BE_JTAG_RST,Bidirectional Reset Enables for 'Functional' Reset JTAG_RST" "0: External reset pin is asserted on a 'Functional'..,1: External reset pin is not asserted on a.." rbitfld.long 0x8 8. "BE_SWT2_RST,Bidirectional Reset Enables for 'Functional' Reset SWT2_RST" "0: External reset pin is asserted on a 'Functional'..,1: External reset pin is not asserted on a.." newline rbitfld.long 0x8 7. "BE_SWT1_RST,Bidirectional Reset Enables for 'Functional' Reset SWT1_RST" "0: External reset pin is asserted on a 'Functional'..,1: External reset pin is not asserted on a.." rbitfld.long 0x8 6. "BE_SWT0_RST,Bidirectional Reset Enables for 'Functional' Reset SWT0_RST" "0: External reset pin is asserted on a 'Functional'..,1: External reset pin is not asserted on a.." newline bitfld.long 0x8 4. "BE_ST_DONE,Bidirectional Reset Enables for 'Functional' Reset ST_DONE" "0: External reset pin is asserted on a 'Functional'..,1: External reset pin is not asserted on a.." rbitfld.long 0x8 3. "BE_FCCU_RST,Bidirectional Reset Enables for 'Functional' Reset FCCU_RST" "0: External reset pin is asserted on a 'Functional'..,1: External reset pin is not asserted on a.." line.long 0xC "FREC,Functional Reset Escalation Counter Register" hexmask.long.byte 0xC 0.--3. 1. "FREC,Functional' Reset Escalation Counter" line.long 0x10 "FRET,Functional Reset Escalation Threshold Register" hexmask.long.byte 0x10 0.--3. 1. "FRET,'Functional' Reset Escalation Threshold" line.long 0x14 "DRET,Destructive Reset Escalation Threshold Register" hexmask.long.byte 0x14 0.--3. 1. "DRET,'Destructive' Reset Escalation Threshold" line.long 0x18 "ERCTRL,External Reset Control Register" bitfld.long 0x18 0. "ERASSERT,ERASSERT" "0: No change,1: External reset is asserted" line.long 0x1C "RDSS,Reset During Standby Status Register" eventfld.long 0x1C 1. "FES_RES,FES_RES" "0: No functional reset event occurred during..,1: Functional reset event occurred during standby.." eventfld.long 0x1C 0. "DES_RES,DES_RES" "0: No destructive reset event occurred during..,1: Destructive reset event occurred during standby.." tree.end tree "MCM_CM7 (Miscellaneous Control Module (Cortex-M7))" base ad:0x0 tree "MCM_0_CM7" base ad:0xE0080000 rgroup.word 0x0++0x3 line.word 0x0 "PLREV,SoC-defined Platform Revision" hexmask.word 0x0 0.--15. 1. "PLREV,The PLREV[15:0] field is specified by a platform input signal to define a software-visible revision number." line.word 0x2 "PCT,Processor Core Type" hexmask.word 0x2 0.--15. 1. "PCT,This MCM design supports the Arm Cortex M7 core. The following value identifies this core complex." group.long 0xC++0x7 line.long 0x0 "CPCR,Core Platform Control" bitfld.long 0x0 27. "CM7_AHBSPRI,AHB Slave Priority" "0: Uses a round-robin arbitration scheme,1: AHB-slave access has priority over a core access" line.long 0x4 "ISCR,Interrupt Status and Control" bitfld.long 0x4 31. "FIDCE,FPU Input Denormal Interrupt Enable" "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x4 28. "FIXCE,FPU Inexact Interrupt Enable" "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x4 27. "FUFCE,FPU Underflow Interrupt Enable" "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x4 26. "FOFCE,FPU Overflow Interrupt Enable" "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x4 25. "FDZCE,FPU Divide-by-Zero Interrupt Enable" "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x4 24. "FIOCE,FPU Invalid Operation Interrupt Enable" "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x4 21. "WABE,TCM Write Abort Interrupt Enable" "0: Disable interrupt,1: Enable Interrupt" rbitfld.long 0x4 15. "FIDC,FPU Input Denormal Interrupt Status" "0: No interrupt,1: Interrupt occurred" newline rbitfld.long 0x4 12. "FIXC,FPU Inexact Interrupt Status" "0: No interrupt,1: Interrupt occurred" rbitfld.long 0x4 11. "FUFC,FPU Underflow Interrupt Status" "0: No interrupt,1: Interrupt occurred" newline rbitfld.long 0x4 10. "FOFC,FPU Overflow Interrupt Status" "0: No interrupt,1: Interrupt occurred" rbitfld.long 0x4 9. "FDZC,FPU Divide-by-Zero Interrupt Status" "0: No interrupt,1: Interrupt occurred" newline rbitfld.long 0x4 8. "FIOC,FPU Invalid Operation Interrupt Status" "0: No interrupt,1: Interrupt occurred" rbitfld.long 0x4 6. "WABSO,Write Abort on Slave Overrun" "0: No write abort overrun,1: Write abort overrun occurred" newline eventfld.long 0x4 5. "WABS,Write Abort on Slave" "0: No write abort occurred on AHBS interface,1: Write abort occurred on AHBS interface" rgroup.long 0x400++0x13 line.long 0x0 "LMEM_DESC_0,Local Memory Descriptor 0" bitfld.long 0x0 31. "LMV,Local Memory Valid" "0: LMEMn not present,1: LMEMn present" bitfld.long 0x0 28. "LMSZH,LMEM Size Hole" "0: LMEMn is a power-of-2 capacity,1: LMEMn is not a power-of-2 with capacity of 0.75.." newline hexmask.long.byte 0x0 24.--27. 1. "LMSZ,Local Memory Size" hexmask.long.byte 0x0 20.--23. 1. "WY,Level 1 Cache Ways" newline bitfld.long 0x0 17.--19. "DPW,Data Path Width" "?,?,2: LMEMn is 32-bits wide,3: LMEMn is 64-bits wide,?,?,?,?" bitfld.long 0x0 13.--15. "MT,Memory Type" "0: ITCM,1: DTCM,2: ICACHE,3: DCACHE,?,?,?,?" line.long 0x4 "LMEM_DESC_1,Local Memory Descriptor 1" bitfld.long 0x4 31. "LMV,Local Memory Valid" "0: LMEMn not present,1: LMEMn present" bitfld.long 0x4 28. "LMSZH,LMEM Size Hole" "0: LMEMn is a power-of-2 capacity,1: LMEMn is not a power-of-2 with capacity of 0.75.." newline hexmask.long.byte 0x4 24.--27. 1. "LMSZ,Local Memory Size" hexmask.long.byte 0x4 20.--23. 1. "WY,Level 1 Cache Ways" newline bitfld.long 0x4 17.--19. "DPW,Data Path Width" "?,?,2: LMEMn is 32-bits wide,3: LMEMn is 64-bits wide,?,?,?,?" bitfld.long 0x4 13.--15. "MT,Memory Type" "0: ITCM,1: DTCM,2: ICACHE,3: DCACHE,?,?,?,?" line.long 0x8 "LMEM_DESC_2,Local Memory Descriptor 2" bitfld.long 0x8 31. "LMV,Local Memory Valid" "0: LMEMn not present,1: LMEMn present" bitfld.long 0x8 28. "LMSZH,LMEM Size Hole" "0: LMEMn is a power-of-2 capacity,1: LMEMn is not a power-of-2 with capacity of 0.75.." newline hexmask.long.byte 0x8 24.--27. 1. "LMSZ,Local Memory Size" hexmask.long.byte 0x8 20.--23. 1. "WY,Level 1 Cache Ways" newline bitfld.long 0x8 17.--19. "DPW,Data Path Width" "?,?,2: LMEMn is 32-bits wide,3: LMEMn is 64-bits wide,?,?,?,?" bitfld.long 0x8 13.--15. "MT,Memory Type" "0: ITCM,1: DTCM,2: ICACHE,3: DCACHE,?,?,?,?" line.long 0xC "LMEM_DESC_3,Local Memory Descriptor 3" bitfld.long 0xC 31. "LMV,Local Memory Valid" "0: LMEMn not present,1: LMEMn present" bitfld.long 0xC 28. "LMSZH,LMEM Size Hole" "0: LMEMn is a power-of-2 capacity,1: LMEMn is not a power-of-2 with capacity of 0.75.." newline hexmask.long.byte 0xC 24.--27. 1. "LMSZ,Local Memory Size" hexmask.long.byte 0xC 20.--23. 1. "WY,Level 1 Cache Ways" newline bitfld.long 0xC 17.--19. "DPW,Data Path Width" "?,?,2: LMEMn is 32-bits wide,3: LMEMn is 64-bits wide,?,?,?,?" bitfld.long 0xC 13.--15. "MT,Memory Type" "0: ITCM,1: DTCM,2: ICACHE,3: DCACHE,?,?,?,?" line.long 0x10 "LMEM_DESC_4,Local Memory Descriptor 4" bitfld.long 0x10 31. "LMV,Local Memory Valid" "0: LMEMn not present,1: LMEMn present" bitfld.long 0x10 28. "LMSZH,LMEM Size Hole" "0: LMEMn is a power-of-2 capacity,1: LMEMn is not a power-of-2 with capacity of 0.75.." newline hexmask.long.byte 0x10 24.--27. 1. "LMSZ,Local Memory Size" hexmask.long.byte 0x10 20.--23. 1. "WY,Level 1 Cache Ways" newline bitfld.long 0x10 17.--19. "DPW,Data Path Width" "?,?,2: LMEMn is 32-bits wide,3: LMEMn is 64-bits wide,?,?,?,?" bitfld.long 0x10 13.--15. "MT,Memory Type" "0: ITCM,1: DTCM,2: ICACHE,3: DCACHE,?,?,?,?" tree.end tree "MCM_1_CM7" base ad:0xE0080000 rgroup.word 0x0++0x3 line.word 0x0 "PLREV,SoC-defined Platform Revision" hexmask.word 0x0 0.--15. 1. "PLREV,The PLREV[15:0] field is specified by a platform input signal to define a software-visible revision number." line.word 0x2 "PCT,Processor Core Type" hexmask.word 0x2 0.--15. 1. "PCT,This MCM design supports the Arm Cortex M7 core. The following value identifies this core complex." group.long 0xC++0x7 line.long 0x0 "CPCR,Core Platform Control" bitfld.long 0x0 27. "CM7_AHBSPRI,AHB Slave Priority" "0: Uses a round-robin arbitration scheme,1: AHB-slave access has priority over a core access" line.long 0x4 "ISCR,Interrupt Status and Control" bitfld.long 0x4 31. "FIDCE,FPU Input Denormal Interrupt Enable" "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x4 28. "FIXCE,FPU Inexact Interrupt Enable" "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x4 27. "FUFCE,FPU Underflow Interrupt Enable" "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x4 26. "FOFCE,FPU Overflow Interrupt Enable" "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x4 25. "FDZCE,FPU Divide-by-Zero Interrupt Enable" "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x4 24. "FIOCE,FPU Invalid Operation Interrupt Enable" "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x4 21. "WABE,TCM Write Abort Interrupt Enable" "0: Disable interrupt,1: Enable Interrupt" rbitfld.long 0x4 15. "FIDC,FPU Input Denormal Interrupt Status" "0: No interrupt,1: Interrupt occurred" newline rbitfld.long 0x4 12. "FIXC,FPU Inexact Interrupt Status" "0: No interrupt,1: Interrupt occurred" rbitfld.long 0x4 11. "FUFC,FPU Underflow Interrupt Status" "0: No interrupt,1: Interrupt occurred" newline rbitfld.long 0x4 10. "FOFC,FPU Overflow Interrupt Status" "0: No interrupt,1: Interrupt occurred" rbitfld.long 0x4 9. "FDZC,FPU Divide-by-Zero Interrupt Status" "0: No interrupt,1: Interrupt occurred" newline rbitfld.long 0x4 8. "FIOC,FPU Invalid Operation Interrupt Status" "0: No interrupt,1: Interrupt occurred" rbitfld.long 0x4 6. "WABSO,Write Abort on Slave Overrun" "0: No write abort overrun,1: Write abort overrun occurred" newline eventfld.long 0x4 5. "WABS,Write Abort on Slave" "0: No write abort occurred on AHBS interface,1: Write abort occurred on AHBS interface" rgroup.long 0x400++0x13 line.long 0x0 "LMEM_DESC_0,Local Memory Descriptor 0" bitfld.long 0x0 31. "LMV,Local Memory Valid" "0: LMEMn not present,1: LMEMn present" bitfld.long 0x0 28. "LMSZH,LMEM Size Hole" "0: LMEMn is a power-of-2 capacity,1: LMEMn is not a power-of-2 with capacity of 0.75.." newline hexmask.long.byte 0x0 24.--27. 1. "LMSZ,Local Memory Size" hexmask.long.byte 0x0 20.--23. 1. "WY,Level 1 Cache Ways" newline bitfld.long 0x0 17.--19. "DPW,Data Path Width" "?,?,2: LMEMn is 32-bits wide,3: LMEMn is 64-bits wide,?,?,?,?" bitfld.long 0x0 13.--15. "MT,Memory Type" "0: ITCM,1: DTCM,2: ICACHE,3: DCACHE,?,?,?,?" line.long 0x4 "LMEM_DESC_1,Local Memory Descriptor 1" bitfld.long 0x4 31. "LMV,Local Memory Valid" "0: LMEMn not present,1: LMEMn present" bitfld.long 0x4 28. "LMSZH,LMEM Size Hole" "0: LMEMn is a power-of-2 capacity,1: LMEMn is not a power-of-2 with capacity of 0.75.." newline hexmask.long.byte 0x4 24.--27. 1. "LMSZ,Local Memory Size" hexmask.long.byte 0x4 20.--23. 1. "WY,Level 1 Cache Ways" newline bitfld.long 0x4 17.--19. "DPW,Data Path Width" "?,?,2: LMEMn is 32-bits wide,3: LMEMn is 64-bits wide,?,?,?,?" bitfld.long 0x4 13.--15. "MT,Memory Type" "0: ITCM,1: DTCM,2: ICACHE,3: DCACHE,?,?,?,?" line.long 0x8 "LMEM_DESC_2,Local Memory Descriptor 2" bitfld.long 0x8 31. "LMV,Local Memory Valid" "0: LMEMn not present,1: LMEMn present" bitfld.long 0x8 28. "LMSZH,LMEM Size Hole" "0: LMEMn is a power-of-2 capacity,1: LMEMn is not a power-of-2 with capacity of 0.75.." newline hexmask.long.byte 0x8 24.--27. 1. "LMSZ,Local Memory Size" hexmask.long.byte 0x8 20.--23. 1. "WY,Level 1 Cache Ways" newline bitfld.long 0x8 17.--19. "DPW,Data Path Width" "?,?,2: LMEMn is 32-bits wide,3: LMEMn is 64-bits wide,?,?,?,?" bitfld.long 0x8 13.--15. "MT,Memory Type" "0: ITCM,1: DTCM,2: ICACHE,3: DCACHE,?,?,?,?" line.long 0xC "LMEM_DESC_3,Local Memory Descriptor 3" bitfld.long 0xC 31. "LMV,Local Memory Valid" "0: LMEMn not present,1: LMEMn present" bitfld.long 0xC 28. "LMSZH,LMEM Size Hole" "0: LMEMn is a power-of-2 capacity,1: LMEMn is not a power-of-2 with capacity of 0.75.." newline hexmask.long.byte 0xC 24.--27. 1. "LMSZ,Local Memory Size" hexmask.long.byte 0xC 20.--23. 1. "WY,Level 1 Cache Ways" newline bitfld.long 0xC 17.--19. "DPW,Data Path Width" "?,?,2: LMEMn is 32-bits wide,3: LMEMn is 64-bits wide,?,?,?,?" bitfld.long 0xC 13.--15. "MT,Memory Type" "0: ITCM,1: DTCM,2: ICACHE,3: DCACHE,?,?,?,?" line.long 0x10 "LMEM_DESC_4,Local Memory Descriptor 4" bitfld.long 0x10 31. "LMV,Local Memory Valid" "0: LMEMn not present,1: LMEMn present" bitfld.long 0x10 28. "LMSZH,LMEM Size Hole" "0: LMEMn is a power-of-2 capacity,1: LMEMn is not a power-of-2 with capacity of 0.75.." newline hexmask.long.byte 0x10 24.--27. 1. "LMSZ,Local Memory Size" hexmask.long.byte 0x10 20.--23. 1. "WY,Level 1 Cache Ways" newline bitfld.long 0x10 17.--19. "DPW,Data Path Width" "?,?,2: LMEMn is 32-bits wide,3: LMEMn is 64-bits wide,?,?,?,?" bitfld.long 0x10 13.--15. "MT,Memory Type" "0: ITCM,1: DTCM,2: ICACHE,3: DCACHE,?,?,?,?" tree.end tree "MCM_2_CM7" base ad:0xE0080000 rgroup.word 0x0++0x3 line.word 0x0 "PLREV,SoC-defined Platform Revision" hexmask.word 0x0 0.--15. 1. "PLREV,The PLREV[15:0] field is specified by a platform input signal to define a software-visible revision number." line.word 0x2 "PCT,Processor Core Type" hexmask.word 0x2 0.--15. 1. "PCT,This MCM design supports the Arm Cortex M7 core. The following value identifies this core complex." group.long 0xC++0x7 line.long 0x0 "CPCR,Core Platform Control" bitfld.long 0x0 27. "CM7_AHBSPRI,AHB Slave Priority" "0: Uses a round-robin arbitration scheme,1: AHB-slave access has priority over a core access" line.long 0x4 "ISCR,Interrupt Status and Control" bitfld.long 0x4 31. "FIDCE,FPU Input Denormal Interrupt Enable" "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x4 28. "FIXCE,FPU Inexact Interrupt Enable" "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x4 27. "FUFCE,FPU Underflow Interrupt Enable" "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x4 26. "FOFCE,FPU Overflow Interrupt Enable" "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x4 25. "FDZCE,FPU Divide-by-Zero Interrupt Enable" "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x4 24. "FIOCE,FPU Invalid Operation Interrupt Enable" "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x4 21. "WABE,TCM Write Abort Interrupt Enable" "0: Disable interrupt,1: Enable Interrupt" rbitfld.long 0x4 15. "FIDC,FPU Input Denormal Interrupt Status" "0: No interrupt,1: Interrupt occurred" newline rbitfld.long 0x4 12. "FIXC,FPU Inexact Interrupt Status" "0: No interrupt,1: Interrupt occurred" rbitfld.long 0x4 11. "FUFC,FPU Underflow Interrupt Status" "0: No interrupt,1: Interrupt occurred" newline rbitfld.long 0x4 10. "FOFC,FPU Overflow Interrupt Status" "0: No interrupt,1: Interrupt occurred" rbitfld.long 0x4 9. "FDZC,FPU Divide-by-Zero Interrupt Status" "0: No interrupt,1: Interrupt occurred" newline rbitfld.long 0x4 8. "FIOC,FPU Invalid Operation Interrupt Status" "0: No interrupt,1: Interrupt occurred" rbitfld.long 0x4 6. "WABSO,Write Abort on Slave Overrun" "0: No write abort overrun,1: Write abort overrun occurred" newline eventfld.long 0x4 5. "WABS,Write Abort on Slave" "0: No write abort occurred on AHBS interface,1: Write abort occurred on AHBS interface" rgroup.long 0x400++0x13 line.long 0x0 "LMEM_DESC_0,Local Memory Descriptor 0" bitfld.long 0x0 31. "LMV,Local Memory Valid" "0: LMEMn not present,1: LMEMn present" bitfld.long 0x0 28. "LMSZH,LMEM Size Hole" "0: LMEMn is a power-of-2 capacity,1: LMEMn is not a power-of-2 with capacity of 0.75.." newline hexmask.long.byte 0x0 24.--27. 1. "LMSZ,Local Memory Size" hexmask.long.byte 0x0 20.--23. 1. "WY,Level 1 Cache Ways" newline bitfld.long 0x0 17.--19. "DPW,Data Path Width" "?,?,2: LMEMn is 32-bits wide,3: LMEMn is 64-bits wide,?,?,?,?" bitfld.long 0x0 13.--15. "MT,Memory Type" "0: ITCM,1: DTCM,2: ICACHE,3: DCACHE,?,?,?,?" line.long 0x4 "LMEM_DESC_1,Local Memory Descriptor 1" bitfld.long 0x4 31. "LMV,Local Memory Valid" "0: LMEMn not present,1: LMEMn present" bitfld.long 0x4 28. "LMSZH,LMEM Size Hole" "0: LMEMn is a power-of-2 capacity,1: LMEMn is not a power-of-2 with capacity of 0.75.." newline hexmask.long.byte 0x4 24.--27. 1. "LMSZ,Local Memory Size" hexmask.long.byte 0x4 20.--23. 1. "WY,Level 1 Cache Ways" newline bitfld.long 0x4 17.--19. "DPW,Data Path Width" "?,?,2: LMEMn is 32-bits wide,3: LMEMn is 64-bits wide,?,?,?,?" bitfld.long 0x4 13.--15. "MT,Memory Type" "0: ITCM,1: DTCM,2: ICACHE,3: DCACHE,?,?,?,?" line.long 0x8 "LMEM_DESC_2,Local Memory Descriptor 2" bitfld.long 0x8 31. "LMV,Local Memory Valid" "0: LMEMn not present,1: LMEMn present" bitfld.long 0x8 28. "LMSZH,LMEM Size Hole" "0: LMEMn is a power-of-2 capacity,1: LMEMn is not a power-of-2 with capacity of 0.75.." newline hexmask.long.byte 0x8 24.--27. 1. "LMSZ,Local Memory Size" hexmask.long.byte 0x8 20.--23. 1. "WY,Level 1 Cache Ways" newline bitfld.long 0x8 17.--19. "DPW,Data Path Width" "?,?,2: LMEMn is 32-bits wide,3: LMEMn is 64-bits wide,?,?,?,?" bitfld.long 0x8 13.--15. "MT,Memory Type" "0: ITCM,1: DTCM,2: ICACHE,3: DCACHE,?,?,?,?" line.long 0xC "LMEM_DESC_3,Local Memory Descriptor 3" bitfld.long 0xC 31. "LMV,Local Memory Valid" "0: LMEMn not present,1: LMEMn present" bitfld.long 0xC 28. "LMSZH,LMEM Size Hole" "0: LMEMn is a power-of-2 capacity,1: LMEMn is not a power-of-2 with capacity of 0.75.." newline hexmask.long.byte 0xC 24.--27. 1. "LMSZ,Local Memory Size" hexmask.long.byte 0xC 20.--23. 1. "WY,Level 1 Cache Ways" newline bitfld.long 0xC 17.--19. "DPW,Data Path Width" "?,?,2: LMEMn is 32-bits wide,3: LMEMn is 64-bits wide,?,?,?,?" bitfld.long 0xC 13.--15. "MT,Memory Type" "0: ITCM,1: DTCM,2: ICACHE,3: DCACHE,?,?,?,?" line.long 0x10 "LMEM_DESC_4,Local Memory Descriptor 4" bitfld.long 0x10 31. "LMV,Local Memory Valid" "0: LMEMn not present,1: LMEMn present" bitfld.long 0x10 28. "LMSZH,LMEM Size Hole" "0: LMEMn is a power-of-2 capacity,1: LMEMn is not a power-of-2 with capacity of 0.75.." newline hexmask.long.byte 0x10 24.--27. 1. "LMSZ,Local Memory Size" hexmask.long.byte 0x10 20.--23. 1. "WY,Level 1 Cache Ways" newline bitfld.long 0x10 17.--19. "DPW,Data Path Width" "?,?,2: LMEMn is 32-bits wide,3: LMEMn is 64-bits wide,?,?,?,?" bitfld.long 0x10 13.--15. "MT,Memory Type" "0: ITCM,1: DTCM,2: ICACHE,3: DCACHE,?,?,?,?" tree.end tree "MCM_3_CM7" base ad:0xE0080000 rgroup.word 0x0++0x3 line.word 0x0 "PLREV,SoC-defined Platform Revision" hexmask.word 0x0 0.--15. 1. "PLREV,The PLREV[15:0] field is specified by a platform input signal to define a software-visible revision number." line.word 0x2 "PCT,Processor Core Type" hexmask.word 0x2 0.--15. 1. "PCT,This MCM design supports the Arm Cortex M7 core. The following value identifies this core complex." group.long 0xC++0x7 line.long 0x0 "CPCR,Core Platform Control" bitfld.long 0x0 27. "CM7_AHBSPRI,AHB Slave Priority" "0: Uses a round-robin arbitration scheme,1: AHB-slave access has priority over a core access" line.long 0x4 "ISCR,Interrupt Status and Control" bitfld.long 0x4 31. "FIDCE,FPU Input Denormal Interrupt Enable" "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x4 28. "FIXCE,FPU Inexact Interrupt Enable" "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x4 27. "FUFCE,FPU Underflow Interrupt Enable" "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x4 26. "FOFCE,FPU Overflow Interrupt Enable" "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x4 25. "FDZCE,FPU Divide-by-Zero Interrupt Enable" "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x4 24. "FIOCE,FPU Invalid Operation Interrupt Enable" "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x4 21. "WABE,TCM Write Abort Interrupt Enable" "0: Disable interrupt,1: Enable Interrupt" rbitfld.long 0x4 15. "FIDC,FPU Input Denormal Interrupt Status" "0: No interrupt,1: Interrupt occurred" newline rbitfld.long 0x4 12. "FIXC,FPU Inexact Interrupt Status" "0: No interrupt,1: Interrupt occurred" rbitfld.long 0x4 11. "FUFC,FPU Underflow Interrupt Status" "0: No interrupt,1: Interrupt occurred" newline rbitfld.long 0x4 10. "FOFC,FPU Overflow Interrupt Status" "0: No interrupt,1: Interrupt occurred" rbitfld.long 0x4 9. "FDZC,FPU Divide-by-Zero Interrupt Status" "0: No interrupt,1: Interrupt occurred" newline rbitfld.long 0x4 8. "FIOC,FPU Invalid Operation Interrupt Status" "0: No interrupt,1: Interrupt occurred" rbitfld.long 0x4 6. "WABSO,Write Abort on Slave Overrun" "0: No write abort overrun,1: Write abort overrun occurred" newline eventfld.long 0x4 5. "WABS,Write Abort on Slave" "0: No write abort occurred on AHBS interface,1: Write abort occurred on AHBS interface" rgroup.long 0x400++0x13 line.long 0x0 "LMEM_DESC_0,Local Memory Descriptor 0" bitfld.long 0x0 31. "LMV,Local Memory Valid" "0: LMEMn not present,1: LMEMn present" bitfld.long 0x0 28. "LMSZH,LMEM Size Hole" "0: LMEMn is a power-of-2 capacity,1: LMEMn is not a power-of-2 with capacity of 0.75.." newline hexmask.long.byte 0x0 24.--27. 1. "LMSZ,Local Memory Size" hexmask.long.byte 0x0 20.--23. 1. "WY,Level 1 Cache Ways" newline bitfld.long 0x0 17.--19. "DPW,Data Path Width" "?,?,2: LMEMn is 32-bits wide,3: LMEMn is 64-bits wide,?,?,?,?" bitfld.long 0x0 13.--15. "MT,Memory Type" "0: ITCM,1: DTCM,2: ICACHE,3: DCACHE,?,?,?,?" line.long 0x4 "LMEM_DESC_1,Local Memory Descriptor 1" bitfld.long 0x4 31. "LMV,Local Memory Valid" "0: LMEMn not present,1: LMEMn present" bitfld.long 0x4 28. "LMSZH,LMEM Size Hole" "0: LMEMn is a power-of-2 capacity,1: LMEMn is not a power-of-2 with capacity of 0.75.." newline hexmask.long.byte 0x4 24.--27. 1. "LMSZ,Local Memory Size" hexmask.long.byte 0x4 20.--23. 1. "WY,Level 1 Cache Ways" newline bitfld.long 0x4 17.--19. "DPW,Data Path Width" "?,?,2: LMEMn is 32-bits wide,3: LMEMn is 64-bits wide,?,?,?,?" bitfld.long 0x4 13.--15. "MT,Memory Type" "0: ITCM,1: DTCM,2: ICACHE,3: DCACHE,?,?,?,?" line.long 0x8 "LMEM_DESC_2,Local Memory Descriptor 2" bitfld.long 0x8 31. "LMV,Local Memory Valid" "0: LMEMn not present,1: LMEMn present" bitfld.long 0x8 28. "LMSZH,LMEM Size Hole" "0: LMEMn is a power-of-2 capacity,1: LMEMn is not a power-of-2 with capacity of 0.75.." newline hexmask.long.byte 0x8 24.--27. 1. "LMSZ,Local Memory Size" hexmask.long.byte 0x8 20.--23. 1. "WY,Level 1 Cache Ways" newline bitfld.long 0x8 17.--19. "DPW,Data Path Width" "?,?,2: LMEMn is 32-bits wide,3: LMEMn is 64-bits wide,?,?,?,?" bitfld.long 0x8 13.--15. "MT,Memory Type" "0: ITCM,1: DTCM,2: ICACHE,3: DCACHE,?,?,?,?" line.long 0xC "LMEM_DESC_3,Local Memory Descriptor 3" bitfld.long 0xC 31. "LMV,Local Memory Valid" "0: LMEMn not present,1: LMEMn present" bitfld.long 0xC 28. "LMSZH,LMEM Size Hole" "0: LMEMn is a power-of-2 capacity,1: LMEMn is not a power-of-2 with capacity of 0.75.." newline hexmask.long.byte 0xC 24.--27. 1. "LMSZ,Local Memory Size" hexmask.long.byte 0xC 20.--23. 1. "WY,Level 1 Cache Ways" newline bitfld.long 0xC 17.--19. "DPW,Data Path Width" "?,?,2: LMEMn is 32-bits wide,3: LMEMn is 64-bits wide,?,?,?,?" bitfld.long 0xC 13.--15. "MT,Memory Type" "0: ITCM,1: DTCM,2: ICACHE,3: DCACHE,?,?,?,?" line.long 0x10 "LMEM_DESC_4,Local Memory Descriptor 4" bitfld.long 0x10 31. "LMV,Local Memory Valid" "0: LMEMn not present,1: LMEMn present" bitfld.long 0x10 28. "LMSZH,LMEM Size Hole" "0: LMEMn is a power-of-2 capacity,1: LMEMn is not a power-of-2 with capacity of 0.75.." newline hexmask.long.byte 0x10 24.--27. 1. "LMSZ,Local Memory Size" hexmask.long.byte 0x10 20.--23. 1. "WY,Level 1 Cache Ways" newline bitfld.long 0x10 17.--19. "DPW,Data Path Width" "?,?,2: LMEMn is 32-bits wide,3: LMEMn is 64-bits wide,?,?,?,?" bitfld.long 0x10 13.--15. "MT,Memory Type" "0: ITCM,1: DTCM,2: ICACHE,3: DCACHE,?,?,?,?" tree.end tree.end tree "MDM_AP (Miscellaneous Debug Module Access Port)" base edp:0x600 rgroup.long 0x0++0x3 line.long 0x0 "MDMAPSTTS,Status" bitfld.long 0x0 31. "CM72DBGRSTRD,Cortex-M7_2 Debug Restarted" "0: In Debug mode,1: In Normal mode" bitfld.long 0x0 29. "CM71DBGRSTRD,Cortex-M7_1 Debug Restarted" "0: In Debug mode,1: In Normal mode" newline bitfld.long 0x0 28. "CM70DBGRSTRD,Cortex-M7_0 Debug Restarted" "0: In Debug mode,1: In Normal mode" bitfld.long 0x0 27. "CM73DBGRSTRD,Cortex-M7_3 Debug Restarted" "0: In Debug mode,1: In Normal mode" newline bitfld.long 0x0 26. "CM73SLPNG,CM7_3 Sleeping" "0: Not in Sleep mode,1: In Sleep mode" bitfld.long 0x0 25. "CM73DPSLP,Cortex-M7_3 Deep Sleep" "0: Not in Deep Sleep mode,1: In Deep Sleep mode" newline bitfld.long 0x0 24. "CM73HLT,CM7_3 Debug Halted" "0: Core is not halted,1: Core is halted" bitfld.long 0x0 23. "CM0PSLPNG,Cortex-M0+ Sleeping" "0: Not in Sleep mode,1: In Sleep mode" newline bitfld.long 0x0 22. "CM72SLPNG,CM7_2 Sleeping" "0: Not in Sleep mode,1: In Sleep mode" bitfld.long 0x0 21. "CM71SLPNG,CM7_1 Sleeping" "0: Not in Sleep mode,1: In Sleep mode" newline bitfld.long 0x0 20. "CM70SLPNG,Cortex-M7_0 Sleeping" "0: Not in Sleep mode,1: In Sleep mode" bitfld.long 0x0 19. "CM0PDPSLP,Cortex-M0+ Deep Sleep" "0: Not in Deep Sleep mode,1: In Deep Sleep mode" newline bitfld.long 0x0 18. "CM72DPSLP,Cortex-M7_2 Deep Sleep" "0: Not in Deep Sleep mode,1: In Deep Sleep mode" bitfld.long 0x0 17. "CM71DPSLP,Cortex-M7_1 Deep Sleep" "0: Not in Deep Sleep mode,1: In Deep Sleep mode" newline bitfld.long 0x0 16. "CM70DPSLP,Cortex-M7_0 Deep Sleep" "0: Not in Deep Sleep mode,1: In Deep Sleep mode" bitfld.long 0x0 15. "HSEHLT,Cortex-M0+ Halted" "0: Core is not halted,1: Core is halted" newline bitfld.long 0x0 14. "CM72HLT,CM7_2 Debug Halted" "0: Core is not halted,1: Core is halted" bitfld.long 0x0 13. "CM71HLT,CM7_1 Debug Halted" "0: Core is not halted,1: Core is halted" newline bitfld.long 0x0 12. "CM70HLT,Cortex-M7_0 Halted" "0: Core is not halted,1: Core is halted" bitfld.long 0x0 2. "FUNCRST,Functional Reset" "0: Not in functional reset,1: In functional reset" newline bitfld.long 0x0 1. "DESTRST,Destructive Reset" "0: Not in destructive reset,1: In destructive reset" group.long 0x4++0x3 line.long 0x0 "MDMAPCTL,Control" bitfld.long 0x0 31. "CM72DBGRSRT,Cortex-M7_2 Debug Restart" "0: Normal operation,1: Request asserted" bitfld.long 0x0 29. "CM71DBGRSRT,Cortex-M7_1 Debug Restart" "0: Normal operation,1: Request asserted" newline bitfld.long 0x0 28. "CM70DBGRSRT,Cortex-M7_0 Debug Restart" "0: Normal operation,1: Request asserted" bitfld.long 0x0 27. "CM73DBGRSRT,Cortex-M7_3 Debug Restart" "0: Normal operation,1: Request asserted" newline bitfld.long 0x0 22. "SWOOVRD,SWO Override" "0: Not overridden and SWO generates the trace..,1: Is overridden" bitfld.long 0x0 21. "CM7_3_CORE_ACCESS,Debugger Access To Application Cortex-M7_3" "0: Supported,1: Not supported" newline bitfld.long 0x0 20. "TRIUOVRD,TPIU Override" "0: Not overridden and TPIU generates the trace..,1: Is overridden and asserted" bitfld.long 0x0 19. "CM7_2_CHK,Cortex-M7_2 Check" "0: Supported,1: Not supported" newline bitfld.long 0x0 18. "CM7_2_CORE_ACCESS,Debugger Access To Application Cortex-M7_2" "0: Supported,1: Not supported" bitfld.long 0x0 17. "CM7_1_CORE_ACCESS,Debugger Access To Application Cortex-M7_1" "0: Supported,1: Not supported" newline bitfld.long 0x0 16. "CM7_0_CORE_ACCESS,Debugger Access To Application Cortex-M7_0" "0: Supported,1: Not supported" bitfld.long 0x0 15. "POR_WDG_DIS_FUNC_RST,Power Watchdog Status" "0: Power watchdog is disabled,1: Power watchdog is enabled" newline bitfld.long 0x0 14. "CM73DBGREQ,Cortex-M7_3 Debug Request" "0: Debug request is not generated,1: Debug request is generated" bitfld.long 0x0 13. "DBGRSTFASTPAD,Debug Over Reset Via Fast Pads" "0: Disabled,1: Enabled" newline bitfld.long 0x0 12. "DBGRSTSLOWPAD,Debug Over Reset Via Slow Pads" "0: Disabled,1: Enabled" bitfld.long 0x0 10. "CM72DBGREQ,Cortex-M7_2 Debug Request" "0: Debug request is not generated,1: Debug request is generated" newline bitfld.long 0x0 9. "CM71DBGREQ,Cortex-M7_1 Debug Request" "0: Debug request is not generated,1: Debug request is generated" bitfld.long 0x0 8. "CM70DBGREQ,Cortex-M7_0 Debug Request" "0: Debug request is not generated,1: Debug request is generated" newline bitfld.long 0x0 5. "SYSFUNCRST,System Functional Reset" "0: Deasserted,1: Asserted" bitfld.long 0x0 4. "SYSRESETREQ,System Destructive Reset" "0: Deasserted,1: Asserted" group.long 0x30++0x3 line.long 0x0 "MDMAPWIREN,WIR Enable" bitfld.long 0x0 1. "PRVNTRSTEN,Prevent Reset Enable" "0: Automatic low power entry enabled,1: Low power entry enabled controlled by bit field.." bitfld.long 0x0 0. "LWPWREN,Low Power Debug Enable" "0: Disabled,1: Enabled" group.long 0x38++0x3 line.long 0x0 "MDMAPWIRREL,MDM AP WIR Release" bitfld.long 0x0 1. "PRVNTRSTRGM,Prevent Reset" "0: Normal operation,1: MC_RGM prevented" bitfld.long 0x0 0. "WTRSTRGM,Wait In Reset B" "0: Normal operation,1: Wait supported" tree.end tree "MSCM (Miscellaneous System Control Module)" base ad:0x40260000 rgroup.long 0x0++0x1B line.long 0x0 "CPXTYPE,Processor X Type" hexmask.long 0x0 0.--31. 1. "PERSONALITY,Personality of CPx" line.long 0x4 "CPXNUM,Processor X Number" bitfld.long 0x4 0.--2. "CPN,Processor Number" "0: Cortex-M7 core 0,1: Cortex-M7 core 1,2: Cortex-M7 core 2,3: Cortex-M7 core 3,?,?,?,?" line.long 0x8 "CPXREV,Processor X Revision" hexmask.long.byte 0x8 0.--7. 1. "RYPZ,Processor Revision" line.long 0xC "CPXCFG0,Processor X Configuration 0" hexmask.long.byte 0xC 24.--31. 1. "ICSZ,Level 1 Instruction Cache Size" newline hexmask.long.byte 0xC 16.--23. 1. "ICWY,L1 Instruction Cache Ways" newline hexmask.long.byte 0xC 8.--15. 1. "DCSZ,L1 Data Cache Size" newline hexmask.long.byte 0xC 0.--7. 1. "DCWY,L1 Data Cache Ways" line.long 0x10 "CPXCFG1,Processor X Configuration 1" hexmask.long.byte 0x10 24.--31. 1. "L2SZ,L2 Cache Size" newline hexmask.long.byte 0x10 16.--23. 1. "L2WY,L2 Cache Ways" line.long 0x14 "CPXCFG2,Processor X Configuration 2" hexmask.long.byte 0x14 24.--31. 1. "DTCMSZ,Tightly Coupled Data Memory Size" newline hexmask.long.byte 0x14 16.--23. 1. "ITCMSZ,Instruction Tightly Coupled Memory Size" line.long 0x18 "CPXCFG3,Processor x Configuration 3" bitfld.long 0x18 4. "CPY,Cryptography" "0: Not supported,1: Supported" newline bitfld.long 0x18 3. "CMP,Core Memory Protection Unit" "0: Not included,1: Included" newline bitfld.long 0x18 2. "MMU,Memory Management Unit" "0: Not supported,1: Supported" newline bitfld.long 0x18 1. "SIMD,SIMD/NEON Instruction Support" "0: Not included,1: Included" newline bitfld.long 0x18 0. "FPU,Floating Point Unit" "0: Not provided,1: Provided" rgroup.long 0x20++0x1B line.long 0x0 "CP0TYPE,Processor 0 Type" hexmask.long 0x0 0.--31. 1. "PERSONALITY,Processor Personality" line.long 0x4 "CP0NUM,Processor 0 Number" bitfld.long 0x4 0.--1. "CPN,Processor Number" "0,1,2,3" line.long 0x8 "CP0REV,Processor 0 Count" hexmask.long.byte 0x8 0.--7. 1. "RYPZ,Processor Revision" line.long 0xC "CP0CFG0,Processor 0 Configuration 0" hexmask.long.byte 0xC 24.--31. 1. "ICSZ,Level 1 Instruction Cache Size" newline hexmask.long.byte 0xC 16.--23. 1. "ICWY,L1 Instruction Cache Ways" newline hexmask.long.byte 0xC 8.--15. 1. "DCSZ,L1 Data Cache Size" newline hexmask.long.byte 0xC 0.--7. 1. "DCWY,L1 Data Cache Ways" line.long 0x10 "CP0CFG1,Processor 0 Configuration 1" hexmask.long.byte 0x10 24.--31. 1. "L2SZ,L2 Cache Size" newline hexmask.long.byte 0x10 16.--23. 1. "L2WY,L2 Cache Ways" line.long 0x14 "CP0CFG2,Processor 0 Configuration 2" hexmask.long.byte 0x14 24.--31. 1. "DTCMSZ,Tightly Coupled Data Memory Size" newline hexmask.long.byte 0x14 16.--23. 1. "ITCMSZ,Instruction Tightly Coupled Memory Size" line.long 0x18 "CP0CFG3,Processor 0 Configuration 3" bitfld.long 0x18 4. "CPY,Cryptography" "0: Not supported,1: Supported" newline bitfld.long 0x18 3. "CMP,Core Memory Protection Unit" "0: Not included,1: Included" newline bitfld.long 0x18 2. "MMU,Memory Management Unit" "0: Not supported,1: Supported" newline bitfld.long 0x18 1. "SIMD,SIMD/NEON Instruction Support" "0: Not included,1: Included" newline bitfld.long 0x18 0. "FPU,Floating Point Unit" "0: Not provided,1: Provided" rgroup.long 0x40++0x1B line.long 0x0 "CP1TYPE,Processor 1 Type" hexmask.long 0x0 0.--31. 1. "PERSONALITY,Personality Processor" line.long 0x4 "CP1NUM,Processor 1 Number" bitfld.long 0x4 0.--1. "CPN,Processor Number" "0,1,2,3" line.long 0x8 "CP1REV,Processor 1 Count" hexmask.long.byte 0x8 0.--7. 1. "RYPZ,Processor Revision" line.long 0xC "CP1CFG0,Processor 1 Configuration 0" hexmask.long.byte 0xC 24.--31. 1. "ICSZ,Level 1 Instruction Cache Size" newline hexmask.long.byte 0xC 16.--23. 1. "ICWY,Level 1 Instruction Cache Ways" newline hexmask.long.byte 0xC 8.--15. 1. "DCSZ,L1 Data Cache Size" newline hexmask.long.byte 0xC 0.--7. 1. "DCWY,L1 Data Cache Ways" line.long 0x10 "CP1CFG1,Processor 1 Configuration 1" hexmask.long.byte 0x10 24.--31. 1. "L2SZ,L2 Cache Size" newline hexmask.long.byte 0x10 16.--23. 1. "L2WY,L2 Cache Ways" line.long 0x14 "CP1CFG2,Processor 1 Configuration 2" hexmask.long.byte 0x14 24.--31. 1. "DTCMSZ,Tightly Coupled Data Memory Size" newline hexmask.long.byte 0x14 16.--23. 1. "ITCMSZ,Instruction Tightly Coupled Memory Size" line.long 0x18 "CP1CFG3,Processor 1 Configuration 3" bitfld.long 0x18 4. "CPY,Cryptography" "0: Not supported,1: Supported" newline bitfld.long 0x18 3. "CMP,Core Memory Protection Unit" "0: Not included,1: Included" newline bitfld.long 0x18 2. "MMU,Memory Management Unit" "0: Not supported,1: Supported" newline bitfld.long 0x18 1. "SIMD,SIMD/NEON Instruction Support" "0: Not included,1: Included" newline bitfld.long 0x18 0. "FPU,Floating Point Unit" "0: Not included,1: Included" rgroup.long 0x60++0x1B line.long 0x0 "CP2TYPE,Processor 2 Type" hexmask.long 0x0 0.--31. 1. "PERSONALITY,Processor Personality" line.long 0x4 "CP2NUM,Processor 2 Number" bitfld.long 0x4 0.--1. "CPN,Processor Number" "0,1,2,3" line.long 0x8 "CP2REV,Processor 2 Count" hexmask.long.byte 0x8 0.--7. 1. "RYPZ,Processor Revision" line.long 0xC "CP2CFG0,Processor 2 Configuration 0" hexmask.long.byte 0xC 24.--31. 1. "ICSZ,Level 1 Instruction Cache Size" newline hexmask.long.byte 0xC 16.--23. 1. "ICWY,Level 1 Instruction Cache Ways" newline hexmask.long.byte 0xC 8.--15. 1. "DCSZ,L1 Data Cache Size" newline hexmask.long.byte 0xC 0.--7. 1. "DCWY,L1 Data Cache Ways" line.long 0x10 "CP2CFG1,Processor 2 Configuration 1" hexmask.long.byte 0x10 24.--31. 1. "L2SZ,L2 Cache Size" newline hexmask.long.byte 0x10 16.--23. 1. "L2WY,L2 Cache Ways" line.long 0x14 "CP2CFG2,Processor 2 Configuration 2" hexmask.long.byte 0x14 24.--31. 1. "DTCMSZ,Tightly Coupled Data Memory Size" newline hexmask.long.byte 0x14 16.--23. 1. "ITCMSZ,Instruction Tightly Coupled Memory Size" line.long 0x18 "CP2CFG3,Processor 2 Configuration 3" bitfld.long 0x18 4. "CPY,Cryptography" "0: Not supported,1: Supported" newline bitfld.long 0x18 3. "CMP,Core Memory Protection Unit" "0: Not included,1: Included" newline bitfld.long 0x18 2. "MMU,Memory Management Unit" "0: Not supported,1: Supported" newline bitfld.long 0x18 1. "SIMD,SIMD/NEON Instruction Support" "0: Not included,1: Included" newline bitfld.long 0x18 0. "FPU,Floating Point Unit" "0: Not included,1: Included" rgroup.long 0x80++0x1B line.long 0x0 "CP3TYPE,Processor 3 Type" hexmask.long 0x0 0.--31. 1. "PERSONALITY,Processor Personality" line.long 0x4 "CP3NUM,Processor 3 Number" bitfld.long 0x4 0.--1. "CPN,Processor Number" "0,1,2,3" line.long 0x8 "CP3REV,Processor 3 Count" hexmask.long.byte 0x8 0.--7. 1. "RYPZ,Processor Revision" line.long 0xC "CP3CFG0,Processor 3 Configuration 0" hexmask.long.byte 0xC 24.--31. 1. "ICSZ,Level 1 Instruction Cache Size" newline hexmask.long.byte 0xC 16.--23. 1. "ICWY,Level 1 Instruction Cache Ways" newline hexmask.long.byte 0xC 8.--15. 1. "DCSZ,L1 Data Cache Size" newline hexmask.long.byte 0xC 0.--7. 1. "DCWY,L1 Data Cache Ways" line.long 0x10 "CP3CFG1,Processor 3 Configuration 1" hexmask.long.byte 0x10 24.--31. 1. "L2SZ,L2 Cache Size" newline hexmask.long.byte 0x10 16.--23. 1. "L2WY,L2 Cache Ways" line.long 0x14 "CP3CFG2,Processor 3 Configuration 2" hexmask.long.byte 0x14 24.--31. 1. "DTCMSZ,Tightly Coupled Data Memory Size" newline hexmask.long.byte 0x14 16.--23. 1. "ITCMSZ,Instruction Tightly Coupled Memory Size" line.long 0x18 "CP3CFG3,Processor 3 Configuration 3" bitfld.long 0x18 4. "CPY,Cryptography" "0: Not supported,1: Supported" newline bitfld.long 0x18 3. "CMP,Core Memory Protection Unit" "0: Not included,1: Included" newline bitfld.long 0x18 2. "MMU,Memory Management Unit" "0: Not supported,1: Supported" newline bitfld.long 0x18 1. "SIMD,SIMD/NEON Instruction Support" "0: Not included,1: Included" newline bitfld.long 0x18 0. "FPU,Floating Point Unit" "0: Not included,1: Included" group.long 0x200++0x7F line.long 0x0 "IRCP0ISR0,Interrupt Router CP0 Interrupt Status" eventfld.long 0x0 3. "CP3_INT,CP3-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted" newline eventfld.long 0x0 2. "CP2_INT,CP2-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted" newline eventfld.long 0x0 1. "CP1_INT,CP1-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: to-CPn Interrupt" newline eventfld.long 0x0 0. "CP0_INT,CP0-to-CPn Interrupt" "0: to-CPn Interrupt,1: Interrupt to CPn asserted" line.long 0x4 "IRCP0IGR0,Interrupt Router CP0 Interrupt Generation" bitfld.long 0x4 0. "INT_EN,Interrupt Enable" "0,1" line.long 0x8 "IRCP0ISR1,Interrupt Router CP0 Interrupt Status" eventfld.long 0x8 3. "CP3_INT,CP3-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted" newline eventfld.long 0x8 2. "CP2_INT,CP2-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted" newline eventfld.long 0x8 1. "CP1_INT,CP1-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: to-CPn Interrupt" newline eventfld.long 0x8 0. "CP0_INT,CP0-to-CPn Interrupt" "0: to-CPn Interrupt,1: Interrupt to CPn asserted" line.long 0xC "IRCP0IGR1,Interrupt Router CP0 Interrupt Generation" bitfld.long 0xC 0. "INT_EN,Interrupt Enable" "0,1" line.long 0x10 "IRCP0ISR2,Interrupt Router CP0 Interrupt Status" eventfld.long 0x10 3. "CP3_INT,CP3-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted" newline eventfld.long 0x10 2. "CP2_INT,CP2-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted" newline eventfld.long 0x10 1. "CP1_INT,CP1-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: to-CPn Interrupt" newline eventfld.long 0x10 0. "CP0_INT,CP0-to-CPn Interrupt" "0: to-CPn Interrupt,1: Interrupt to CPn asserted" line.long 0x14 "IRCP0IGR2,Interrupt Router CP0 Interrupt Generation" bitfld.long 0x14 0. "INT_EN,Interrupt Enable" "0,1" line.long 0x18 "IRCP0ISR3,Interrupt Router CP0 Interrupt Status" eventfld.long 0x18 3. "CP3_INT,CP3-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted" newline eventfld.long 0x18 2. "CP2_INT,CP2-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted" newline eventfld.long 0x18 1. "CP1_INT,CP1-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: to-CPn Interrupt" newline eventfld.long 0x18 0. "CP0_INT,CP0-to-CPn Interrupt" "0: to-CPn Interrupt,1: Interrupt to CPn asserted" line.long 0x1C "IRCP0IGR3,Interrupt Router CP0 Interrupt Generation" bitfld.long 0x1C 0. "INT_EN,Interrupt Enable" "0,1" line.long 0x20 "IRCP1ISR0,Interrupt Router CP1 Interrupt Status" eventfld.long 0x20 3. "CP3_INT,CP3-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted" newline eventfld.long 0x20 2. "CP2_INT,CP2-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted" newline eventfld.long 0x20 1. "CP1_INT,CP1-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: to-CPn Interrupt" newline eventfld.long 0x20 0. "CP0_INT,CP0-to-CPn Interrupt" "0: to-CPn Interrupt,1: Interrupt to CPn asserted" line.long 0x24 "IRCP1IGR0,Interrupt Router CP1 Interrupt Generation" bitfld.long 0x24 0. "INT_EN,Interrupt Enable" "0,1" line.long 0x28 "IRCP1ISR1,Interrupt Router CP1 Interrupt Status" eventfld.long 0x28 3. "CP3_INT,CP3-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted" newline eventfld.long 0x28 2. "CP2_INT,CP2-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted" newline eventfld.long 0x28 1. "CP1_INT,CP1-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: to-CPn Interrupt" newline eventfld.long 0x28 0. "CP0_INT,CP0-to-CPn Interrupt" "0: to-CPn Interrupt,1: Interrupt to CPn asserted" line.long 0x2C "IRCP1IGR1,Interrupt Router CP1 Interrupt Generation" bitfld.long 0x2C 0. "INT_EN,Interrupt Enable" "0,1" line.long 0x30 "IRCP1ISR2,Interrupt Router CP1 Interrupt Status" eventfld.long 0x30 3. "CP3_INT,CP3-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted" newline eventfld.long 0x30 2. "CP2_INT,CP2-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted" newline eventfld.long 0x30 1. "CP1_INT,CP1-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: to-CPn Interrupt" newline eventfld.long 0x30 0. "CP0_INT,CP0-to-CPn Interrupt" "0: to-CPn Interrupt,1: Interrupt to CPn asserted" line.long 0x34 "IRCP1IGR2,Interrupt Router CP1 Interrupt Generation" bitfld.long 0x34 0. "INT_EN,Interrupt Enable" "0,1" line.long 0x38 "IRCP1ISR3,Interrupt Router CP1 Interrupt Status" eventfld.long 0x38 3. "CP3_INT,CP3-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted" newline eventfld.long 0x38 2. "CP2_INT,CP2-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted" newline eventfld.long 0x38 1. "CP1_INT,CP1-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: to-CPn Interrupt" newline eventfld.long 0x38 0. "CP0_INT,CP0-to-CPn Interrupt" "0: to-CPn Interrupt,1: Interrupt to CPn asserted" line.long 0x3C "IRCP1IGR3,Interrupt Router CP1 Interrupt Generation" bitfld.long 0x3C 0. "INT_EN,Interrupt Enable" "0,1" line.long 0x40 "IRCP2ISR0,Interrupt Router CP2 Interrupt Status" eventfld.long 0x40 3. "CP3_INT,CP3-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted" newline eventfld.long 0x40 2. "CP2_INT,CP2-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted" newline eventfld.long 0x40 1. "CP1_INT,CP1-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: to-CPn Interrupt" newline eventfld.long 0x40 0. "CP0_INT,CP0-to-CPn Interrupt" "0: to-CPn Interrupt,1: Interrupt to CPn asserted" line.long 0x44 "IRCP2IGR0,Interrupt Router CP2 Interrupt Generation" bitfld.long 0x44 0. "INT_EN,Interrupt Enable" "0,1" line.long 0x48 "IRCP2ISR1,Interrupt Router CP2 Interrupt Status" eventfld.long 0x48 3. "CP3_INT,CP3-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted" newline eventfld.long 0x48 2. "CP2_INT,CP2-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted" newline eventfld.long 0x48 1. "CP1_INT,CP1-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: to-CPn Interrupt" newline eventfld.long 0x48 0. "CP0_INT,CP0-to-CPn Interrupt" "0: to-CPn Interrupt,1: Interrupt to CPn asserted" line.long 0x4C "IRCP2IGR1,Interrupt Router CP2 Interrupt Generation" bitfld.long 0x4C 0. "INT_EN,Interrupt Enable" "0,1" line.long 0x50 "IRCP2ISR2,Interrupt Router CP2 Interrupt Status" eventfld.long 0x50 3. "CP3_INT,CP3-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted" newline eventfld.long 0x50 2. "CP2_INT,CP2-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted" newline eventfld.long 0x50 1. "CP1_INT,CP1-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: to-CPn Interrupt" newline eventfld.long 0x50 0. "CP0_INT,CP0-to-CPn Interrupt" "0: to-CPn Interrupt,1: Interrupt to CPn asserted" line.long 0x54 "IRCP2IGR2,Interrupt Router CP2 Interrupt Generation" bitfld.long 0x54 0. "INT_EN,Interrupt Enable" "0,1" line.long 0x58 "IRCP2ISR3,Interrupt Router CP2 Interrupt Status" eventfld.long 0x58 3. "CP3_INT,CP3-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted" newline eventfld.long 0x58 2. "CP2_INT,CP2-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted" newline eventfld.long 0x58 1. "CP1_INT,CP1-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: to-CPn Interrupt" newline eventfld.long 0x58 0. "CP0_INT,CP0-to-CPn Interrupt" "0: to-CPn Interrupt,1: Interrupt to CPn asserted" line.long 0x5C "IRCP2IGR3,Interrupt Router CP2 Interrupt Generation" bitfld.long 0x5C 0. "INT_EN,Interrupt Enable" "0,1" line.long 0x60 "IRCP3ISR0,Interrupt Router CP3 Interrupt Status" eventfld.long 0x60 3. "CP3_INT,CP3-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted" newline eventfld.long 0x60 2. "CP2_INT,CP2-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted" newline eventfld.long 0x60 1. "CP1_INT,CP1-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: to-CPn Interrupt" newline eventfld.long 0x60 0. "CP0_INT,CP0-to-CPn Interrupt" "0: to-CPn Interrupt,1: Interrupt to CPn asserted" line.long 0x64 "IRCP3IGR0,Interrupt Router CP3 Interrupt Generation" bitfld.long 0x64 0. "INT_EN,Interrupt Enable" "0,1" line.long 0x68 "IRCP3ISR1,Interrupt Router CP3 Interrupt Status" eventfld.long 0x68 3. "CP3_INT,CP3-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted" newline eventfld.long 0x68 2. "CP2_INT,CP2-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted" newline eventfld.long 0x68 1. "CP1_INT,CP1-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: to-CPn Interrupt" newline eventfld.long 0x68 0. "CP0_INT,CP0-to-CPn Interrupt" "0: to-CPn Interrupt,1: Interrupt to CPn asserted" line.long 0x6C "IRCP3IGR1,Interrupt Router CP3 Interrupt Generation" bitfld.long 0x6C 0. "INT_EN,Interrupt Enable" "0,1" line.long 0x70 "IRCP3ISR2,Interrupt Router CP3 Interrupt Status" eventfld.long 0x70 3. "CP3_INT,CP3-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted" newline eventfld.long 0x70 2. "CP2_INT,CP2-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted" newline eventfld.long 0x70 1. "CP1_INT,CP1-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: to-CPn Interrupt" newline eventfld.long 0x70 0. "CP0_INT,CP0-to-CPn Interrupt" "0: to-CPn Interrupt,1: Interrupt to CPn asserted" line.long 0x74 "IRCP3IGR2,Interrupt Router CP3 Interrupt Generation" bitfld.long 0x74 0. "INT_EN,Interrupt Enable" "0,1" line.long 0x78 "IRCP3ISR3,Interrupt Router CP3 Interrupt Status" eventfld.long 0x78 3. "CP3_INT,CP3-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted" newline eventfld.long 0x78 2. "CP2_INT,CP2-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted" newline eventfld.long 0x78 1. "CP1_INT,CP1-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: to-CPn Interrupt" newline eventfld.long 0x78 0. "CP0_INT,CP0-to-CPn Interrupt" "0: to-CPn Interrupt,1: Interrupt to CPn asserted" line.long 0x7C "IRCP3IGR3,Interrupt Router CP3 Interrupt Generation" bitfld.long 0x7C 0. "INT_EN,Interrupt Enable" "0,1" group.long 0x400++0x3 line.long 0x0 "IRCPCFG,Interrupt Router Configuration" bitfld.long 0x0 31. "LOCK,Lock" "0: Register can be written by any privileged write,1: Register is locked (read-only) until the next.." newline bitfld.long 0x0 3. "CP3_TR,CP3 as Trusted Core" "0: Not trusted,1: Trusted" newline bitfld.long 0x0 2. "CP2_TR,CP2 as Trusted Core" "0: Not trusted,1: Trusted" newline bitfld.long 0x0 1. "CP1_TR,CP1 as Trusted Core" "0: Not trusted,1: Trusted" newline bitfld.long 0x0 0. "CP0_TR,CP0 as Trusted Core" "0: Not trusted,1: Trusted" group.long 0x500++0x3 line.long 0x0 "XN_CTRL,Memory Execution Control" bitfld.long 0x0 31. "HLK,Hard Lock" "0: Disabled,1: Enabled" newline bitfld.long 0x0 30. "SLK,Soft Lock" "0: Disabled,1: Enabled" newline bitfld.long 0x0 23. "CM7_3_DTCM,Transaction Control For Cortex-M7_3 DTCM" "0: Transaction enabled,1: Transaction disabled" newline bitfld.long 0x0 22. "CM7_2_DTCM,Transaction Control For Cortex-M7_2 DTCM" "0: Transaction enabled,1: Transaction disabled" newline bitfld.long 0x0 21. "CM7_1_DTCM,Transaction Control For Cortex-M7_1 DTCM" "0: Transaction enabled,1: Transaction disabled" newline bitfld.long 0x0 20. "CM7_0_DTCM,Transaction Control For Cortex-M7_0 DTCM" "0: Transaction enabled,1: Transaction disabled" newline bitfld.long 0x0 19. "CM7_3_DIS_D0_D1TCM_EXEC,Disable D0 and D1 TCM Execution For Cortex-M7_3" "0: Execution enabled,1: Execution disabled" newline bitfld.long 0x0 18. "CM7_2_DIS_D0_D1TCM_EXEC,Disable D0 and D1 TCM Execution For Cortex-M7_2" "0: Execution enabled,1: Execution disabled" newline bitfld.long 0x0 17. "CM7_1_DIS_D0_D1TCM_EXEC,D0 and D1 TCM Execution For Cortex-M7_1" "0: Execution enabled,1: Execution disabled" newline bitfld.long 0x0 16. "CM7_0_DIS_D0_D1TCM_EXEC,D0 And D1 TCM Execution For Cortex-M7_0" "0: Execution enabled,1: Execution disabled" newline bitfld.long 0x0 15. "CM7_3_ITCM,Transaction Control For Cortex-M7_3 ITCM" "0: Execution enabled,1: Execution disabled" newline bitfld.long 0x0 14. "CM7_2_ITCM,Transaction Control For Cortex-M7_2 ITCM" "0: Execution enabled,1: Execution disabled" newline bitfld.long 0x0 13. "CM7_1_ITCM,Transaction Control For Cortex-M7_1 ITCM" "0: Execution enabled,1: Execution disabled" newline bitfld.long 0x0 12. "CM7_0_ITCM,Transaction Control For Cortex-M7_0 ITCM" "0: Execution enabled,1: Execution disabled" newline bitfld.long 0x0 11. "CM7_3_DIS_ITCM_EXEC,ITCM Execution for Cortex-M7_3" "0: Execution enabled,1: Execution disabled" newline bitfld.long 0x0 10. "CM7_2_DIS_ITCM_EXEC,ITCM Execution for Cortex-M7_2" "0: Execution enabled,1: Execution disabled" newline bitfld.long 0x0 9. "CM7_1_DIS_ITCM_EXEC,ITCM Execution For Cortex-M7_1" "0: Execution enabled,1: Execution disabled" newline bitfld.long 0x0 8. "CM7_0_DIS_ITCM_EXEC,ITCM Execution For Cortex-M7_0" "0: Execution enabled,1: Execution disabled" newline bitfld.long 0x0 2. "PRAM_2,Transaction Control For PRAM 2" "0: Transaction enabled,1: Transaction disabled" newline bitfld.long 0x0 1. "PRAM_1,Transaction Control For PRAM 1" "0: Transaction enabled,1: Transaction disabled" newline bitfld.long 0x0 0. "PRAM0,Transaction Control For PRAM 0" "0: Transaction enabled,1: Transaction disabled" group.long 0x600++0x7 line.long 0x0 "ENEDC,Enable Interconnect Error Detection" bitfld.long 0x0 29. "ADD_CM7_1_TCM,Address Check For Cortex-M7_1_TCM" "0: Disabled,1: Enabled" newline bitfld.long 0x0 28. "CM7_1_TCM,Write Data Check For Cortex-M7_1_TCM" "0: Disabled,1: Enabled" newline bitfld.long 0x0 27. "ADD_CM7_0_TCM,Address Check For Cortex-M7_0_TCM" "0: Disabled,1: Enabled" newline bitfld.long 0x0 26. "CM7_0_TCM,Write Data Check For Cortex-M7_0_TCM" "0: Disabled,1: Enabled" newline bitfld.long 0x0 25. "ADD_AIPS2,Address Check For AIPS2" "0: Disabled,1: Enabled" newline bitfld.long 0x0 24. "AIPS2,Write Data Check For AIPS2" "0: Disabled,1: Enabled" newline bitfld.long 0x0 23. "ADD_AIPS1,Address Check For AIPS1" "0: Disabled,1: Enabled" newline bitfld.long 0x0 22. "AIPS1,Write Data Check For AIPS1" "0: Disabled,1: Enabled" newline bitfld.long 0x0 21. "ADD_AIPS0,Address Check For AIPS0" "0: Disabled,1: Enabled" newline bitfld.long 0x0 20. "AIPS0,Write Data Check For AIPS0" "0: Disabled,1: Enabled" newline bitfld.long 0x0 19. "ADD_QSPI,Address Check For QuadSPI" "0: Disabled,1: Enabled" newline bitfld.long 0x0 18. "QSPI,Write Data Check For QuadSPI" "0: Disabled,1: Enabled" newline bitfld.long 0x0 15. "ADD_PRAM1,Address Check For PRAM1" "0: Disabled,1: Enabled" newline bitfld.long 0x0 14. "PRAM1,Write Data Check For PRAM1" "0: Disabled,1: Enabled" newline bitfld.long 0x0 13. "ADD_PRAM0,Address Check For PRAM0" "0: Disabled,1: Enabled" newline bitfld.long 0x0 12. "PRAM0,Write Data Check For PRAM0" "0: Disabled,1: Enabled" newline bitfld.long 0x0 11. "ADD_PF2,Enable Address Check For PF2" "0: Disabled,1: Enabled" newline bitfld.long 0x0 10. "ADD_PF1,Address Check For PF1" "0: Disabled,1: Enabled" newline bitfld.long 0x0 9. "ADD_PF0,Address Check For PF0" "0: Disabled,1: Enabled" newline bitfld.long 0x0 7. "CM7_1_AHBP,Read Data Check For Cortex-M7_1_AHBP" "0: Disabled,1: Enabled" newline bitfld.long 0x0 6. "CM7_1_AHBM,Read Data Check For Cortex-M7_1_AHBM" "0: Disabled,1: Enabled" newline bitfld.long 0x0 5. "ENET,Read Data Check For ENET" "0: Disabled,1: Enabled" newline bitfld.long 0x0 4. "HSE,Read Data Check For HSE_B" "0: Disabled,1: Enabled" newline bitfld.long 0x0 2. "EDMA,Read Data Check For eDMA" "0: Disabled,1: Enabled" newline bitfld.long 0x0 1. "CM7_0_AHBP,Read Data Check For Cortex-M7_0_AHBP" "0: Disabled,1: Enabled" newline bitfld.long 0x0 0. "CM7_0_AHBM,Read Data Check For Cortex-M7_0_AHBM" "0: Disabled,1: Enabled" line.long 0x4 "ENEDC1,Enable Interconnect Error Detection" bitfld.long 0x4 24. "TCM_GSKT_ADDR_CHK,TCM Gasket Address Check" "0: Disabled,1: Enabled" newline bitfld.long 0x4 23. "SLV_CHK_ACE_ACCEL_RESULT_M1_GSKT_ADDR_CHK,Slave Check Accelerator Result M1 Gasket Address Check" "0: Disabled,1: Enabled" newline bitfld.long 0x4 22. "SLV_CHK_ACE_ACCEL_RESULT_M1_GSKT_WDATA_CHK,Slave Check Accelerator Result M1 Gasket Write Data Check" "0: Disabled,1: Enabled" newline bitfld.long 0x4 21. "SLV_CHK_ACE_ADDR_CHK,Slave Check Accelerator Address" "0: Disabled,1: Enabled" newline bitfld.long 0x4 20. "MSTR_CHK_ACE_FEED_CHK,Master Check Accelerator Feed" "0: Disabled,1: Enabled" newline bitfld.long 0x4 19. "MSTR_CHK_ACE_RESULT_CHK,Master Check Accelerator Result" "0: Disabled,1: Enabled" newline bitfld.long 0x4 18. "CM7_3_AHBP,Enable Read Data Check Cortex-M7_3_AHBP" "0: Disabled,1: Enabled" newline bitfld.long 0x4 17. "CM7_3_AHBM,Enable Read Data Check Cortex-M7_3_AHBM" "0: Disabled,1: Enabled" newline bitfld.long 0x4 15. "ADD_CM7_2_TCM,Enable Address Check Cortex-M7_2_TCM" "0: Disabled,1: Enabled" newline bitfld.long 0x4 14. "CM7_2_TCM,Enable Write Data Check Cortex-M7_2_TCM" "0: Disabled,1: Enabled" newline bitfld.long 0x4 13. "CM7_3_ADDR_CHK,Enable Address Check Cortex-M7_3_TCM" "0: Disabled,1: Enabled" newline bitfld.long 0x4 12. "CM7_3_WDATA_CHK,Enable Write Data Check Cortex-M7_3_TCM" "0: Disabled,1: Enabled" newline bitfld.long 0x4 11. "ADD_EN_PRAM2,Enable Address Check PRAM 2" "0: Disabled,1: Enabled" newline bitfld.long 0x4 10. "EN_PRAM2,Enable Write Data Check PRAM 2" "0: Disabled,1: Enabled" newline bitfld.long 0x4 7. "MSTR_CHECK_ENET1,Master Check ENET1" "0: Disabled,1: Enabled" newline bitfld.long 0x4 6. "EDMA_S1,Enable Address Check eDMA S1" "0: Disabled,1: Enabled" newline bitfld.long 0x4 5. "EDMA_S0,Enable Address Check eDMA S0" "0: Disabled,1: Enabled" newline bitfld.long 0x4 4. "PFLASH_3,Enable Address Check PFlash3" "0: Disabled,1: Enabled" newline bitfld.long 0x4 3. "CM7_2_AHBP,Enable Read Data Check Cortex-M7_2_AHBP" "0: Disabled,1: Enabled" newline bitfld.long 0x4 2. "CM7_2_AHBM,Enable Read Data Check Cortex-M7_2_AHBM" "0: Disabled,1: Enabled" group.long 0x700++0x3 line.long 0x0 "IAHBCFGREG,AHB Gasket Configuration" bitfld.long 0x0 27. "HSE_CMX_GSKT_DAP_DISABLE_OPT_WR,Determines whether write burst optimizations in the HSE_B CMX gasket are enabled or disabled" "0: Enabled,1: Disabled" newline bitfld.long 0x0 26. "ACE_GSKT_DISABLE_OPT_WR,Determines whether write burst optimizations in the ace gasket are enabled or disabled" "0: Enabled,1: Disabled" newline bitfld.long 0x0 25. "ACE_ACCEL_RESULT_M1_GSKT_DISABLE_OPT_WR,Determines whether write burst optimizations in the ace accelerator result m1 gasket are enabled or disabled" "0: Enabled,1: Disabled" newline bitfld.long 0x0 24. "CM7_3_AHBS_DIS_WR_OPT,Determines whether write burst optimizations in the Cortex-M7_3_AHBS gasket are enabled or disabled" "0: Enabled,1: Disabled" newline bitfld.long 0x0 23. "CM7_3_AHBP_DIS_WR_OPT,Determines whether write burst optimizations in the Cortex-M7_3_AHBP gasket are enabled or disabled" "0: Enabled,1: Disabled" newline bitfld.long 0x0 22. "CM7_2_AHBP_DIS_WR_OPT,Determines whether write burst optimizations in the Cortex-M7_2_AHBP gasket are enabled or disabled" "0: Enabled,1: Disabled" newline bitfld.long 0x0 21. "CM7_1_AHBP_DIS_WR_OPT,Determines whether write burst optimizations in the Cortex-M7_1_AHBP gasket are enabled or disabled" "0: Enabled,1: Disabled" newline bitfld.long 0x0 20. "CM7_0_AHBP_DIS_WR_OPT,Determines whether write burst optimizations in the Cortex-M7_0_AHBP gasket are enabled or disabled" "0: Enabled,1: Disabled" newline bitfld.long 0x0 19. "CM7_3_AHBM_DIS_WR_OPT,Determines whether write burst optimizations in the Cortex-M7_3_AHBM gasket are enabled or disabled" "0: Enabled,1: Disabled" newline bitfld.long 0x0 18. "CM7_2_AHBM_DIS_WR_OPT,Determines whether write burst optimizations in the Cortex-M7_2_AHBM gasket are enabled or disabled" "0: Enabled,1: Disabled" newline bitfld.long 0x0 17. "CM7_1_AHBM_DIS_WR_OPT,Determines whether write burst optimizations in the Cortex-M7_1_AHBM gasket are enabled or disabled" "0: Enabled,1: Disabled" newline bitfld.long 0x0 16. "CM7_0_AHBM_DIS_WR_OPT,Determines whether write burst optimizations in the Cortex-M7_0_AHBM gasket are enabled or disabled" "0: Enabled,1: Disabled" newline bitfld.long 0x0 15. "PRAM2_DIS_WR_OPT,Determines whether write burst optimizations in the PRAM2 gasket are enabled or disabled" "0: Enabled,1: Disabled" newline bitfld.long 0x0 14. "PRAM1_DIS_WR_OPT,Determines whether write burst optimizations in the PRAM1 gasket are enabled or disabled" "0: Enabled,1: Disabled" newline bitfld.long 0x0 13. "GMAC1_DIS_WR_OPT,Determines whether write burst optimizations in the GMAC1 gasket are enabled or disabled" "0: Enabled,1: Disabled" newline bitfld.long 0x0 12. "USDHC_DIS_WR_OPT,Determines whether write burst optimizations in the uSDHC gasket are enabled" "0: Enabled,1: Disabled" newline bitfld.long 0x0 11. "AIPS0_DIS_WR_OPT,Determines whether write burst optimizations in the AIPS2 AHB gasket are enabled" "0: Enabled,1: Disabled" newline bitfld.long 0x0 10. "AIPS2_DIS_WR_OPT,Determines whether write burst optimizations in the AIPS2 AHB gasket are enabled" "0: Enabled,1: Disabled" newline bitfld.long 0x0 9. "AIPS1_DIS_WR_OPT,Determines whether write burst optimizations in the AIPS1 AHB gasket are enabled" "0: Enabled,1: Disabled" newline bitfld.long 0x0 8. "CM7_2_AHBS_DIS_WR_OPT,Determines whether write burst optimizations in the Cortex-M7_2_AHBS gasket are enabled or disabled" "0: Enabled,1: Disabled" newline bitfld.long 0x0 7. "CM7_1_AHBS_DIS_WR_OPT,Determines whether write burst optimizations in the Cortex-M7_1_AHBS gasket are enabled or disabled" "0: Enabled,1: Disabled" newline bitfld.long 0x0 6. "CM7_0_AHBS_DIS_WR_OPT,Determines whether write burst optimizations in the Cortex-M7_0_AHBS gasket are enabled or disabled" "0: Enabled,1: Disabled" newline bitfld.long 0x0 5. "QSPI_DIS_WR_OPT,Determines whether write burst optimizations in the QuadSPI AHB gasket are enabled" "0: Enabled,1: Disabled" newline bitfld.long 0x0 4. "TCM_DIS_WR_OPT,Determines whether write burst optimizations in the TCM AHB gasket are enabled" "0: Enabled,1: Disabled" newline bitfld.long 0x0 3. "HSE_DIS_WR_OPT,Determines whether write burst optimizations in the HSE_B AHB gasket are enabled" "0: Enabled,1: Disabled" newline bitfld.long 0x0 2. "DMA_AXBS_S1_DIS_WR_OPT,Determines whether write burst optimizations in the DMA AXBS S1 AHB gasket are enabled" "0: Enabled,1: Disabled" newline bitfld.long 0x0 1. "DMA_AXBS_S0_DIS_WR_OPT,Determines whether write burst optimizations in the DMA AXBS S0 AHB gasket are enabled" "0: Enabled,1: Disabled" newline bitfld.long 0x0 0. "EMAC_DIS_WR_OPT,Determines whether write burst optimizations in the EMAC AHB gasket are enabled" "0: Enabled,1: Disabled" repeat 240. (increment 0x0 0x1)(increment 0x0 0x2) group.word ($2+0x880)++0x1 line.word 0x0 "IRSPRC[$1],Interrupt Router Shared Peripheral Routing Control" bitfld.word 0x0 15. "LOCK,Lock" "0: Writes to IRSPRCn allowed,1: Writes to IRSPRCn ignored" newline bitfld.word 0x0 3. "M7_3,Enable Cortex-M7_3 Interrupt Steering" "0: Routing disabled,1: Routing enabled" newline bitfld.word 0x0 2. "M7_2,Enable Cortex-M7_2 Interrupt Steering" "0: Routing disabled,1: Routing enabled" newline bitfld.word 0x0 1. "M7_1,Enable Cortex-M7_1 Interrupt Steering" "0: Routing disabled,1: Routing enabled" newline bitfld.word 0x0 0. "M7_0,Enable Cortex-M7_0 Interrupt Steering" "0: Routing disabled,1: Routing enabled" repeat.end tree.end tree "MU (Messaging Unit)" base ad:0x0 tree "MU_0__MUB" base ad:0x4038C000 rgroup.long 0x0++0x7 line.long 0x0 "VER,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Set Number" line.long 0x4 "PAR,Parameter" hexmask.long.byte 0x4 24.--31. 1. "FLAG_WIDTH,Flag Width" hexmask.long.byte 0x4 16.--23. 1. "GIR_NUM,General-Purpose Interrupt Request Number" newline hexmask.long.byte 0x4 8.--15. 1. "RR_NUM,Receive Register Number" hexmask.long.byte 0x4 0.--7. 1. "TR_NUM,Transmit Register Number" group.long 0x8++0xB line.long 0x0 "CR,Control" bitfld.long 0x0 1. "MURIE,MUB Reset Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x0 0. "MUR,MU Reset" "0: Idle,1: Reset" line.long 0x4 "SR,Status" rbitfld.long 0x4 6. "RFP,MUB Receive Full Pending" "0: Not pending. MUA is not writing to a TRn register.,1: Pending. MUA is writing to a TRn register." rbitfld.long 0x4 5. "TEP,MUB Transmit Empty Pending" "0: Not pending. MUA is reading no RRn register.,1: Pending. MUA is reading an RRn register." newline rbitfld.long 0x4 4. "GIRP,MUB General-Purpose Interrupt Pending" "0: No request sent,1: Request sent" rbitfld.long 0x4 3. "FUP,MUB Flags Update Pending" "0: No pending update flags (initiated by MUB),1: Pending update flags (initiated by MUB)" newline rbitfld.long 0x4 2. "EP,MUB Side Event Pending" "0: Not pending,1: Pending" eventfld.long 0x4 1. "MURIP,MU Reset Interrupt Pending Flag" "0: Reset not issued,1: Reset issued" newline rbitfld.long 0x4 0. "MURS,MUA and MUB Reset State" "0: Out of reset,1: In reset" line.long 0x8 "CCR0,Core Control 0" bitfld.long 0x8 0. "NMI,MUA Nonmaskable Interrupt Request" "0: Nonmaskable interrupt not issued,1: Nonmaskable interrupt issued" group.long 0x18++0x3 line.long 0x0 "CSSR0,Core Sticky Status 0" eventfld.long 0x0 0. "NMIC,Processor B Nonmaskable Interrupt Clear" "0: Default,1: Clear MUA_CCR0[NMI]" group.long 0x100++0x3 line.long 0x0 "FCR,Flag Control" bitfld.long 0x0 31. "F31,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." bitfld.long 0x0 30. "F30,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." newline bitfld.long 0x0 29. "F29,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." bitfld.long 0x0 28. "F28,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." newline bitfld.long 0x0 27. "F27,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." bitfld.long 0x0 26. "F26,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." newline bitfld.long 0x0 25. "F25,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." bitfld.long 0x0 24. "F24,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." newline bitfld.long 0x0 23. "F23,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." bitfld.long 0x0 22. "F22,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." newline bitfld.long 0x0 21. "F21,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." bitfld.long 0x0 20. "F20,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." newline bitfld.long 0x0 19. "F19,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." bitfld.long 0x0 18. "F18,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." newline bitfld.long 0x0 17. "F17,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." bitfld.long 0x0 16. "F16,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." newline bitfld.long 0x0 15. "F15,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." bitfld.long 0x0 14. "F14,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." newline bitfld.long 0x0 13. "F13,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." bitfld.long 0x0 12. "F12,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." newline bitfld.long 0x0 11. "F11,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." bitfld.long 0x0 10. "F10,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." newline bitfld.long 0x0 9. "F9,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." bitfld.long 0x0 8. "F8,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." newline bitfld.long 0x0 7. "F7,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." bitfld.long 0x0 6. "F6,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." newline bitfld.long 0x0 5. "F5,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." bitfld.long 0x0 4. "F4,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." newline bitfld.long 0x0 3. "F3,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." bitfld.long 0x0 2. "F2,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." newline bitfld.long 0x0 1. "F1,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." bitfld.long 0x0 0. "F0,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." rgroup.long 0x104++0x3 line.long 0x0 "FSR,Flag Status" bitfld.long 0x0 31. "F31,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." bitfld.long 0x0 30. "F30,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." newline bitfld.long 0x0 29. "F29,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." bitfld.long 0x0 28. "F28,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." newline bitfld.long 0x0 27. "F27,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." bitfld.long 0x0 26. "F26,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." newline bitfld.long 0x0 25. "F25,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." bitfld.long 0x0 24. "F24,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." newline bitfld.long 0x0 23. "F23,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." bitfld.long 0x0 22. "F22,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." newline bitfld.long 0x0 21. "F21,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." bitfld.long 0x0 20. "F20,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." newline bitfld.long 0x0 19. "F19,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." bitfld.long 0x0 18. "F18,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." newline bitfld.long 0x0 17. "F17,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." bitfld.long 0x0 16. "F16,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." newline bitfld.long 0x0 15. "F15,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." bitfld.long 0x0 14. "F14,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." newline bitfld.long 0x0 13. "F13,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." bitfld.long 0x0 12. "F12,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." newline bitfld.long 0x0 11. "F11,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." bitfld.long 0x0 10. "F10,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." newline bitfld.long 0x0 9. "F9,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." bitfld.long 0x0 8. "F8,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." newline bitfld.long 0x0 7. "F7,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." bitfld.long 0x0 6. "F6,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." newline bitfld.long 0x0 5. "F5,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." bitfld.long 0x0 4. "F4,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." newline bitfld.long 0x0 3. "F3,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." bitfld.long 0x0 2. "F2,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." newline bitfld.long 0x0 1. "F1,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." bitfld.long 0x0 0. "F0,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." group.long 0x110++0xB line.long 0x0 "GIER,General-Purpose Interrupt Enable" bitfld.long 0x0 31. "GIE31,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 30. "GIE30,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 29. "GIE29,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 28. "GIE28,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 27. "GIE27,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 26. "GIE26,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 25. "GIE25,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 24. "GIE24,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 23. "GIE23,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 22. "GIE22,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 21. "GIE21,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 20. "GIE20,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 19. "GIE19,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 18. "GIE18,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 17. "GIE17,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 16. "GIE16,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 15. "GIE15,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 14. "GIE14,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 13. "GIE13,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 12. "GIE12,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 11. "GIE11,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 10. "GIE10,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 9. "GIE9,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 8. "GIE8,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 7. "GIE7,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 6. "GIE6,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 5. "GIE5,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 4. "GIE4,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 3. "GIE3,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "GIE2,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "GIE1,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "GIE0,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" line.long 0x4 "GCR,General-Purpose Control" bitfld.long 0x4 31. "GIR31,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 30. "GIR30,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 29. "GIR29,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 28. "GIR28,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 27. "GIR27,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 26. "GIR26,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 25. "GIR25,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 24. "GIR24,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 23. "GIR23,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 22. "GIR22,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 21. "GIR21,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 20. "GIR20,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 19. "GIR19,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 18. "GIR18,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 17. "GIR17,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 16. "GIR16,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 15. "GIR15,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 14. "GIR14,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 13. "GIR13,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 12. "GIR12,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 11. "GIR11,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 10. "GIR10,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 9. "GIR9,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 8. "GIR8,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 7. "GIR7,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 6. "GIR6,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 5. "GIR5,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 4. "GIR4,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 3. "GIR3,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 2. "GIR2,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 1. "GIR1,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 0. "GIR0,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" line.long 0x8 "GSR,General-purpose Status" eventfld.long 0x8 31. "GIP31,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 30. "GIP30,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 29. "GIP29,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 28. "GIP28,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 27. "GIP27,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 26. "GIP26,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 25. "GIP25,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 24. "GIP24,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 23. "GIP23,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 22. "GIP22,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 21. "GIP21,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 20. "GIP20,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 19. "GIP19,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 18. "GIP18,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 17. "GIP17,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 16. "GIP16,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 15. "GIP15,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 14. "GIP14,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 13. "GIP13,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 12. "GIP12,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 11. "GIP11,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 10. "GIP10,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 9. "GIP9,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 8. "GIP8,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 7. "GIP7,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 6. "GIP6,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 5. "GIP5,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 4. "GIP4,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 3. "GIP3,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 2. "GIP2,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 1. "GIP1,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 0. "GIP0,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" group.long 0x120++0x3 line.long 0x0 "TCR,Transmit Control" bitfld.long 0x0 3. "TIE3,MUB Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "TIE2,MUB Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "TIE1,MUB Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "TIE0,MUB Transmit Interrupt Enable n" "0: Disable,1: Enable" rgroup.long 0x124++0x3 line.long 0x0 "TSR,Transmit Status" bitfld.long 0x0 3. "TE3,MUB Transmit n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 2. "TE2,MUB Transmit n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 1. "TE1,MUB Transmit n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 0. "TE0,MUB Transmit n Empty" "0: Not empty,1: Empty" group.long 0x128++0x3 line.long 0x0 "RCR,Receive Control" bitfld.long 0x0 3. "RIE3,MUB Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "RIE2,MUB Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "RIE1,MUB Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "RIE0,MUB Receive Interrupt Enable n" "0: Disable,1: Enable" rgroup.long 0x12C++0x3 line.long 0x0 "RSR,Receive Status" bitfld.long 0x0 3. "RF3,MUB Receive Register n Full" "0: Not full,1: Full" bitfld.long 0x0 2. "RF2,MUB Receive Register n Full" "0: Not full,1: Full" newline bitfld.long 0x0 1. "RF1,MUB Receive Register n Full" "0: Not full,1: Full" bitfld.long 0x0 0. "RF0,MUB Receive Register n Full" "0: Not full,1: Full" repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x200)++0x3 line.long 0x0 "TR[$1],Transmit" hexmask.long 0x0 0.--31. 1. "TR_DATA,MUB Transmit Data" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x280)++0x3 line.long 0x0 "RR[$1],Receive" hexmask.long 0x0 0.--31. 1. "RR_DATA,MUB Receive Data" repeat.end tree.end tree "MU_1__MUB" base ad:0x404EC000 rgroup.long 0x0++0x7 line.long 0x0 "VER,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Set Number" line.long 0x4 "PAR,Parameter" hexmask.long.byte 0x4 24.--31. 1. "FLAG_WIDTH,Flag Width" hexmask.long.byte 0x4 16.--23. 1. "GIR_NUM,General-Purpose Interrupt Request Number" newline hexmask.long.byte 0x4 8.--15. 1. "RR_NUM,Receive Register Number" hexmask.long.byte 0x4 0.--7. 1. "TR_NUM,Transmit Register Number" group.long 0x8++0xB line.long 0x0 "CR,Control" bitfld.long 0x0 1. "MURIE,MUB Reset Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x0 0. "MUR,MU Reset" "0: Idle,1: Reset" line.long 0x4 "SR,Status" rbitfld.long 0x4 6. "RFP,MUB Receive Full Pending" "0: Not pending. MUA is not writing to a TRn register.,1: Pending. MUA is writing to a TRn register." rbitfld.long 0x4 5. "TEP,MUB Transmit Empty Pending" "0: Not pending. MUA is reading no RRn register.,1: Pending. MUA is reading an RRn register." newline rbitfld.long 0x4 4. "GIRP,MUB General-Purpose Interrupt Pending" "0: No request sent,1: Request sent" rbitfld.long 0x4 3. "FUP,MUB Flags Update Pending" "0: No pending update flags (initiated by MUB),1: Pending update flags (initiated by MUB)" newline rbitfld.long 0x4 2. "EP,MUB Side Event Pending" "0: Not pending,1: Pending" eventfld.long 0x4 1. "MURIP,MU Reset Interrupt Pending Flag" "0: Reset not issued,1: Reset issued" newline rbitfld.long 0x4 0. "MURS,MUA and MUB Reset State" "0: Out of reset,1: In reset" line.long 0x8 "CCR0,Core Control 0" bitfld.long 0x8 0. "NMI,MUA Nonmaskable Interrupt Request" "0: Nonmaskable interrupt not issued,1: Nonmaskable interrupt issued" group.long 0x18++0x3 line.long 0x0 "CSSR0,Core Sticky Status 0" eventfld.long 0x0 0. "NMIC,Processor B Nonmaskable Interrupt Clear" "0: Default,1: Clear MUA_CCR0[NMI]" group.long 0x100++0x3 line.long 0x0 "FCR,Flag Control" bitfld.long 0x0 31. "F31,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." bitfld.long 0x0 30. "F30,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." newline bitfld.long 0x0 29. "F29,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." bitfld.long 0x0 28. "F28,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." newline bitfld.long 0x0 27. "F27,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." bitfld.long 0x0 26. "F26,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." newline bitfld.long 0x0 25. "F25,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." bitfld.long 0x0 24. "F24,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." newline bitfld.long 0x0 23. "F23,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." bitfld.long 0x0 22. "F22,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." newline bitfld.long 0x0 21. "F21,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." bitfld.long 0x0 20. "F20,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." newline bitfld.long 0x0 19. "F19,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." bitfld.long 0x0 18. "F18,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." newline bitfld.long 0x0 17. "F17,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." bitfld.long 0x0 16. "F16,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." newline bitfld.long 0x0 15. "F15,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." bitfld.long 0x0 14. "F14,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." newline bitfld.long 0x0 13. "F13,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." bitfld.long 0x0 12. "F12,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." newline bitfld.long 0x0 11. "F11,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." bitfld.long 0x0 10. "F10,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." newline bitfld.long 0x0 9. "F9,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." bitfld.long 0x0 8. "F8,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." newline bitfld.long 0x0 7. "F7,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." bitfld.long 0x0 6. "F6,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." newline bitfld.long 0x0 5. "F5,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." bitfld.long 0x0 4. "F4,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." newline bitfld.long 0x0 3. "F3,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." bitfld.long 0x0 2. "F2,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." newline bitfld.long 0x0 1. "F1,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." bitfld.long 0x0 0. "F0,MUB to MUA Flag n" "0: Clear MUA_FSR[Fn].,1: Set MUA_FSR[Fn]." rgroup.long 0x104++0x3 line.long 0x0 "FSR,Flag Status" bitfld.long 0x0 31. "F31,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." bitfld.long 0x0 30. "F30,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." newline bitfld.long 0x0 29. "F29,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." bitfld.long 0x0 28. "F28,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." newline bitfld.long 0x0 27. "F27,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." bitfld.long 0x0 26. "F26,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." newline bitfld.long 0x0 25. "F25,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." bitfld.long 0x0 24. "F24,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." newline bitfld.long 0x0 23. "F23,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." bitfld.long 0x0 22. "F22,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." newline bitfld.long 0x0 21. "F21,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." bitfld.long 0x0 20. "F20,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." newline bitfld.long 0x0 19. "F19,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." bitfld.long 0x0 18. "F18,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." newline bitfld.long 0x0 17. "F17,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." bitfld.long 0x0 16. "F16,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." newline bitfld.long 0x0 15. "F15,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." bitfld.long 0x0 14. "F14,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." newline bitfld.long 0x0 13. "F13,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." bitfld.long 0x0 12. "F12,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." newline bitfld.long 0x0 11. "F11,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." bitfld.long 0x0 10. "F10,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." newline bitfld.long 0x0 9. "F9,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." bitfld.long 0x0 8. "F8,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." newline bitfld.long 0x0 7. "F7,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." bitfld.long 0x0 6. "F6,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." newline bitfld.long 0x0 5. "F5,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." bitfld.long 0x0 4. "F4,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." newline bitfld.long 0x0 3. "F3,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." bitfld.long 0x0 2. "F2,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." newline bitfld.long 0x0 1. "F1,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." bitfld.long 0x0 0. "F0,MUA to MUB-Side Flag n" "0: MUA_FCR[Fn] = 0.,1: MUA_FCR[Fn] = 1." group.long 0x110++0xB line.long 0x0 "GIER,General-Purpose Interrupt Enable" bitfld.long 0x0 31. "GIE31,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 30. "GIE30,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 29. "GIE29,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 28. "GIE28,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 27. "GIE27,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 26. "GIE26,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 25. "GIE25,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 24. "GIE24,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 23. "GIE23,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 22. "GIE22,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 21. "GIE21,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 20. "GIE20,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 19. "GIE19,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 18. "GIE18,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 17. "GIE17,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 16. "GIE16,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 15. "GIE15,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 14. "GIE14,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 13. "GIE13,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 12. "GIE12,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 11. "GIE11,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 10. "GIE10,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 9. "GIE9,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 8. "GIE8,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 7. "GIE7,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 6. "GIE6,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 5. "GIE5,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 4. "GIE4,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 3. "GIE3,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "GIE2,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "GIE1,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "GIE0,MUB General-purpose Interrupt Enable n" "0: Disable,1: Enable" line.long 0x4 "GCR,General-Purpose Control" bitfld.long 0x4 31. "GIR31,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 30. "GIR30,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 29. "GIR29,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 28. "GIR28,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 27. "GIR27,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 26. "GIR26,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 25. "GIR25,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 24. "GIR24,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 23. "GIR23,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 22. "GIR22,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 21. "GIR21,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 20. "GIR20,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 19. "GIR19,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 18. "GIR18,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 17. "GIR17,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 16. "GIR16,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 15. "GIR15,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 14. "GIR14,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 13. "GIR13,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 12. "GIR12,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 11. "GIR11,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 10. "GIR10,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 9. "GIR9,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 8. "GIR8,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 7. "GIR7,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 6. "GIR6,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 5. "GIR5,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 4. "GIR4,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 3. "GIR3,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 2. "GIR2,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" newline bitfld.long 0x4 1. "GIR1,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" bitfld.long 0x4 0. "GIR0,MUB General-Purpose Interrupt Request n" "0: Not requested,1: Requested" line.long 0x8 "GSR,General-purpose Status" eventfld.long 0x8 31. "GIP31,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 30. "GIP30,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 29. "GIP29,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 28. "GIP28,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 27. "GIP27,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 26. "GIP26,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 25. "GIP25,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 24. "GIP24,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 23. "GIP23,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 22. "GIP22,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 21. "GIP21,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 20. "GIP20,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 19. "GIP19,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 18. "GIP18,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 17. "GIP17,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 16. "GIP16,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 15. "GIP15,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 14. "GIP14,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 13. "GIP13,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 12. "GIP12,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 11. "GIP11,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 10. "GIP10,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 9. "GIP9,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 8. "GIP8,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 7. "GIP7,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 6. "GIP6,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 5. "GIP5,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 4. "GIP4,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 3. "GIP3,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 2. "GIP2,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" newline eventfld.long 0x8 1. "GIP1,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" eventfld.long 0x8 0. "GIP0,MUB General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" group.long 0x120++0x3 line.long 0x0 "TCR,Transmit Control" bitfld.long 0x0 3. "TIE3,MUB Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "TIE2,MUB Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "TIE1,MUB Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "TIE0,MUB Transmit Interrupt Enable n" "0: Disable,1: Enable" rgroup.long 0x124++0x3 line.long 0x0 "TSR,Transmit Status" bitfld.long 0x0 3. "TE3,MUB Transmit n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 2. "TE2,MUB Transmit n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 1. "TE1,MUB Transmit n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 0. "TE0,MUB Transmit n Empty" "0: Not empty,1: Empty" group.long 0x128++0x3 line.long 0x0 "RCR,Receive Control" bitfld.long 0x0 3. "RIE3,MUB Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "RIE2,MUB Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "RIE1,MUB Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "RIE0,MUB Receive Interrupt Enable n" "0: Disable,1: Enable" rgroup.long 0x12C++0x3 line.long 0x0 "RSR,Receive Status" bitfld.long 0x0 3. "RF3,MUB Receive Register n Full" "0: Not full,1: Full" bitfld.long 0x0 2. "RF2,MUB Receive Register n Full" "0: Not full,1: Full" newline bitfld.long 0x0 1. "RF1,MUB Receive Register n Full" "0: Not full,1: Full" bitfld.long 0x0 0. "RF0,MUB Receive Register n Full" "0: Not full,1: Full" repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x200)++0x3 line.long 0x0 "TR[$1],Transmit" hexmask.long 0x0 0.--31. 1. "TR_DATA,MUB Transmit Data" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x280)++0x3 line.long 0x0 "RR[$1],Receive" hexmask.long 0x0 0.--31. 1. "RR_DATA,MUB Receive Data" repeat.end tree.end tree "MU_2__MUA" base ad:0x400B8000 rgroup.long 0x0++0x7 line.long 0x0 "VER,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Set Number" line.long 0x4 "PAR,Parameter" hexmask.long.byte 0x4 24.--31. 1. "FLAG_WIDTH,Flag Width" hexmask.long.byte 0x4 16.--23. 1. "GIR_NUM,General-Purpose Interrupt Request Number" newline hexmask.long.byte 0x4 8.--15. 1. "RR_NUM,Receive Register Number" hexmask.long.byte 0x4 0.--7. 1. "TR_NUM,Transmit Register Number" group.long 0x8++0x7 line.long 0x0 "CR,Control" bitfld.long 0x0 1. "MURIE,MUA Reset Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x0 0. "MUR,MU Reset" "0: Idle,1: Reset" line.long 0x4 "SR,Status" rbitfld.long 0x4 6. "RFP,MUA Receive Full Pending" "0: Not pending. MUB is not writing to a TRn register.,1: Pending. MUB is writing to a TRn register." rbitfld.long 0x4 5. "TEP,MUA Transmit Empty Pending" "0: Not pending. MUB is reading no RRn register.,1: Pending. MUB is reading an RRn register." newline rbitfld.long 0x4 4. "GIRP,MUA General-Purpose Interrupt Pending" "0: No request sent,1: Request sent" rbitfld.long 0x4 3. "FUP,MUA Flags Update Pending" "0: No pending update flags (initiated by MUA),1: Pending update flags (initiated by MUA)" newline rbitfld.long 0x4 2. "EP,MUA Side Event Pending" "0: Not pending,1: Pending" eventfld.long 0x4 1. "MURIP,MU Reset Interrupt Pending Flag" "0: Reset not issued,1: Reset issued" newline rbitfld.long 0x4 0. "MURS,MUA and MUB Reset State" "0: Out of reset,1: In reset" group.long 0x100++0x3 line.long 0x0 "FCR,Flag Control" bitfld.long 0x0 2. "F2,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 1. "F1,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 0. "F0,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." rgroup.long 0x104++0x3 line.long 0x0 "FSR,Flag Status" bitfld.long 0x0 2. "F2,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 1. "F1,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 0. "F0,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." group.long 0x110++0xB line.long 0x0 "GIER,General-Purpose Interrupt Enable" bitfld.long 0x0 0. "GIE0,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" line.long 0x4 "GCR,General-Purpose Control" bitfld.long 0x4 0. "GIR0,MUA General-Purpose Interrupt Request n" "0: Not requested,1: Requested" line.long 0x8 "GSR,General-purpose Status" eventfld.long 0x8 0. "GIP0,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" group.long 0x120++0x3 line.long 0x0 "TCR,Transmit Control" bitfld.long 0x0 3. "TIE3,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "TIE2,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "TIE1,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "TIE0,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" rgroup.long 0x124++0x3 line.long 0x0 "TSR,Transmit Status" bitfld.long 0x0 3. "TE3,MUA Transmit n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 2. "TE2,MUA Transmit n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 1. "TE1,MUA Transmit n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 0. "TE0,MUA Transmit n Empty" "0: Not empty,1: Empty" group.long 0x128++0x3 line.long 0x0 "RCR,Receive Control" bitfld.long 0x0 3. "RIE3,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "RIE2,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "RIE1,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "RIE0,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" rgroup.long 0x12C++0x3 line.long 0x0 "RSR,Receive Status" bitfld.long 0x0 3. "RF3,MUA Receive Register n Full" "0: Not full,1: Full" bitfld.long 0x0 2. "RF2,MUA Receive Register n Full" "0: Not full,1: Full" newline bitfld.long 0x0 1. "RF1,MUA Receive Register n Full" "0: Not full,1: Full" bitfld.long 0x0 0. "RF0,MUA Receive Register n Full" "0: Not full,1: Full" repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x200)++0x3 line.long 0x0 "TR[$1],Transmit" hexmask.long 0x0 0.--31. 1. "TR_DATA,MUA Transmit Data" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x280)++0x3 line.long 0x0 "RR[$1],Receive" hexmask.long 0x0 0.--31. 1. "RR_DATA,MUA Receive Data" repeat.end tree.end tree "MU_2__MUB" base ad:0x400BC000 rgroup.long 0x0++0x7 line.long 0x0 "VER,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Set Number" line.long 0x4 "PAR,Parameter" hexmask.long.byte 0x4 24.--31. 1. "FLAG_WIDTH,Flag Width" hexmask.long.byte 0x4 16.--23. 1. "GIR_NUM,General-Purpose Interrupt Request Number" newline hexmask.long.byte 0x4 8.--15. 1. "RR_NUM,Receive Register Number" hexmask.long.byte 0x4 0.--7. 1. "TR_NUM,Transmit Register Number" group.long 0x8++0x7 line.long 0x0 "CR,Control" bitfld.long 0x0 1. "MURIE,MUA Reset Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x0 0. "MUR,MU Reset" "0: Idle,1: Reset" line.long 0x4 "SR,Status" rbitfld.long 0x4 6. "RFP,MUA Receive Full Pending" "0: Not pending. MUB is not writing to a TRn register.,1: Pending. MUB is writing to a TRn register." rbitfld.long 0x4 5. "TEP,MUA Transmit Empty Pending" "0: Not pending. MUB is reading no RRn register.,1: Pending. MUB is reading an RRn register." newline rbitfld.long 0x4 4. "GIRP,MUA General-Purpose Interrupt Pending" "0: No request sent,1: Request sent" rbitfld.long 0x4 3. "FUP,MUA Flags Update Pending" "0: No pending update flags (initiated by MUA),1: Pending update flags (initiated by MUA)" newline rbitfld.long 0x4 2. "EP,MUA Side Event Pending" "0: Not pending,1: Pending" eventfld.long 0x4 1. "MURIP,MU Reset Interrupt Pending Flag" "0: Reset not issued,1: Reset issued" newline rbitfld.long 0x4 0. "MURS,MUA and MUB Reset State" "0: Out of reset,1: In reset" group.long 0x100++0x3 line.long 0x0 "FCR,Flag Control" bitfld.long 0x0 2. "F2,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 1. "F1,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 0. "F0,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." rgroup.long 0x104++0x3 line.long 0x0 "FSR,Flag Status" bitfld.long 0x0 2. "F2,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 1. "F1,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 0. "F0,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." group.long 0x110++0xB line.long 0x0 "GIER,General-Purpose Interrupt Enable" bitfld.long 0x0 0. "GIE0,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" line.long 0x4 "GCR,General-Purpose Control" bitfld.long 0x4 0. "GIR0,MUA General-Purpose Interrupt Request n" "0: Not requested,1: Requested" line.long 0x8 "GSR,General-purpose Status" eventfld.long 0x8 0. "GIP0,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" group.long 0x120++0x3 line.long 0x0 "TCR,Transmit Control" bitfld.long 0x0 3. "TIE3,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "TIE2,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "TIE1,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "TIE0,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" rgroup.long 0x124++0x3 line.long 0x0 "TSR,Transmit Status" bitfld.long 0x0 3. "TE3,MUA Transmit n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 2. "TE2,MUA Transmit n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 1. "TE1,MUA Transmit n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 0. "TE0,MUA Transmit n Empty" "0: Not empty,1: Empty" group.long 0x128++0x3 line.long 0x0 "RCR,Receive Control" bitfld.long 0x0 3. "RIE3,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "RIE2,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "RIE1,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "RIE0,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" rgroup.long 0x12C++0x3 line.long 0x0 "RSR,Receive Status" bitfld.long 0x0 3. "RF3,MUA Receive Register n Full" "0: Not full,1: Full" bitfld.long 0x0 2. "RF2,MUA Receive Register n Full" "0: Not full,1: Full" newline bitfld.long 0x0 1. "RF1,MUA Receive Register n Full" "0: Not full,1: Full" bitfld.long 0x0 0. "RF0,MUA Receive Register n Full" "0: Not full,1: Full" repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x200)++0x3 line.long 0x0 "TR[$1],Transmit" hexmask.long 0x0 0.--31. 1. "TR_DATA,MUA Transmit Data" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x280)++0x3 line.long 0x0 "RR[$1],Receive" hexmask.long 0x0 0.--31. 1. "RR_DATA,MUA Receive Data" repeat.end tree.end tree "MU_3__MUA" base ad:0x400C4000 rgroup.long 0x0++0x7 line.long 0x0 "VER,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Set Number" line.long 0x4 "PAR,Parameter" hexmask.long.byte 0x4 24.--31. 1. "FLAG_WIDTH,Flag Width" hexmask.long.byte 0x4 16.--23. 1. "GIR_NUM,General-Purpose Interrupt Request Number" newline hexmask.long.byte 0x4 8.--15. 1. "RR_NUM,Receive Register Number" hexmask.long.byte 0x4 0.--7. 1. "TR_NUM,Transmit Register Number" group.long 0x8++0x7 line.long 0x0 "CR,Control" bitfld.long 0x0 1. "MURIE,MUA Reset Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x0 0. "MUR,MU Reset" "0: Idle,1: Reset" line.long 0x4 "SR,Status" rbitfld.long 0x4 6. "RFP,MUA Receive Full Pending" "0: Not pending. MUB is not writing to a TRn register.,1: Pending. MUB is writing to a TRn register." rbitfld.long 0x4 5. "TEP,MUA Transmit Empty Pending" "0: Not pending. MUB is reading no RRn register.,1: Pending. MUB is reading an RRn register." newline rbitfld.long 0x4 4. "GIRP,MUA General-Purpose Interrupt Pending" "0: No request sent,1: Request sent" rbitfld.long 0x4 3. "FUP,MUA Flags Update Pending" "0: No pending update flags (initiated by MUA),1: Pending update flags (initiated by MUA)" newline rbitfld.long 0x4 2. "EP,MUA Side Event Pending" "0: Not pending,1: Pending" eventfld.long 0x4 1. "MURIP,MU Reset Interrupt Pending Flag" "0: Reset not issued,1: Reset issued" newline rbitfld.long 0x4 0. "MURS,MUA and MUB Reset State" "0: Out of reset,1: In reset" group.long 0x100++0x3 line.long 0x0 "FCR,Flag Control" bitfld.long 0x0 2. "F2,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 1. "F1,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 0. "F0,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." rgroup.long 0x104++0x3 line.long 0x0 "FSR,Flag Status" bitfld.long 0x0 2. "F2,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 1. "F1,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 0. "F0,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." group.long 0x110++0xB line.long 0x0 "GIER,General-Purpose Interrupt Enable" bitfld.long 0x0 0. "GIE0,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" line.long 0x4 "GCR,General-Purpose Control" bitfld.long 0x4 0. "GIR0,MUA General-Purpose Interrupt Request n" "0: Not requested,1: Requested" line.long 0x8 "GSR,General-purpose Status" eventfld.long 0x8 0. "GIP0,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" group.long 0x120++0x3 line.long 0x0 "TCR,Transmit Control" bitfld.long 0x0 3. "TIE3,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "TIE2,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "TIE1,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "TIE0,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" rgroup.long 0x124++0x3 line.long 0x0 "TSR,Transmit Status" bitfld.long 0x0 3. "TE3,MUA Transmit n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 2. "TE2,MUA Transmit n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 1. "TE1,MUA Transmit n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 0. "TE0,MUA Transmit n Empty" "0: Not empty,1: Empty" group.long 0x128++0x3 line.long 0x0 "RCR,Receive Control" bitfld.long 0x0 3. "RIE3,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "RIE2,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "RIE1,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "RIE0,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" rgroup.long 0x12C++0x3 line.long 0x0 "RSR,Receive Status" bitfld.long 0x0 3. "RF3,MUA Receive Register n Full" "0: Not full,1: Full" bitfld.long 0x0 2. "RF2,MUA Receive Register n Full" "0: Not full,1: Full" newline bitfld.long 0x0 1. "RF1,MUA Receive Register n Full" "0: Not full,1: Full" bitfld.long 0x0 0. "RF0,MUA Receive Register n Full" "0: Not full,1: Full" repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x200)++0x3 line.long 0x0 "TR[$1],Transmit" hexmask.long 0x0 0.--31. 1. "TR_DATA,MUA Transmit Data" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x280)++0x3 line.long 0x0 "RR[$1],Receive" hexmask.long 0x0 0.--31. 1. "RR_DATA,MUA Receive Data" repeat.end tree.end tree "MU_3__MUB" base ad:0x400C8000 rgroup.long 0x0++0x7 line.long 0x0 "VER,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Set Number" line.long 0x4 "PAR,Parameter" hexmask.long.byte 0x4 24.--31. 1. "FLAG_WIDTH,Flag Width" hexmask.long.byte 0x4 16.--23. 1. "GIR_NUM,General-Purpose Interrupt Request Number" newline hexmask.long.byte 0x4 8.--15. 1. "RR_NUM,Receive Register Number" hexmask.long.byte 0x4 0.--7. 1. "TR_NUM,Transmit Register Number" group.long 0x8++0x7 line.long 0x0 "CR,Control" bitfld.long 0x0 1. "MURIE,MUA Reset Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x0 0. "MUR,MU Reset" "0: Idle,1: Reset" line.long 0x4 "SR,Status" rbitfld.long 0x4 6. "RFP,MUA Receive Full Pending" "0: Not pending. MUB is not writing to a TRn register.,1: Pending. MUB is writing to a TRn register." rbitfld.long 0x4 5. "TEP,MUA Transmit Empty Pending" "0: Not pending. MUB is reading no RRn register.,1: Pending. MUB is reading an RRn register." newline rbitfld.long 0x4 4. "GIRP,MUA General-Purpose Interrupt Pending" "0: No request sent,1: Request sent" rbitfld.long 0x4 3. "FUP,MUA Flags Update Pending" "0: No pending update flags (initiated by MUA),1: Pending update flags (initiated by MUA)" newline rbitfld.long 0x4 2. "EP,MUA Side Event Pending" "0: Not pending,1: Pending" eventfld.long 0x4 1. "MURIP,MU Reset Interrupt Pending Flag" "0: Reset not issued,1: Reset issued" newline rbitfld.long 0x4 0. "MURS,MUA and MUB Reset State" "0: Out of reset,1: In reset" group.long 0x100++0x3 line.long 0x0 "FCR,Flag Control" bitfld.long 0x0 2. "F2,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 1. "F1,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 0. "F0,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." rgroup.long 0x104++0x3 line.long 0x0 "FSR,Flag Status" bitfld.long 0x0 2. "F2,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 1. "F1,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 0. "F0,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." group.long 0x110++0xB line.long 0x0 "GIER,General-Purpose Interrupt Enable" bitfld.long 0x0 0. "GIE0,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" line.long 0x4 "GCR,General-Purpose Control" bitfld.long 0x4 0. "GIR0,MUA General-Purpose Interrupt Request n" "0: Not requested,1: Requested" line.long 0x8 "GSR,General-purpose Status" eventfld.long 0x8 0. "GIP0,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" group.long 0x120++0x3 line.long 0x0 "TCR,Transmit Control" bitfld.long 0x0 3. "TIE3,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "TIE2,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "TIE1,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "TIE0,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" rgroup.long 0x124++0x3 line.long 0x0 "TSR,Transmit Status" bitfld.long 0x0 3. "TE3,MUA Transmit n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 2. "TE2,MUA Transmit n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 1. "TE1,MUA Transmit n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 0. "TE0,MUA Transmit n Empty" "0: Not empty,1: Empty" group.long 0x128++0x3 line.long 0x0 "RCR,Receive Control" bitfld.long 0x0 3. "RIE3,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "RIE2,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "RIE1,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "RIE0,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" rgroup.long 0x12C++0x3 line.long 0x0 "RSR,Receive Status" bitfld.long 0x0 3. "RF3,MUA Receive Register n Full" "0: Not full,1: Full" bitfld.long 0x0 2. "RF2,MUA Receive Register n Full" "0: Not full,1: Full" newline bitfld.long 0x0 1. "RF1,MUA Receive Register n Full" "0: Not full,1: Full" bitfld.long 0x0 0. "RF0,MUA Receive Register n Full" "0: Not full,1: Full" repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x200)++0x3 line.long 0x0 "TR[$1],Transmit" hexmask.long 0x0 0.--31. 1. "TR_DATA,MUA Transmit Data" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x280)++0x3 line.long 0x0 "RR[$1],Receive" hexmask.long 0x0 0.--31. 1. "RR_DATA,MUA Receive Data" repeat.end tree.end tree "MU_4__MUA" base ad:0x400CC000 rgroup.long 0x0++0x7 line.long 0x0 "VER,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Set Number" line.long 0x4 "PAR,Parameter" hexmask.long.byte 0x4 24.--31. 1. "FLAG_WIDTH,Flag Width" hexmask.long.byte 0x4 16.--23. 1. "GIR_NUM,General-Purpose Interrupt Request Number" newline hexmask.long.byte 0x4 8.--15. 1. "RR_NUM,Receive Register Number" hexmask.long.byte 0x4 0.--7. 1. "TR_NUM,Transmit Register Number" group.long 0x8++0x7 line.long 0x0 "CR,Control" bitfld.long 0x0 1. "MURIE,MUA Reset Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x0 0. "MUR,MU Reset" "0: Idle,1: Reset" line.long 0x4 "SR,Status" rbitfld.long 0x4 6. "RFP,MUA Receive Full Pending" "0: Not pending. MUB is not writing to a TRn register.,1: Pending. MUB is writing to a TRn register." rbitfld.long 0x4 5. "TEP,MUA Transmit Empty Pending" "0: Not pending. MUB is reading no RRn register.,1: Pending. MUB is reading an RRn register." newline rbitfld.long 0x4 4. "GIRP,MUA General-Purpose Interrupt Pending" "0: No request sent,1: Request sent" rbitfld.long 0x4 3. "FUP,MUA Flags Update Pending" "0: No pending update flags (initiated by MUA),1: Pending update flags (initiated by MUA)" newline rbitfld.long 0x4 2. "EP,MUA Side Event Pending" "0: Not pending,1: Pending" eventfld.long 0x4 1. "MURIP,MU Reset Interrupt Pending Flag" "0: Reset not issued,1: Reset issued" newline rbitfld.long 0x4 0. "MURS,MUA and MUB Reset State" "0: Out of reset,1: In reset" group.long 0x100++0x3 line.long 0x0 "FCR,Flag Control" bitfld.long 0x0 2. "F2,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 1. "F1,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 0. "F0,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." rgroup.long 0x104++0x3 line.long 0x0 "FSR,Flag Status" bitfld.long 0x0 2. "F2,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 1. "F1,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 0. "F0,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." group.long 0x110++0xB line.long 0x0 "GIER,General-Purpose Interrupt Enable" bitfld.long 0x0 0. "GIE0,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" line.long 0x4 "GCR,General-Purpose Control" bitfld.long 0x4 0. "GIR0,MUA General-Purpose Interrupt Request n" "0: Not requested,1: Requested" line.long 0x8 "GSR,General-purpose Status" eventfld.long 0x8 0. "GIP0,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" group.long 0x120++0x3 line.long 0x0 "TCR,Transmit Control" bitfld.long 0x0 3. "TIE3,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "TIE2,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "TIE1,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "TIE0,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" rgroup.long 0x124++0x3 line.long 0x0 "TSR,Transmit Status" bitfld.long 0x0 3. "TE3,MUA Transmit n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 2. "TE2,MUA Transmit n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 1. "TE1,MUA Transmit n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 0. "TE0,MUA Transmit n Empty" "0: Not empty,1: Empty" group.long 0x128++0x3 line.long 0x0 "RCR,Receive Control" bitfld.long 0x0 3. "RIE3,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "RIE2,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "RIE1,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "RIE0,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" rgroup.long 0x12C++0x3 line.long 0x0 "RSR,Receive Status" bitfld.long 0x0 3. "RF3,MUA Receive Register n Full" "0: Not full,1: Full" bitfld.long 0x0 2. "RF2,MUA Receive Register n Full" "0: Not full,1: Full" newline bitfld.long 0x0 1. "RF1,MUA Receive Register n Full" "0: Not full,1: Full" bitfld.long 0x0 0. "RF0,MUA Receive Register n Full" "0: Not full,1: Full" repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x200)++0x3 line.long 0x0 "TR[$1],Transmit" hexmask.long 0x0 0.--31. 1. "TR_DATA,MUA Transmit Data" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x280)++0x3 line.long 0x0 "RR[$1],Receive" hexmask.long 0x0 0.--31. 1. "RR_DATA,MUA Receive Data" repeat.end tree.end tree "MU_4__MUB" base ad:0x400D0000 rgroup.long 0x0++0x7 line.long 0x0 "VER,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Set Number" line.long 0x4 "PAR,Parameter" hexmask.long.byte 0x4 24.--31. 1. "FLAG_WIDTH,Flag Width" hexmask.long.byte 0x4 16.--23. 1. "GIR_NUM,General-Purpose Interrupt Request Number" newline hexmask.long.byte 0x4 8.--15. 1. "RR_NUM,Receive Register Number" hexmask.long.byte 0x4 0.--7. 1. "TR_NUM,Transmit Register Number" group.long 0x8++0x7 line.long 0x0 "CR,Control" bitfld.long 0x0 1. "MURIE,MUA Reset Interrupt Enable" "0: Disable,1: Enable" bitfld.long 0x0 0. "MUR,MU Reset" "0: Idle,1: Reset" line.long 0x4 "SR,Status" rbitfld.long 0x4 6. "RFP,MUA Receive Full Pending" "0: Not pending. MUB is not writing to a TRn register.,1: Pending. MUB is writing to a TRn register." rbitfld.long 0x4 5. "TEP,MUA Transmit Empty Pending" "0: Not pending. MUB is reading no RRn register.,1: Pending. MUB is reading an RRn register." newline rbitfld.long 0x4 4. "GIRP,MUA General-Purpose Interrupt Pending" "0: No request sent,1: Request sent" rbitfld.long 0x4 3. "FUP,MUA Flags Update Pending" "0: No pending update flags (initiated by MUA),1: Pending update flags (initiated by MUA)" newline rbitfld.long 0x4 2. "EP,MUA Side Event Pending" "0: Not pending,1: Pending" eventfld.long 0x4 1. "MURIP,MU Reset Interrupt Pending Flag" "0: Reset not issued,1: Reset issued" newline rbitfld.long 0x4 0. "MURS,MUA and MUB Reset State" "0: Out of reset,1: In reset" group.long 0x100++0x3 line.long 0x0 "FCR,Flag Control" bitfld.long 0x0 2. "F2,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." bitfld.long 0x0 1. "F1,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." newline bitfld.long 0x0 0. "F0,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn].,1: Set MUB_FSR[Fn]." rgroup.long 0x104++0x3 line.long 0x0 "FSR,Flag Status" bitfld.long 0x0 2. "F2,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." bitfld.long 0x0 1. "F1,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." newline bitfld.long 0x0 0. "F0,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0.,1: MUB_FCR[Fn] = 1." group.long 0x110++0xB line.long 0x0 "GIER,General-Purpose Interrupt Enable" bitfld.long 0x0 0. "GIE0,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable" line.long 0x4 "GCR,General-Purpose Control" bitfld.long 0x4 0. "GIR0,MUA General-Purpose Interrupt Request n" "0: Not requested,1: Requested" line.long 0x8 "GSR,General-purpose Status" eventfld.long 0x8 0. "GIP0,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending" group.long 0x120++0x3 line.long 0x0 "TCR,Transmit Control" bitfld.long 0x0 3. "TIE3,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "TIE2,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "TIE1,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "TIE0,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable" rgroup.long 0x124++0x3 line.long 0x0 "TSR,Transmit Status" bitfld.long 0x0 3. "TE3,MUA Transmit n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 2. "TE2,MUA Transmit n Empty" "0: Not empty,1: Empty" newline bitfld.long 0x0 1. "TE1,MUA Transmit n Empty" "0: Not empty,1: Empty" bitfld.long 0x0 0. "TE0,MUA Transmit n Empty" "0: Not empty,1: Empty" group.long 0x128++0x3 line.long 0x0 "RCR,Receive Control" bitfld.long 0x0 3. "RIE3,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 2. "RIE2,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "RIE1,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" bitfld.long 0x0 0. "RIE0,MUA Receive Interrupt Enable n" "0: Disable,1: Enable" rgroup.long 0x12C++0x3 line.long 0x0 "RSR,Receive Status" bitfld.long 0x0 3. "RF3,MUA Receive Register n Full" "0: Not full,1: Full" bitfld.long 0x0 2. "RF2,MUA Receive Register n Full" "0: Not full,1: Full" newline bitfld.long 0x0 1. "RF1,MUA Receive Register n Full" "0: Not full,1: Full" bitfld.long 0x0 0. "RF0,MUA Receive Register n Full" "0: Not full,1: Full" repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x200)++0x3 line.long 0x0 "TR[$1],Transmit" hexmask.long 0x0 0.--31. 1. "TR_DATA,MUA Transmit Data" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x280)++0x3 line.long 0x0 "RR[$1],Receive" hexmask.long 0x0 0.--31. 1. "RR_DATA,MUA Receive Data" repeat.end tree.end tree.end tree "PFLASH (Flash Memory Controller)" base ad:0x40268000 repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "PFCR[$1],Platform Flash Memory Configuration i" bitfld.long 0x0 5. "P0_DPFEN,Port0 Data Prefetch Enable" "0: Disable,1: Enable" bitfld.long 0x0 4. "P0_CPFEN,Port0 Code Prefetch Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 1. "P0_DBFEN,Port0 PFLASH Line Read Data Buffers Enable" "0: Disable,1: Enable" bitfld.long 0x0 0. "P0_CBFEN,Port0 PFLASH Line Read Code Buffers Enable" "0: Disable,1: Enable" repeat.end group.long 0x10++0x7 line.long 0x0 "PFCR4,Platform Flash Memory Configuration 4" bitfld.long 0x0 7. "DMEEE,Disable Multi-Bit ECC Error Exception" "0: Error response sent on system bus for multi-bit..,1: Error response not sent on system bus for.." bitfld.long 0x0 1.--3. "BLK4_PS,Block 4 Pipe Select" "0: Block 4 access can be through any of the command..,1: Block 4 access is always through pipe1,2: Block 4 access is always through pipe2,3: Block 4 access is always through pipe3,4: Block 4 access can be through any of the command..,5: Block 4 access can be through any of the command..,6: Block 4 access can be through any of the command..,7: Block 4 access can be through any of the command.." newline bitfld.long 0x0 0. "DERR_SUP,Data Error Suppression" "0: Reports ECC events on data flash memory accesses,1: Single-bit and multi-bit ECC events on data.." line.long 0x4 "PFAPR,Platform Flash Memory Access Protection" bitfld.long 0x4 30.--31. "M0AP,Master n Access Protection" "0: This master can perform read accesses,1: This master can perform read accesses,2: This master cannot perform any read accesses,3: This master can perform read accesses" bitfld.long 0x4 28.--29. "M1AP,Master n Access Protection" "0: This master can perform read accesses,1: This master can perform read accesses,2: This master cannot perform any read accesses,3: This master can perform read accesses" newline bitfld.long 0x4 26.--27. "M2AP,Master n Access Protection" "0: This master can perform read accesses,1: This master can perform read accesses,2: This master cannot perform any read accesses,3: This master can perform read accesses" bitfld.long 0x4 24.--25. "M3AP,Master n Access Protection" "0: This master can perform read accesses,1: This master can perform read accesses,2: This master cannot perform any read accesses,3: This master can perform read accesses" newline bitfld.long 0x4 22.--23. "M4AP,Master n Access Protection" "0: This master can perform read accesses,1: This master can perform read accesses,2: This master cannot perform any read accesses,3: This master can perform read accesses" bitfld.long 0x4 20.--21. "M5AP,Master n Access Protection" "0: This master can perform read accesses,1: This master can perform read accesses,2: This master cannot perform any read accesses,3: This master can perform read accesses" newline bitfld.long 0x4 18.--19. "M6AP,Master n Access Protection" "0: This master can perform read accesses,1: This master can perform read accesses,2: This master cannot perform any read accesses,3: This master can perform read accesses" bitfld.long 0x4 16.--17. "M7AP,Master n Access Protection" "0: This master can perform read accesses,1: This master can perform read accesses,2: This master cannot perform any read accesses,3: This master can perform read accesses" newline bitfld.long 0x4 14.--15. "M8AP,Master n Access Protection" "0: This master can perform read accesses,1: This master can perform read accesses,2: This master cannot perform any read accesses,3: This master can perform read accesses" bitfld.long 0x4 12.--13. "M9AP,Master n Access Protection" "0: This master can perform read accesses,1: This master can perform read accesses,2: This master cannot perform any read accesses,3: This master can perform read accesses" newline bitfld.long 0x4 10.--11. "M10AP,Master n Access Protection" "0: This master can perform read accesses,1: This master can perform read accesses,2: This master cannot perform any read accesses,3: This master can perform read accesses" bitfld.long 0x4 8.--9. "M11AP,Master n Access Protection" "0: This master can perform read accesses,1: This master can perform read accesses,2: This master cannot perform any read accesses,3: This master can perform read accesses" newline bitfld.long 0x4 6.--7. "M12AP,Master n Access Protection" "0: This master can perform read accesses,1: This master can perform read accesses,2: This master cannot perform any read accesses,3: This master can perform read accesses" bitfld.long 0x4 4.--5. "M13AP,Master n Access Protection" "0: This master can perform read accesses,1: This master can perform read accesses,2: This master cannot perform any read accesses,3: This master can perform read accesses" newline bitfld.long 0x4 2.--3. "M14AP,Master n Access Protection" "0: This master can perform read accesses,1: This master can perform read accesses,2: This master cannot perform any read accesses,3: This master can perform read accesses" bitfld.long 0x4 0.--1. "M15AP,Master n Access Protection" "0: This master can perform read accesses,1: This master can perform read accesses,2: This master cannot perform any read accesses,3: This master can perform read accesses" group.long 0x300++0x3 line.long 0x0 "PFCPGM_PEADR_L,Platform Flash Memory Program Erase Address Logical" hexmask.long 0x0 0.--31. 1. "PEADR_L,Program Erase Address Logical" rgroup.long 0x304++0x3 line.long 0x0 "PFCPGM_PEADR_P,Platform Flash Memory Program Erase Address Physical" hexmask.long 0x0 0.--31. 1. "PEADR_P,Program Erase Address Physical" group.long 0x308++0x3 line.long 0x0 "PFCPGM_XPEADR_L,Platform Flash Memory Express Program Erase Address Logical" hexmask.long 0x0 0.--31. 1. "XPEADR_L,Express Program Erase Address Logical" rgroup.long 0x30C++0x3 line.long 0x0 "PFCPGM_XPEADR_P,Platform Flash Memory Express Program Erase Address Physical" hexmask.long 0x0 0.--31. 1. "XPEADR_P,Express Program Erase Address Physical" repeat 5. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x340)++0x3 line.long 0x0 "PFCBLK_SPELOCK[$1],Block n Sector Program Erase Lock" hexmask.long 0x0 0.--31. 1. "SLCK,Sector Lock" repeat.end group.long 0x358++0x3 line.long 0x0 "PFCBLKU_SPELOCK,Block UTEST Sector Program Erase Lock" bitfld.long 0x0 0. "SLCK,Sector Lock" "0,1" repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x35C)++0x3 line.long 0x0 "PFCBLK_SSPELOCK[$1],Block n Super Sector Program Erase Lock" hexmask.long 0x0 0.--27. 1. "SSLCK,Super Sector Lock" repeat.end repeat 5. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x380)++0x3 line.long 0x0 "PFCBLK_SETSLOCK[$1],Block n Set Sector Lock" hexmask.long 0x0 0.--31. 1. "SETSLCK,If the vector bit value = 0 the corresponding lock bit is not owned by any master" repeat.end group.long 0x398++0x3 line.long 0x0 "PFCBLKU_SETSLOCK,Block UTEST Set Sector Lock" bitfld.long 0x0 0. "SETSLCK,Set Sector Lock" "0,1" repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x39C)++0x3 line.long 0x0 "PFCBLK_SSETSLOCK[$1],Block n Set Super Sector Lock" hexmask.long 0x0 0.--27. 1. "SSETSLCK,Set Super Sector Lock" repeat.end repeat 5. (list 0x0 0x1 0x2 0x3 0x4)(list ad:0x402683C0 ad:0x402683E0 ad:0x40268400 ad:0x40268420 ad:0x40268440) tree "PFCBLKi_LOCKMASTER_S[$1]" base $2 repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2)++0x3 line.long 0x0 "PFCBLK_LOCKMASTER_S[$1],Block a Lock Master Sector b" hexmask.long 0x0 0.--31. 1. "LOCKMASTER_S,Block a Lock Master Sector b" repeat.end tree.end repeat.end base ad:0x40268000 rgroup.long 0x480++0x3 line.long 0x0 "PFCBLKU_LOCKMASTER_S,Block UTEST Lock Master Sector" hexmask.long.byte 0x0 0.--7. 1. "LOCKMASTER_S,Lock Master Sector" repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x40268484 ad:0x402684A0 ad:0x402684BC ad:0x402684D8) tree "PFCBLKi_LOCKMASTER_SS[$1]" base $2 repeat 7. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2)++0x3 line.long 0x0 "PFCBLK_LOCKMASTER_SS[$1],Block m Lock Master Super Sector n" hexmask.long 0x0 0.--31. 1. "LOCKMASTER_SS,Block a Lock Master Super Sector b" repeat.end tree.end repeat.end tree.end tree "PIT (Periodic Interrupt Timer)" base ad:0x0 tree "PIT_0" base ad:0x400B0000 group.long 0x0++0x3 line.long 0x0 "MCR,PIT Module Control" bitfld.long 0x0 2. "MDIS_RTI,Module Disable for RTI" "0: Enables,1: Disables" bitfld.long 0x0 1. "MDIS,Module Disable for PIT" "0: Enables,1: Disables" bitfld.long 0x0 0. "FRZ,Freeze" "0: Timers run in Debug mode,1: Timers stop in Debug mode" rgroup.long 0xE0++0x7 line.long 0x0 "LTMR64H,PIT Upper Lifetimer" hexmask.long 0x0 0.--31. 1. "LTH,Lifetimer Value" line.long 0x4 "LTMR64L,PIT Lower Lifetimer" hexmask.long 0x4 0.--31. 1. "LTL,Lifetimer Value" group.long 0xEC++0x7 line.long 0x0 "RTI_LDVAL_STAT,RTI Timer Load Value Sync Status" bitfld.long 0x0 0. "RT_STAT,Sync Status" "0: Not loaded,1: Loaded" line.long 0x4 "RTI_LDVAL,RTI Timer Load Value" hexmask.long 0x4 0.--31. 1. "TSV,Timer Start Value" rgroup.long 0xF4++0x3 line.long 0x0 "RTI_CVAL,Current RTI Timer Value" hexmask.long 0x0 0.--31. 1. "TVL,Current Timer Value" group.long 0xF8++0x7 line.long 0x0 "RTI_TCTRL,RTI Timer Control" bitfld.long 0x0 1. "TIE,Timer Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x0 0. "TEN,Timer Enable Bit" "0: Disables,1: Enables. The RTI timer begins counting down." line.long 0x4 "RTI_TFLG,RTI Timer Interrupt Flag" eventfld.long 0x4 0. "TIF,Timer Interrupt Flag" "0: Timer still counting down,1: Timer has expired" repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x400B0100 ad:0x400B0110 ad:0x400B0120 ad:0x400B0130) tree "TIMER[$1]" base $2 group.long ($2)++0x3 line.long 0x0 "LDVAL,Timer Load Value" hexmask.long 0x0 0.--31. 1. "TSV,Timer Start Value" rgroup.long ($2+0x4)++0x3 line.long 0x0 "CVAL,Current Timer Value" hexmask.long 0x0 0.--31. 1. "TVL,Timer Value" group.long ($2+0x8)++0x7 line.long 0x0 "TCTRL,Timer Control" bitfld.long 0x0 2. "CHN,Chain Mode" "0: Unchains,1: Chains" bitfld.long 0x0 1. "TIE,Timer Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x0 0. "TEN,Timer Enable" "0: Disables,1: Enables. The timer begins counting down." line.long 0x4 "TFLG,Timer Flag" eventfld.long 0x4 0. "TIF,Timer Interrupt Flag" "0: Timer has not expired,1: Timer expired" tree.end repeat.end tree.end tree "PIT_1" base ad:0x400B4000 group.long 0x0++0x3 line.long 0x0 "MCR,PIT Module Control" bitfld.long 0x0 1. "MDIS,Module Disable for PIT" "0: Enables,1: Disables" bitfld.long 0x0 0. "FRZ,Freeze" "0: Timers run in Debug mode,1: Timers stop in Debug mode" repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x400B4100 ad:0x400B4110 ad:0x400B4120 ad:0x400B4130) tree "TIMER[$1]" base $2 group.long ($2)++0x3 line.long 0x0 "LDVAL,Timer Load Value" hexmask.long 0x0 0.--31. 1. "TSV,Timer Start Value" rgroup.long ($2+0x4)++0x3 line.long 0x0 "CVAL,Current Timer Value" hexmask.long 0x0 0.--31. 1. "TVL,Timer Value" group.long ($2+0x8)++0x7 line.long 0x0 "TCTRL,Timer Control" bitfld.long 0x0 2. "CHN,Chain Mode" "0: Unchains,1: Chains" bitfld.long 0x0 1. "TIE,Timer Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x0 0. "TEN,Timer Enable" "0: Disables,1: Enables. The timer begins counting down." line.long 0x4 "TFLG,Timer Flag" eventfld.long 0x4 0. "TIF,Timer Interrupt Flag" "0: Timer has not expired,1: Timer expired" tree.end repeat.end tree.end tree "PIT_2" base ad:0x402FC000 group.long 0x0++0x3 line.long 0x0 "MCR,PIT Module Control" bitfld.long 0x0 1. "MDIS,Module Disable for PIT" "0: Enables,1: Disables" bitfld.long 0x0 0. "FRZ,Freeze" "0: Timers run in Debug mode,1: Timers stop in Debug mode" repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x402FC100 ad:0x402FC110 ad:0x402FC120 ad:0x402FC130) tree "TIMER[$1]" base $2 group.long ($2)++0x3 line.long 0x0 "LDVAL,Timer Load Value" hexmask.long 0x0 0.--31. 1. "TSV,Timer Start Value" rgroup.long ($2+0x4)++0x3 line.long 0x0 "CVAL,Current Timer Value" hexmask.long 0x0 0.--31. 1. "TVL,Timer Value" group.long ($2+0x8)++0x7 line.long 0x0 "TCTRL,Timer Control" bitfld.long 0x0 2. "CHN,Chain Mode" "0: Unchains,1: Chains" bitfld.long 0x0 1. "TIE,Timer Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x0 0. "TEN,Timer Enable" "0: Disables,1: Enables. The timer begins counting down." line.long 0x4 "TFLG,Timer Flag" eventfld.long 0x4 0. "TIF,Timer Interrupt Flag" "0: Timer has not expired,1: Timer expired" tree.end repeat.end tree.end tree "PIT_3" base ad:0x40300000 group.long 0x0++0x3 line.long 0x0 "MCR,PIT Module Control" bitfld.long 0x0 1. "MDIS,Module Disable for PIT" "0: Enables,1: Disables" bitfld.long 0x0 0. "FRZ,Freeze" "0: Timers run in Debug mode,1: Timers stop in Debug mode" repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x40300100 ad:0x40300110 ad:0x40300120 ad:0x40300130) tree "TIMER[$1]" base $2 group.long ($2)++0x3 line.long 0x0 "LDVAL,Timer Load Value" hexmask.long 0x0 0.--31. 1. "TSV,Timer Start Value" rgroup.long ($2+0x4)++0x3 line.long 0x0 "CVAL,Current Timer Value" hexmask.long 0x0 0.--31. 1. "TVL,Timer Value" group.long ($2+0x8)++0x7 line.long 0x0 "TCTRL,Timer Control" bitfld.long 0x0 2. "CHN,Chain Mode" "0: Unchains,1: Chains" bitfld.long 0x0 1. "TIE,Timer Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x0 0. "TEN,Timer Enable" "0: Disables,1: Enables. The timer begins counting down." line.long 0x4 "TFLG,Timer Flag" eventfld.long 0x4 0. "TIF,Timer Interrupt Flag" "0: Timer has not expired,1: Timer expired" tree.end repeat.end tree.end tree.end tree "PLL (PLL Digital Interface)" base ad:0x0 tree "PLL" base ad:0x402E0000 group.long 0x0++0x13 line.long 0x0 "PLLCR,PLL Control" bitfld.long 0x0 31. "PLLPD,PLL Power Down" "0: Powered up,1: Powered down" line.long 0x4 "PLLSR,PLL Status" eventfld.long 0x4 3. "LOL,Loss-Of-Lock Flag" "0: No loss of lock detected,1: Loss of lock detected" rbitfld.long 0x4 2. "LOCK,Lock Status" "0: Unlocked,1: Locked" line.long 0x8 "PLLDV,PLL Divider" hexmask.long.byte 0x8 25.--30. 1. "ODIV2,Output frequency divider for raw PLL clock." bitfld.long 0x8 12.--14. "RDIV,Input Clock Predivider" "0: Divide by 1,1: Divide by 1,2: Divide by 2,3: Divide by 3,4: Divide by 4,5: Divide by 5,6: Divide by 6,7: Divide by 7" hexmask.long.byte 0x8 0.--7. 1. "MFI,Integer Portion Of Loop Divider" line.long 0xC "PLLFM,PLL Frequency Modulation" bitfld.long 0xC 30. "SSCGBYP,Frequency Modulation (Spread Spectrum Clock Generation) Bypass" "0: Not bypassed,1: Bypassed" bitfld.long 0xC 29. "SPREADCTL,Modulation Type Selection" "?,1: Spread below nominal frequency" hexmask.long.word 0xC 16.--25. 1. "STEPSIZE,Frequency Modulation Step Size" newline hexmask.long.word 0xC 0.--10. 1. "STEPNO,Number Of Steps Of Modulation Period Or Frequency Modulation" line.long 0x10 "PLLFD,PLL Fractional Divider" bitfld.long 0x10 30. "SDMEN,Fractional Mode Enable" "0: Disabled,1: Enabled" bitfld.long 0x10 29. "SDM2,Fractional Mode Configuration" "0,1" bitfld.long 0x10 28. "SDM3,Fractional Mode Configuration" "0,1" newline hexmask.long.word 0x10 0.--14. 1. "MFN,Numerator Of Fractional Loop Division Factor" group.long 0x18++0x3 line.long 0x0 "PLLCAL2,PLL Calibration Register 2" bitfld.long 0x0 7.--8. "ULKCTL,Unlock Control Accuracy" "0: Unlock range = Expected value +/- 9 (recommended..,1: Unlock range = Expected value +/- 17..,2: Unlock range = Expected value +/- 33,3: Unlock range = Expected value +/- 5" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "PLLODIV_[$1],PLL Output Divider" bitfld.long 0x0 31. "DE,Divider Enable" "0: Disabled,1: Enabled" hexmask.long.byte 0x0 16.--23. 1. "DIV,Division Value" repeat.end tree.end tree "PLL_AUX" base ad:0x402E4000 group.long 0x0++0xB line.long 0x0 "PLLCR,PLL Control" bitfld.long 0x0 31. "PLLPD,PLL Power Down" "0: Powered up,1: Powered down" line.long 0x4 "PLLSR,PLL Status" eventfld.long 0x4 3. "LOL,Loss-Of-Lock Flag" "0: No loss of lock detected,1: Loss of lock detected" rbitfld.long 0x4 2. "LOCK,Lock Status" "0: Unlocked,1: Locked" line.long 0x8 "PLLDV,PLL Divider" hexmask.long.byte 0x8 25.--30. 1. "ODIV2,Output frequency divider for raw PLL clock." bitfld.long 0x8 12.--14. "RDIV,Input Clock Predivider" "0: Divide by 1,1: Divide by 1,2: Divide by 2,3: Divide by 3,4: Divide by 4,5: Divide by 5,6: Divide by 6,7: Divide by 7" hexmask.long.byte 0x8 0.--7. 1. "MFI,Integer Portion Of Loop Divider" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "PLLODIV_[$1],PLL Output Divider" bitfld.long 0x0 31. "DE,Divider Enable" "0: Disabled,1: Enabled" hexmask.long.byte 0x0 16.--20. 1. "DIV,Division Value" repeat.end tree.end tree.end tree "PMC (Power Management Controller)" base ad:0x402E8000 group.long 0x0++0xB line.long 0x0 "LVSC,Low Voltage Status and Control" eventfld.long 0x0 31. "PORF,POR Flag" "0: No POR event,1: POR event" eventfld.long 0x0 27. "GNG11OSC2F,Go/NoGo Detect Flag On Second PLL Part Of V11 Domain" "0: No event,1: NoGo event" eventfld.long 0x0 26. "GNG25OSC2F,GO/NoGo Detect Flag On Second PLL Part Of V25 Domain" "0: No event,1: NoGo event" newline eventfld.long 0x0 25. "GNG11OSCF,Go/NoGo Detect Flag On Osc Part Of V11 Domain" "0: No event,1: NoGo event" eventfld.long 0x0 24. "GNG25OSCF,GO/NoGo Detect Flag On Osc Part Of V25 Domain" "0: No event,1: NoGo event" eventfld.long 0x0 23. "LVR11LPF,LVR11LP Flag On V11 Domain" "0: No event,1: Event" newline eventfld.long 0x0 22. "LVR11F,LVR11 Flag On V11 Domain In FPM" "0: No event,1: Event" eventfld.long 0x0 21. "LVR25LPF,LVR25LP Flag On V25 Domain" "0: No event,1: Event" eventfld.long 0x0 20. "LVR25F,LVR25 Flag On V25 Domain In FPM" "0: No event,1: Event" newline eventfld.long 0x0 19. "LVRBLPF,LVRBLP Flag On VDD_HV_B Domain" "0: No event,1: Event" eventfld.long 0x0 18. "LVRBF,LVRB Flag On VDD_HV_B Domain In FPM" "0: No event,1: Event" eventfld.long 0x0 17. "LVRALPF,LVRALP Flag On VDD_HV_A Domain" "0: No event,1: Event" newline eventfld.long 0x0 16. "LVRAF,LVRA Flag On VDD_HV_A Domain In FPM" "0: No event,1: Event" rbitfld.long 0x0 14. "HVD15S,HVD15 Status On V15 Domain In FPM" "0: Below threshold or LPM,1: Above threshold and FPM" rbitfld.long 0x0 12. "LVD5AS,LVD5A Status On VDD_HV_A Domain In FPM" "0: Above threshold,1: Below threshold" newline rbitfld.long 0x0 11. "HVD11S,HVD11 Status On V11 Domain In FPM" "0: Below threshold or LPM,1: Above threshold and FPM" rbitfld.long 0x0 10. "HVD25S,HVD25 Status On V25 Domain In FPM" "0: Below threshold or LPM,1: Above threshold and FPM" rbitfld.long 0x0 9. "HVDBS,HVDB Status On VDD_HV_B Domain In FPM" "0: Below threshold or LPM,1: Above threshold and FPM" newline rbitfld.long 0x0 8. "HVDAS,HVDA Status On VDD_HV_A Domain In FPM" "0: Below threshold or LPM,1: Above threshold and FPM" eventfld.long 0x0 6. "HVD15F,HVD15 Flag On V15 Domain In FPM" "0: Not changed,1: Changed" eventfld.long 0x0 4. "LVD5AF,LVD5A Flag On VDD_HV_A Domain In FPM" "0: Not changed,1: Changed" newline eventfld.long 0x0 3. "HVD11F,HVD11 Flag On V11 Domain In FPM" "0: Not changed,1: Changed" eventfld.long 0x0 2. "HVD25F,HVD25 Flag On V25 Domain In FPM" "0: Not changed,1: Changed" eventfld.long 0x0 1. "HVDBF,HVDB Flag On VDD_HV_B Domain In FPM" "0: Not changed,1: Changed" newline eventfld.long 0x0 0. "HVDAF,HVDA Flag On VDD_HV_A Domain In FPM" "0: Not changed,1: Changed" line.long 0x4 "CONFIG,PMC Configuration" bitfld.long 0x4 9. "LVDIE,Low Voltage Detect Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x4 8. "HVDIE,HVD Interrupt Enable" "0: Disables,1: Enables" bitfld.long 0x4 7. "LMSMPSEN,V15 Switched-Mode Power Supply Enable" "0: Disables,1: Enables" newline bitfld.long 0x4 4. "LVRBLPEN,LVRBLP Enable During LPM" "0: Disables,1: Enables" bitfld.long 0x4 3. "LPM25EN,V25 Domain Enable During LPM" "0: Disables,1: Enables" rbitfld.long 0x4 0. "LMEN,Last Mile Regulator Enable" "0,1" line.long 0x8 "SMPSCONFIG,SMPS Configuration" hexmask.long.byte 0x8 24.--28. 1. "ONTIME5V,SMPS Duty Cycle For 5 V Range" rbitfld.long 0x8 23. "PGATES,PMOS_CTRL Status" "0: Driven to VSS_DCDC,1: Driven to VDD_DCDC" hexmask.long.byte 0x8 16.--20. 1. "ONTIME3V,SMPS Duty Cycle For 3 V Range" newline hexmask.long.byte 0x8 8.--12. 1. "PERIOD,SMPS Period" bitfld.long 0x8 7. "DITHEREN,IRC Dither Enable" "0: Disables,1: Enables" bitfld.long 0x8 5.--6. "DITHERCFG,IRC Dither Configuration" "0,1,2,3" newline bitfld.long 0x8 4. "LPM15EN,V15 Domain Enable During LPM" "0: Not kept on target,1: Kept on target" hexmask.long.byte 0x8 0.--3. 1. "CFG,SMPS Configuration Select" rgroup.long 0xC++0x3 line.long 0x0 "VERID,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" bitfld.long 0x0 0. "LMFEAT,Last Mile Regulator Feature" "0: Not available,1: Available" tree.end tree "PRAMC (RAM Controller)" base ad:0x0 tree "PRAMC_0" base ad:0x40264000 group.long 0x0++0x3 line.long 0x0 "PRCR1,Platform RAM Configuration register 1" bitfld.long 0x0 6. "P0_BO_DIS,Port p0 read burst optimization disable." "0: 64-bit WRP4 read bursts are optimized such that..,1: 64-bit WRP4 read bursts are not optimized; the.." bitfld.long 0x0 0. "FT_DIS,Flow-through disabled" "0: RAM read data is passed directly to the system..,1: RAM read data is registered prior to returning.." tree.end tree "PRAMC_1" base ad:0x40464000 group.long 0x0++0x3 line.long 0x0 "PRCR1,Platform RAM Configuration register 1" bitfld.long 0x0 6. "P0_BO_DIS,Port p0 read burst optimization disable." "0: 64-bit WRP4 read bursts are optimized such that..,1: 64-bit WRP4 read bursts are not optimized; the.." bitfld.long 0x0 0. "FT_DIS,Flow-through disabled" "0: RAM read data is passed directly to the system..,1: RAM read data is registered prior to returning.." tree.end tree "PRAMC_2" base ad:0x40468000 group.long 0x0++0x3 line.long 0x0 "PRCR1,Platform RAM Configuration register 1" bitfld.long 0x0 6. "P0_BO_DIS,Port p0 read burst optimization disable." "0: 64-bit WRP4 read bursts are optimized such that..,1: 64-bit WRP4 read bursts are not optimized; the.." bitfld.long 0x0 0. "FT_DIS,Flow-through disabled" "0: RAM read data is passed directly to the system..,1: RAM read data is registered prior to returning.." tree.end tree.end tree "QUADSPI (Quad Serial Peripheral Interface)" base ad:0x0 tree "QUADSPI" base ad:0x404CC000 group.long 0x0++0x3 line.long 0x0 "MCR,Module Configuration Register" bitfld.long 0x0 24.--25. "DQS_FA_SEL,DQS clock for sampling read data at flash memory A" "0,1,2,3" newline bitfld.long 0x0 17. "ISD3FA,Idle signal drive IOFA[3] flash memory A" "0: IOFA[3] is driven to logic L,1: IOFA[3] is driven to logic H" newline bitfld.long 0x0 16. "ISD2FA,Idle signal drive IOFA[2] flash memory A" "0: IOFA[2] is driven to logic L.,1: IOFA[2] is driven to logic H." newline bitfld.long 0x0 14. "MDIS,Module disable" "0: Enable QuadSPI clocks,1: Allow external logic to disable QuadSPI clocks" newline bitfld.long 0x0 11. "CLR_TXF,Clear TX FIFO/buffer" "0: No action,1: Read and write pointers of the TX buffer are.." newline bitfld.long 0x0 10. "CLR_RXF,Clear RX FIFO" "0: No action,1: Read and write pointers of the RX buffer are.." newline bitfld.long 0x0 1. "SWRSTHD,Software reset for AHB domain" "0,1" newline bitfld.long 0x0 0. "SWRSTSD,Software reset for serial flash memory domain" "0,1" group.long 0x8++0x1F line.long 0x0 "IPCR,IP Configuration Register" hexmask.long.byte 0x0 24.--27. 1. "SEQID,Points to a sequence in the LUT" newline bitfld.long 0x0 23. "ARB_UNLOCK,Arbitration Unlock" "0,1" newline bitfld.long 0x0 22. "ARB_LOCK,Arbitration Lock" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "IDATSZ,IP data transfer size" line.long 0x4 "FLSHCR,Flash Memory Configuration Register" bitfld.long 0x4 16.--17. "TDH,Serial flash memory data in hold time" "0: Data aligned with the posedge of internal..,1: Data aligned with 2x serial flash memory half..,?,?" newline hexmask.long.byte 0x4 8.--11. 1. "TCSH,Serial flash memory CS hold time" newline hexmask.long.byte 0x4 0.--3. 1. "TCSS,Serial flash memory CS setup time" line.long 0x8 "BUF0CR,Buffer 0 Configuration Register" bitfld.long 0x8 31. "HP_EN,High priority enable" "0,1" newline hexmask.long.byte 0x8 8.--15. 1. "ADATSZ,AHB data transfer size" newline hexmask.long.byte 0x8 0.--3. 1. "MSTRID,Master ID" line.long 0xC "BUF1CR,Buffer 1 Configuration Register" hexmask.long.byte 0xC 8.--15. 1. "ADATSZ,AHB data transfer size" newline hexmask.long.byte 0xC 0.--3. 1. "MSTRID,Master ID" line.long 0x10 "BUF2CR,Buffer 2 Configuration Register" hexmask.long.byte 0x10 8.--15. 1. "ADATSZ,AHB data transfer size" newline hexmask.long.byte 0x10 0.--3. 1. "MSTRID,Master ID" line.long 0x14 "BUF3CR,Buffer 3 Configuration Register" bitfld.long 0x14 31. "ALLMST,All master enable" "0,1" newline hexmask.long.byte 0x14 8.--15. 1. "ADATSZ,AHB data transfer size" newline hexmask.long.byte 0x14 0.--3. 1. "MSTRID,Master ID" line.long 0x18 "BFGENCR,Buffer Generic Configuration Register" hexmask.long.byte 0x18 12.--15. 1. "SEQID,Points to a sequence in the LUT." line.long 0x1C "SOCCR,SOC Configuration Register" hexmask.long 0x1C 0.--31. 1. "SOCCFG,SOC configuration" group.long 0x30++0xB line.long 0x0 "BUF0IND,Buffer 0 Top Index Register" hexmask.long.byte 0x0 3.--10. 1. "TPINDX0,Top index of buffer 0" line.long 0x4 "BUF1IND,Buffer 1 Top Index Register" hexmask.long.byte 0x4 3.--10. 1. "TPINDX1,Top index of buffer 1" line.long 0x8 "BUF2IND,Buffer 2 Top Index Register" hexmask.long.byte 0x8 3.--10. 1. "TPINDX2,Top index of buffer 2" group.long 0x60++0x3 line.long 0x0 "DLLCRA,DLL Flash Memory A Configuration Register" bitfld.long 0x0 31. "DLLEN,DLL enable" "0: DLL reference logic remains in reset and should..,1: Enables DLL logic. Set it to 1 after all the.." newline bitfld.long 0x0 30. "FREQEN,Frequency enable" "0: Selects delay chain for low frequency of operation,1: Selects delay chain for high frequency of.." newline hexmask.long.byte 0x0 24.--27. 1. "DLL_REFCNTR,DLL reference counter" newline hexmask.long.byte 0x0 20.--23. 1. "DLLRES,DLL resolution" newline hexmask.long.byte 0x0 16.--19. 1. "SLV_FINE_OFFSET,Fine offset delay elements in incoming DQS" newline bitfld.long 0x0 12.--14. "SLV_DLY_OFFSET,T/16 offset delay elements in incoming DQS" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "SLV_DLY_COARSE,Delay elements in each delay tap" newline bitfld.long 0x0 4. "DLL_CDL8,DLL CDL8 Enable" "0: DLL is implemented to support within 2x variation,1: DLL is implemented to support within 3x.." newline bitfld.long 0x0 3. "SLAVE_AUTO_UPDT,Slave chain update" "0: Auto-update feature is disabled.,1: Auto-update feature is enabled." newline bitfld.long 0x0 2. "SLV_EN,Slave enable" "0: DLL slave logic remains in reset and its value..,1: Enables DQS slave delay chain and should be 1.." newline bitfld.long 0x0 1. "SLV_DLL_BYPASS,Slave DLL bypass" "0: Disables manual selection of coarse delays in..,1: Enables selection of number of delays in each.." newline bitfld.long 0x0 0. "SLV_UPD,Slave update" "0: Disables any further update on DQS slave delay..,1: Updates the DQS slave delay chain with either.." group.long 0x100++0xB line.long 0x0 "SFAR,Serial Flash Memory Address Register" hexmask.long 0x0 0.--31. 1. "SFADR,Serial flash memory address" line.long 0x4 "SFACR,Serial Flash Memory Address Configuration Register" bitfld.long 0x4 20. "CAS_INTRLVD,CAS Interleaving" "0: CAS interleaving is disabled,1: CAS interleaving is enabled" newline bitfld.long 0x4 16. "WA,Word addressable" "0: Byte addressable serial flash memory mode,1: Word (2-byte) addressable serial flash memory mode" newline hexmask.long.byte 0x4 0.--3. 1. "CAS,Column address space" line.long 0x8 "SMPR,Sampling Register" bitfld.long 0x8 24.--26. "DLLFSMPFA,Selects the nth tap provided by slave delay chain for flash memory A" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6. "FSDLY,Full-speed delay selection for internal/pad loop back DQS sampling" "0,1" newline bitfld.long 0x8 5. "FSPHS,Full-speed phase selection for SDR instructions" "0,1" rgroup.long 0x10C++0x3 line.long 0x0 "RBSR,RX Buffer Status Register" hexmask.long.word 0x0 16.--31. 1. "RDCTR,Read counter" newline hexmask.long.byte 0x0 0.--5. 1. "RDBFL,RX buffer fill level" group.long 0x110++0x3 line.long 0x0 "RBCT,RX Buffer Control Register" hexmask.long.byte 0x0 0.--4. 1. "WMRK,RX buffer watermark" rgroup.long 0x12C++0x3 line.long 0x0 "DLLSR,DLL Status Register" bitfld.long 0x0 15. "DLLA_LOCK,DLL A lock status" "0,1" newline bitfld.long 0x0 14. "SLVA_LOCK,Slave high lock status" "0,1" newline bitfld.long 0x0 13. "DLLA_RANGE_ERR,DLL master delay chain" "0,1" newline bitfld.long 0x0 12. "DLLA_FINE_UNDERFLOW,Fine delay chain underflow" "0,1" newline hexmask.long.byte 0x0 4.--7. 1. "DLLA_SLV_FINE_VAL,Fine delay cells in slave delay chain" newline hexmask.long.byte 0x0 0.--3. 1. "DLLA_SLV_COARSE_VAL,Coarse delay cells in slave delay chain" rgroup.long 0x134++0x3 line.long 0x0 "DLSR_FA,Data Learning Status Flash Memory A Register" bitfld.long 0x0 31. "DLPFFA,Data learning pattern fail" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "POS_EDGE,DLP positive edge match signature for flash memory A" newline hexmask.long.byte 0x0 0.--7. 1. "NEG_EDGE,DLP negative edge match signature for flash memory A" rgroup.long 0x150++0x3 line.long 0x0 "TBSR,TX Buffer Status Register" hexmask.long.word 0x0 16.--31. 1. "TRCTR,Transmit counter" newline hexmask.long.word 0x0 0.--8. 1. "TRBFL,TX buffer fill level" group.long 0x154++0x7 line.long 0x0 "TBDR,TX Buffer Data Register" hexmask.long 0x0 0.--31. 1. "TXDATA,TX data" line.long 0x4 "TBCT,TX Buffer Control Register" hexmask.long.byte 0x4 0.--7. 1. "WMRK,Watermark for TX buffer" rgroup.long 0x15C++0x3 line.long 0x0 "SR,Status Register" bitfld.long 0x0 27. "TXFULL,TX buffer full" "0,1" newline bitfld.long 0x0 26. "TXDMA,TX DMA" "0,1" newline bitfld.long 0x0 25. "TXWA,TX buffer watermark available" "0,1" newline bitfld.long 0x0 24. "TXNE,TX buffer not empty" "0,1" newline bitfld.long 0x0 23. "RXDMA,RX buffer DMA" "0,1" newline bitfld.long 0x0 19. "RXFULL,RX buffer full" "0,1" newline bitfld.long 0x0 16. "RXWE,RX buffer watermark exceeded" "0,1" newline bitfld.long 0x0 14. "AHB3FUL,AHB 3 buffer full" "0,1" newline bitfld.long 0x0 13. "AHB2FUL,AHB 2 buffer full" "0,1" newline bitfld.long 0x0 12. "AHB1FUL,AHB 1 buffer full" "0,1" newline bitfld.long 0x0 11. "AHB0FUL,AHB 0 buffer full" "0,1" newline bitfld.long 0x0 10. "AHB3NE,AHB 3 buffer not empty" "0,1" newline bitfld.long 0x0 9. "AHB2NE,AHB 2 buffer not empty" "0,1" newline bitfld.long 0x0 8. "AHB1NE,AHB 1 buffer not empty" "0,1" newline bitfld.long 0x0 7. "AHB0NE,AHB 0 buffer not empty" "0,1" newline bitfld.long 0x0 6. "AHBTRN,AHB access transaction pending" "0,1" newline bitfld.long 0x0 2. "AHB_ACC,AHB read access" "0,1" newline bitfld.long 0x0 1. "IP_ACC,IP access" "0,1" newline bitfld.long 0x0 0. "BUSY,Module busy" "0,1" group.long 0x160++0x7 line.long 0x0 "FR,Flag Register" eventfld.long 0x0 28. "DLLABRT,DLL abort" "?,1: This field is set whenever DLL is unlocked while.." newline eventfld.long 0x0 27. "TBFF,TX buffer fill flag" "0,1" newline eventfld.long 0x0 26. "TBUF,TX buffer underrun flag" "0,1" newline eventfld.long 0x0 24. "DLLUNLCK,DLL unlock" "?,1: This field is set whenever DLL unlock event.." newline eventfld.long 0x0 23. "ILLINE,Illegal instruction error flag" "0,1" newline eventfld.long 0x0 17. "RBOF,RX buffer overflow flag" "0,1" newline eventfld.long 0x0 16. "RBDF,RX buffer drain flag" "0,1" newline eventfld.long 0x0 14. "AITEF,AHB illegal transaction error flag" "0,1" newline eventfld.long 0x0 13. "AIBSEF,AHB illegal burst size error flag" "0,1" newline eventfld.long 0x0 12. "ABOF,AHB buffer overflow flag" "0,1" newline eventfld.long 0x0 10. "CRCAEF,Sets when there is CRC or ECC error for flash memory A" "0: CRCEF interrupt is not generated.,1: CRCEF interrupt is generated." newline eventfld.long 0x0 6. "IPIEF,IP command trigger could not be executed error flag" "0,1" newline eventfld.long 0x0 0. "TFF,IP command transaction finished flag" "0,1" line.long 0x4 "RSER,Interrupt and DMA Request Select and Enable Register" bitfld.long 0x4 27. "TBFIE,TX buffer fill interrupt enable flag" "0: No TBFF interrupt is generated.,1: TBFF interrupt is generated." newline bitfld.long 0x4 26. "TBUIE,TX buffer underrun interrupt enable flag" "0: No TBUF interrupt is generated,1: TBUF interrupt is generated" newline bitfld.long 0x4 25. "TBFDE,TX buffer fill DMA enable" "0: No DMA request is generated,1: DMA request is generated" newline bitfld.long 0x4 24. "DLLULIE,DLL unlock interrupt enable" "?,1: Write 1 to this to enable generation of.." newline bitfld.long 0x4 23. "ILLINIE,Illegal instruction error interrupt enable" "0: No ILLINE interrupt is generated.,1: ILLINE interrupt is generated." newline bitfld.long 0x4 21. "RBDDE,RX buffer drain DMA enable" "0: No DMA request is generated.,1: DMA request is generated." newline bitfld.long 0x4 17. "RBOIE,RX buffer overflow interrupt enable" "0: No RBOF interrupt is generated.,1: RBOF interrupt is generated." newline bitfld.long 0x4 16. "RBDIE,RX buffer drain interrupt enable" "0: No RBDF interrupt is generated.,1: RBDF Interrupt is generated." newline bitfld.long 0x4 14. "AITIE,AHB illegal transaction interrupt enable flag" "0: No AITEF interrupt is generated.,1: AITEF interrupt is generated." newline bitfld.long 0x4 13. "AIBSIE,AHB illegal burst size interrupt enable flag" "0: No AIBSEF interrupt is generated.,1: AIBSEF interrupt is generated." newline bitfld.long 0x4 12. "ABOIE,AHB buffer overflow interrupt enable flag" "0: No ABOF interrupt is generated.,1: ABOF interrupt is generated." newline bitfld.long 0x4 10. "CRCAIE,CRC and ECC interrupt enable for flash memory A" "0: CRCAEF interrupt is not generated.,1: CRCAEF interrupt is generated." newline bitfld.long 0x4 6. "IPIEIE,IP command trigger during IP access error interrupt enable flag" "0: No IPIEF interrupt is generated,1: IPIEF interrupt is generated" newline bitfld.long 0x4 0. "TFIE,Transaction finished interrupt enable flag" "0: No TFF interrupt is generated.,1: TFF interrupt is generated." rgroup.long 0x168++0x3 line.long 0x0 "SPNDST,Sequence Suspend Status Register" hexmask.long.byte 0x0 9.--15. 1. "DATLFT,Data left" newline bitfld.long 0x0 6.--7. "SPDBUF,Suspended buffer" "0,1,2,3" newline bitfld.long 0x0 0. "SUSPND,Suspended state" "0,1" group.long 0x16C++0x3 line.long 0x0 "SPTRCLR,Sequence Pointer Clear Register" bitfld.long 0x0 8. "IPPTRC,IP pointer clear" "?,1: Clears the sequence pointer for IP accesses as.." newline bitfld.long 0x0 0. "BFPTRC,Buffer pointer clear" "?,1: Clears the sequence pointer for AHB read.." group.long 0x180++0x7 line.long 0x0 "SFA1AD,Serial Flash Memory A1 Top Address Register" hexmask.long.tbyte 0x0 10.--31. 1. "TPADA1,Top address for serial flash memory A1" line.long 0x4 "SFA2AD,Serial Flash Memory A2 Top Address Register" hexmask.long.tbyte 0x4 10.--31. 1. "TPADA2,Top address for serial flash memory A2" repeat 32. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x200)++0x3 line.long 0x0 "RBDR[$1],RX Buffer Data Register" hexmask.long 0x0 0.--31. 1. "RXDATA,RX data" repeat.end group.long 0x300++0x7 line.long 0x0 "LUTKEY,LUT Key Register" hexmask.long 0x0 0.--31. 1. "KEY,Key to lock or unlock the LUT" line.long 0x4 "LCKCR,LUT Lock Configuration Register" bitfld.long 0x4 1. "UNLOCK,Unlock LUT" "0,1" newline bitfld.long 0x4 0. "LOCK,Lock LUT" "0,1" group.long 0x310++0x13F line.long 0x0 "LUT0,LUT Register" hexmask.long.byte 0x0 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x0 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x0 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x0 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x0 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x0 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x4 "LUT1,LUT Register" hexmask.long.byte 0x4 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x4 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x4 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x4 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x4 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x4 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x8 "LUT2,LUT Register" hexmask.long.byte 0x8 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x8 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x8 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x8 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x8 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x8 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xC "LUT3,LUT Register" hexmask.long.byte 0xC 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xC 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xC 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xC 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xC 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xC 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x10 "LUT4,LUT Register" hexmask.long.byte 0x10 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x10 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x10 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x10 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x10 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x10 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x14 "LUT5,LUT Register" hexmask.long.byte 0x14 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x14 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x14 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x14 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x14 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x14 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x18 "LUT6,LUT Register" hexmask.long.byte 0x18 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x18 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x18 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x18 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x18 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x18 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x1C "LUT7,LUT Register" hexmask.long.byte 0x1C 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x1C 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x1C 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x1C 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x1C 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x1C 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x20 "LUT8,LUT Register" hexmask.long.byte 0x20 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x20 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x20 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x20 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x20 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x20 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x24 "LUT9,LUT Register" hexmask.long.byte 0x24 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x24 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x24 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x24 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x24 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x24 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x28 "LUT10,LUT Register" hexmask.long.byte 0x28 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x28 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x28 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x28 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x28 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x28 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x2C "LUT11,LUT Register" hexmask.long.byte 0x2C 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x2C 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x2C 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x2C 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x2C 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x2C 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x30 "LUT12,LUT Register" hexmask.long.byte 0x30 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x30 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x30 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x30 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x30 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x30 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x34 "LUT13,LUT Register" hexmask.long.byte 0x34 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x34 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x34 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x34 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x34 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x34 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x38 "LUT14,LUT Register" hexmask.long.byte 0x38 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x38 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x38 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x38 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x38 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x38 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x3C "LUT15,LUT Register" hexmask.long.byte 0x3C 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x3C 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x3C 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x3C 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x3C 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x3C 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x40 "LUT16,LUT Register" hexmask.long.byte 0x40 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x40 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x40 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x40 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x40 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x40 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x44 "LUT17,LUT Register" hexmask.long.byte 0x44 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x44 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x44 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x44 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x44 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x44 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x48 "LUT18,LUT Register" hexmask.long.byte 0x48 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x48 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x48 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x48 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x48 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x48 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x4C "LUT19,LUT Register" hexmask.long.byte 0x4C 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x4C 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x4C 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x4C 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x4C 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x4C 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x50 "LUT20,LUT Register" hexmask.long.byte 0x50 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x50 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x50 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x50 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x50 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x50 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x54 "LUT21,LUT Register" hexmask.long.byte 0x54 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x54 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x54 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x54 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x54 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x54 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x58 "LUT22,LUT Register" hexmask.long.byte 0x58 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x58 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x58 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x58 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x58 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x58 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x5C "LUT23,LUT Register" hexmask.long.byte 0x5C 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x5C 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x5C 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x5C 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x5C 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x5C 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x60 "LUT24,LUT Register" hexmask.long.byte 0x60 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x60 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x60 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x60 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x60 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x60 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x64 "LUT25,LUT Register" hexmask.long.byte 0x64 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x64 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x64 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x64 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x64 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x64 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x68 "LUT26,LUT Register" hexmask.long.byte 0x68 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x68 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x68 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x68 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x68 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x68 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x6C "LUT27,LUT Register" hexmask.long.byte 0x6C 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x6C 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x6C 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x6C 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x6C 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x6C 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x70 "LUT28,LUT Register" hexmask.long.byte 0x70 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x70 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x70 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x70 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x70 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x70 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x74 "LUT29,LUT Register" hexmask.long.byte 0x74 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x74 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x74 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x74 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x74 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x74 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x78 "LUT30,LUT Register" hexmask.long.byte 0x78 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x78 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x78 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x78 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x78 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x78 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x7C "LUT31,LUT Register" hexmask.long.byte 0x7C 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x7C 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x7C 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x7C 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x7C 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x7C 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x80 "LUT32,LUT Register" hexmask.long.byte 0x80 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x80 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x80 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x80 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x80 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x80 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x84 "LUT33,LUT Register" hexmask.long.byte 0x84 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x84 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x84 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x84 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x84 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x84 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x88 "LUT34,LUT Register" hexmask.long.byte 0x88 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x88 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x88 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x88 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x88 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x88 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x8C "LUT35,LUT Register" hexmask.long.byte 0x8C 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x8C 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x8C 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x8C 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x8C 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x8C 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x90 "LUT36,LUT Register" hexmask.long.byte 0x90 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x90 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x90 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x90 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x90 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x90 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x94 "LUT37,LUT Register" hexmask.long.byte 0x94 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x94 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x94 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x94 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x94 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x94 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x98 "LUT38,LUT Register" hexmask.long.byte 0x98 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x98 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x98 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x98 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x98 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x98 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x9C "LUT39,LUT Register" hexmask.long.byte 0x9C 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x9C 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x9C 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x9C 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x9C 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x9C 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xA0 "LUT40,LUT Register" hexmask.long.byte 0xA0 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xA0 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xA0 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xA0 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xA0 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xA0 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xA4 "LUT41,LUT Register" hexmask.long.byte 0xA4 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xA4 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xA4 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xA4 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xA4 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xA4 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xA8 "LUT42,LUT Register" hexmask.long.byte 0xA8 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xA8 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xA8 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xA8 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xA8 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xA8 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xAC "LUT43,LUT Register" hexmask.long.byte 0xAC 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xAC 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xAC 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xAC 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xAC 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xAC 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xB0 "LUT44,LUT Register" hexmask.long.byte 0xB0 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xB0 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xB0 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xB0 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xB0 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xB0 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xB4 "LUT45,LUT Register" hexmask.long.byte 0xB4 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xB4 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xB4 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xB4 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xB4 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xB4 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xB8 "LUT46,LUT Register" hexmask.long.byte 0xB8 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xB8 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xB8 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xB8 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xB8 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xB8 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xBC "LUT47,LUT Register" hexmask.long.byte 0xBC 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xBC 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xBC 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xBC 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xBC 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xBC 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xC0 "LUT48,LUT Register" hexmask.long.byte 0xC0 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xC0 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xC0 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xC0 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xC0 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xC0 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xC4 "LUT49,LUT Register" hexmask.long.byte 0xC4 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xC4 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xC4 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xC4 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xC4 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xC4 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xC8 "LUT50,LUT Register" hexmask.long.byte 0xC8 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xC8 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xC8 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xC8 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xC8 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xC8 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xCC "LUT51,LUT Register" hexmask.long.byte 0xCC 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xCC 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xCC 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xCC 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xCC 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xCC 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xD0 "LUT52,LUT Register" hexmask.long.byte 0xD0 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xD0 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xD0 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xD0 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xD0 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xD0 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xD4 "LUT53,LUT Register" hexmask.long.byte 0xD4 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xD4 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xD4 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xD4 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xD4 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xD4 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xD8 "LUT54,LUT Register" hexmask.long.byte 0xD8 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xD8 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xD8 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xD8 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xD8 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xD8 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xDC "LUT55,LUT Register" hexmask.long.byte 0xDC 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xDC 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xDC 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xDC 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xDC 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xDC 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xE0 "LUT56,LUT Register" hexmask.long.byte 0xE0 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xE0 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xE0 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xE0 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xE0 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xE0 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xE4 "LUT57,LUT Register" hexmask.long.byte 0xE4 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xE4 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xE4 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xE4 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xE4 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xE4 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xE8 "LUT58,LUT Register" hexmask.long.byte 0xE8 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xE8 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xE8 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xE8 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xE8 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xE8 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xEC "LUT59,LUT Register" hexmask.long.byte 0xEC 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xEC 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xEC 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xEC 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xEC 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xEC 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xF0 "LUT60,LUT Register" hexmask.long.byte 0xF0 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xF0 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xF0 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xF0 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xF0 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xF0 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xF4 "LUT61,LUT Register" hexmask.long.byte 0xF4 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xF4 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xF4 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xF4 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xF4 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xF4 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xF8 "LUT62,LUT Register" hexmask.long.byte 0xF8 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xF8 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xF8 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xF8 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xF8 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xF8 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0xFC "LUT63,LUT Register" hexmask.long.byte 0xFC 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0xFC 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xFC 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0xFC 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0xFC 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0xFC 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x100 "LUT64,LUT Register" hexmask.long.byte 0x100 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x100 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x100 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x100 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x100 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x100 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x104 "LUT65,LUT Register" hexmask.long.byte 0x104 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x104 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x104 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x104 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x104 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x104 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x108 "LUT66,LUT Register" hexmask.long.byte 0x108 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x108 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x108 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x108 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x108 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x108 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x10C "LUT67,LUT Register" hexmask.long.byte 0x10C 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x10C 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x10C 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x10C 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x10C 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x10C 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x110 "LUT68,LUT Register" hexmask.long.byte 0x110 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x110 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x110 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x110 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x110 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x110 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x114 "LUT69,LUT Register" hexmask.long.byte 0x114 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x114 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x114 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x114 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x114 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x114 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x118 "LUT70,LUT Register" hexmask.long.byte 0x118 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x118 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x118 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x118 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x118 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x118 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x11C "LUT71,LUT Register" hexmask.long.byte 0x11C 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x11C 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x11C 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x11C 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x11C 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x11C 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x120 "LUT72,LUT Register" hexmask.long.byte 0x120 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x120 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x120 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x120 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x120 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x120 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x124 "LUT73,LUT Register" hexmask.long.byte 0x124 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x124 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x124 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x124 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x124 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x124 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x128 "LUT74,LUT Register" hexmask.long.byte 0x128 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x128 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x128 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x128 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x128 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x128 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x12C "LUT75,LUT Register" hexmask.long.byte 0x12C 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x12C 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x12C 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x12C 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x12C 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x12C 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x130 "LUT76,LUT Register" hexmask.long.byte 0x130 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x130 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x130 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x130 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x130 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x130 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x134 "LUT77,LUT Register" hexmask.long.byte 0x134 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x134 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x134 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x134 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x134 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x134 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x138 "LUT78,LUT Register" hexmask.long.byte 0x138 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x138 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x138 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x138 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x138 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x138 0.--7. 1. "OPRND0,Operand for INSTR0" line.long 0x13C "LUT79,LUT Register" hexmask.long.byte 0x13C 26.--31. 1. "INSTR1,Instruction 1" newline bitfld.long 0x13C 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x13C 16.--23. 1. "OPRND1,Operand for INSTR1" newline hexmask.long.byte 0x13C 10.--15. 1. "INSTR0,Instruction 0" newline bitfld.long 0x13C 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: NA" newline hexmask.long.byte 0x13C 0.--7. 1. "OPRND0,Operand for INSTR0" repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x404CC800 ad:0x404CC820 ad:0x404CC840 ad:0x404CC860 ad:0x404CC880 ad:0x404CC8A0 ad:0x404CC8C0 ad:0x404CC8E0) tree "FRAD[$1]" base $2 group.long ($2)++0xF line.long 0x0 "FRAD_WORD0,Flash Region Start Address" hexmask.long.word 0x0 16.--31. 1. "STARTADR,Start Address" line.long 0x4 "FRAD_WORD1,Flash Region End Address" hexmask.long.word 0x4 16.--31. 1. "ENDADR,End Address" line.long 0x8 "FRAD_WORD2,Flash Region Privileges" hexmask.long.byte 0x8 24.--29. 1. "EALO,Exclusive Access Lock Owner" bitfld.long 0x8 3.--5. "MD1ACP,Master Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MD0ACP,Master Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "FRAD_WORD3,Flash Region Lock Control" bitfld.long 0xC 31. "VLD,Valid" "0: FRAD-Assignment is invalid,1: FRAD-Assignment is valid" bitfld.long 0xC 29.--30. "LOCK,Descriptor Lock" "0: Lock disabled. Descriptor registers can be..,1: Lock disabled. Descriptor registers can be..,2: Lock enabled. Descriptors are read-only. MDnACP..,3: Lock enabled. Descriptor registers are read-only." newline bitfld.long 0xC 24.--25. "EAL,Exclusive Access Lock" "0: No lock. Write permissions available for all..,1: NA,2: Lock enabled. Write permissions revoked for all..,3: Lock enabled. Exclusive write permission for.." rgroup.long ($2+0x10)++0x7 line.long 0x0 "FRAD_WORD4,Flash Region Compare Address Status" hexmask.long 0x0 0.--31. 1. "CMP_ADDR,Capture Address" line.long 0x4 "FRAD_WORD5,Flash Region Compare Status Data" bitfld.long 0x4 30. "CMPVALID,Comparison Valid" "0: Access result/status not available,1: Access result/status is available" bitfld.long 0x4 29. "CMP_ERR,Comparison Error" "0: No error,1: Access error" newline bitfld.long 0x4 7. "CMP_PA,Capture Privilege Attribute" "0: Non-privilege transaction,1: Privilege transaction" bitfld.long 0x4 6. "CMP_SA,Capture Secure Attribute" "0: Non-secure transaction,1: Secure transaction" newline hexmask.long.byte 0x4 0.--5. 1. "CMP_MDID,Capture MDID Value" tree.end repeat.end repeat 2. (list 0x0 0x1)(list ad:0x404CC900 ad:0x404CC910) tree "MDAD[$1]" base $2 group.long ($2)++0x3 line.long 0x0 "TGMDAD,Target Group n Master Domain Access Descriptor" bitfld.long 0x0 31. "VLD,Valid" "0: MDAD-Assignment is invalid,1: MDAD-Assignment is valid" bitfld.long 0x0 29. "LCK,Descriptor Lock" "0: Lock disabled. Registers can be written.,1: Lock disabled registers are read-only" newline bitfld.long 0x0 14.--15. "SA,Secure Attribute" "0: NA. This option should not be used. Allows the..,1: Allow the bus attribute for this master to..,2: Allow the bus attribute for this master to..,3: Allow the bus master's attribute: Both secure.." bitfld.long 0x0 12. "MASKTYPE,Mask Type" "0: ANDed mask,1: ORed mask" newline hexmask.long.byte 0x0 6.--11. 1. "MASK,Mask" hexmask.long.byte 0x0 0.--5. 1. "MIDMATCH,Master ID Reference" rgroup.long ($2+0x4)++0x3 line.long 0x0 "TGSFAR,Target Group n SFAR Address" hexmask.long 0x0 0.--31. 1. "SFARADDR,SFAR Address" group.long ($2+0x8)++0x7 line.long 0x0 "TGSFARS,Target Group n SFAR Status" rbitfld.long 0x0 31. "VLD,Valid" "0: SFAR-Assignment is invalid,1: SFAR-Assignment is valid" rbitfld.long 0x0 30. "ERR,Error" "0: SFAR with required attributes,1: SFAR without required attributes" newline eventfld.long 0x0 29. "CLR,Clear" "0,1" rbitfld.long 0x0 12. "PA,Privileged Attribute" "0: Non-privileged,1: Privileged" newline rbitfld.long 0x0 10. "SA,Secure Attribute" "0: Non-secure,1: Secure" hexmask.long.byte 0x0 0.--5. 1. "TG_MID,Transaction Master ID" line.long 0x4 "TGIPCRS,Target Group n IPCR Status" rbitfld.long 0x4 31. "VLD,Valid" "0: IPCR-assignment is invalid,1: IPCR-assignment is valid and queue is locked." rbitfld.long 0x4 29.--30. "ERR,Error" "0: IPCR programming with required attributes,1: IPCR-DATZ programming without required attributes,2: IPCR-SEQID programming without required attributes,3: IPCR-DATZ and SEQID both programming without.." newline eventfld.long 0x4 28. "CLR,Clear" "0,1" rbitfld.long 0x4 22. "ARB_UNLOCK,Arbitration Unlock" "0: No effect,1: Arbitration unlock is requested" newline rbitfld.long 0x4 21. "ARB_LOCK,Arbitration Lock" "0: No effect,1: Arbitration lock is requested" rbitfld.long 0x4 20. "PAR,Parallel Mode Enable Value" "0,1" newline hexmask.long.byte 0x4 16.--19. 1. "SEQID,SEQID Value" hexmask.long.word 0x4 0.--15. 1. "IDATSZ,IDATSZ Value" tree.end repeat.end base ad:0x404CC000 group.long 0x920++0xF line.long 0x0 "MGC,Master Global Configuration" bitfld.long 0x0 31. "GVLD,Global Valid access control" "0: Access controls are disabled. No descriptor..,1: Access controls are enabled." newline bitfld.long 0x0 29. "GVLDMDAD,Global Valid MDAD" "0: MDADs are disabled,1: MDADs are enabled" newline bitfld.long 0x0 27. "GVLDFRAD,Global Valid FRAD" "0: FRADs are disabled,1: FRADs are enabled" newline bitfld.long 0x0 10.--11. "GCLCK,Global Configuration Lock" "0: Global Lock disabled. Registers can be written..,1: NA,2: Lock enabled. Only the global configuration lock..,3: Lock enabled. All registers are read only until.." newline hexmask.long.byte 0x0 0.--5. 1. "GCLCKMID,Global configuration Lock Owner Status" line.long 0x4 "MRC,Master Read Command" bitfld.long 0x4 30. "VLDCMD03,Valid command" "0: READ_CMD3 value invalid,1: READ_CMD3 value valid" newline hexmask.long.byte 0x4 24.--29. 1. "READ_CMD3,Read Command 3" newline bitfld.long 0x4 22. "VLDCMD02,Valid command" "0: READ_CMD2 value invalid,1: READ_CMD2 value valid" newline hexmask.long.byte 0x4 16.--21. 1. "READ_CMD2,Read Command 2" newline hexmask.long.byte 0x4 8.--13. 1. "READ_CMD1,Read Command 1" newline hexmask.long.byte 0x4 0.--5. 1. "READ_CMD0,Read Command 0" line.long 0x8 "MTO,Master Timeout" hexmask.long 0x8 0.--31. 1. "WRITE_TO,Write Timeout" line.long 0xC "FLSEQREQ,FlashSeq Request" rbitfld.long 0xC 31. "VLD,Valid" "0: Status is invalid,1: Status is valid" newline eventfld.long 0xC 29. "CLR,Clear" "0,1" newline rbitfld.long 0xC 27. "TIMEOUT,Timeout Error Status" "0: Instruction completed without timeout error,1: Instruction aborted after timeout error" newline rbitfld.long 0xC 22. "CMD,Instruction Type" "0: Read Instruction Sequence,1: Non-Read Instruction Sequence" newline hexmask.long.byte 0xC 16.--19. 1. "SEQID,Sequence ID" newline rbitfld.long 0xC 12.--14. "FRAD,Flash Region Descriptor Number" "0,1,2,3,4,5,6,7" newline rbitfld.long 0xC 10. "ARB_LOCK,Arbitration Lock" "0: Arbitration was not locked,1: Arbitration was locked" newline rbitfld.long 0xC 9. "PA,Privilege Attribute" "0: Non-privilege Transaction,1: Privilege Transaction" newline rbitfld.long 0xC 8. "SA,Secure Attribute" "0: Non-secure Transaction,1: Secure Transaction" newline rbitfld.long 0xC 6. "REQ_TG,FlashSeq Request Target Group" "0: TG0,1: TG1" newline hexmask.long.byte 0xC 0.--5. 1. "REQ_MID,FlashSeq Request Master ID" rgroup.long 0x930++0x3 line.long 0x0 "FSMSTAT,FSM Status" bitfld.long 0x0 31. "VLD,Valid" "0: Status is invalid. No IPS transfer is queued.,1: Status is valid. IPS transfer is queued or.." newline bitfld.long 0x0 17. "ARB_LOCK,Arbitration Lock" "0: Arbitration not locked,1: Arbitration locked" newline bitfld.long 0x0 16. "CMD,Command" "0: Read instruction sequence,1: Non-read instruction sequence" newline hexmask.long.byte 0x0 8.--13. 1. "MID,Master ID" newline bitfld.long 0x0 0.--1. "STATE,FSM State Status" "0: Transaction is Queued but QuadSPI is busy with..,1: TBDR lock is open. IPS master can write in TBDR.,2: Write transfer is triggered. SEQID is written to..,3: Read transfer is triggered. SEQID is written to.." group.long 0x934++0xB line.long 0x0 "IPSERROR,IPS Error" eventfld.long 0x0 29. "CLR,Clear" "0,1" newline rbitfld.long 0x0 15. "FRADPROG,FRAD Descriptor Program Status" "0: Some or all of the FRAD descriptors are programmed,1: None of the FRAD descriptors are programmed" newline rbitfld.long 0x0 14. "MDADPROG,TG/MDAD Descriptor Program Status" "0: One or both of target group descriptors programmed,1: None of the target group descriptors are.." newline rbitfld.long 0x0 13. "TG1MID,TGn Master-ID Status" "0: TGn master-ID check passed,1: TGn master-ID check failed" newline rbitfld.long 0x0 12. "TG0MID,TGn Master-ID Status" "0: TGn master-ID check passed,1: TGn master-ID check failed" newline rbitfld.long 0x0 11. "TG1SEC,TGn Security Status" "0: Security attribute check passed for TGn,1: Security attribute check failed for TGn" newline rbitfld.long 0x0 10. "TG0SEC,TGn Security Status" "0: Security attribute check passed for TGn,1: Security attribute check failed for TGn" newline rbitfld.long 0x0 9. "TG1LCK,TGn Lock" "0: TGn queue SEQID is not written yet.,1: TGn queue SEQID is written and queue is locked" newline rbitfld.long 0x0 8. "TG0LCK,TGn Lock" "0: TGn queue SEQID is not written yet.,1: TGn queue SEQID is written and queue is locked" newline hexmask.long.byte 0x0 0.--5. 1. "MID,IPS DID Master ID" line.long 0x4 "ERRSTAT,Error Status" rbitfld.long 0x4 14. "TO_ERR,Timeout Error" "0: No timeout Error generated,1: Timeout error is generated" newline rbitfld.long 0x4 13. "TG1IPCR,TGn IPCR Error" "0: No Error generated,1: Error is generated" newline rbitfld.long 0x4 12. "TG0IPCR,TGn IPCR Error" "0: No Error generated,1: Error is generated" newline rbitfld.long 0x4 11. "TG1SFAR,TGn SFAR Error" "0: No Error generated,1: Error is generated" newline rbitfld.long 0x4 10. "TG0SFAR,TGn SFAR Error" "0: No Error generated,1: Error is generated" newline rbitfld.long 0x4 9. "IPS_ERR,IPS Error" "0: No Error generated,1: Error is generated" newline eventfld.long 0x4 8. "FRAD7ACC,FRADn Access Error" "0: No valid Error transaction,1: Transaction is with error and target queue is.." newline eventfld.long 0x4 7. "FRAD6ACC,FRADn Access Error" "0: No valid Error transaction,1: Transaction is with error and target queue is.." newline eventfld.long 0x4 6. "FRAD5ACC,FRADn Access Error" "0: No valid Error transaction,1: Transaction is with error and target queue is.." newline eventfld.long 0x4 5. "FRAD4ACC,FRADn Access Error" "0: No valid Error transaction,1: Transaction is with error and target queue is.." newline eventfld.long 0x4 4. "FRAD3ACC,FRADn Access Error" "0: No valid Error transaction,1: Transaction is with error and target queue is.." newline eventfld.long 0x4 3. "FRAD2ACC,FRADn Access Error" "0: No valid Error transaction,1: Transaction is with error and target queue is.." newline eventfld.long 0x4 2. "FRAD1ACC,FRADn Access Error" "0: No valid Error transaction,1: Transaction is with error and target queue is.." newline eventfld.long 0x4 1. "FRAD0ACC,FRADn Access Error" "0: No valid Error transaction,1: Transaction is with error and target queue is.." newline eventfld.long 0x4 0. "FRADMTCH,No FRAD Match Error" "0: No Error generated,1: Transaction does not lie within any FRAD address.." line.long 0x8 "INT_EN,Interrupt Enable" bitfld.long 0x8 14. "TO_ERR,Timeout Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x8 13. "TG1IPCR,TGn IPCR Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x8 12. "TG0IPCR,TGn IPCR Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x8 11. "TG1SFAR,TGn SFAR Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x8 10. "TG0SFAR,TGn SFAR Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x8 9. "IPS_ERR,IPS Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x8 8. "FRAD7ACC,FRADn Access Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x8 7. "FRAD6ACC,FRADn Access Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x8 6. "FRAD5ACC,FRADn Access Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x8 5. "FRAD4ACC,FRADn Access Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x8 4. "FRAD3ACC,FRADn Access Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x8 3. "FRAD2ACC,FRADn Access Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x8 2. "FRAD1ACC,FRADn Access Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x8 1. "FRAD0ACC,FRADn Access Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x8 0. "FRADMTCH,No FRAD Match Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" tree.end tree "QUADSPI_ARDB" base ad:0x68000000 repeat 32. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2)++0x3 line.long 0x0 "ARDB[$1],AHB RX Data Buffer Register" hexmask.long 0x0 0.--31. 1. "ARXD,ARDB provided RX buffer data" repeat.end tree.end tree.end tree "RTC (Real Time Clock)" base ad:0x40288000 group.long 0x0++0xB line.long 0x0 "RTCSUPV,RTC Supervisor control register" bitfld.long 0x0 31. "SUPV,RTC Supervisor Bit" "0: All registers are accessible in both user as..,1: All other registers are accessible in the.." line.long 0x4 "RTCC,RTC Control register" bitfld.long 0x4 31. "CNTEN,Counter Enable" "0: Counter disabled,1: Counter enabled" bitfld.long 0x4 30. "RTCIE,RTC Interrupt Enable" "0: RTC interrupts disabled,1: RTC interrupts enabled" newline bitfld.long 0x4 29. "FRZEN,Freeze Enable Bit" "0: Counter does not freeze in debug mode,1: Counter freezes in debug mode" bitfld.long 0x4 28. "ROVREN,Counter Roll Over wakeup/Interrupt Enable" "0: RTC rollover wakeup/interrupt disabled,1: RTC rollover wakeup/interrupt enabled" newline bitfld.long 0x4 15. "APIEN,Autonomous Periodic Interrupt Enable" "0: API disabled,1: API enabled" bitfld.long 0x4 14. "APIIE,API Interrupt Enable" "0: API interrupts disabled,1: API interrupts enabled" newline bitfld.long 0x4 12.--13. "CLKSEL,Clock select" "0: Clock source 0,1: Clock source 1,2: Clock source 2,3: Clock source 3" bitfld.long 0x4 11. "DIV512EN,Divide by 512 enable" "0: Divide by 512 is disabled,1: Divide by 512 is enabled" newline bitfld.long 0x4 10. "DIV32EN,Divide by 32 enable" "0: Divide by 32 is disabled,1: Divide by 32 is enabled" bitfld.long 0x4 0. "TRIG_EN,Trigger enable for Analog Comparator" "0,1" line.long 0x8 "RTCS,RTC Status register" eventfld.long 0x8 29. "RTCF,RTC Interrupt Flag" "0: RTC counter is not equal to RTCVAL,1: RTC counter matches RTCVAL" rbitfld.long 0x8 18. "INV_RTC,Invalid RTC write" "0,1" newline rbitfld.long 0x8 17. "INV_API,Invalid APIVAL write" "0,1" eventfld.long 0x8 13. "APIF,API Interrupt Flag" "0: Counter is not equal to API offset value,1: Counter matches the API offset value" newline eventfld.long 0x8 10. "ROVRF,Counter Roll Over Interrupt Flag" "0: RTC has not rolled over,1: RTC has rolled over" rgroup.long 0xC++0x3 line.long 0x0 "RTCCNT,RTC Counter register" hexmask.long 0x0 0.--31. 1. "RTCCNT,RTC Counter Value" group.long 0x10++0x7 line.long 0x0 "APIVAL,API Compare value register" hexmask.long 0x0 0.--31. 1. "APIVAL,API Compare Value" line.long 0x4 "RTCVAL,RTC Compare value register" hexmask.long 0x4 0.--31. 1. "RTCVAL,RTC Compare Value" tree.end tree "SAI (Synchronous Audio Interface)" base ad:0x0 tree "SAI_0" base ad:0x4036C000 rgroup.long 0x0++0x7 line.long 0x0 "VERID,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Specification Number" line.long 0x4 "PARAM,Parameter" hexmask.long.byte 0x4 16.--19. 1. "FRAME,Frame Size" hexmask.long.byte 0x4 8.--11. 1. "FIFO,FIFO Size" newline hexmask.long.byte 0x4 0.--3. 1. "DATALINE,Number of Datalinks" group.long 0x8++0x17 line.long 0x0 "TCSR,Transmit Control" bitfld.long 0x0 31. "TE,Transmitter Enable" "0: Transmitter is disabled.,1: Transmitter is enabled or transmitter has been.." bitfld.long 0x0 29. "DBGE,Debug Enable" "0: Transmitter is disabled in Debug mode after..,1: Transmitter is enabled in Debug mode." newline bitfld.long 0x0 28. "BCE,Bit Clock Enable" "0: Transmit bit clock is disabled.,1: Transmit bit clock is enabled." bitfld.long 0x0 25. "FR,FIFO Reset" "0: No effect.,1: FIFO reset." newline bitfld.long 0x0 24. "SR,Software Reset" "0: No effect,1: Software reset" eventfld.long 0x0 20. "WSF,Word Start Flag" "0: Start of word not detected.,1: Start of word detected." newline eventfld.long 0x0 19. "SEF,Sync Error Flag" "0: Sync error not detected.,1: Frame sync error detected." eventfld.long 0x0 18. "FEF,FIFO Error Flag" "0: Transmit underrun not detected.,1: Transmit underrun detected." newline rbitfld.long 0x0 17. "FWF,FIFO Warning Flag" "0: No enabled transmit FIFO is empty.,1: Enabled transmit FIFO is empty." rbitfld.long 0x0 16. "FRF,FIFO Request Flag" "0: Transmit FIFO watermark has not been reached.,1: Transmit FIFO watermark has been reached." newline bitfld.long 0x0 12. "WSIE,Word Start Interrupt Enable" "0: Disables interrupt.,1: Enables interrupt." bitfld.long 0x0 11. "SEIE,Sync Error Interrupt Enable" "0: Disables interrupt.,1: Enables interrupt." newline bitfld.long 0x0 10. "FEIE,FIFO Error Interrupt Enable" "0: Disables the interrupt.,1: Enables the interrupt." bitfld.long 0x0 9. "FWIE,FIFO Warning Interrupt Enable" "0: Disables the interrupt.,1: Enables the interrupt." newline bitfld.long 0x0 8. "FRIE,FIFO Request Interrupt Enable" "0: Disables the interrupt.,1: Enables the interrupt." bitfld.long 0x0 1. "FWDE,FIFO Warning DMA Enable" "0: Disables the DMA warning.,1: Enables the DMA warning." newline bitfld.long 0x0 0. "FRDE,FIFO Request DMA Enable" "0: Disables the DMA request.,1: Enables the DMA request." line.long 0x4 "TCR1,Transmit Configuration 1" bitfld.long 0x4 0.--2. "TFW,Transmit FIFO Watermark" "0: 1 FIFO word,1: 2 FIFO words,2: (TFW +1) FIFO words,3: (TFW +1) FIFO words,4: (TFW +1) FIFO words,5: (TFW +1) FIFO words,6: (TFW +1) FIFO words,7: 8 FIFO words" line.long 0x8 "TCR2,Transmit Configuration 2" bitfld.long 0x8 30. "SYNC,Synchronous Mode" "0: Asynchronous mode,1: Synchronous with receiver" bitfld.long 0x8 28. "BCI,Bit Clock Input" "0: No effect.,1: Internal logic is clocked as if bit clock was.." newline bitfld.long 0x8 26.--27. "MSEL,MCLK Select" "0: Bus Clock selected.,1: Master Clock (MCLK) 1 option selected.,2: Master Clock (MCLK) 2 option selected.,3: Master Clock (MCLK) 3 option selected." bitfld.long 0x8 25. "BCP,Bit Clock Polarity" "0: Bit clock is active high with drive outputs on..,1: Bit clock is active low with drive outputs on.." newline bitfld.long 0x8 24. "BCD,Bit Clock Direction" "0: Bit clock is generated externally in Slave mode.,1: Bit clock is generated internally in Master mode." bitfld.long 0x8 23. "BYP,Bit Clock Bypass" "0: Internal bit clock is generated from bit clock..,1: Internal bit clock is divide-by-one of the audio.." newline hexmask.long.byte 0x8 0.--7. 1. "DIV,Bit Clock Divide" line.long 0xC "TCR3,Transmit Configuration 3" hexmask.long.byte 0xC 24.--27. 1. "CFR,Channel FIFO Reset" hexmask.long.byte 0xC 16.--19. 1. "TCE,Transmit Channel Enable" newline hexmask.long.byte 0xC 0.--3. 1. "WDFL,Word Flag Configuration" line.long 0x10 "TCR4,Transmit Configuration 4" bitfld.long 0x10 28. "FCONT,FIFO Continue on Error" "0: On FIFO error SAI continues from the start of..,1: On FIFO error SAI continues from the same word.." bitfld.long 0x10 26.--27. "FCOMB,FIFO Combine Mode" "0: FIFO Combine mode disabled.,1: FIFO Combine mode enabled on FIFO reads (from..,2: FIFO Combine mode enabled on FIFO writes (by..,3: FIFO Combine mode enabled on FIFO reads (from.." newline bitfld.long 0x10 24.--25. "FPACK,FIFO Packing Mode" "0: FIFO packing is disabled.,?,2: 8-bit FIFO packing is enabled.,3: 16-bit FIFO packing is enabled." hexmask.long.byte 0x10 16.--19. 1. "FRSZ,Frame size" newline hexmask.long.byte 0x10 8.--12. 1. "SYWD,Sync Width" bitfld.long 0x10 5. "CHMOD,Channel Mode" "0: TDM mode transmit data pins are 3-stated when..,1: Output mode transmit data pins are never.." newline bitfld.long 0x10 4. "MF,MSB First" "0: LSB is transmitted first.,1: MSB is transmitted first." bitfld.long 0x10 3. "FSE,Frame Sync Early" "0: Frame sync asserts with the first bit of the..,1: Frame sync asserts one bit before the first bit.." newline bitfld.long 0x10 2. "ONDEM,On Demand Mode" "0: Internal frame sync is generated continuously.,1: Internal frame sync is generated when the FIFO.." bitfld.long 0x10 1. "FSP,Frame Sync Polarity" "0: Frame sync is active high.,1: Frame sync is active low." newline bitfld.long 0x10 0. "FSD,Frame Sync Direction" "0: Frame sync is generated externally in Slave mode.,1: Frame sync is generated internally in Master mode." line.long 0x14 "TCR5,Transmit Configuration 5" hexmask.long.byte 0x14 24.--28. 1. "WNW,Word N Width" hexmask.long.byte 0x14 16.--20. 1. "W0W,Word 0 Width" newline hexmask.long.byte 0x14 8.--12. 1. "FBT,First Bit Shifted" repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x20)++0x3 line.long 0x0 "TDR[$1],Transmit Data" hexmask.long 0x0 0.--31. 1. "TDR,Transmit Data Register" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x40)++0x3 line.long 0x0 "TFR[$1],Transmit FIFO" bitfld.long 0x0 31. "WCP,Write Channel Pointer" "0: No effect,1: FIFO Combine mode is enabled for FIFO writes and.." hexmask.long.byte 0x0 16.--19. 1. "WFP,Write FIFO Pointer" newline hexmask.long.byte 0x0 0.--3. 1. "RFP,Read FIFO Pointer" repeat.end group.long 0x60++0x3 line.long 0x0 "TMR,Transmit Mask" hexmask.long.word 0x0 0.--15. 1. "TWM,Transmit Word Mask" group.long 0x88++0x17 line.long 0x0 "RCSR,Receive Control" bitfld.long 0x0 31. "RE,Receiver Enable" "0: Receiver is disabled.,1: Receiver is enabled or receiver has been.." bitfld.long 0x0 29. "DBGE,Debug Enable" "0: Receiver is disabled in Debug mode after..,1: Receiver is enabled in Debug mode." newline bitfld.long 0x0 28. "BCE,Bit Clock Enable" "0: Receive bit clock is disabled.,1: Receive bit clock is enabled." bitfld.long 0x0 25. "FR,FIFO Reset" "0: No effect.,1: FIFO reset." newline bitfld.long 0x0 24. "SR,Software Reset" "0: No effect.,1: Software reset." eventfld.long 0x0 20. "WSF,Word Start Flag" "0: Start of word not detected.,1: Start of word detected." newline eventfld.long 0x0 19. "SEF,Sync Error Flag" "0: Sync error not detected.,1: Frame sync error detected." eventfld.long 0x0 18. "FEF,FIFO Error Flag" "0: Receive overflow not detected.,1: Receive overflow detected." newline rbitfld.long 0x0 17. "FWF,FIFO Warning Flag" "0: No enabled receive FIFO is full.,1: Enabled receive FIFO is full." rbitfld.long 0x0 16. "FRF,FIFO Request Flag" "0: Receive FIFO watermark not reached.,1: Receive FIFO watermark has been reached." newline bitfld.long 0x0 12. "WSIE,Word Start Interrupt Enable" "0: Disables interrupt.,1: Enables interrupt." bitfld.long 0x0 11. "SEIE,Sync Error Interrupt Enable" "0: Disables interrupt.,1: Enables interrupt." newline bitfld.long 0x0 10. "FEIE,FIFO Error Interrupt Enable" "0: Disables the interrupt.,1: Enables the interrupt." bitfld.long 0x0 9. "FWIE,FIFO Warning Interrupt Enable" "0: Disables the interrupt.,1: Enables the interrupt." newline bitfld.long 0x0 8. "FRIE,FIFO Request Interrupt Enable" "0: Disables the interrupt.,1: Enables the interrupt." bitfld.long 0x0 1. "FWDE,FIFO Warning DMA Enable" "0: Disables DMA warnings.,1: Enables DMA warnings." newline bitfld.long 0x0 0. "FRDE,FIFO Request DMA Enable" "0: Disables the DMA request.,1: Enables the DMA request." line.long 0x4 "RCR1,Receive Configuration 1" bitfld.long 0x4 0.--2. "RFW,Receive FIFO Watermark" "0: 1 FIFO word,1: 2 FIFO words,2: (RFW value + 1) FIFO words,3: (RFW value + 1) FIFO words,4: (RFW value + 1) FIFO words,5: (RFW value + 1) FIFO words,6: (RFW value + 1) FIFO words,7: 8 FIFO words" line.long 0x8 "RCR2,Receive Configuration 2" bitfld.long 0x8 30. "SYNC,Synchronous Mode" "0: Asynchronous mode,1: Synchronous with transmitter" bitfld.long 0x8 28. "BCI,Bit Clock Input" "0: No effect.,1: Internal logic is clocked as if bit clock was.." newline bitfld.long 0x8 26.--27. "MSEL,MCLK Select" "0: Bus Clock selected.,1: Master Clock (MCLK) 1 option selected.,2: Master Clock (MCLK) 2 option selected.,3: Master Clock (MCLK) 3 option selected." bitfld.long 0x8 25. "BCP,Bit Clock Polarity" "0: Bit clock is active high with drive outputs on..,1: Bit clock is active low with drive outputs on.." newline bitfld.long 0x8 24. "BCD,Bit Clock Direction" "0: Bit clock is generated externally in Slave mode.,1: Bit clock is generated internally in Master mode." bitfld.long 0x8 23. "BYP,Bit Clock Bypass" "0: Internal bit clock is generated from bit clock..,1: Internal bit clock is divide-by-one of the audio.." newline hexmask.long.byte 0x8 0.--7. 1. "DIV,Bit Clock Divide" line.long 0xC "RCR3,Receive Configuration 3" hexmask.long.byte 0xC 24.--27. 1. "CFR,Channel FIFO Reset" hexmask.long.byte 0xC 16.--19. 1. "RCE,Receive Channel Enable" newline hexmask.long.byte 0xC 0.--3. 1. "WDFL,Word Flag Configuration" line.long 0x10 "RCR4,Receive Configuration 4" bitfld.long 0x10 28. "FCONT,FIFO Continue on Error" "0: On FIFO error SAI continues from the start of..,1: On FIFO error SAI continues from the same word.." bitfld.long 0x10 26.--27. "FCOMB,FIFO Combine Mode" "0: FIFO Combine mode disabled.,1: FIFO Combine mode enabled on FIFO writes (from..,2: FIFO Combine mode enabled on FIFO reads (by..,3: FIFO Combine mode enabled on FIFO writes (from.." newline bitfld.long 0x10 24.--25. "FPACK,FIFO Packing Mode" "0: FIFO packing is disabled,?,2: 8-bit FIFO packing is enabled,3: 16-bit FIFO packing is enabled" hexmask.long.byte 0x10 16.--19. 1. "FRSZ,Frame Size" newline hexmask.long.byte 0x10 8.--12. 1. "SYWD,Sync Width" bitfld.long 0x10 4. "MF,MSB First" "0: LSB is received first.,1: MSB is received first." newline bitfld.long 0x10 3. "FSE,Frame Sync Early" "0: Frame sync asserts with the first bit of the..,1: Frame sync asserts one bit before the first bit.." bitfld.long 0x10 2. "ONDEM,On Demand Mode" "0: Internal frame sync is generated continuously.,1: Internal frame sync is generated when the FIFO.." newline bitfld.long 0x10 1. "FSP,Frame Sync Polarity" "0: Frame sync is active high.,1: Frame sync is active low." bitfld.long 0x10 0. "FSD,Frame Sync Direction" "0: Frame Sync is generated externally in Slave mode.,1: Frame Sync is generated internally in Master mode." line.long 0x14 "RCR5,Receive Configuration 5" hexmask.long.byte 0x14 24.--28. 1. "WNW,Word N Width" hexmask.long.byte 0x14 16.--20. 1. "W0W,Word 0 Width" newline hexmask.long.byte 0x14 8.--12. 1. "FBT,First Bit Shifted" repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0xA0)++0x3 line.long 0x0 "RDR[$1],Receive Data" hexmask.long 0x0 0.--31. 1. "RDR,Receive Data Register" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0xC0)++0x3 line.long 0x0 "RFR[$1],Receive FIFO" hexmask.long.byte 0x0 16.--19. 1. "WFP,Write FIFO Pointer" bitfld.long 0x0 15. "RCP,Receive Channel Pointer" "0: No effect.,1: FIFO Combine mode is enabled for FIFO reads and.." newline hexmask.long.byte 0x0 0.--3. 1. "RFP,Read FIFO Pointer" repeat.end group.long 0xE0++0x3 line.long 0x0 "RMR,Receive Mask" hexmask.long.word 0x0 0.--15. 1. "RWM,Receive Word Mask" tree.end tree "SAI_1" base ad:0x404DC000 rgroup.long 0x0++0x7 line.long 0x0 "VERID,Version ID" hexmask.long.byte 0x0 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x0 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x0 0.--15. 1. "FEATURE,Feature Specification Number" line.long 0x4 "PARAM,Parameter" hexmask.long.byte 0x4 16.--19. 1. "FRAME,Frame Size" hexmask.long.byte 0x4 8.--11. 1. "FIFO,FIFO Size" newline hexmask.long.byte 0x4 0.--3. 1. "DATALINE,Number of Datalinks" group.long 0x8++0x1B line.long 0x0 "TCSR,Transmit Control" bitfld.long 0x0 31. "TE,Transmitter Enable" "0: Transmitter is disabled.,1: Transmitter is enabled or transmitter has been.." bitfld.long 0x0 29. "DBGE,Debug Enable" "0: Transmitter is disabled in Debug mode after..,1: Transmitter is enabled in Debug mode." newline bitfld.long 0x0 28. "BCE,Bit Clock Enable" "0: Transmit bit clock is disabled.,1: Transmit bit clock is enabled." bitfld.long 0x0 25. "FR,FIFO Reset" "0: No effect.,1: FIFO reset." newline bitfld.long 0x0 24. "SR,Software Reset" "0: No effect,1: Software reset" eventfld.long 0x0 20. "WSF,Word Start Flag" "0: Start of word not detected.,1: Start of word detected." newline eventfld.long 0x0 19. "SEF,Sync Error Flag" "0: Sync error not detected.,1: Frame sync error detected." eventfld.long 0x0 18. "FEF,FIFO Error Flag" "0: Transmit underrun not detected.,1: Transmit underrun detected." newline rbitfld.long 0x0 17. "FWF,FIFO Warning Flag" "0: No enabled transmit FIFO is empty.,1: Enabled transmit FIFO is empty." rbitfld.long 0x0 16. "FRF,FIFO Request Flag" "0: Transmit FIFO watermark has not been reached.,1: Transmit FIFO watermark has been reached." newline bitfld.long 0x0 12. "WSIE,Word Start Interrupt Enable" "0: Disables interrupt.,1: Enables interrupt." bitfld.long 0x0 11. "SEIE,Sync Error Interrupt Enable" "0: Disables interrupt.,1: Enables interrupt." newline bitfld.long 0x0 10. "FEIE,FIFO Error Interrupt Enable" "0: Disables the interrupt.,1: Enables the interrupt." bitfld.long 0x0 9. "FWIE,FIFO Warning Interrupt Enable" "0: Disables the interrupt.,1: Enables the interrupt." newline bitfld.long 0x0 8. "FRIE,FIFO Request Interrupt Enable" "0: Disables the interrupt.,1: Enables the interrupt." bitfld.long 0x0 1. "FWDE,FIFO Warning DMA Enable" "0: Disables the DMA warning.,1: Enables the DMA warning." newline bitfld.long 0x0 0. "FRDE,FIFO Request DMA Enable" "0: Disables the DMA request.,1: Enables the DMA request." line.long 0x4 "TCR1,Transmit Configuration 1" bitfld.long 0x4 0.--2. "TFW,Transmit FIFO Watermark" "0: 1 FIFO word,1: 2 FIFO words,2: (TFW +1) FIFO words,3: (TFW +1) FIFO words,4: (TFW +1) FIFO words,5: (TFW +1) FIFO words,6: (TFW +1) FIFO words,7: 8 FIFO words" line.long 0x8 "TCR2,Transmit Configuration 2" bitfld.long 0x8 30. "SYNC,Synchronous Mode" "0: Asynchronous mode,1: Synchronous with receiver" bitfld.long 0x8 28. "BCI,Bit Clock Input" "0: No effect.,1: Internal logic is clocked as if bit clock was.." newline bitfld.long 0x8 26.--27. "MSEL,MCLK Select" "0: Bus Clock selected.,1: Master Clock (MCLK) 1 option selected.,2: Master Clock (MCLK) 2 option selected.,3: Master Clock (MCLK) 3 option selected." bitfld.long 0x8 25. "BCP,Bit Clock Polarity" "0: Bit clock is active high with drive outputs on..,1: Bit clock is active low with drive outputs on.." newline bitfld.long 0x8 24. "BCD,Bit Clock Direction" "0: Bit clock is generated externally in Slave mode.,1: Bit clock is generated internally in Master mode." bitfld.long 0x8 23. "BYP,Bit Clock Bypass" "0: Internal bit clock is generated from bit clock..,1: Internal bit clock is divide-by-one of the audio.." newline hexmask.long.byte 0x8 0.--7. 1. "DIV,Bit Clock Divide" line.long 0xC "TCR3,Transmit Configuration 3" bitfld.long 0xC 16. "TCE,Transmit Channel Enable" "0,1" hexmask.long.byte 0xC 0.--3. 1. "WDFL,Word Flag Configuration" line.long 0x10 "TCR4,Transmit Configuration 4" bitfld.long 0x10 28. "FCONT,FIFO Continue on Error" "0: On FIFO error SAI continues from the start of..,1: On FIFO error SAI continues from the same word.." bitfld.long 0x10 24.--25. "FPACK,FIFO Packing Mode" "0: FIFO packing is disabled.,?,2: 8-bit FIFO packing is enabled.,3: 16-bit FIFO packing is enabled." newline hexmask.long.byte 0x10 16.--19. 1. "FRSZ,Frame size" hexmask.long.byte 0x10 8.--12. 1. "SYWD,Sync Width" newline bitfld.long 0x10 5. "CHMOD,Channel Mode" "0: TDM mode transmit data pins are 3-stated when..,1: Output mode transmit data pins are never.." bitfld.long 0x10 4. "MF,MSB First" "0: LSB is transmitted first.,1: MSB is transmitted first." newline bitfld.long 0x10 3. "FSE,Frame Sync Early" "0: Frame sync asserts with the first bit of the..,1: Frame sync asserts one bit before the first bit.." bitfld.long 0x10 2. "ONDEM,On Demand Mode" "0: Internal frame sync is generated continuously.,1: Internal frame sync is generated when the FIFO.." newline bitfld.long 0x10 1. "FSP,Frame Sync Polarity" "0: Frame sync is active high.,1: Frame sync is active low." bitfld.long 0x10 0. "FSD,Frame Sync Direction" "0: Frame sync is generated externally in Slave mode.,1: Frame sync is generated internally in Master mode." line.long 0x14 "TCR5,Transmit Configuration 5" hexmask.long.byte 0x14 24.--28. 1. "WNW,Word N Width" hexmask.long.byte 0x14 16.--20. 1. "W0W,Word 0 Width" newline hexmask.long.byte 0x14 8.--12. 1. "FBT,First Bit Shifted" line.long 0x18 "TDR0,Transmit Data" hexmask.long 0x18 0.--31. 1. "TDR,Transmit Data Register" rgroup.long 0x40++0x3 line.long 0x0 "TFR0,Transmit FIFO" hexmask.long.byte 0x0 16.--19. 1. "WFP,Write FIFO Pointer" hexmask.long.byte 0x0 0.--3. 1. "RFP,Read FIFO Pointer" group.long 0x60++0x3 line.long 0x0 "TMR,Transmit Mask" hexmask.long.word 0x0 0.--15. 1. "TWM,Transmit Word Mask" group.long 0x88++0x17 line.long 0x0 "RCSR,Receive Control" bitfld.long 0x0 31. "RE,Receiver Enable" "0: Receiver is disabled.,1: Receiver is enabled or receiver has been.." bitfld.long 0x0 29. "DBGE,Debug Enable" "0: Receiver is disabled in Debug mode after..,1: Receiver is enabled in Debug mode." newline bitfld.long 0x0 28. "BCE,Bit Clock Enable" "0: Receive bit clock is disabled.,1: Receive bit clock is enabled." bitfld.long 0x0 25. "FR,FIFO Reset" "0: No effect.,1: FIFO reset." newline bitfld.long 0x0 24. "SR,Software Reset" "0: No effect.,1: Software reset." eventfld.long 0x0 20. "WSF,Word Start Flag" "0: Start of word not detected.,1: Start of word detected." newline eventfld.long 0x0 19. "SEF,Sync Error Flag" "0: Sync error not detected.,1: Frame sync error detected." eventfld.long 0x0 18. "FEF,FIFO Error Flag" "0: Receive overflow not detected.,1: Receive overflow detected." newline rbitfld.long 0x0 17. "FWF,FIFO Warning Flag" "0: No enabled receive FIFO is full.,1: Enabled receive FIFO is full." rbitfld.long 0x0 16. "FRF,FIFO Request Flag" "0: Receive FIFO watermark not reached.,1: Receive FIFO watermark has been reached." newline bitfld.long 0x0 12. "WSIE,Word Start Interrupt Enable" "0: Disables interrupt.,1: Enables interrupt." bitfld.long 0x0 11. "SEIE,Sync Error Interrupt Enable" "0: Disables interrupt.,1: Enables interrupt." newline bitfld.long 0x0 10. "FEIE,FIFO Error Interrupt Enable" "0: Disables the interrupt.,1: Enables the interrupt." bitfld.long 0x0 9. "FWIE,FIFO Warning Interrupt Enable" "0: Disables the interrupt.,1: Enables the interrupt." newline bitfld.long 0x0 8. "FRIE,FIFO Request Interrupt Enable" "0: Disables the interrupt.,1: Enables the interrupt." bitfld.long 0x0 1. "FWDE,FIFO Warning DMA Enable" "0: Disables DMA warnings.,1: Enables DMA warnings." newline bitfld.long 0x0 0. "FRDE,FIFO Request DMA Enable" "0: Disables the DMA request.,1: Enables the DMA request." line.long 0x4 "RCR1,Receive Configuration 1" bitfld.long 0x4 0.--2. "RFW,Receive FIFO Watermark" "0: 1 FIFO word,1: 2 FIFO words,2: (RFW value + 1) FIFO words,3: (RFW value + 1) FIFO words,4: (RFW value + 1) FIFO words,5: (RFW value + 1) FIFO words,6: (RFW value + 1) FIFO words,7: 8 FIFO words" line.long 0x8 "RCR2,Receive Configuration 2" bitfld.long 0x8 30. "SYNC,Synchronous Mode" "0: Asynchronous mode,1: Synchronous with transmitter" bitfld.long 0x8 28. "BCI,Bit Clock Input" "0: No effect.,1: Internal logic is clocked as if bit clock was.." newline bitfld.long 0x8 26.--27. "MSEL,MCLK Select" "0: Bus Clock selected.,1: Master Clock (MCLK) 1 option selected.,2: Master Clock (MCLK) 2 option selected.,3: Master Clock (MCLK) 3 option selected." bitfld.long 0x8 25. "BCP,Bit Clock Polarity" "0: Bit clock is active high with drive outputs on..,1: Bit clock is active low with drive outputs on.." newline bitfld.long 0x8 24. "BCD,Bit Clock Direction" "0: Bit clock is generated externally in Slave mode.,1: Bit clock is generated internally in Master mode." bitfld.long 0x8 23. "BYP,Bit Clock Bypass" "0: Internal bit clock is generated from bit clock..,1: Internal bit clock is divide-by-one of the audio.." newline hexmask.long.byte 0x8 0.--7. 1. "DIV,Bit Clock Divide" line.long 0xC "RCR3,Receive Configuration 3" bitfld.long 0xC 16. "RCE,Receive Channel Enable" "0,1" hexmask.long.byte 0xC 0.--3. 1. "WDFL,Word Flag Configuration" line.long 0x10 "RCR4,Receive Configuration 4" bitfld.long 0x10 28. "FCONT,FIFO Continue on Error" "0: On FIFO error SAI continues from the start of..,1: On FIFO error SAI continues from the same word.." bitfld.long 0x10 24.--25. "FPACK,FIFO Packing Mode" "0: FIFO packing is disabled,?,2: 8-bit FIFO packing is enabled,3: 16-bit FIFO packing is enabled" newline hexmask.long.byte 0x10 16.--19. 1. "FRSZ,Frame Size" hexmask.long.byte 0x10 8.--12. 1. "SYWD,Sync Width" newline bitfld.long 0x10 4. "MF,MSB First" "0: LSB is received first.,1: MSB is received first." bitfld.long 0x10 3. "FSE,Frame Sync Early" "0: Frame sync asserts with the first bit of the..,1: Frame sync asserts one bit before the first bit.." newline bitfld.long 0x10 2. "ONDEM,On Demand Mode" "0: Internal frame sync is generated continuously.,1: Internal frame sync is generated when the FIFO.." bitfld.long 0x10 1. "FSP,Frame Sync Polarity" "0: Frame sync is active high.,1: Frame sync is active low." newline bitfld.long 0x10 0. "FSD,Frame Sync Direction" "0: Frame Sync is generated externally in Slave mode.,1: Frame Sync is generated internally in Master mode." line.long 0x14 "RCR5,Receive Configuration 5" hexmask.long.byte 0x14 24.--28. 1. "WNW,Word N Width" hexmask.long.byte 0x14 16.--20. 1. "W0W,Word 0 Width" newline hexmask.long.byte 0x14 8.--12. 1. "FBT,First Bit Shifted" rgroup.long 0xA0++0x3 line.long 0x0 "RDR0,Receive Data" hexmask.long 0x0 0.--31. 1. "RDR,Receive Data Register" rgroup.long 0xC0++0x3 line.long 0x0 "RFR0,Receive FIFO" hexmask.long.byte 0x0 16.--19. 1. "WFP,Write FIFO Pointer" hexmask.long.byte 0x0 0.--3. 1. "RFP,Read FIFO Pointer" group.long 0xE0++0x3 line.long 0x0 "RMR,Receive Mask" hexmask.long.word 0x0 0.--15. 1. "RWM,Receive Word Mask" tree.end tree.end tree "SDA_AP (Serial Data Access Port)" base edp:0x700 rgroup.long 0x0++0x3 line.long 0x0 "AUTHSTTS,Authentication Status" bitfld.long 0x0 30. "APPDBGEN,Application Debug Enabled or Disabled" "0: Application debug disabled,1: Application debug enabled" bitfld.long 0x0 3. "SWAPPDBG,Software Application Debug" "0: Software application debug disabled,1: Software application debug enabled" newline bitfld.long 0x0 2. "UIDSTATUS,User Identification Status" "0: UID is not ready and is invalid,1: UID is ready and is valid" bitfld.long 0x0 0. "CHALRDY,Challenge Ready" "0: Challenge is not ready,1: Challenge is ready" wgroup.long 0x4++0x3 line.long 0x0 "AUTHCTL,Authentication Control" bitfld.long 0x0 1. "HSENEWDATACTL,New Data Control" "0: Does not indicate that the debugger has consumed..,1: Indicates that the debugger has consumed the.." bitfld.long 0x0 0. "HSEAUTHREQ,Debug Enablement Authentication Request" "0: Does not start the authentication request,1: Starts the authentication request" repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x10)++0x3 line.long 0x0 "KEYCHAL[$1],Key Challenge" hexmask.long 0x0 0.--31. 1. "KEYCHAL,Debug Enablement Key Challenge" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x40)++0x3 line.long 0x0 "KEYRESP[$1],Key Response" hexmask.long 0x0 0.--31. 1. "KEYRESP,Debug Enablement Key Response" repeat.end rgroup.long 0x70++0x7 line.long 0x0 "UID0,User Identification 0" hexmask.long 0x0 0.--31. 1. "UID0,User ID 0" line.long 0x4 "UID1,User Identification 1" hexmask.long 0x4 0.--31. 1. "UID1,User ID 1" group.long 0x80++0x3 line.long 0x0 "DBGENCTRL,Debug Enable Control" bitfld.long 0x0 29. "CNIDEN,Core Non-Invasive Debug Enable" "0: Disabled,1: Enabled" bitfld.long 0x0 28. "CDBGEN,Core Debug Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 7. "GSPNIDEN,Global Secure Privileged Non-Invasive Debug Enable" "0: Disabled,1: Enabled" bitfld.long 0x0 6. "GSPIDEN,Global Secure Privileged Debug Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 5. "GNIDEN,Global Non-Invasive Debug Enable" "0: Disabled,1: Enabled" bitfld.long 0x0 4. "GDBGEN,Global Debug Enable" "0: Disabled,1: Enabled" group.long 0x90++0x3 line.long 0x0 "SDAAPRSTCTRL,Reset Control" bitfld.long 0x0 28. "RSTRELTLCM73,Reset Release Cortex-M7_3" "0: Core is in reset,1: Reset is released" bitfld.long 0x0 27. "RSTRELTLCM72,Reset Release Cortex-M7_2" "0: Core is in reset,1: Reset is released" newline bitfld.long 0x0 26. "RSTRELTLCM71,Reset Release Cortex-M7_1" "0: Core is in reset,1: Reset is released" bitfld.long 0x0 25. "RSTRELTLCM70,Reset Release Cortex-M7_0" "0: Core is in reset,1: Reset is released" rgroup.long 0xA0++0x3 line.long 0x0 "SDAAPGENSTATUS0,SDA_AP Generic Status" hexmask.long 0x0 0.--31. 1. "SDAAPGENSTATUS,DAP Generic Status" group.long 0xA4++0x3 line.long 0x0 "SDAAPGENCTRL0,Generic Control 0" bitfld.long 0x0 0. "JTAG_CR_EN,JTAG CR Enable" "0: Function performed on the basis of SWJ-DP mode,1: Function performed on the basis of JTAG mode" rgroup.long 0xB0++0x3 line.long 0x0 "SDAAPGENSTATUS1,SDA_AP Generic Status" hexmask.long 0x0 0.--31. 1. "SDAAPGENSTATUS,DAP Generic Status" rgroup.long 0xC0++0x3 line.long 0x0 "SDAAPGENSTATUS2,SDA_AP Generic Status" hexmask.long 0x0 0.--31. 1. "SDAAPGENSTATUS,DAP Generic Status" rgroup.long 0xD0++0x3 line.long 0x0 "SDAAPGENSTATUS3,SDA_AP Generic Status" hexmask.long 0x0 0.--31. 1. "SDAAPGENSTATUS,DAP Generic Status" rgroup.long 0xE0++0x3 line.long 0x0 "SDAAPGENSTATUS4,SDA_AP Generic Status" hexmask.long 0x0 0.--31. 1. "SDAAPGENSTATUS,DAP Generic Status" rgroup.long 0xFC++0x3 line.long 0x0 "ID,Identity" hexmask.long 0x0 0.--31. 1. "ID,Identity" tree.end tree "SELFTEST_GPR (Self-Test General-Purpose Registers)" base ad:0x403B0000 group.long 0x0++0x3 line.long 0x0 "CONFIG_REG,Configuration register" bitfld.long 0x0 8. "PCS_ENABLE_END,PCS Enable End" "0,1" bitfld.long 0x0 7. "PCS_ENABLE_START,PCS Enable Start" "0,1" bitfld.long 0x0 4.--6. "PCS_STEP_SIZE,PCS Step Size" "0,1,2,3,4,5,6,7" group.long 0x14++0x3 line.long 0x0 "LBIST_PROG_REG,LBIST Program" hexmask.long.byte 0x0 0.--7. 1. "LBIST_SHIFT_COUNT,LBIST Shift Count" tree.end tree "SEMA42 (Semaphores2)" base ad:0x40460000 group.byte 0x0++0xF line.byte 0x0 "GATE3,Gate" hexmask.byte 0x0 0.--3. 1. "GTFSM,Gate Finite State Machine" line.byte 0x1 "GATE2,Gate" hexmask.byte 0x1 0.--3. 1. "GTFSM,Gate Finite State Machine" line.byte 0x2 "GATE1,Gate" hexmask.byte 0x2 0.--3. 1. "GTFSM,Gate Finite State Machine" line.byte 0x3 "GATE0,Gate" hexmask.byte 0x3 0.--3. 1. "GTFSM,Gate Finite State Machine" line.byte 0x4 "GATE7,Gate" hexmask.byte 0x4 0.--3. 1. "GTFSM,Gate Finite State Machine" line.byte 0x5 "GATE6,Gate" hexmask.byte 0x5 0.--3. 1. "GTFSM,Gate Finite State Machine" line.byte 0x6 "GATE5,Gate" hexmask.byte 0x6 0.--3. 1. "GTFSM,Gate Finite State Machine" line.byte 0x7 "GATE4,Gate" hexmask.byte 0x7 0.--3. 1. "GTFSM,Gate Finite State Machine" line.byte 0x8 "GATE11,Gate" hexmask.byte 0x8 0.--3. 1. "GTFSM,Gate Finite State Machine" line.byte 0x9 "GATE10,Gate" hexmask.byte 0x9 0.--3. 1. "GTFSM,Gate Finite State Machine" line.byte 0xA "GATE9,Gate" hexmask.byte 0xA 0.--3. 1. "GTFSM,Gate Finite State Machine" line.byte 0xB "GATE8,Gate" hexmask.byte 0xB 0.--3. 1. "GTFSM,Gate Finite State Machine" line.byte 0xC "GATE15,Gate" hexmask.byte 0xC 0.--3. 1. "GTFSM,Gate Finite State Machine" line.byte 0xD "GATE14,Gate" hexmask.byte 0xD 0.--3. 1. "GTFSM,Gate Finite State Machine" line.byte 0xE "GATE13,Gate" hexmask.byte 0xE 0.--3. 1. "GTFSM,Gate Finite State Machine" line.byte 0xF "GATE12,Gate" hexmask.byte 0xF 0.--3. 1. "GTFSM,Gate Finite State Machine" rgroup.word 0x42++0x1 line.word 0x0 "RSTGT_R,Reset Gate Read" bitfld.word 0x0 12.--13. "RSTGSM,Reset Gate Finite State Machine" "0: Idle waiting for the first data pattern write.,1: Waiting for the second data pattern write,2: The 2-write sequence has completed. Generate the..,?" hexmask.word.byte 0x0 8.--11. 1. "RSTGMS,Reset Gate Domain" hexmask.word.byte 0x0 0.--7. 1. "RSTGTN,Reset Gate Number" wgroup.word 0x42++0x1 line.word 0x0 "RSTGT_W,Reset Gate Write" hexmask.word.byte 0x0 8.--15. 1. "RSTGDP,Reset Gate Data Pattern" hexmask.word.byte 0x0 0.--7. 1. "RSTGTN,Reset Gate Number" tree.end tree "SIRC (Slow Internal RC Oscillator)" base ad:0x402C8000 rgroup.long 0x4++0x3 line.long 0x0 "SR,Status Register" bitfld.long 0x0 0. "STATUS,Status bit for SIRC" "0: SIRC is off or unstable,1: SIRC is on and stable" group.long 0xC++0x3 line.long 0x0 "MISCELLANEOUS_IN,Miscellaneous input" bitfld.long 0x0 8. "STANDBY_ENABLE,Standby Enable for SIRC" "0: SIRC disables in Standby mode,1: SIRC enables in Standby mode" tree.end tree "SIUL2 (System Integration Unit Lite2)" base ad:0x40290000 rgroup.long 0x4++0x7 line.long 0x0 "MIDR1,SIUL2 MCU ID 1" hexmask.long.byte 0x0 26.--31. 1. "PRODUCT_LINE_LETTER,Product Line Letter" newline hexmask.long.word 0x0 16.--25. 1. "PART_NO,MCU Part Number" newline hexmask.long.byte 0x0 4.--7. 1. "MAJOR_MASK,Major Mask Revision" newline hexmask.long.byte 0x0 0.--3. 1. "MINOR_MASK,Minor Mask Revision" line.long 0x4 "MIDR2,SIUL2 MCU ID 2" bitfld.long 0x4 29.--31. "TECHNOLOGY,Technology" "?,1: C40EFS3,?,?,?,?,?,?" newline bitfld.long 0x4 26.--28. "TEMPERATURE,Temperature" "?,?,2: V = 105C,?,4: M = 125C,?,?,?" newline hexmask.long.byte 0x4 20.--25. 1. "PACKAGE,Package" newline hexmask.long.byte 0x4 16.--19. 1. "FREQUENCY,Frequency" newline bitfld.long 0x4 14.--15. "FLASH_CODE,Flash Code" "?,?,2: Monolithic,?" newline bitfld.long 0x4 12.--13. "FLASH_DATA,Flash Data" "?,?,2: Monolithic,?" newline hexmask.long.byte 0x4 8.--11. 1. "FLASH_SIZE_DATA,Flash Size Data" newline hexmask.long.byte 0x4 0.--7. 1. "FLASH_SIZE_CODE,Flash Size Code" group.long 0x10++0x3 line.long 0x0 "DISR0,SIUL2 DMA/Interrupt Status Flag 0" eventfld.long 0x0 31. "EIF31,External Interrupt Status Flag 31" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER31 and.." newline eventfld.long 0x0 30. "EIF30,External Interrupt Status Flag 30" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER30 and.." newline eventfld.long 0x0 29. "EIF29,External Interrupt Status Flag 29" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER29 and.." newline eventfld.long 0x0 28. "EIF28,External Interrupt Status Flag 28" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER28 and.." newline eventfld.long 0x0 27. "EIF27,External Interrupt Status Flag 27" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER27 and.." newline eventfld.long 0x0 26. "EIF26,External Interrupt Status Flag 26" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER26 and.." newline eventfld.long 0x0 25. "EIF25,External Interrupt Status Flag 25" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER25 and.." newline eventfld.long 0x0 24. "EIF24,External Interrupt Status Flag 24" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER24 and.." newline eventfld.long 0x0 23. "EIF23,External Interrupt Status Flag 23" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER23 and.." newline eventfld.long 0x0 22. "EIF22,External Interrupt Status Flag 22" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER22 and.." newline eventfld.long 0x0 21. "EIF21,External Interrupt Status Flag 21" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER21 and.." newline eventfld.long 0x0 20. "EIF20,External Interrupt Status Flag 20" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER20 and.." newline eventfld.long 0x0 19. "EIF19,External Interrupt Status Flag 19" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER19 and.." newline eventfld.long 0x0 18. "EIF18,External Interrupt Status Flag 18" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER18 and.." newline eventfld.long 0x0 17. "EIF17,External Interrupt Status Flag 17" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER17 and.." newline eventfld.long 0x0 16. "EIF16,External Interrupt Status Flag 16" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER16 and.." newline eventfld.long 0x0 15. "EIF15,External Interrupt Status Flag 15" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER15 and.." newline eventfld.long 0x0 14. "EIF14,External Interrupt Status Flag 14" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER14 and.." newline eventfld.long 0x0 13. "EIF13,External Interrupt Status Flag 13" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER13 and.." newline eventfld.long 0x0 12. "EIF12,External Interrupt Status Flag 12" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER12 and.." newline eventfld.long 0x0 11. "EIF11,External Interrupt Status Flag 11" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER11 and.." newline eventfld.long 0x0 10. "EIF10,External Interrupt Status Flag 10" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER10 and.." newline eventfld.long 0x0 9. "EIF9,External Interrupt Status Flag 9" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER9 and.." newline eventfld.long 0x0 8. "EIF8,External Interrupt Status Flag 8" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER8 and.." newline eventfld.long 0x0 7. "EIF7,External Interrupt Status Flag 7" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER7 and.." newline eventfld.long 0x0 6. "EIF6,External Interrupt Status Flag 6" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER6 and.." newline eventfld.long 0x0 5. "EIF5,External Interrupt Status Flag 5" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER5 and.." newline eventfld.long 0x0 4. "EIF4,External Interrupt Status Flag 4" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER4 and.." newline eventfld.long 0x0 3. "EIF3,External Interrupt Status Flag 3" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER3 and.." newline eventfld.long 0x0 2. "EIF2,External Interrupt Status Flag 2" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER2 and.." newline eventfld.long 0x0 1. "EIF1,External Interrupt Status Flag 1" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER1 and.." newline eventfld.long 0x0 0. "EIF0,External Interrupt Status Flag 0" "0: No interrupt event has occurred on the pad.,1: An interrupt event as defined by IREER0 and.." group.long 0x18++0x3 line.long 0x0 "DIRER0,SIUL2 DMA/Interrupt Request Enable 0" bitfld.long 0x0 31. "EIRE31,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 30. "EIRE30,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 29. "EIRE29,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 28. "EIRE28,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 27. "EIRE27,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 26. "EIRE26,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 25. "EIRE25,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 24. "EIRE24,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 23. "EIRE23,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 22. "EIRE22,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 21. "EIRE21,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 20. "EIRE20,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 19. "EIRE19,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 18. "EIRE18,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 17. "EIRE17,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 16. "EIRE16,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 15. "EIRE15,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 14. "EIRE14,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 13. "EIRE13,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 12. "EIRE12,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 11. "EIRE11,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 10. "EIRE10,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 9. "EIRE9,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 8. "EIRE8,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 7. "EIRE7,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 6. "EIRE6,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 5. "EIRE5,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 4. "EIRE4,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 3. "EIRE3,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 2. "EIRE2,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 1. "EIRE1,External Interrupt Request Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 0. "EIRE0,External Interrupt Request Enable" "0: Disabled,1: Enabled" group.long 0x20++0x3 line.long 0x0 "DIRSR0,SIUL2 DMA/Interrupt Request Select 0" bitfld.long 0x0 31. "DIRSR31,DMA/Interrupt Request Select Register" "0: Interrupt request,?" newline bitfld.long 0x0 30. "DIRSR30,DMA/Interrupt Request Select Register" "0: Interrupt request,?" newline bitfld.long 0x0 29. "DIRSR29,DMA/Interrupt Request Select Register" "0: Interrupt request,?" newline bitfld.long 0x0 28. "DIRSR28,DMA/Interrupt Request Select Register" "0: Interrupt request,?" newline bitfld.long 0x0 27. "DIRSR27,DMA/Interrupt Request Select Register" "0: Interrupt request,?" newline bitfld.long 0x0 26. "DIRSR26,DMA/Interrupt Request Select Register" "0: Interrupt request,?" newline bitfld.long 0x0 25. "DIRSR25,DMA/Interrupt Request Select Register" "0: Interrupt request,?" newline bitfld.long 0x0 24. "DIRSR24,DMA/Interrupt Request Select Register" "0: Interrupt request,?" newline bitfld.long 0x0 23. "DIRSR23,DMA/Interrupt Request Select Register" "0: Interrupt request,?" newline bitfld.long 0x0 22. "DIRSR22,DMA/Interrupt Request Select Register" "0: Interrupt request,?" newline bitfld.long 0x0 21. "DIRSR21,DMA/Interrupt Request Select Register" "0: Interrupt request,?" newline bitfld.long 0x0 20. "DIRSR20,DMA/Interrupt Request Select Register" "0: Interrupt request,?" newline bitfld.long 0x0 19. "DIRSR19,DMA/Interrupt Request Select Register" "0: Interrupt request,?" newline bitfld.long 0x0 18. "DIRSR18,DMA/Interrupt Request Select Register" "0: Interrupt request,?" newline bitfld.long 0x0 17. "DIRSR17,DMA/Interrupt Request Select Register" "0: Interrupt request,?" newline bitfld.long 0x0 16. "DIRSR16,DMA/Interrupt Request Select Register" "0: Interrupt request,?" newline bitfld.long 0x0 15. "DIRSR15,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 14. "DIRSR14,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 13. "DIRSR13,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 12. "DIRSR12,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 11. "DIRSR11,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 10. "DIRSR10,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 9. "DIRSR9,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 8. "DIRSR8,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 7. "DIRSR7,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 6. "DIRSR6,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 5. "DIRSR5,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 4. "DIRSR4,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 3. "DIRSR3,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 2. "DIRSR2,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 1. "DIRSR1,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" newline bitfld.long 0x0 0. "DIRSR0,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request" group.long 0x28++0x3 line.long 0x0 "IREER0,SIUL2 Interrupt Rising-Edge Event Enable 0" bitfld.long 0x0 31. "IREE31,Enables rising-edge events to set DISR0[EIF31]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 30. "IREE30,Enables rising-edge events to set DISR0[EIF30]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 29. "IREE29,Enables rising-edge events to set DISR0[EIF29]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 28. "IREE28,Enables rising-edge events to set DISR0[EIF28]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 27. "IREE27,Enables rising-edge events to set DISR0[EIF27]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 26. "IREE26,Enables rising-edge events to set DISR0[EIF26]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 25. "IREE25,Enables rising-edge events to set DISR0[EIF25]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 24. "IREE24,Enables rising-edge events to set DISR0[EIF24]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 23. "IREE23,Enables rising-edge events to set DISR0[EIF23]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 22. "IREE22,Enables rising-edge events to set DISR0[EIF22]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 21. "IREE21,Enables rising-edge events to set DISR0[EIF21]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 20. "IREE20,Enables rising-edge events to set DISR0[EIF20]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 19. "IREE19,Enables rising-edge events to set DISR0[EIF19]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 18. "IREE18,Enables rising-edge events to set DISR0[EIF18]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 17. "IREE17,Enables rising-edge events to set DISR0[EIF17]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 16. "IREE16,Enables rising-edge events to set DISR0[EIF16]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 15. "IREE15,Enables rising-edge events to set DISR0[EIF15]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 14. "IREE14,Enables rising-edge events to set DISR0[EIF14]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 13. "IREE13,Enables rising-edge events to set DISR0[EIF13]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 12. "IREE12,Enables rising-edge events to set DISR0[EIF12]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 11. "IREE11,Enables rising-edge events to set DISR0[EIF11]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 10. "IREE10,Enables rising-edge events to set DISR0[EIF10]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 9. "IREE9,Enables rising-edge events to set DISR0[EIF9]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 8. "IREE8,Enables rising-edge events to set DISR0[EIF8]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 7. "IREE7,Enables rising-edge events to set DISR0[EIF7]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 6. "IREE6,Enables rising-edge events to set DISR0[EIF6]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 5. "IREE5,Enables rising-edge events to set DISR0[EIF5]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 4. "IREE4,Enables rising-edge events to set DISR0[EIF4]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 3. "IREE3,Enables rising-edge events to set DISR0[EIF3]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 2. "IREE2,Enables rising-edge events to set DISR0[EIF2]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 1. "IREE1,Enables rising-edge events to set DISR0[EIF1]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 0. "IREE0,Enables rising-edge events to set DISR0[EIF0]." "0: Disabled,1: Enabled" group.long 0x30++0x3 line.long 0x0 "IFEER0,SIUL2 Interrupt Falling-Edge Event Enable 0" bitfld.long 0x0 31. "IFEE31,Enables falling-edge events to set DISR0[EIF31]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 30. "IFEE30,Enables falling-edge events to set DISR0[EIF30]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 29. "IFEE29,Enables falling-edge events to set DISR0[EIF29]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 28. "IFEE28,Enables falling-edge events to set DISR0[EIF28]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 27. "IFEE27,Enables falling-edge events to set DISR0[EIF27]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 26. "IFEE26,Enables falling-edge events to set DISR0[EIF26]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 25. "IFEE25,Enables falling-edge events to set DISR0[EIF25]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 24. "IFEE24,Enables falling-edge events to set DISR0[EIF24]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 23. "IFEE23,Enables falling-edge events to set DISR0[EIF23]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 22. "IFEE22,Enables falling-edge events to set DISR0[EIF22]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 21. "IFEE21,Enables falling-edge events to set DISR0[EIF21]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 20. "IFEE20,Enables falling-edge events to set DISR0[EIF20]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 19. "IFEE19,Enables falling-edge events to set DISR0[EIF19]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 18. "IFEE18,Enables falling-edge events to set DISR0[EIF18]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 17. "IFEE17,Enables falling-edge events to set DISR0[EIF17]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 16. "IFEE16,Enables falling-edge events to set DISR0[EIF16]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 15. "IFEE15,Enables falling-edge events to set DISR0[EIF15]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 14. "IFEE14,Enables falling-edge events to set DISR0[EIF14]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 13. "IFEE13,Enables falling-edge events to set DISR0[EIF13]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 12. "IFEE12,Enables falling-edge events to set DISR0[EIF12]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 11. "IFEE11,Enables falling-edge events to set DISR0[EIF11]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 10. "IFEE10,Enables falling-edge events to set DISR0[EIF10]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 9. "IFEE9,Enables falling-edge events to set DISR0[EIF9]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 8. "IFEE8,Enables falling-edge events to set DISR0[EIF8]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 7. "IFEE7,Enables falling-edge events to set DISR0[EIF7]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 6. "IFEE6,Enables falling-edge events to set DISR0[EIF6]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 5. "IFEE5,Enables falling-edge events to set DISR0[EIF5]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 4. "IFEE4,Enables falling-edge events to set DISR0[EIF4]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 3. "IFEE3,Enables falling-edge events to set DISR0[EIF3]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 2. "IFEE2,Enables falling-edge events to set DISR0[EIF2]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 1. "IFEE1,Enables falling-edge events to set DISR0[EIF1]." "0: Disabled,1: Enabled" newline bitfld.long 0x0 0. "IFEE0,Enables falling-edge events to set DISR0[EIF0]." "0: Disabled,1: Enabled" group.long 0x38++0x3 line.long 0x0 "IFER0,SIUL2 Interrupt Filter Enable 0" bitfld.long 0x0 31. "IFE31,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 30. "IFE30,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 29. "IFE29,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 28. "IFE28,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 27. "IFE27,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 26. "IFE26,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 25. "IFE25,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 24. "IFE24,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 23. "IFE23,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 22. "IFE22,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 21. "IFE21,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 20. "IFE20,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 19. "IFE19,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 18. "IFE18,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 17. "IFE17,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 16. "IFE16,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 15. "IFE15,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 14. "IFE14,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 13. "IFE13,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 12. "IFE12,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 11. "IFE11,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 10. "IFE10,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 9. "IFE9,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 8. "IFE8,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 7. "IFE7,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 6. "IFE6,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 5. "IFE5,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 4. "IFE4,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 3. "IFE3,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 2. "IFE2,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 1. "IFE1,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" newline bitfld.long 0x0 0. "IFE0,Enables digital glitch filter on the interrupt pad input." "0: Disabled,1: Enabled" group.long 0x40++0x83 line.long 0x0 "IFMCR0,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x0 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x4 "IFMCR1,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x4 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x8 "IFMCR2,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x8 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0xC "IFMCR3,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0xC 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x10 "IFMCR4,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x10 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x14 "IFMCR5,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x14 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x18 "IFMCR6,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x18 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x1C "IFMCR7,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x1C 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x20 "IFMCR8,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x20 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x24 "IFMCR9,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x24 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x28 "IFMCR10,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x28 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x2C "IFMCR11,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x2C 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x30 "IFMCR12,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x30 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x34 "IFMCR13,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x34 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x38 "IFMCR14,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x38 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x3C "IFMCR15,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x3C 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x40 "IFMCR16,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x40 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x44 "IFMCR17,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x44 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x48 "IFMCR18,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x48 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x4C "IFMCR19,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x4C 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x50 "IFMCR20,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x50 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x54 "IFMCR21,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x54 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x58 "IFMCR22,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x58 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x5C "IFMCR23,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x5C 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x60 "IFMCR24,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x60 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x64 "IFMCR25,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x64 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x68 "IFMCR26,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x68 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x6C "IFMCR27,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x6C 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x70 "IFMCR28,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x70 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x74 "IFMCR29,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x74 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x78 "IFMCR30,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x78 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x7C "IFMCR31,SIUL2 Interrupt Filter Maximum Counter" hexmask.long.byte 0x7C 0.--3. 1. "MAXCNT,Maximum Interrupt Filter Counter setting" line.long 0x80 "IFCPR,SIUL2 Interrupt Filter Clock Prescaler" hexmask.long.byte 0x80 0.--3. 1. "IFCP,Interrupt Filter Clock Prescaler setting" group.long 0x100++0x17 line.long 0x0 "MUX0_EMIOS_EN1,SIUL2 User Defined" bitfld.long 0x0 31. "EMIOSFLG15_EN,EMIOS0 Output Flag 15 Monitor Enable" "0,1" newline bitfld.long 0x0 30. "EMIOSFLG14_EN,EMIOS0 Output Flag 14 Monitor Enable" "0,1" newline bitfld.long 0x0 29. "EMIOSFLG13_EN,EMIOS0 Output Flag 13 Monitor Enable" "0,1" newline bitfld.long 0x0 28. "EMIOSFLG12_EN,EMIOS0 Output Flag 12 Monitor Enable" "0,1" newline bitfld.long 0x0 27. "EMIOSFLG11_EN,EMIOS0 Output Flag 11 Monitor Enable" "0,1" newline bitfld.long 0x0 26. "EMIOSFLG10_EN,EMIOS0 Output Flag 10 Monitor Enable" "0,1" newline bitfld.long 0x0 25. "EMIOSFLG9_EN,EMIOS0 Output Flag 9 Monitor Enable" "0,1" newline bitfld.long 0x0 24. "EMIOSFLG8_EN,EMIOS0 Output Flag 8 Monitor Enable" "0,1" newline bitfld.long 0x0 23. "EMIOSFLG7_EN,EMIOS0 Output Flag 7 Monitor Enable" "0,1" newline bitfld.long 0x0 22. "EMIOSFLG6_EN,EMIOS0 Output Flag 6 Monitor Enable" "0,1" newline bitfld.long 0x0 21. "EMIOSFLG5_EN,EMIOS0 Output Flag 5 Monitor Enable" "0,1" newline bitfld.long 0x0 20. "EMIOSFLG4_EN,EMIOS0 Output Flag 4 Monitor Enable" "0,1" newline bitfld.long 0x0 19. "EMIOSFLG3_EN,EMIOS0 Output Flag 3 Monitor Enable" "0,1" newline bitfld.long 0x0 18. "EMIOSFLG2_EN,EMIOS0 Output Flag 2 Monitor Enable" "0,1" newline bitfld.long 0x0 17. "EMIOSFLG1_EN,EMIOS0 Output Flag 1 Monitor Enable" "0,1" newline bitfld.long 0x0 16. "EMIOSFLG0_EN,EMIOS0 Output Flag 0 Monitor Enable" "0,1" newline bitfld.long 0x0 7. "EMIOSFLG23_EN,EMIOS0 Output Flag 23 Monitor Enable" "0,1" newline bitfld.long 0x0 6. "EMIOSFLG22_EN,EMIOS0 Output Flag 22 Monitor Enable" "0,1" newline bitfld.long 0x0 5. "EMIOSFLG21_EN,EMIOS0 Output Flag 21 Monitor Enable" "0,1" newline bitfld.long 0x0 4. "EMIOSFLG20_EN,EMIOS0 Output Flag 20 Monitor Enable" "0,1" newline bitfld.long 0x0 3. "EMIOSFLG19_EN,EMIOS0 Output Flag 19 Monitor Enable" "0,1" newline bitfld.long 0x0 2. "EMIOSFLG18_EN,EMIOS0 Output Flag 18 Monitor Enable" "0,1" newline bitfld.long 0x0 1. "EMIOSFLG17_EN,EMIOS0 Output Flag 17 Monitor Enable" "0,1" newline bitfld.long 0x0 0. "EMIOSFLG16_EN,EMIOS0 Output Flag 16 Monitor Enable" "0,1" line.long 0x4 "MUX0_MISC_EN,SIUL2 User Defined" bitfld.long 0x4 26. "BCTUADC2INT_EN,BCTU ADC2DR Interrupt Request Monitor Enable" "0,1" newline bitfld.long 0x4 25. "BCTUADC1INT_EN,BCTU ADC1DR Interrupt Request Monitor Enable" "0,1" newline bitfld.long 0x4 24. "BCTUADC0INT_EN,BCTU ADC0DR Interrupt Request Monitor Enable" "0,1" newline bitfld.long 0x4 23. "BCTULISTINT_EN,BCTU Conversion List Interrupt Request Enable" "0,1" newline bitfld.long 0x4 22. "BCTUFIFO1INT_EN,BCTU FIFO0 Interrupt Request Monitor Enable" "0,1" newline bitfld.long 0x4 21. "BCTUFIFO0INT_EN,BCTU FIFO0 Interrupt Request Monitor Enable" "0,1" newline bitfld.long 0x4 20. "BCTUADC2DMA_EN,BCTU ADC2DR DMA Request Monitor Enable" "0,1" newline bitfld.long 0x4 19. "BCTUADC1DMA_EN,BCTU ADC1DR DMA Request Monitor Enable" "0,1" newline bitfld.long 0x4 18. "BCTUADC0DMA_EN,BCTU ADC0DR DMA Request Monitor Enable" "0,1" newline bitfld.long 0x4 17. "BCTUFIFO1DMA_EN,BCTU FIFO1 DMA Request Monitor Enable" "0,1" newline bitfld.long 0x4 16. "BCTUFIFO0DMA_EN,BCTU FIFO0 DMA Request Monitor Enable" "0,1" newline bitfld.long 0x4 11. "LPUART3TRG_EN,LPUART3 Output Trigger Monitor Enable" "0,1" newline bitfld.long 0x4 10. "LPUART2TRG_EN,LPUART2 Output Trigger Monitor Enable" "0,1" newline bitfld.long 0x4 9. "LPUART1TRG_EN,LPUART1 Output Trigger Monitor Enable" "0,1" newline bitfld.long 0x4 8. "LPUART0TRG_EN,LPUART0 Output Trigger Monitor Enable" "0,1" newline bitfld.long 0x4 2. "ADC2EOC_EN,ADC2 End of Conversion Trigger Monitor" "0,1" newline bitfld.long 0x4 1. "ADC1EOC_EN,ADC1 End of Conversion Trigger Monitor" "0,1" newline bitfld.long 0x4 0. "ADC0EOC_EN,ADC0 End of Conversion Trigger Monitor" "0,1" line.long 0x8 "MUX1_EMIOS_EN,SIUL2 User Defined" bitfld.long 0x8 31. "EMIOSFLG15_EN,EMIOS0 Output Flag 15 Monitor Enable" "0,1" newline bitfld.long 0x8 30. "EMIOSFLG14_EN,EMIOS0 Output Flag 14 Monitor Enable" "0,1" newline bitfld.long 0x8 29. "EMIOSFLG13_EN,EMIOS0 Output Flag 13 Monitor Enable" "0,1" newline bitfld.long 0x8 28. "EMIOSFLG12_EN,EMIOS0 Output Flag 12 Monitor Enable" "0,1" newline bitfld.long 0x8 27. "EMIOSFLG11_EN,EMIOS0 Output Flag 11 Monitor Enable" "0,1" newline bitfld.long 0x8 26. "EMIOSFLG10_EN,EMIOS0 Output Flag 10 Monitor Enable" "0,1" newline bitfld.long 0x8 25. "EMIOSFLG9_EN,EMIOS0 Output Flag 9 Monitor Enable" "0,1" newline bitfld.long 0x8 24. "EMIOSFLG8_EN,EMIOS0 Output Flag 8 Monitor Enable" "0,1" newline bitfld.long 0x8 23. "EMIOSFLG7_EN,EMIOS0 Output Flag 7 Monitor Enable" "0,1" newline bitfld.long 0x8 22. "EMIOSFLG6_EN,EMIOS0 Output Flag 6 Monitor Enable" "0,1" newline bitfld.long 0x8 21. "EMIOSFLG5_EN,EMIOS0 Output Flag 5 Monitor Enable" "0,1" newline bitfld.long 0x8 20. "EMIOSFLG4_EN,EMIOS0 Output Flag 4 Monitor Enable" "0,1" newline bitfld.long 0x8 19. "EMIOSFLG3_EN,EMIOS0 Output Flag 3 Monitor Enable" "0,1" newline bitfld.long 0x8 18. "EMIOSFLG2_EN,EMIOS0 Output Flag 2 Monitor Enable" "0,1" newline bitfld.long 0x8 17. "EMIOSFLG1_EN,EMIOS0 Output Flag 1 Monitor Enable" "0,1" newline bitfld.long 0x8 16. "EMIOSFLG0_EN,EMIOS0 Output Flag 0 Monitor Enable" "0,1" newline bitfld.long 0x8 7. "EMIOSFLG23_EN,EMIOS0 Output Flag 23 Monitor Enable" "0,1" newline bitfld.long 0x8 6. "EMIOSFLG22_EN,EMIOS0 Output Flag 22 Monitor Enable" "0,1" newline bitfld.long 0x8 5. "EMIOSFLG21_EN,EMIOS0 Output Flag 21 Monitor Enable" "0,1" newline bitfld.long 0x8 4. "EMIOSFLG20_EN,EMIOS0 Output Flag 20 Monitor Enable" "0,1" newline bitfld.long 0x8 3. "EMIOSFLG19_EN,EMIOS0 Output Flag 19 Monitor Enable" "0,1" newline bitfld.long 0x8 2. "EMIOSFLG18_EN,EMIOS0 Output Flag 18 Monitor Enable" "0,1" newline bitfld.long 0x8 1. "EMIOSFLG17_EN,EMIOS0 Output Flag 17 Monitor Enable" "0,1" newline bitfld.long 0x8 0. "EMIOSFLG16_EN,EMIOS0 Output Flag 16 Monitor Enable" "0,1" line.long 0xC "MUX1_MISC_EN,SIUL2 User Defined" bitfld.long 0xC 26. "BCTUADC2INT_EN,BCTU ADC2DR Interrupt Request Monitor Enable" "0,1" newline bitfld.long 0xC 25. "BCTUADC1INT_EN,BCTU ADC1DR Interrupt Request Monitor Enable" "0,1" newline bitfld.long 0xC 24. "BCTUADC0INT_EN,BCTU ADC0DR Interrupt Request Monitor Enable" "0,1" newline bitfld.long 0xC 23. "BCTULISTINT_EN,BCTU Conversion List Interrupt Request Enable" "0,1" newline bitfld.long 0xC 22. "BCTUFIFO1INT_EN,BCTU FIFO0 Interrupt Request Monitor Enable" "0,1" newline bitfld.long 0xC 21. "BCTUFIFO0INT_EN,BCTU FIFO0 Interrupt Request Monitor Enable" "0,1" newline bitfld.long 0xC 20. "BCTUADC2DMA_EN,BCTU ADC2DR DMA Request Monitor Enable" "0,1" newline bitfld.long 0xC 19. "BCTUADC1DMA_EN,BCTU ADC1DR DMA Request Monitor Enable" "0,1" newline bitfld.long 0xC 18. "BCTUADC0DMA_EN,BCTU ADC0DR DMA Request Monitor Enable" "0,1" newline bitfld.long 0xC 17. "BCTUFIFO1DMA_EN,BCTU FIFO1 DMA Request Monitor Enable" "0,1" newline bitfld.long 0xC 16. "BCTUFIFO0DMA_EN,BCTU FIFO0 DMA Request Monitor Enable" "0,1" newline bitfld.long 0xC 11. "LPUART3TRG_EN,LPUART3 Output Trigger Monitor Enable" "0,1" newline bitfld.long 0xC 10. "LPUART2TRG_EN,LPUART2 Output Trigger Monitor Enable" "0,1" newline bitfld.long 0xC 9. "LPUART1TRG_EN,LPUART1 Output Trigger Monitor Enable" "0,1" newline bitfld.long 0xC 8. "LPUART0TRG_EN,LPUART0 Output Trigger Monitor Enable" "0,1" newline bitfld.long 0xC 2. "ADC2EOC_EN,ADC2 End of Conversion Trigger Monitor" "0,1" newline bitfld.long 0xC 1. "ADC1EOC_EN,ADC1 End of Conversion Trigger Monitor" "0,1" newline bitfld.long 0xC 0. "ADC0EOC_EN,ADC0 End of Conversion Trigger Monitor" "0,1" line.long 0x10 "MUX2_EMIOS_EN,SIUL2 User Defined" bitfld.long 0x10 31. "EMIOSFLG15_EN,EMIOS0 Output Flag 15 Monitor Enable" "0,1" newline bitfld.long 0x10 30. "EMIOSFLG14_EN,EMIOS0 Output Flag 14 Monitor Enable" "0,1" newline bitfld.long 0x10 29. "EMIOSFLG13_EN,EMIOS0 Output Flag 13 Monitor Enable" "0,1" newline bitfld.long 0x10 28. "EMIOSFLG12_EN,EMIOS0 Output Flag 12 Monitor Enable" "0,1" newline bitfld.long 0x10 27. "EMIOSFLG11_EN,EMIOS0 Output Flag 11 Monitor Enable" "0,1" newline bitfld.long 0x10 26. "EMIOSFLG10_EN,EMIOS0 Output Flag 10 Monitor Enable" "0,1" newline bitfld.long 0x10 25. "EMIOSFLG9_EN,EMIOS0 Output Flag 9 Monitor Enable" "0,1" newline bitfld.long 0x10 24. "EMIOSFLG8_EN,EMIOS0 Output Flag 8 Monitor Enable" "0,1" newline bitfld.long 0x10 23. "EMIOSFLG7_EN,EMIOS0 Output Flag 7 Monitor Enable" "0,1" newline bitfld.long 0x10 22. "EMIOSFLG6_EN,EMIOS0 Output Flag 6 Monitor Enable" "0,1" newline bitfld.long 0x10 21. "EMIOSFLG5_EN,EMIOS0 Output Flag 5 Monitor Enable" "0,1" newline bitfld.long 0x10 20. "EMIOSFLG4_EN,EMIOS0 Output Flag 4 Monitor Enable" "0,1" newline bitfld.long 0x10 19. "EMIOSFLG3_EN,EMIOS0 Output Flag 3 Monitor Enable" "0,1" newline bitfld.long 0x10 18. "EMIOSFLG2_EN,EMIOS0 Output Flag 2 Monitor Enable" "0,1" newline bitfld.long 0x10 17. "EMIOSFLG1_EN,EMIOS0 Output Flag 1 Monitor Enable" "0,1" newline bitfld.long 0x10 16. "EMIOSFLG0_EN,EMIOS0 Output Flag 0 Monitor Enable" "0,1" newline bitfld.long 0x10 7. "EMIOSFLG23_EN,EMIOS0 Output Flag 23 Monitor Enable" "0,1" newline bitfld.long 0x10 6. "EMIOSFLG22_EN,EMIOS0 Output Flag 22 Monitor Enable" "0,1" newline bitfld.long 0x10 5. "EMIOSFLG21_EN,EMIOS0 Output Flag 21 Monitor Enable" "0,1" newline bitfld.long 0x10 4. "EMIOSFLG20_EN,EMIOS0 Output Flag 20 Monitor Enable" "0,1" newline bitfld.long 0x10 3. "EMIOSFLG19_EN,EMIOS0 Output Flag 19 Monitor Enable" "0,1" newline bitfld.long 0x10 2. "EMIOSFLG18_EN,EMIOS0 Output Flag 18 Monitor Enable" "0,1" newline bitfld.long 0x10 1. "EMIOSFLG17_EN,EMIOS0 Output Flag 17 Monitor Enable" "0,1" newline bitfld.long 0x10 0. "EMIOSFLG16_EN,EMIOS0 Output Flag 16 Monitor Enable" "0,1" line.long 0x14 "MUX2_MISC_EN,SIUL2 User Defined" bitfld.long 0x14 26. "BCTUADC2INT_EN,BCTU ADC2DR Interrupt Request Monitor Enable" "0,1" newline bitfld.long 0x14 25. "BCTUADC1INT_EN,BCTU ADC1DR Interrupt Request Monitor Enable" "0,1" newline bitfld.long 0x14 24. "BCTUADC0INT_EN,BCTU ADC0DR Interrupt Request Monitor Enable" "0,1" newline bitfld.long 0x14 23. "BCTULISTINT_EN,BCTU Conversion List Interrupt Request Enable" "0,1" newline bitfld.long 0x14 22. "BCTUFIFO1INT_EN,BCTU FIFO0 Interrupt Request Monitor Enable" "0,1" newline bitfld.long 0x14 21. "BCTUFIFO0INT_EN,BCTU FIFO0 Interrupt Request Monitor Enable" "0,1" newline bitfld.long 0x14 20. "BCTUADC2DMA_EN,BCTU ADC2DR DMA Request Monitor Enable" "0,1" newline bitfld.long 0x14 19. "BCTUADC1DMA_EN,BCTU ADC1DR DMA Request Monitor Enable" "0,1" newline bitfld.long 0x14 18. "BCTUADC0DMA_EN,BCTU ADC0DR DMA Request Monitor Enable" "0,1" newline bitfld.long 0x14 17. "BCTUFIFO1DMA_EN,BCTU FIFO1 DMA Request Monitor Enable" "0,1" newline bitfld.long 0x14 16. "BCTUFIFO0DMA_EN,BCTU FIFO0 DMA Request Monitor Enable" "0,1" newline bitfld.long 0x14 11. "LPUART3TRG_EN,LPUART3 Output Trigger Monitor Enable" "0,1" newline bitfld.long 0x14 10. "LPUART2TRG_EN,LPUART2 Output Trigger Monitor Enable" "0,1" newline bitfld.long 0x14 9. "LPUART1TRG_EN,LPUART1 Output Trigger Monitor Enable" "0,1" newline bitfld.long 0x14 8. "LPUART0TRG_EN,LPUART0 Output Trigger Monitor Enable" "0,1" newline bitfld.long 0x14 2. "ADC2EOC_EN,ADC2 End of Conversion Trigger Monitor" "0,1" newline bitfld.long 0x14 1. "ADC1EOC_EN,ADC1 End of Conversion Trigger Monitor" "0,1" newline bitfld.long 0x14 0. "ADC0EOC_EN,ADC0 End of Conversion Trigger Monitor" "0,1" rgroup.long 0x200++0x7 line.long 0x0 "MIDR3,SIUL2 MCU ID 3" hexmask.long.byte 0x0 26.--31. 1. "PROD_FAM_LET,Product Family Letter" newline hexmask.long.word 0x0 16.--25. 1. "PROD_FAM_NO,Product Family Number" newline hexmask.long.byte 0x0 10.--15. 1. "PART_NO_SUF,Part Number Suffix" newline hexmask.long.byte 0x0 0.--5. 1. "SYS_RAM_SIZE,System RAM Size" line.long 0x4 "MIDR4,SIUL2 MCU ID 4" bitfld.long 0x4 14.--15. "CORE_PLAT_FET_1,Core Platform Options Feature" "0,1,2,3" newline bitfld.long 0x4 5.--6. "SEC_FET,Security Feature" "?,1: HSE,?,?" newline bitfld.long 0x4 3.--4. "EMAC_FET,Ethernet Feature" "0: No Ethernet,1: Ethernet present,?,?" newline bitfld.long 0x4 0.--2. "CORE_PLAT_FET_2,Core Platform Options Feature" "0,1,2,3,4,5,6,7" group.long 0x240++0x97 line.long 0x0 "MSCR0,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x0 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x0 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x0 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x0 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x0 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x0 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x0 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x0 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x0 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x0 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x4 "MSCR1,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x4 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x4 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x4 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x4 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x4 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x4 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x4 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x4 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x4 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x4 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x8 "MSCR2,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x8 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x8 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x8 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x8 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x8 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x8 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x8 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x8 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x8 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x8 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x8 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x8 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x8 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xC "MSCR3,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xC 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xC 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xC 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xC 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xC 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xC 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xC 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xC 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xC 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xC 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x10 "MSCR4,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x10 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x10 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x10 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x10 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x10 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x10 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x10 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x10 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x10 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x10 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x10 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x10 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x10 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x10 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x14 "MSCR5,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x14 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x14 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x14 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x14 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x14 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x14 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x14 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x14 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x14 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x14 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x14 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x14 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x14 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x14 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x18 "MSCR6,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x18 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x18 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x18 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x18 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x18 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x18 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x18 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x18 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x18 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x18 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x18 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x18 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x18 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x18 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x1C "MSCR7,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x1C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x1C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x1C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x1C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x1C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x1C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x1C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x1C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x1C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x20 "MSCR8,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x20 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x20 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x20 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x20 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x20 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x20 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x20 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x20 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x20 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x20 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x20 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x20 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x20 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x20 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x24 "MSCR9,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x24 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x24 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x24 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x24 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x24 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x24 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x24 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x24 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x24 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x24 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x24 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x24 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x24 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x24 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x28 "MSCR10,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x28 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x28 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x28 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x28 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x28 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x28 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x28 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x28 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x28 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x28 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x28 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x28 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x28 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x28 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x2C "MSCR11,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x2C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x2C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x2C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x2C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x2C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x2C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x2C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x2C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x2C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x2C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x2C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x30 "MSCR12,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x30 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x30 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x30 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x30 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x30 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x30 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x30 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x30 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x30 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x30 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x30 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x30 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x30 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x30 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x34 "MSCR13,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x34 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x34 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x34 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x34 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x34 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x34 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x34 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x34 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x34 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x34 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x34 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x34 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x34 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x34 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x38 "MSCR14,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x38 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x38 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x38 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x38 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x38 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x38 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x38 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x38 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x38 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x38 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x38 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x38 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x38 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x38 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x3C "MSCR15,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x3C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x3C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x3C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x3C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x3C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x3C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x3C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x3C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x3C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x3C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x3C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x40 "MSCR16,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x40 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x40 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x40 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x40 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x40 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x40 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x40 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x40 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x40 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x40 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x40 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x40 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x40 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x40 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x44 "MSCR17,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x44 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x44 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x44 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x44 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x44 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x44 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x44 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x44 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x44 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x44 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x44 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x44 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x44 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x44 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x48 "MSCR18,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x48 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x48 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x48 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x48 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x48 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x48 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x48 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x48 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x48 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x48 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x48 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x48 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x48 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x48 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x4C "MSCR19,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x4C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x4C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x4C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x4C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x4C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x4C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x4C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x4C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x4C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x4C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x4C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x50 "MSCR20,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x50 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x50 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x50 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x50 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x50 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x50 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x50 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x50 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x50 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x50 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x50 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x50 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x50 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x50 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x54 "MSCR21,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x54 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x54 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x54 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x54 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x54 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x54 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x54 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x54 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x54 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x54 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x54 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x54 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x54 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x54 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x58 "MSCR22,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x58 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x58 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x58 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x58 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x58 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x58 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x58 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x58 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x58 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x58 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x58 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x58 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x58 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x58 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x5C "MSCR23,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x5C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x5C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x5C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x5C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x5C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x5C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x5C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x5C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x5C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x5C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x5C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x60 "MSCR24,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x60 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x60 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x60 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x60 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x60 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x60 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x60 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x60 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x60 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x60 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x60 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x60 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x60 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x60 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x64 "MSCR25,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x64 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x64 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x64 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x64 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x64 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x64 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x64 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x64 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x64 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x64 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x64 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x64 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x64 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x64 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x68 "MSCR26,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x68 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x68 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x68 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x68 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x68 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x68 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x68 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x68 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x68 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x68 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x68 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x68 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x68 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x68 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x6C "MSCR27,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x6C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x6C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x6C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x6C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x6C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x6C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x6C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x6C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x6C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x6C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x6C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x70 "MSCR28,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x70 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x70 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x70 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x70 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x70 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x70 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x70 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x70 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x70 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x70 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x70 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x70 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x70 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x70 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x74 "MSCR29,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x74 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x74 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x74 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x74 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x74 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x74 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x74 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x74 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x74 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x74 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x74 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x74 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x74 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x74 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x78 "MSCR30,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x78 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x78 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x78 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x78 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x78 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x78 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x78 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x78 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x78 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x78 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x78 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x78 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x78 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x78 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x7C "MSCR31,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x7C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x7C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x7C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x7C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x7C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x7C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x7C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x7C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x7C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x7C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x7C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x80 "MSCR32,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x80 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x80 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x80 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x80 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x80 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x80 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x80 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x80 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x80 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x80 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x80 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x80 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x80 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x80 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x84 "MSCR33,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x84 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x84 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x84 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x84 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x84 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x84 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x84 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x84 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x84 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x84 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x84 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x84 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x84 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x84 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x88 "MSCR34,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x88 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x88 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x88 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x88 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x88 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x88 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x88 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x88 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x88 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x88 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x88 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x88 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x88 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x88 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x8C "MSCR35,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x8C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x8C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x8C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x8C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x8C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x8C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x8C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x8C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x8C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x8C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x8C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x8C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x8C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x8C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x90 "MSCR36,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x90 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x90 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x90 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x90 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x90 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x90 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x90 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x90 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x90 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x90 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x90 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x90 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x90 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x90 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x94 "MSCR37,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x94 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x94 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x94 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x94 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x94 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x94 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x94 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x94 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x94 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x94 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x94 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x94 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x94 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x94 0. "SSS_0,Source Signal Select_0" "0,1" group.long 0x2E0++0x193 line.long 0x0 "MSCR40,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x0 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x0 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x0 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x0 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x0 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x0 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x0 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x0 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x0 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x0 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x4 "MSCR41,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x4 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x4 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x4 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x4 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x4 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x4 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x4 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x4 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x4 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x4 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x8 "MSCR42,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x8 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x8 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x8 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x8 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x8 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x8 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x8 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x8 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x8 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x8 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x8 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x8 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x8 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xC "MSCR43,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xC 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xC 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xC 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xC 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xC 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xC 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xC 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xC 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xC 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xC 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x10 "MSCR44,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x10 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x10 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x10 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x10 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x10 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x10 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x10 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x10 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x10 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x10 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x10 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x10 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x10 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x10 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x14 "MSCR45,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x14 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x14 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x14 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x14 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x14 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x14 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x14 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x14 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x14 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x14 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x14 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x14 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x14 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x14 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x18 "MSCR46,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x18 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x18 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x18 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x18 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x18 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x18 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x18 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x18 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x18 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x18 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x18 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x18 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x18 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x18 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x1C "MSCR47,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x1C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x1C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x1C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x1C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x1C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x1C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x1C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x1C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x1C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x20 "MSCR48,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x20 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x20 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x20 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x20 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x20 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x20 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x20 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x20 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x20 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x20 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x20 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x20 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x20 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x20 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x24 "MSCR49,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x24 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x24 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x24 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x24 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x24 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x24 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x24 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x24 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x24 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x24 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x24 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x24 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x24 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x24 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x28 "MSCR50,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x28 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x28 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x28 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x28 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x28 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x28 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x28 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x28 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x28 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x28 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x28 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x28 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x28 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x28 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x2C "MSCR51,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x2C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x2C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x2C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x2C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x2C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x2C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x2C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x2C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x2C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x2C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x2C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x30 "MSCR52,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x30 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x30 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x30 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x30 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x30 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x30 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x30 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x30 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x30 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x30 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x30 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x30 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x30 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x30 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x34 "MSCR53,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x34 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x34 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x34 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x34 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x34 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x34 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x34 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x34 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x34 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x34 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x34 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x34 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x34 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x34 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x38 "MSCR54,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x38 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x38 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x38 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x38 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x38 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x38 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x38 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x38 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x38 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x38 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x38 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x38 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x38 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x38 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x3C "MSCR55,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x3C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x3C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x3C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x3C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x3C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x3C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x3C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x3C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x3C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x3C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x3C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x40 "MSCR56,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x40 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x40 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x40 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x40 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x40 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x40 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x40 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x40 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x40 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x40 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x40 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x40 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x40 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x40 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x44 "MSCR57,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x44 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x44 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x44 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x44 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x44 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x44 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x44 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x44 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x44 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x44 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x44 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x44 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x44 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x44 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x48 "MSCR58,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x48 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x48 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x48 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x48 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x48 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x48 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x48 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x48 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x48 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x48 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x48 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x48 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x48 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x48 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x4C "MSCR59,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x4C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x4C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x4C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x4C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x4C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x4C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x4C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x4C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x4C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x4C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x4C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x50 "MSCR60,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x50 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x50 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x50 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x50 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x50 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x50 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x50 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x50 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x50 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x50 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x50 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x50 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x50 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x50 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x54 "MSCR61,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x54 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x54 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x54 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x54 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x54 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x54 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x54 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x54 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x54 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x54 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x54 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x54 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x54 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x54 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x58 "MSCR62,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x58 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x58 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x58 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x58 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x58 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x58 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x58 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x58 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x58 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x58 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x58 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x58 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x58 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x58 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x5C "MSCR63,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x5C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x5C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x5C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x5C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x5C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x5C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x5C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x5C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x5C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x5C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x5C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x60 "MSCR64,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x60 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x60 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x60 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x60 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x60 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x60 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x60 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x60 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x60 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x60 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x60 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x60 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x60 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x60 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x64 "MSCR65,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x64 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x64 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x64 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x64 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x64 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x64 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x64 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x64 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x64 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x64 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x64 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x64 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x64 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x64 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x68 "MSCR66,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x68 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x68 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x68 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x68 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x68 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x68 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x68 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x68 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x68 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x68 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x68 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x68 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x68 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x68 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x6C "MSCR67,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x6C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x6C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x6C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x6C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x6C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x6C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x6C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x6C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x6C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x6C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x6C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x70 "MSCR68,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x70 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x70 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x70 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x70 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x70 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x70 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x70 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x70 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x70 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x70 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x70 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x70 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x70 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x70 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x74 "MSCR69,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x74 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x74 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x74 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x74 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x74 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x74 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x74 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x74 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x74 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x74 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x74 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x74 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x74 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x74 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x78 "MSCR70,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x78 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x78 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x78 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x78 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x78 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x78 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x78 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x78 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x78 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x78 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x78 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x78 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x78 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x78 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x7C "MSCR71,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x7C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x7C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x7C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x7C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x7C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x7C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x7C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x7C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x7C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x7C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x7C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x80 "MSCR72,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x80 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x80 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x80 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x80 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x80 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x80 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x80 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x80 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x80 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x80 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x80 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x80 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x80 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x80 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x84 "MSCR73,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x84 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x84 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x84 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x84 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x84 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x84 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x84 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x84 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x84 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x84 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x84 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x84 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x84 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x84 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x88 "MSCR74,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x88 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x88 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x88 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x88 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x88 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x88 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x88 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x88 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x88 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x88 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x88 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x88 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x88 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x88 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x8C "MSCR75,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x8C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x8C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x8C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x8C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x8C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x8C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x8C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x8C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x8C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x8C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x8C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x8C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x8C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x8C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x90 "MSCR76,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x90 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x90 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x90 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x90 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x90 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x90 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x90 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x90 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x90 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x90 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x90 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x90 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x90 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x90 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x94 "MSCR77,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x94 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x94 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x94 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x94 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x94 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x94 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x94 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x94 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x94 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x94 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x94 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x94 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x94 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x94 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x98 "MSCR78,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x98 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x98 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x98 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x98 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x98 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x98 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x98 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x98 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x98 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x98 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x98 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x98 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x98 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x98 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x9C "MSCR79,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x9C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x9C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x9C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x9C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x9C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x9C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x9C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x9C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x9C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x9C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x9C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x9C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x9C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x9C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xA0 "MSCR80,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xA0 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xA0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xA0 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xA0 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xA0 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xA0 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xA0 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xA0 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xA0 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xA0 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xA0 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xA0 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xA0 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xA0 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xA4 "MSCR81,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xA4 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xA4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xA4 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xA4 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xA4 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xA4 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xA4 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xA4 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xA4 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xA4 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xA4 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xA4 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xA4 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xA4 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xA8 "MSCR82,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xA8 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xA8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xA8 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xA8 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xA8 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xA8 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xA8 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xA8 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xA8 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xA8 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xA8 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xA8 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xA8 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xA8 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xAC "MSCR83,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xAC 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xAC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xAC 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xAC 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xAC 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xAC 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xAC 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xAC 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xAC 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xAC 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xAC 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xAC 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xAC 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xAC 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xB0 "MSCR84,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xB0 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xB0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xB0 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xB0 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xB0 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xB0 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xB0 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xB0 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xB0 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xB0 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xB0 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xB0 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xB0 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xB0 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xB4 "MSCR85,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xB4 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xB4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xB4 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xB4 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xB4 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xB4 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xB4 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xB4 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xB4 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xB4 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xB4 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xB4 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xB4 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xB4 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xB8 "MSCR86,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xB8 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xB8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xB8 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xB8 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xB8 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xB8 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xB8 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xB8 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xB8 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xB8 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xB8 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xB8 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xB8 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xB8 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xBC "MSCR87,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xBC 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xBC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xBC 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xBC 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xBC 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xBC 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xBC 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xBC 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xBC 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xBC 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xBC 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xBC 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xBC 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xBC 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xC0 "MSCR88,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xC0 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xC0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC0 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xC0 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC0 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xC0 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC0 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xC0 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xC0 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xC0 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xC0 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xC0 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xC0 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xC0 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xC4 "MSCR89,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xC4 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xC4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC4 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xC4 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC4 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xC4 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC4 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xC4 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xC4 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xC4 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xC4 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xC4 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xC4 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xC4 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xC8 "MSCR90,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xC8 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xC8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC8 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xC8 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC8 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xC8 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC8 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xC8 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xC8 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xC8 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xC8 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xC8 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xC8 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xC8 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xCC "MSCR91,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xCC 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xCC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xCC 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xCC 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xCC 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xCC 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xCC 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xCC 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xCC 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xCC 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xCC 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xCC 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xCC 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xCC 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xD0 "MSCR92,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xD0 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xD0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xD0 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xD0 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xD0 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xD0 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xD0 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xD0 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xD0 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xD0 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xD0 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xD0 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xD0 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xD0 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xD4 "MSCR93,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xD4 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xD4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xD4 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xD4 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xD4 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xD4 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xD4 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xD4 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xD4 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xD4 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xD4 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xD4 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xD4 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xD4 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xD8 "MSCR94,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xD8 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xD8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xD8 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xD8 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xD8 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xD8 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xD8 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xD8 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xD8 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xD8 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xD8 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xD8 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xD8 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xD8 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xDC "MSCR95,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xDC 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xDC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xDC 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xDC 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xDC 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xDC 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xDC 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xDC 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xDC 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xDC 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xDC 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xDC 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xDC 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xDC 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xE0 "MSCR96,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xE0 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xE0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xE0 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xE0 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xE0 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xE0 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xE0 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xE0 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xE0 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xE0 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xE0 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xE0 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xE0 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xE0 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xE4 "MSCR97,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xE4 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xE4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xE4 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xE4 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xE4 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xE4 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xE4 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xE4 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xE4 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xE4 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xE4 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xE4 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xE4 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xE4 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xE8 "MSCR98,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xE8 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xE8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xE8 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xE8 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xE8 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xE8 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xE8 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xE8 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xE8 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xE8 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xE8 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xE8 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xE8 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xE8 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xEC "MSCR99,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xEC 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xEC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xEC 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xEC 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xEC 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xEC 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xEC 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xEC 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xEC 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xEC 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xEC 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xEC 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xEC 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xEC 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xF0 "MSCR100,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xF0 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xF0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xF0 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xF0 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xF0 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xF0 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xF0 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xF0 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xF0 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xF0 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xF0 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xF0 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xF0 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xF0 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xF4 "MSCR101,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xF4 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xF4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xF4 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xF4 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xF4 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xF4 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xF4 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xF4 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xF4 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xF4 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xF4 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xF4 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xF4 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xF4 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xF8 "MSCR102,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xF8 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xF8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xF8 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xF8 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xF8 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xF8 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xF8 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xF8 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xF8 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xF8 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xF8 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xF8 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xF8 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xF8 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xFC "MSCR103,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xFC 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xFC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xFC 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xFC 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xFC 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xFC 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xFC 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xFC 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xFC 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xFC 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xFC 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xFC 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xFC 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xFC 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x100 "MSCR104,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x100 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x100 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x100 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x100 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x100 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x100 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x100 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x100 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x100 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x100 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x100 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x100 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x100 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x100 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x104 "MSCR105,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x104 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x104 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x104 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x104 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x104 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x104 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x104 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x104 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x104 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x104 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x104 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x104 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x104 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x104 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x108 "MSCR106,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x108 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x108 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x108 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x108 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x108 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x108 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x108 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x108 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x108 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x108 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x108 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x108 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x108 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x108 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x10C "MSCR107,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x10C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x10C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x10C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x10C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x10C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x10C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x10C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x10C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x10C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x10C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x10C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x10C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x10C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x10C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x110 "MSCR108,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x110 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x110 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x110 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x110 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x110 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x110 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x110 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x110 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x110 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x110 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x110 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x110 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x110 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x110 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x114 "MSCR109,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x114 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x114 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x114 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x114 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x114 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x114 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x114 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x114 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x114 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x114 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x114 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x114 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x114 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x114 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x118 "MSCR110,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x118 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x118 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x118 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x118 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x118 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x118 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x118 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x118 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x118 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x118 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x118 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x118 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x118 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x118 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x11C "MSCR111,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x11C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x11C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x11C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x11C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x11C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x11C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x11C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x11C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x11C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x11C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x11C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x11C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x11C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x11C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x120 "MSCR112,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x120 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x120 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x120 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x120 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x120 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x120 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x120 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x120 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x120 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x120 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x120 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x120 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x120 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x120 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x124 "MSCR113,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x124 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x124 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x124 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x124 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x124 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x124 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x124 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x124 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x124 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x124 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x124 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x124 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x124 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x124 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x128 "MSCR114,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x128 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x128 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x128 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x128 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x128 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x128 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x128 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x128 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x128 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x128 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x128 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x128 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x128 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x128 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x12C "MSCR115,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x12C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x12C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x12C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x12C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x12C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x12C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x12C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x12C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x12C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x12C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x12C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x12C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x12C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x12C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x130 "MSCR116,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x130 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x130 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x130 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x130 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x130 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x130 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x130 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x130 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x130 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x130 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x130 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x130 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x130 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x130 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x134 "MSCR117,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x134 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x134 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x134 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x134 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x134 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x134 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x134 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x134 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x134 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x134 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x134 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x134 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x134 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x134 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x138 "MSCR118,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x138 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x138 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x138 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x138 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x138 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x138 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x138 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x138 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x138 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x138 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x138 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x138 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x138 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x138 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x13C "MSCR119,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x13C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x13C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x13C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x13C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x13C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x13C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x13C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x13C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x13C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x13C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x13C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x13C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x13C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x13C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x140 "MSCR120,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x140 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x140 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x140 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x140 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x140 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x140 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x140 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x140 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x140 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x140 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x140 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x140 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x140 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x140 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x144 "MSCR121,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x144 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x144 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x144 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x144 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x144 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x144 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x144 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x144 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x144 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x144 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x144 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x144 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x144 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x144 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x148 "MSCR122,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x148 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x148 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x148 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x148 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x148 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x148 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x148 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x148 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x148 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x148 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x148 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x148 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x148 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x148 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x14C "MSCR123,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x14C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x14C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x14C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x14C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x14C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x14C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x14C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x14C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x14C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x14C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x14C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x14C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x14C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x14C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x150 "MSCR124,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x150 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x150 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x150 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x150 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x150 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x150 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x150 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x150 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x150 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x150 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x150 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x150 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x150 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x150 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x154 "MSCR125,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x154 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x154 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x154 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x154 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x154 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x154 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x154 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x154 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x154 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x154 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x154 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x154 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x154 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x154 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x158 "MSCR126,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x158 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x158 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x158 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x158 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x158 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x158 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x158 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x158 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x158 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x158 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x158 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x158 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x158 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x158 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x15C "MSCR127,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x15C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x15C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x15C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x15C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x15C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x15C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x15C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x15C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x15C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x15C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x15C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x15C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x15C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x15C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x160 "MSCR128,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x160 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x160 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x160 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x160 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x160 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x160 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x160 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x160 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x160 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x160 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x160 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x160 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x160 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x160 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x164 "MSCR129,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x164 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x164 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x164 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x164 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x164 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x164 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x164 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x164 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x164 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x164 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x164 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x164 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x164 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x164 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x168 "MSCR130,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x168 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x168 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x168 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x168 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x168 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x168 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x168 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x168 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x168 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x168 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x168 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x168 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x168 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x168 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x16C "MSCR131,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x16C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x16C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x16C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x16C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x16C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x16C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x16C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x16C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x16C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x16C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x16C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x16C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x16C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x16C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x170 "MSCR132,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x170 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x170 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x170 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x170 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x170 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x170 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x170 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x170 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x170 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x170 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x170 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x170 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x170 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x170 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x174 "MSCR133,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x174 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x174 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x174 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x174 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x174 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x174 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x174 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x174 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x174 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x174 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x174 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x174 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x174 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x174 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x178 "MSCR134,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x178 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x178 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x178 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x178 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x178 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x178 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x178 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x178 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x178 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x178 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x178 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x178 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x178 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x178 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x17C "MSCR135,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x17C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x17C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x17C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x17C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x17C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x17C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x17C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x17C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x17C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x17C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x17C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x17C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x17C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x17C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x180 "MSCR136,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x180 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x180 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x180 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x180 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x180 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x180 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x180 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x180 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x180 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x180 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x180 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x180 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x180 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x180 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x184 "MSCR137,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x184 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x184 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x184 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x184 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x184 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x184 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x184 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x184 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x184 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x184 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x184 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x184 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x184 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x184 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x188 "MSCR138,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x188 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x188 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x188 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x188 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x188 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x188 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x188 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x188 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x188 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x188 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x188 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x188 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x188 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x188 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x18C "MSCR139,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x18C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x18C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x18C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x18C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x18C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x18C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x18C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x18C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x18C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x18C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x18C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x18C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x18C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x18C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x190 "MSCR140,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x190 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x190 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x190 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x190 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x190 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x190 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x190 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x190 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x190 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x190 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x190 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x190 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x190 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x190 0. "SSS_0,Source Signal Select_0" "0,1" group.long 0x478++0x17B line.long 0x0 "MSCR142,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x0 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x0 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x0 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x0 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x0 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x0 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x0 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x0 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x0 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x0 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x0 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x4 "MSCR143,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x4 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x4 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x4 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x4 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x4 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x4 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x4 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x4 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x4 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x4 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x8 "MSCR144,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x8 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x8 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x8 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x8 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x8 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x8 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x8 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x8 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x8 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x8 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x8 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x8 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x8 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xC "MSCR145,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xC 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xC 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xC 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xC 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xC 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xC 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xC 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xC 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xC 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xC 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x10 "MSCR146,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x10 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x10 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x10 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x10 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x10 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x10 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x10 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x10 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x10 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x10 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x10 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x10 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x10 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x10 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x14 "MSCR147,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x14 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x14 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x14 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x14 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x14 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x14 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x14 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x14 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x14 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x14 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x14 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x14 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x14 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x14 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x18 "MSCR148,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x18 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x18 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x18 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x18 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x18 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x18 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x18 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x18 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x18 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x18 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x18 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x18 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x18 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x18 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x1C "MSCR149,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x1C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x1C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x1C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x1C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x1C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x1C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x1C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x1C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x1C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x1C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x20 "MSCR150,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x20 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x20 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x20 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x20 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x20 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x20 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x20 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x20 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x20 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x20 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x20 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x20 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x20 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x20 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x24 "MSCR151,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x24 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x24 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x24 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x24 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x24 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x24 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x24 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x24 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x24 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x24 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x24 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x24 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x24 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x24 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x28 "MSCR152,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x28 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x28 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x28 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x28 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x28 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x28 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x28 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x28 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x28 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x28 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x28 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x28 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x28 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x28 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x2C "MSCR153,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x2C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x2C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x2C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x2C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x2C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x2C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x2C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x2C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x2C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x2C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x2C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x2C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x30 "MSCR154,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x30 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x30 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x30 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x30 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x30 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x30 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x30 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x30 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x30 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x30 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x30 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x30 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x30 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x30 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x34 "MSCR155,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x34 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x34 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x34 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x34 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x34 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x34 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x34 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x34 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x34 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x34 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x34 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x34 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x34 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x34 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x38 "MSCR156,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x38 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x38 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x38 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x38 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x38 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x38 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x38 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x38 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x38 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x38 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x38 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x38 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x38 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x38 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x3C "MSCR157,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x3C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x3C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x3C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x3C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x3C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x3C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x3C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x3C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x3C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x3C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x3C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x3C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x40 "MSCR158,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x40 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x40 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x40 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x40 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x40 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x40 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x40 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x40 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x40 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x40 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x40 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x40 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x40 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x40 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x44 "MSCR159,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x44 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x44 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x44 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x44 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x44 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x44 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x44 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x44 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x44 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x44 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x44 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x44 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x44 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x44 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x48 "MSCR160,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x48 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x48 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x48 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x48 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x48 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x48 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x48 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x48 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x48 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x48 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x48 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x48 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x48 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x48 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x4C "MSCR161,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x4C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x4C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x4C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x4C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x4C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x4C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x4C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x4C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x4C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x4C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x4C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x4C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x50 "MSCR162,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x50 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x50 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x50 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x50 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x50 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x50 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x50 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x50 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x50 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x50 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x50 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x50 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x50 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x50 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x54 "MSCR163,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x54 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x54 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x54 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x54 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x54 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x54 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x54 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x54 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x54 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x54 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x54 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x54 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x54 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x54 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x58 "MSCR164,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x58 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x58 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x58 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x58 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x58 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x58 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x58 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x58 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x58 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x58 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x58 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x58 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x58 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x58 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x5C "MSCR165,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x5C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x5C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x5C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x5C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x5C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x5C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x5C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x5C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x5C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x5C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x5C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x5C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x60 "MSCR166,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x60 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x60 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x60 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x60 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x60 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x60 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x60 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x60 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x60 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x60 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x60 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x60 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x60 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x60 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x64 "MSCR167,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x64 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x64 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x64 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x64 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x64 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x64 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x64 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x64 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x64 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x64 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x64 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x64 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x64 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x64 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x68 "MSCR168,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x68 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x68 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x68 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x68 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x68 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x68 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x68 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x68 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x68 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x68 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x68 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x68 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x68 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x68 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x6C "MSCR169,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x6C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x6C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x6C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x6C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x6C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x6C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x6C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x6C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x6C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x6C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x6C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x6C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x70 "MSCR170,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x70 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x70 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x70 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x70 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x70 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x70 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x70 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x70 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x70 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x70 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x70 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x70 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x70 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x70 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x74 "MSCR171,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x74 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x74 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x74 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x74 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x74 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x74 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x74 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x74 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x74 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x74 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x74 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x74 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x74 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x74 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x78 "MSCR172,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x78 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x78 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x78 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x78 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x78 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x78 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x78 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x78 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x78 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x78 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x78 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x78 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x78 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x78 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x7C "MSCR173,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x7C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x7C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x7C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x7C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x7C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x7C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x7C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x7C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x7C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x7C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x7C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x7C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x80 "MSCR174,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x80 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x80 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x80 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x80 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x80 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x80 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x80 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x80 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x80 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x80 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x80 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x80 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x80 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x80 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x84 "MSCR175,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x84 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x84 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x84 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x84 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x84 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x84 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x84 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x84 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x84 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x84 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x84 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x84 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x84 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x84 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x88 "MSCR176,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x88 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x88 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x88 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x88 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x88 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x88 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x88 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x88 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x88 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x88 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x88 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x88 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x88 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x88 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x8C "MSCR177,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x8C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x8C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x8C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x8C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x8C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x8C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x8C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x8C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x8C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x8C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x8C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x8C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x8C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x8C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x90 "MSCR178,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x90 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x90 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x90 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x90 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x90 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x90 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x90 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x90 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x90 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x90 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x90 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x90 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x90 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x90 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x94 "MSCR179,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x94 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x94 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x94 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x94 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x94 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x94 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x94 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x94 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x94 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x94 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x94 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x94 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x94 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x94 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x98 "MSCR180,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x98 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x98 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x98 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x98 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x98 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x98 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x98 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x98 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x98 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x98 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x98 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x98 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x98 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x98 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x9C "MSCR181,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x9C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x9C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x9C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x9C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x9C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x9C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x9C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x9C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x9C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x9C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x9C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x9C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x9C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x9C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xA0 "MSCR182,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xA0 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xA0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xA0 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xA0 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xA0 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xA0 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xA0 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xA0 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xA0 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xA0 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xA0 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xA0 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xA0 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xA0 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xA4 "MSCR183,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xA4 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xA4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xA4 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xA4 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xA4 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xA4 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xA4 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xA4 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xA4 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xA4 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xA4 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xA4 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xA4 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xA4 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xA8 "MSCR184,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xA8 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xA8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xA8 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xA8 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xA8 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xA8 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xA8 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xA8 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xA8 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xA8 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xA8 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xA8 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xA8 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xA8 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xAC "MSCR185,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xAC 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xAC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xAC 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xAC 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xAC 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xAC 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xAC 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xAC 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xAC 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xAC 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xAC 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xAC 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xAC 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xAC 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xB0 "MSCR186,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xB0 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xB0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xB0 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xB0 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xB0 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xB0 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xB0 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xB0 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xB0 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xB0 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xB0 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xB0 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xB0 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xB0 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xB4 "MSCR187,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xB4 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xB4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xB4 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xB4 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xB4 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xB4 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xB4 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xB4 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xB4 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xB4 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xB4 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xB4 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xB4 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xB4 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xB8 "MSCR188,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xB8 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xB8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xB8 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xB8 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xB8 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xB8 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xB8 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xB8 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xB8 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xB8 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xB8 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xB8 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xB8 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xB8 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xBC "MSCR189,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xBC 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xBC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xBC 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xBC 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xBC 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xBC 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xBC 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xBC 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xBC 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xBC 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xBC 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xBC 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xBC 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xBC 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xC0 "MSCR190,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xC0 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xC0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC0 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xC0 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC0 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xC0 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC0 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xC0 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xC0 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xC0 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xC0 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xC0 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xC0 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xC0 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xC4 "MSCR191,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xC4 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xC4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC4 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xC4 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC4 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xC4 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC4 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xC4 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xC4 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xC4 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xC4 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xC4 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xC4 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xC4 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xC8 "MSCR192,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xC8 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xC8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC8 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xC8 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC8 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xC8 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xC8 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xC8 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xC8 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xC8 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xC8 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xC8 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xC8 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xC8 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xCC "MSCR193,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xCC 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xCC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xCC 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xCC 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xCC 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xCC 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xCC 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xCC 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xCC 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xCC 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xCC 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xCC 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xCC 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xCC 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xD0 "MSCR194,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xD0 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xD0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xD0 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xD0 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xD0 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xD0 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xD0 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xD0 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xD0 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xD0 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xD0 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xD0 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xD0 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xD0 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xD4 "MSCR195,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xD4 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xD4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xD4 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xD4 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xD4 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xD4 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xD4 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xD4 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xD4 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xD4 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xD4 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xD4 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xD4 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xD4 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xD8 "MSCR196,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xD8 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xD8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xD8 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xD8 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xD8 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xD8 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xD8 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xD8 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xD8 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xD8 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xD8 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xD8 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xD8 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xD8 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xDC "MSCR197,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xDC 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xDC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xDC 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xDC 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xDC 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xDC 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xDC 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xDC 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xDC 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xDC 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xDC 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xDC 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xDC 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xDC 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xE0 "MSCR198,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xE0 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xE0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xE0 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xE0 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xE0 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xE0 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xE0 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xE0 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xE0 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xE0 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xE0 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xE0 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xE0 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xE0 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xE4 "MSCR199,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xE4 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xE4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xE4 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xE4 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xE4 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xE4 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xE4 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xE4 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xE4 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xE4 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xE4 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xE4 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xE4 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xE4 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xE8 "MSCR200,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xE8 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xE8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xE8 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xE8 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xE8 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xE8 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xE8 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xE8 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xE8 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xE8 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xE8 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xE8 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xE8 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xE8 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xEC "MSCR201,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xEC 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xEC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xEC 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xEC 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xEC 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xEC 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xEC 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xEC 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xEC 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xEC 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xEC 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xEC 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xEC 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xEC 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xF0 "MSCR202,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xF0 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xF0 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xF0 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xF0 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xF0 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xF0 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xF0 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xF0 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xF0 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xF0 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xF0 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xF0 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xF0 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xF0 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xF4 "MSCR203,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xF4 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xF4 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xF4 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xF4 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xF4 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xF4 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xF4 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xF4 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xF4 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xF4 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xF4 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xF4 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xF4 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xF4 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xF8 "MSCR204,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xF8 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xF8 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xF8 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xF8 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xF8 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xF8 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xF8 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xF8 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xF8 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xF8 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xF8 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xF8 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xF8 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xF8 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0xFC "MSCR205,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0xFC 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0xFC 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xFC 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0xFC 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0xFC 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0xFC 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0xFC 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0xFC 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0xFC 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0xFC 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0xFC 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0xFC 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0xFC 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0xFC 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x100 "MSCR206,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x100 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x100 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x100 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x100 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x100 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x100 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x100 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x100 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x100 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x100 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x100 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x100 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x100 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x100 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x104 "MSCR207,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x104 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x104 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x104 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x104 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x104 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x104 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x104 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x104 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x104 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x104 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x104 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x104 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x104 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x104 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x108 "MSCR208,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x108 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x108 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x108 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x108 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x108 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x108 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x108 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x108 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x108 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x108 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x108 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x108 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x108 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x108 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x10C "MSCR209,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x10C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x10C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x10C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x10C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x10C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x10C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x10C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x10C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x10C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x10C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x10C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x10C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x10C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x10C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x110 "MSCR210,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x110 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x110 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x110 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x110 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x110 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x110 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x110 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x110 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x110 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x110 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x110 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x110 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x110 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x110 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x114 "MSCR211,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x114 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x114 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x114 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x114 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x114 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x114 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x114 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x114 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x114 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x114 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x114 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x114 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x114 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x114 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x118 "MSCR212,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x118 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x118 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x118 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x118 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x118 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x118 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x118 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x118 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x118 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x118 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x118 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x118 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x118 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x118 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x11C "MSCR213,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x11C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x11C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x11C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x11C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x11C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x11C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x11C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x11C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x11C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x11C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x11C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x11C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x11C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x11C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x120 "MSCR214,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x120 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x120 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x120 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x120 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x120 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x120 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x120 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x120 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x120 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x120 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x120 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x120 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x120 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x120 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x124 "MSCR215,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x124 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x124 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x124 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x124 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x124 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x124 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x124 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x124 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x124 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x124 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x124 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x124 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x124 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x124 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x128 "MSCR216,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x128 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x128 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x128 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x128 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x128 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x128 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x128 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x128 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x128 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x128 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x128 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x128 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x128 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x128 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x12C "MSCR217,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x12C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x12C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x12C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x12C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x12C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x12C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x12C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x12C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x12C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x12C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x12C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x12C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x12C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x12C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x130 "MSCR218,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x130 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x130 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x130 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x130 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x130 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x130 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x130 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x130 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x130 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x130 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x130 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x130 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x130 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x130 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x134 "MSCR219,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x134 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x134 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x134 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x134 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x134 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x134 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x134 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x134 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x134 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x134 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x134 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x134 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x134 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x134 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x138 "MSCR220,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x138 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x138 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x138 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x138 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x138 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x138 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x138 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x138 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x138 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x138 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x138 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x138 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x138 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x138 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x13C "MSCR221,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x13C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x13C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x13C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x13C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x13C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x13C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x13C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x13C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x13C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x13C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x13C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x13C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x13C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x13C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x140 "MSCR222,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x140 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x140 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x140 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x140 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x140 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x140 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x140 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x140 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x140 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x140 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x140 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x140 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x140 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x140 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x144 "MSCR223,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x144 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x144 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x144 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x144 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x144 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x144 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x144 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x144 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x144 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x144 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x144 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x144 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x144 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x144 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x148 "MSCR224,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x148 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x148 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x148 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x148 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x148 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x148 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x148 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x148 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x148 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x148 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x148 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x148 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x148 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x148 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x14C "MSCR225,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x14C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x14C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x14C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x14C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x14C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x14C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x14C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x14C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x14C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x14C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x14C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x14C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x14C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x14C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x150 "MSCR226,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x150 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x150 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x150 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x150 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x150 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x150 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x150 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x150 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x150 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x150 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x150 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x150 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x150 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x150 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x154 "MSCR227,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x154 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x154 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x154 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x154 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x154 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x154 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x154 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x154 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x154 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x154 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x154 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x154 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x154 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x154 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x158 "MSCR228,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x158 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x158 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x158 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x158 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x158 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x158 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x158 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x158 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x158 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x158 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x158 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x158 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x158 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x158 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x15C "MSCR229,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x15C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x15C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x15C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x15C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x15C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x15C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x15C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x15C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x15C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x15C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x15C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x15C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x15C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x15C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x160 "MSCR230,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x160 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x160 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x160 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x160 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x160 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x160 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x160 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x160 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x160 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x160 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x160 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x160 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x160 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x160 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x164 "MSCR231,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x164 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x164 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x164 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x164 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x164 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x164 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x164 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x164 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x164 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x164 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x164 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x164 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x164 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x164 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x168 "MSCR232,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x168 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x168 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x168 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x168 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x168 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x168 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x168 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x168 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x168 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x168 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x168 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x168 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x168 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x168 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x16C "MSCR233,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x16C 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x16C 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x16C 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x16C 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x16C 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x16C 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x16C 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x16C 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x16C 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x16C 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x16C 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x16C 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x16C 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x16C 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x170 "MSCR234,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x170 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x170 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x170 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x170 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x170 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x170 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x170 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x170 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x170 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x170 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x170 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x170 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x170 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x170 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x174 "MSCR235,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x174 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x174 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x174 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x174 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x174 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x174 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x174 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x174 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x174 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x174 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x174 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x174 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x174 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x174 0. "SSS_0,Source Signal Select_0" "0,1" line.long 0x178 "MSCR236,SIUL2 Multiplexed Signal Configuration Register" bitfld.long 0x178 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled" newline bitfld.long 0x178 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x178 17. "INV,Invert" "0: Don't invert,1: Invert" newline bitfld.long 0x178 16. "PKE,Pad keeping enable" "0: Disabled,1: Enabled" newline bitfld.long 0x178 14. "SRC,Slew Rate Control" "0: Fastest setting,1: Slowest setting" newline bitfld.long 0x178 13. "PUE,Pull Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x178 11. "PUS,Pull Select" "0: Pull down,1: Pull up" newline bitfld.long 0x178 8. "DSE,DSE" "0: Disabled,1: Enabled" newline bitfld.long 0x178 6. "IFE,IFE" "0: Disabled,1: Enabled" newline bitfld.long 0x178 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable" newline bitfld.long 0x178 3. "SSS_3,Source Signal Select_3" "0,1" newline bitfld.long 0x178 2. "SSS_2,Source Signal Select_2" "0,1" newline bitfld.long 0x178 1. "SSS_1,Source Signal Select_1" "0,1" newline bitfld.long 0x178 0. "SSS_0,Source Signal Select_0" "0,1" group.long 0xA40++0x17 line.long 0x0 "IMCR0,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x0 0.--3. 1. "SSS,Source Signal Select" line.long 0x4 "IMCR1,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x4 0.--3. 1. "SSS,Source Signal Select" line.long 0x8 "IMCR2,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x8 0.--3. 1. "SSS,Source Signal Select" line.long 0xC "IMCR3,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xC 0.--3. 1. "SSS,Source Signal Select" line.long 0x10 "IMCR4,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x10 0.--3. 1. "SSS,Source Signal Select" line.long 0x14 "IMCR5,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x14 0.--3. 1. "SSS,Source Signal Select" group.long 0xA80++0xDF line.long 0x0 "IMCR16,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x0 0.--3. 1. "SSS,Source Signal Select" line.long 0x4 "IMCR17,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x4 0.--3. 1. "SSS,Source Signal Select" line.long 0x8 "IMCR18,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x8 0.--3. 1. "SSS,Source Signal Select" line.long 0xC "IMCR19,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xC 0.--3. 1. "SSS,Source Signal Select" line.long 0x10 "IMCR20,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x10 0.--3. 1. "SSS,Source Signal Select" line.long 0x14 "IMCR21,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x14 0.--3. 1. "SSS,Source Signal Select" line.long 0x18 "IMCR22,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x18 0.--3. 1. "SSS,Source Signal Select" line.long 0x1C "IMCR23,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x1C 0.--3. 1. "SSS,Source Signal Select" line.long 0x20 "IMCR24,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x20 0.--3. 1. "SSS,Source Signal Select" line.long 0x24 "IMCR25,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x24 0.--3. 1. "SSS,Source Signal Select" line.long 0x28 "IMCR26,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x28 0.--3. 1. "SSS,Source Signal Select" line.long 0x2C "IMCR27,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x2C 0.--3. 1. "SSS,Source Signal Select" line.long 0x30 "IMCR28,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x30 0.--3. 1. "SSS,Source Signal Select" line.long 0x34 "IMCR29,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x34 0.--3. 1. "SSS,Source Signal Select" line.long 0x38 "IMCR30,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x38 0.--3. 1. "SSS,Source Signal Select" line.long 0x3C "IMCR31,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x3C 0.--3. 1. "SSS,Source Signal Select" line.long 0x40 "IMCR32,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x40 0.--3. 1. "SSS,Source Signal Select" line.long 0x44 "IMCR33,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x44 0.--3. 1. "SSS,Source Signal Select" line.long 0x48 "IMCR34,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x48 0.--3. 1. "SSS,Source Signal Select" line.long 0x4C "IMCR35,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x4C 0.--3. 1. "SSS,Source Signal Select" line.long 0x50 "IMCR36,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x50 0.--3. 1. "SSS,Source Signal Select" line.long 0x54 "IMCR37,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x54 0.--3. 1. "SSS,Source Signal Select" line.long 0x58 "IMCR38,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x58 0.--3. 1. "SSS,Source Signal Select" line.long 0x5C "IMCR39,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x5C 0.--3. 1. "SSS,Source Signal Select" line.long 0x60 "IMCR40,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x60 0.--3. 1. "SSS,Source Signal Select" line.long 0x64 "IMCR41,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x64 0.--3. 1. "SSS,Source Signal Select" line.long 0x68 "IMCR42,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x68 0.--3. 1. "SSS,Source Signal Select" line.long 0x6C "IMCR43,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x6C 0.--3. 1. "SSS,Source Signal Select" line.long 0x70 "IMCR44,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x70 0.--3. 1. "SSS,Source Signal Select" line.long 0x74 "IMCR45,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x74 0.--3. 1. "SSS,Source Signal Select" line.long 0x78 "IMCR46,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x78 0.--3. 1. "SSS,Source Signal Select" line.long 0x7C "IMCR47,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x7C 0.--3. 1. "SSS,Source Signal Select" line.long 0x80 "IMCR48,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x80 0.--3. 1. "SSS,Source Signal Select" line.long 0x84 "IMCR49,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x84 0.--3. 1. "SSS,Source Signal Select" line.long 0x88 "IMCR50,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x88 0.--3. 1. "SSS,Source Signal Select" line.long 0x8C "IMCR51,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x8C 0.--3. 1. "SSS,Source Signal Select" line.long 0x90 "IMCR52,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x90 0.--3. 1. "SSS,Source Signal Select" line.long 0x94 "IMCR53,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x94 0.--3. 1. "SSS,Source Signal Select" line.long 0x98 "IMCR54,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x98 0.--3. 1. "SSS,Source Signal Select" line.long 0x9C "IMCR55,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x9C 0.--3. 1. "SSS,Source Signal Select" line.long 0xA0 "IMCR56,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xA0 0.--3. 1. "SSS,Source Signal Select" line.long 0xA4 "IMCR57,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xA4 0.--3. 1. "SSS,Source Signal Select" line.long 0xA8 "IMCR58,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xA8 0.--3. 1. "SSS,Source Signal Select" line.long 0xAC "IMCR59,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xAC 0.--3. 1. "SSS,Source Signal Select" line.long 0xB0 "IMCR60,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xB0 0.--3. 1. "SSS,Source Signal Select" line.long 0xB4 "IMCR61,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xB4 0.--3. 1. "SSS,Source Signal Select" line.long 0xB8 "IMCR62,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xB8 0.--3. 1. "SSS,Source Signal Select" line.long 0xBC "IMCR63,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xBC 0.--3. 1. "SSS,Source Signal Select" line.long 0xC0 "IMCR64,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xC0 0.--3. 1. "SSS,Source Signal Select" line.long 0xC4 "IMCR65,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xC4 0.--3. 1. "SSS,Source Signal Select" line.long 0xC8 "IMCR66,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xC8 0.--3. 1. "SSS,Source Signal Select" line.long 0xCC "IMCR67,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xCC 0.--3. 1. "SSS,Source Signal Select" line.long 0xD0 "IMCR68,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xD0 0.--3. 1. "SSS,Source Signal Select" line.long 0xD4 "IMCR69,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xD4 0.--3. 1. "SSS,Source Signal Select" line.long 0xD8 "IMCR70,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xD8 0.--3. 1. "SSS,Source Signal Select" line.long 0xDC "IMCR71,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xDC 0.--3. 1. "SSS,Source Signal Select" group.long 0xB80++0x5F line.long 0x0 "IMCR80,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x0 0.--3. 1. "SSS,Source Signal Select" line.long 0x4 "IMCR81,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x4 0.--3. 1. "SSS,Source Signal Select" line.long 0x8 "IMCR82,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x8 0.--3. 1. "SSS,Source Signal Select" line.long 0xC "IMCR83,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xC 0.--3. 1. "SSS,Source Signal Select" line.long 0x10 "IMCR84,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x10 0.--3. 1. "SSS,Source Signal Select" line.long 0x14 "IMCR85,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x14 0.--3. 1. "SSS,Source Signal Select" line.long 0x18 "IMCR86,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x18 0.--3. 1. "SSS,Source Signal Select" line.long 0x1C "IMCR87,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x1C 0.--3. 1. "SSS,Source Signal Select" line.long 0x20 "IMCR88,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x20 0.--3. 1. "SSS,Source Signal Select" line.long 0x24 "IMCR89,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x24 0.--3. 1. "SSS,Source Signal Select" line.long 0x28 "IMCR90,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x28 0.--3. 1. "SSS,Source Signal Select" line.long 0x2C "IMCR91,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x2C 0.--3. 1. "SSS,Source Signal Select" line.long 0x30 "IMCR92,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x30 0.--3. 1. "SSS,Source Signal Select" line.long 0x34 "IMCR93,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x34 0.--3. 1. "SSS,Source Signal Select" line.long 0x38 "IMCR94,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x38 0.--3. 1. "SSS,Source Signal Select" line.long 0x3C "IMCR95,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x3C 0.--3. 1. "SSS,Source Signal Select" line.long 0x40 "IMCR96,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x40 0.--3. 1. "SSS,Source Signal Select" line.long 0x44 "IMCR97,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x44 0.--3. 1. "SSS,Source Signal Select" line.long 0x48 "IMCR98,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x48 0.--3. 1. "SSS,Source Signal Select" line.long 0x4C "IMCR99,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x4C 0.--3. 1. "SSS,Source Signal Select" line.long 0x50 "IMCR100,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x50 0.--3. 1. "SSS,Source Signal Select" line.long 0x54 "IMCR101,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x54 0.--3. 1. "SSS,Source Signal Select" line.long 0x58 "IMCR102,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x58 0.--3. 1. "SSS,Source Signal Select" line.long 0x5C "IMCR103,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x5C 0.--3. 1. "SSS,Source Signal Select" group.long 0xC00++0x5F line.long 0x0 "IMCR112,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x0 0.--3. 1. "SSS,Source Signal Select" line.long 0x4 "IMCR113,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x4 0.--3. 1. "SSS,Source Signal Select" line.long 0x8 "IMCR114,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x8 0.--3. 1. "SSS,Source Signal Select" line.long 0xC "IMCR115,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xC 0.--3. 1. "SSS,Source Signal Select" line.long 0x10 "IMCR116,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x10 0.--3. 1. "SSS,Source Signal Select" line.long 0x14 "IMCR117,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x14 0.--3. 1. "SSS,Source Signal Select" line.long 0x18 "IMCR118,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x18 0.--3. 1. "SSS,Source Signal Select" line.long 0x1C "IMCR119,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x1C 0.--3. 1. "SSS,Source Signal Select" line.long 0x20 "IMCR120,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x20 0.--3. 1. "SSS,Source Signal Select" line.long 0x24 "IMCR121,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x24 0.--3. 1. "SSS,Source Signal Select" line.long 0x28 "IMCR122,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x28 0.--3. 1. "SSS,Source Signal Select" line.long 0x2C "IMCR123,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x2C 0.--3. 1. "SSS,Source Signal Select" line.long 0x30 "IMCR124,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x30 0.--3. 1. "SSS,Source Signal Select" line.long 0x34 "IMCR125,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x34 0.--3. 1. "SSS,Source Signal Select" line.long 0x38 "IMCR126,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x38 0.--3. 1. "SSS,Source Signal Select" line.long 0x3C "IMCR127,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x3C 0.--3. 1. "SSS,Source Signal Select" line.long 0x40 "IMCR128,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x40 0.--3. 1. "SSS,Source Signal Select" line.long 0x44 "IMCR129,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x44 0.--3. 1. "SSS,Source Signal Select" line.long 0x48 "IMCR130,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x48 0.--3. 1. "SSS,Source Signal Select" line.long 0x4C "IMCR131,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x4C 0.--3. 1. "SSS,Source Signal Select" line.long 0x50 "IMCR132,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x50 0.--3. 1. "SSS,Source Signal Select" line.long 0x54 "IMCR133,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x54 0.--3. 1. "SSS,Source Signal Select" line.long 0x58 "IMCR134,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x58 0.--3. 1. "SSS,Source Signal Select" line.long 0x5C "IMCR135,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x5C 0.--3. 1. "SSS,Source Signal Select" group.long 0xC80++0x17 line.long 0x0 "IMCR144,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x0 0.--3. 1. "SSS,Source Signal Select" line.long 0x4 "IMCR145,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x4 0.--3. 1. "SSS,Source Signal Select" line.long 0x8 "IMCR146,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x8 0.--3. 1. "SSS,Source Signal Select" line.long 0xC "IMCR147,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xC 0.--3. 1. "SSS,Source Signal Select" line.long 0x10 "IMCR148,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x10 0.--3. 1. "SSS,Source Signal Select" line.long 0x14 "IMCR149,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x14 0.--3. 1. "SSS,Source Signal Select" group.long 0xCA0++0xCB line.long 0x0 "IMCR152,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x0 0.--3. 1. "SSS,Source Signal Select" line.long 0x4 "IMCR153,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x4 0.--3. 1. "SSS,Source Signal Select" line.long 0x8 "IMCR154,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x8 0.--3. 1. "SSS,Source Signal Select" line.long 0xC "IMCR155,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xC 0.--3. 1. "SSS,Source Signal Select" line.long 0x10 "IMCR156,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x10 0.--3. 1. "SSS,Source Signal Select" line.long 0x14 "IMCR157,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x14 0.--3. 1. "SSS,Source Signal Select" line.long 0x18 "IMCR158,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x18 0.--3. 1. "SSS,Source Signal Select" line.long 0x1C "IMCR159,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x1C 0.--3. 1. "SSS,Source Signal Select" line.long 0x20 "IMCR160,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x20 0.--3. 1. "SSS,Source Signal Select" line.long 0x24 "IMCR161,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x24 0.--3. 1. "SSS,Source Signal Select" line.long 0x28 "IMCR162,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x28 0.--3. 1. "SSS,Source Signal Select" line.long 0x2C "IMCR163,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x2C 0.--3. 1. "SSS,Source Signal Select" line.long 0x30 "IMCR164,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x30 0.--3. 1. "SSS,Source Signal Select" line.long 0x34 "IMCR165,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x34 0.--3. 1. "SSS,Source Signal Select" line.long 0x38 "IMCR166,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x38 0.--3. 1. "SSS,Source Signal Select" line.long 0x3C "IMCR167,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x3C 0.--3. 1. "SSS,Source Signal Select" line.long 0x40 "IMCR168,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x40 0.--3. 1. "SSS,Source Signal Select" line.long 0x44 "IMCR169,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x44 0.--3. 1. "SSS,Source Signal Select" line.long 0x48 "IMCR170,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x48 0.--3. 1. "SSS,Source Signal Select" line.long 0x4C "IMCR171,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x4C 0.--3. 1. "SSS,Source Signal Select" line.long 0x50 "IMCR172,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x50 0.--3. 1. "SSS,Source Signal Select" line.long 0x54 "IMCR173,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x54 0.--3. 1. "SSS,Source Signal Select" line.long 0x58 "IMCR174,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x58 0.--3. 1. "SSS,Source Signal Select" line.long 0x5C "IMCR175,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x5C 0.--3. 1. "SSS,Source Signal Select" line.long 0x60 "IMCR176,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x60 0.--3. 1. "SSS,Source Signal Select" line.long 0x64 "IMCR177,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x64 0.--3. 1. "SSS,Source Signal Select" line.long 0x68 "IMCR178,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x68 0.--3. 1. "SSS,Source Signal Select" line.long 0x6C "IMCR179,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x6C 0.--3. 1. "SSS,Source Signal Select" line.long 0x70 "IMCR180,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x70 0.--3. 1. "SSS,Source Signal Select" line.long 0x74 "IMCR181,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x74 0.--3. 1. "SSS,Source Signal Select" line.long 0x78 "IMCR182,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x78 0.--3. 1. "SSS,Source Signal Select" line.long 0x7C "IMCR183,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x7C 0.--3. 1. "SSS,Source Signal Select" line.long 0x80 "IMCR184,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x80 0.--3. 1. "SSS,Source Signal Select" line.long 0x84 "IMCR185,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x84 0.--3. 1. "SSS,Source Signal Select" line.long 0x88 "IMCR186,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x88 0.--3. 1. "SSS,Source Signal Select" line.long 0x8C "IMCR187,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x8C 0.--3. 1. "SSS,Source Signal Select" line.long 0x90 "IMCR188,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x90 0.--3. 1. "SSS,Source Signal Select" line.long 0x94 "IMCR189,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x94 0.--3. 1. "SSS,Source Signal Select" line.long 0x98 "IMCR190,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x98 0.--3. 1. "SSS,Source Signal Select" line.long 0x9C "IMCR191,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x9C 0.--3. 1. "SSS,Source Signal Select" line.long 0xA0 "IMCR192,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xA0 0.--3. 1. "SSS,Source Signal Select" line.long 0xA4 "IMCR193,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xA4 0.--3. 1. "SSS,Source Signal Select" line.long 0xA8 "IMCR194,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xA8 0.--3. 1. "SSS,Source Signal Select" line.long 0xAC "IMCR195,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xAC 0.--3. 1. "SSS,Source Signal Select" line.long 0xB0 "IMCR196,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xB0 0.--3. 1. "SSS,Source Signal Select" line.long 0xB4 "IMCR197,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xB4 0.--3. 1. "SSS,Source Signal Select" line.long 0xB8 "IMCR198,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xB8 0.--3. 1. "SSS,Source Signal Select" line.long 0xBC "IMCR199,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xBC 0.--3. 1. "SSS,Source Signal Select" line.long 0xC0 "IMCR200,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xC0 0.--3. 1. "SSS,Source Signal Select" line.long 0xC4 "IMCR201,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xC4 0.--3. 1. "SSS,Source Signal Select" line.long 0xC8 "IMCR202,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xC8 0.--3. 1. "SSS,Source Signal Select" group.long 0xD8C++0xE7 line.long 0x0 "IMCR211,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x0 0.--3. 1. "SSS,Source Signal Select" line.long 0x4 "IMCR212,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x4 0.--3. 1. "SSS,Source Signal Select" line.long 0x8 "IMCR213,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x8 0.--3. 1. "SSS,Source Signal Select" line.long 0xC "IMCR214,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xC 0.--3. 1. "SSS,Source Signal Select" line.long 0x10 "IMCR215,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x10 0.--3. 1. "SSS,Source Signal Select" line.long 0x14 "IMCR216,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x14 0.--3. 1. "SSS,Source Signal Select" line.long 0x18 "IMCR217,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x18 0.--3. 1. "SSS,Source Signal Select" line.long 0x1C "IMCR218,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x1C 0.--3. 1. "SSS,Source Signal Select" line.long 0x20 "IMCR219,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x20 0.--3. 1. "SSS,Source Signal Select" line.long 0x24 "IMCR220,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x24 0.--3. 1. "SSS,Source Signal Select" line.long 0x28 "IMCR221,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x28 0.--3. 1. "SSS,Source Signal Select" line.long 0x2C "IMCR222,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x2C 0.--3. 1. "SSS,Source Signal Select" line.long 0x30 "IMCR223,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x30 0.--3. 1. "SSS,Source Signal Select" line.long 0x34 "IMCR224,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x34 0.--3. 1. "SSS,Source Signal Select" line.long 0x38 "IMCR225,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x38 0.--3. 1. "SSS,Source Signal Select" line.long 0x3C "IMCR226,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x3C 0.--3. 1. "SSS,Source Signal Select" line.long 0x40 "IMCR227,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x40 0.--3. 1. "SSS,Source Signal Select" line.long 0x44 "IMCR228,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x44 0.--3. 1. "SSS,Source Signal Select" line.long 0x48 "IMCR229,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x48 0.--3. 1. "SSS,Source Signal Select" line.long 0x4C "IMCR230,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x4C 0.--3. 1. "SSS,Source Signal Select" line.long 0x50 "IMCR231,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x50 0.--3. 1. "SSS,Source Signal Select" line.long 0x54 "IMCR232,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x54 0.--3. 1. "SSS,Source Signal Select" line.long 0x58 "IMCR233,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x58 0.--3. 1. "SSS,Source Signal Select" line.long 0x5C "IMCR234,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x5C 0.--3. 1. "SSS,Source Signal Select" line.long 0x60 "IMCR235,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x60 0.--3. 1. "SSS,Source Signal Select" line.long 0x64 "IMCR236,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x64 0.--3. 1. "SSS,Source Signal Select" line.long 0x68 "IMCR237,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x68 0.--3. 1. "SSS,Source Signal Select" line.long 0x6C "IMCR238,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x6C 0.--3. 1. "SSS,Source Signal Select" line.long 0x70 "IMCR239,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x70 0.--3. 1. "SSS,Source Signal Select" line.long 0x74 "IMCR240,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x74 0.--3. 1. "SSS,Source Signal Select" line.long 0x78 "IMCR241,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x78 0.--3. 1. "SSS,Source Signal Select" line.long 0x7C "IMCR242,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x7C 0.--3. 1. "SSS,Source Signal Select" line.long 0x80 "IMCR243,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x80 0.--3. 1. "SSS,Source Signal Select" line.long 0x84 "IMCR244,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x84 0.--3. 1. "SSS,Source Signal Select" line.long 0x88 "IMCR245,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x88 0.--3. 1. "SSS,Source Signal Select" line.long 0x8C "IMCR246,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x8C 0.--3. 1. "SSS,Source Signal Select" line.long 0x90 "IMCR247,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x90 0.--3. 1. "SSS,Source Signal Select" line.long 0x94 "IMCR248,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x94 0.--3. 1. "SSS,Source Signal Select" line.long 0x98 "IMCR249,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x98 0.--3. 1. "SSS,Source Signal Select" line.long 0x9C "IMCR250,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x9C 0.--3. 1. "SSS,Source Signal Select" line.long 0xA0 "IMCR251,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xA0 0.--3. 1. "SSS,Source Signal Select" line.long 0xA4 "IMCR252,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xA4 0.--3. 1. "SSS,Source Signal Select" line.long 0xA8 "IMCR253,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xA8 0.--3. 1. "SSS,Source Signal Select" line.long 0xAC "IMCR254,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xAC 0.--3. 1. "SSS,Source Signal Select" line.long 0xB0 "IMCR255,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xB0 0.--3. 1. "SSS,Source Signal Select" line.long 0xB4 "IMCR256,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xB4 0.--3. 1. "SSS,Source Signal Select" line.long 0xB8 "IMCR257,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xB8 0.--3. 1. "SSS,Source Signal Select" line.long 0xBC "IMCR258,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xBC 0.--3. 1. "SSS,Source Signal Select" line.long 0xC0 "IMCR259,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xC0 0.--3. 1. "SSS,Source Signal Select" line.long 0xC4 "IMCR260,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xC4 0.--3. 1. "SSS,Source Signal Select" line.long 0xC8 "IMCR261,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xC8 0.--3. 1. "SSS,Source Signal Select" line.long 0xCC "IMCR262,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xCC 0.--3. 1. "SSS,Source Signal Select" line.long 0xD0 "IMCR263,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xD0 0.--3. 1. "SSS,Source Signal Select" line.long 0xD4 "IMCR264,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xD4 0.--3. 1. "SSS,Source Signal Select" line.long 0xD8 "IMCR265,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xD8 0.--3. 1. "SSS,Source Signal Select" line.long 0xDC "IMCR266,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xDC 0.--3. 1. "SSS,Source Signal Select" line.long 0xE0 "IMCR267,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xE0 0.--3. 1. "SSS,Source Signal Select" line.long 0xE4 "IMCR268,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xE4 0.--3. 1. "SSS,Source Signal Select" group.long 0xEC4++0x53 line.long 0x0 "IMCR289,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x0 0.--3. 1. "SSS,Source Signal Select" line.long 0x4 "IMCR290,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x4 0.--3. 1. "SSS,Source Signal Select" line.long 0x8 "IMCR291,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x8 0.--3. 1. "SSS,Source Signal Select" line.long 0xC "IMCR292,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xC 0.--3. 1. "SSS,Source Signal Select" line.long 0x10 "IMCR293,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x10 0.--3. 1. "SSS,Source Signal Select" line.long 0x14 "IMCR294,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x14 0.--3. 1. "SSS,Source Signal Select" line.long 0x18 "IMCR295,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x18 0.--3. 1. "SSS,Source Signal Select" line.long 0x1C "IMCR296,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x1C 0.--3. 1. "SSS,Source Signal Select" line.long 0x20 "IMCR297,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x20 0.--3. 1. "SSS,Source Signal Select" line.long 0x24 "IMCR298,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x24 0.--3. 1. "SSS,Source Signal Select" line.long 0x28 "IMCR299,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x28 0.--3. 1. "SSS,Source Signal Select" line.long 0x2C "IMCR300,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x2C 0.--3. 1. "SSS,Source Signal Select" line.long 0x30 "IMCR301,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x30 0.--3. 1. "SSS,Source Signal Select" line.long 0x34 "IMCR302,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x34 0.--3. 1. "SSS,Source Signal Select" line.long 0x38 "IMCR303,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x38 0.--3. 1. "SSS,Source Signal Select" line.long 0x3C "IMCR304,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x3C 0.--3. 1. "SSS,Source Signal Select" line.long 0x40 "IMCR305,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x40 0.--3. 1. "SSS,Source Signal Select" line.long 0x44 "IMCR306,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x44 0.--3. 1. "SSS,Source Signal Select" line.long 0x48 "IMCR307,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x48 0.--3. 1. "SSS,Source Signal Select" line.long 0x4C "IMCR308,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x4C 0.--3. 1. "SSS,Source Signal Select" line.long 0x50 "IMCR309,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x50 0.--3. 1. "SSS,Source Signal Select" group.long 0xF2C++0x2B line.long 0x0 "IMCR315,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x0 0.--3. 1. "SSS,Source Signal Select" line.long 0x4 "IMCR316,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x4 0.--3. 1. "SSS,Source Signal Select" line.long 0x8 "IMCR317,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x8 0.--3. 1. "SSS,Source Signal Select" line.long 0xC "IMCR318,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xC 0.--3. 1. "SSS,Source Signal Select" line.long 0x10 "IMCR319,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x10 0.--3. 1. "SSS,Source Signal Select" line.long 0x14 "IMCR320,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x14 0.--3. 1. "SSS,Source Signal Select" line.long 0x18 "IMCR321,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x18 0.--3. 1. "SSS,Source Signal Select" line.long 0x1C "IMCR322,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x1C 0.--3. 1. "SSS,Source Signal Select" line.long 0x20 "IMCR323,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x20 0.--3. 1. "SSS,Source Signal Select" line.long 0x24 "IMCR324,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x24 0.--3. 1. "SSS,Source Signal Select" line.long 0x28 "IMCR325,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x28 0.--3. 1. "SSS,Source Signal Select" group.long 0xF9C++0x6F line.long 0x0 "IMCR343,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x0 0.--3. 1. "SSS,Source Signal Select" line.long 0x4 "IMCR344,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x4 0.--3. 1. "SSS,Source Signal Select" line.long 0x8 "IMCR345,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x8 0.--3. 1. "SSS,Source Signal Select" line.long 0xC "IMCR346,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xC 0.--3. 1. "SSS,Source Signal Select" line.long 0x10 "IMCR347,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x10 0.--3. 1. "SSS,Source Signal Select" line.long 0x14 "IMCR348,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x14 0.--3. 1. "SSS,Source Signal Select" line.long 0x18 "IMCR349,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x18 0.--3. 1. "SSS,Source Signal Select" line.long 0x1C "IMCR350,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x1C 0.--3. 1. "SSS,Source Signal Select" line.long 0x20 "IMCR351,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x20 0.--3. 1. "SSS,Source Signal Select" line.long 0x24 "IMCR352,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x24 0.--3. 1. "SSS,Source Signal Select" line.long 0x28 "IMCR353,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x28 0.--3. 1. "SSS,Source Signal Select" line.long 0x2C "IMCR354,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x2C 0.--3. 1. "SSS,Source Signal Select" line.long 0x30 "IMCR355,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x30 0.--3. 1. "SSS,Source Signal Select" line.long 0x34 "IMCR356,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x34 0.--3. 1. "SSS,Source Signal Select" line.long 0x38 "IMCR357,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x38 0.--3. 1. "SSS,Source Signal Select" line.long 0x3C "IMCR358,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x3C 0.--3. 1. "SSS,Source Signal Select" line.long 0x40 "IMCR359,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x40 0.--3. 1. "SSS,Source Signal Select" line.long 0x44 "IMCR360,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x44 0.--3. 1. "SSS,Source Signal Select" line.long 0x48 "IMCR361,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x48 0.--3. 1. "SSS,Source Signal Select" line.long 0x4C "IMCR362,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x4C 0.--3. 1. "SSS,Source Signal Select" line.long 0x50 "IMCR363,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x50 0.--3. 1. "SSS,Source Signal Select" line.long 0x54 "IMCR364,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x54 0.--3. 1. "SSS,Source Signal Select" line.long 0x58 "IMCR365,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x58 0.--3. 1. "SSS,Source Signal Select" line.long 0x5C "IMCR366,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x5C 0.--3. 1. "SSS,Source Signal Select" line.long 0x60 "IMCR367,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x60 0.--3. 1. "SSS,Source Signal Select" line.long 0x64 "IMCR368,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x64 0.--3. 1. "SSS,Source Signal Select" line.long 0x68 "IMCR369,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x68 0.--3. 1. "SSS,Source Signal Select" line.long 0x6C "IMCR370,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x6C 0.--3. 1. "SSS,Source Signal Select" group.long 0x1014++0x17 line.long 0x0 "IMCR373,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x0 0.--3. 1. "SSS,Source Signal Select" line.long 0x4 "IMCR374,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x4 0.--3. 1. "SSS,Source Signal Select" line.long 0x8 "IMCR375,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x8 0.--3. 1. "SSS,Source Signal Select" line.long 0xC "IMCR376,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xC 0.--3. 1. "SSS,Source Signal Select" line.long 0x10 "IMCR377,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x10 0.--3. 1. "SSS,Source Signal Select" line.long 0x14 "IMCR378,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x14 0.--3. 1. "SSS,Source Signal Select" group.long 0x1054++0x3 line.long 0x0 "IMCR389,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x0 0.--3. 1. "SSS,Source Signal Select" group.long 0x1078++0x7 line.long 0x0 "IMCR398,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x0 0.--3. 1. "SSS,Source Signal Select" line.long 0x4 "IMCR399,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x4 0.--3. 1. "SSS,Source Signal Select" group.long 0x10A4++0x27 line.long 0x0 "IMCR409,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x0 0.--3. 1. "SSS,Source Signal Select" line.long 0x4 "IMCR410,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x4 0.--3. 1. "SSS,Source Signal Select" line.long 0x8 "IMCR411,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x8 0.--3. 1. "SSS,Source Signal Select" line.long 0xC "IMCR412,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xC 0.--3. 1. "SSS,Source Signal Select" line.long 0x10 "IMCR413,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x10 0.--3. 1. "SSS,Source Signal Select" line.long 0x14 "IMCR414,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x14 0.--3. 1. "SSS,Source Signal Select" line.long 0x18 "IMCR415,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x18 0.--3. 1. "SSS,Source Signal Select" line.long 0x1C "IMCR416,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x1C 0.--3. 1. "SSS,Source Signal Select" line.long 0x20 "IMCR417,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x20 0.--3. 1. "SSS,Source Signal Select" line.long 0x24 "IMCR418,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x24 0.--3. 1. "SSS,Source Signal Select" group.long 0x1120++0x3 line.long 0x0 "IMCR440,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x0 0.--3. 1. "SSS,Source Signal Select" group.long 0x1140++0x57 line.long 0x0 "IMCR448,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x0 0.--3. 1. "SSS,Source Signal Select" line.long 0x4 "IMCR449,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x4 0.--3. 1. "SSS,Source Signal Select" line.long 0x8 "IMCR450,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x8 0.--3. 1. "SSS,Source Signal Select" line.long 0xC "IMCR451,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0xC 0.--3. 1. "SSS,Source Signal Select" line.long 0x10 "IMCR452,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x10 0.--3. 1. "SSS,Source Signal Select" line.long 0x14 "IMCR453,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x14 0.--3. 1. "SSS,Source Signal Select" line.long 0x18 "IMCR454,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x18 0.--3. 1. "SSS,Source Signal Select" line.long 0x1C "IMCR455,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x1C 0.--3. 1. "SSS,Source Signal Select" line.long 0x20 "IMCR456,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x20 0.--3. 1. "SSS,Source Signal Select" line.long 0x24 "IMCR457,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x24 0.--3. 1. "SSS,Source Signal Select" line.long 0x28 "IMCR458,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x28 0.--3. 1. "SSS,Source Signal Select" line.long 0x2C "IMCR459,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x2C 0.--3. 1. "SSS,Source Signal Select" line.long 0x30 "IMCR460,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x30 0.--3. 1. "SSS,Source Signal Select" line.long 0x34 "IMCR461,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x34 0.--3. 1. "SSS,Source Signal Select" line.long 0x38 "IMCR462,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x38 0.--3. 1. "SSS,Source Signal Select" line.long 0x3C "IMCR463,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x3C 0.--3. 1. "SSS,Source Signal Select" line.long 0x40 "IMCR464,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x40 0.--3. 1. "SSS,Source Signal Select" line.long 0x44 "IMCR465,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x44 0.--3. 1. "SSS,Source Signal Select" line.long 0x48 "IMCR466,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x48 0.--3. 1. "SSS,Source Signal Select" line.long 0x4C "IMCR467,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x4C 0.--3. 1. "SSS,Source Signal Select" line.long 0x50 "IMCR468,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x50 0.--3. 1. "SSS,Source Signal Select" line.long 0x54 "IMCR469,SIUL2 Input Multiplexed Signal Configuration" hexmask.long.byte 0x54 0.--3. 1. "SSS,Source Signal Select" group.byte 0x1300++0x23 line.byte 0x0 "GPDO3,SIUL2 GPIO Pad Data Output" bitfld.byte 0x0 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1 "GPDO2,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x2 "GPDO1,SIUL2 GPIO Pad Data Output" bitfld.byte 0x2 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x3 "GPDO0,SIUL2 GPIO Pad Data Output" bitfld.byte 0x3 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x4 "GPDO7,SIUL2 GPIO Pad Data Output" bitfld.byte 0x4 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x5 "GPDO6,SIUL2 GPIO Pad Data Output" bitfld.byte 0x5 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x6 "GPDO5,SIUL2 GPIO Pad Data Output" bitfld.byte 0x6 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x7 "GPDO4,SIUL2 GPIO Pad Data Output" bitfld.byte 0x7 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x8 "GPDO11,SIUL2 GPIO Pad Data Output" bitfld.byte 0x8 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x9 "GPDO10,SIUL2 GPIO Pad Data Output" bitfld.byte 0x9 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0xA "GPDO9,SIUL2 GPIO Pad Data Output" bitfld.byte 0xA 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0xB "GPDO8,SIUL2 GPIO Pad Data Output" bitfld.byte 0xB 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0xC "GPDO15,SIUL2 GPIO Pad Data Output" bitfld.byte 0xC 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0xD "GPDO14,SIUL2 GPIO Pad Data Output" bitfld.byte 0xD 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0xE "GPDO13,SIUL2 GPIO Pad Data Output" bitfld.byte 0xE 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0xF "GPDO12,SIUL2 GPIO Pad Data Output" bitfld.byte 0xF 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x10 "GPDO19,SIUL2 GPIO Pad Data Output" bitfld.byte 0x10 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x11 "GPDO18,SIUL2 GPIO Pad Data Output" bitfld.byte 0x11 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x12 "GPDO17,SIUL2 GPIO Pad Data Output" bitfld.byte 0x12 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x13 "GPDO16,SIUL2 GPIO Pad Data Output" bitfld.byte 0x13 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x14 "GPDO23,SIUL2 GPIO Pad Data Output" bitfld.byte 0x14 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x15 "GPDO22,SIUL2 GPIO Pad Data Output" bitfld.byte 0x15 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x16 "GPDO21,SIUL2 GPIO Pad Data Output" bitfld.byte 0x16 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x17 "GPDO20,SIUL2 GPIO Pad Data Output" bitfld.byte 0x17 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x18 "GPDO27,SIUL2 GPIO Pad Data Output" bitfld.byte 0x18 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x19 "GPDO26,SIUL2 GPIO Pad Data Output" bitfld.byte 0x19 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1A "GPDO25,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1A 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1B "GPDO24,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1B 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1C "GPDO31,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1C 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1D "GPDO30,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1D 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1E "GPDO29,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1E 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1F "GPDO28,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1F 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x20 "GPDO35,SIUL2 GPIO Pad Data Output" bitfld.byte 0x20 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x21 "GPDO34,SIUL2 GPIO Pad Data Output" bitfld.byte 0x21 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x22 "GPDO33,SIUL2 GPIO Pad Data Output" bitfld.byte 0x22 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x23 "GPDO32,SIUL2 GPIO Pad Data Output" bitfld.byte 0x23 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" group.byte 0x1326++0x67 line.byte 0x0 "GPDO37,SIUL2 GPIO Pad Data Output" bitfld.byte 0x0 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1 "GPDO36,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x2 "GPDO43,SIUL2 GPIO Pad Data Output" bitfld.byte 0x2 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x3 "GPDO42,SIUL2 GPIO Pad Data Output" bitfld.byte 0x3 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x4 "GPDO41,SIUL2 GPIO Pad Data Output" bitfld.byte 0x4 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x5 "GPDO40,SIUL2 GPIO Pad Data Output" bitfld.byte 0x5 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x6 "GPDO47,SIUL2 GPIO Pad Data Output" bitfld.byte 0x6 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x7 "GPDO46,SIUL2 GPIO Pad Data Output" bitfld.byte 0x7 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x8 "GPDO45,SIUL2 GPIO Pad Data Output" bitfld.byte 0x8 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x9 "GPDO44,SIUL2 GPIO Pad Data Output" bitfld.byte 0x9 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0xA "GPDO51,SIUL2 GPIO Pad Data Output" bitfld.byte 0xA 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0xB "GPDO50,SIUL2 GPIO Pad Data Output" bitfld.byte 0xB 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0xC "GPDO49,SIUL2 GPIO Pad Data Output" bitfld.byte 0xC 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0xD "GPDO48,SIUL2 GPIO Pad Data Output" bitfld.byte 0xD 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0xE "GPDO55,SIUL2 GPIO Pad Data Output" bitfld.byte 0xE 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0xF "GPDO54,SIUL2 GPIO Pad Data Output" bitfld.byte 0xF 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x10 "GPDO53,SIUL2 GPIO Pad Data Output" bitfld.byte 0x10 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x11 "GPDO52,SIUL2 GPIO Pad Data Output" bitfld.byte 0x11 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x12 "GPDO59,SIUL2 GPIO Pad Data Output" bitfld.byte 0x12 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x13 "GPDO58,SIUL2 GPIO Pad Data Output" bitfld.byte 0x13 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x14 "GPDO57,SIUL2 GPIO Pad Data Output" bitfld.byte 0x14 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x15 "GPDO56,SIUL2 GPIO Pad Data Output" bitfld.byte 0x15 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x16 "GPDO63,SIUL2 GPIO Pad Data Output" bitfld.byte 0x16 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x17 "GPDO62,SIUL2 GPIO Pad Data Output" bitfld.byte 0x17 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x18 "GPDO61,SIUL2 GPIO Pad Data Output" bitfld.byte 0x18 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x19 "GPDO60,SIUL2 GPIO Pad Data Output" bitfld.byte 0x19 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1A "GPDO67,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1A 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1B "GPDO66,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1B 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1C "GPDO65,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1C 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1D "GPDO64,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1D 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1E "GPDO71,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1E 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1F "GPDO70,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1F 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x20 "GPDO69,SIUL2 GPIO Pad Data Output" bitfld.byte 0x20 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x21 "GPDO68,SIUL2 GPIO Pad Data Output" bitfld.byte 0x21 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x22 "GPDO75,SIUL2 GPIO Pad Data Output" bitfld.byte 0x22 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x23 "GPDO74,SIUL2 GPIO Pad Data Output" bitfld.byte 0x23 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x24 "GPDO73,SIUL2 GPIO Pad Data Output" bitfld.byte 0x24 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x25 "GPDO72,SIUL2 GPIO Pad Data Output" bitfld.byte 0x25 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x26 "GPDO79,SIUL2 GPIO Pad Data Output" bitfld.byte 0x26 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x27 "GPDO78,SIUL2 GPIO Pad Data Output" bitfld.byte 0x27 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x28 "GPDO77,SIUL2 GPIO Pad Data Output" bitfld.byte 0x28 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x29 "GPDO76,SIUL2 GPIO Pad Data Output" bitfld.byte 0x29 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x2A "GPDO83,SIUL2 GPIO Pad Data Output" bitfld.byte 0x2A 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x2B "GPDO82,SIUL2 GPIO Pad Data Output" bitfld.byte 0x2B 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x2C "GPDO81,SIUL2 GPIO Pad Data Output" bitfld.byte 0x2C 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x2D "GPDO80,SIUL2 GPIO Pad Data Output" bitfld.byte 0x2D 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x2E "GPDO87,SIUL2 GPIO Pad Data Output" bitfld.byte 0x2E 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x2F "GPDO86,SIUL2 GPIO Pad Data Output" bitfld.byte 0x2F 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x30 "GPDO85,SIUL2 GPIO Pad Data Output" bitfld.byte 0x30 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x31 "GPDO84,SIUL2 GPIO Pad Data Output" bitfld.byte 0x31 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x32 "GPDO91,SIUL2 GPIO Pad Data Output" bitfld.byte 0x32 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x33 "GPDO90,SIUL2 GPIO Pad Data Output" bitfld.byte 0x33 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x34 "GPDO89,SIUL2 GPIO Pad Data Output" bitfld.byte 0x34 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x35 "GPDO88,SIUL2 GPIO Pad Data Output" bitfld.byte 0x35 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x36 "GPDO95,SIUL2 GPIO Pad Data Output" bitfld.byte 0x36 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x37 "GPDO94,SIUL2 GPIO Pad Data Output" bitfld.byte 0x37 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x38 "GPDO93,SIUL2 GPIO Pad Data Output" bitfld.byte 0x38 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x39 "GPDO92,SIUL2 GPIO Pad Data Output" bitfld.byte 0x39 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x3A "GPDO99,SIUL2 GPIO Pad Data Output" bitfld.byte 0x3A 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x3B "GPDO98,SIUL2 GPIO Pad Data Output" bitfld.byte 0x3B 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x3C "GPDO97,SIUL2 GPIO Pad Data Output" bitfld.byte 0x3C 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x3D "GPDO96,SIUL2 GPIO Pad Data Output" bitfld.byte 0x3D 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x3E "GPDO103,SIUL2 GPIO Pad Data Output" bitfld.byte 0x3E 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x3F "GPDO102,SIUL2 GPIO Pad Data Output" bitfld.byte 0x3F 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x40 "GPDO101,SIUL2 GPIO Pad Data Output" bitfld.byte 0x40 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x41 "GPDO100,SIUL2 GPIO Pad Data Output" bitfld.byte 0x41 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x42 "GPDO107,SIUL2 GPIO Pad Data Output" bitfld.byte 0x42 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x43 "GPDO106,SIUL2 GPIO Pad Data Output" bitfld.byte 0x43 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x44 "GPDO105,SIUL2 GPIO Pad Data Output" bitfld.byte 0x44 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x45 "GPDO104,SIUL2 GPIO Pad Data Output" bitfld.byte 0x45 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x46 "GPDO111,SIUL2 GPIO Pad Data Output" bitfld.byte 0x46 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x47 "GPDO110,SIUL2 GPIO Pad Data Output" bitfld.byte 0x47 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x48 "GPDO109,SIUL2 GPIO Pad Data Output" bitfld.byte 0x48 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x49 "GPDO108,SIUL2 GPIO Pad Data Output" bitfld.byte 0x49 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x4A "GPDO115,SIUL2 GPIO Pad Data Output" bitfld.byte 0x4A 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x4B "GPDO114,SIUL2 GPIO Pad Data Output" bitfld.byte 0x4B 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x4C "GPDO113,SIUL2 GPIO Pad Data Output" bitfld.byte 0x4C 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x4D "GPDO112,SIUL2 GPIO Pad Data Output" bitfld.byte 0x4D 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x4E "GPDO119,SIUL2 GPIO Pad Data Output" bitfld.byte 0x4E 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x4F "GPDO118,SIUL2 GPIO Pad Data Output" bitfld.byte 0x4F 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x50 "GPDO117,SIUL2 GPIO Pad Data Output" bitfld.byte 0x50 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x51 "GPDO116,SIUL2 GPIO Pad Data Output" bitfld.byte 0x51 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x52 "GPDO123,SIUL2 GPIO Pad Data Output" bitfld.byte 0x52 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x53 "GPDO122,SIUL2 GPIO Pad Data Output" bitfld.byte 0x53 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x54 "GPDO121,SIUL2 GPIO Pad Data Output" bitfld.byte 0x54 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x55 "GPDO120,SIUL2 GPIO Pad Data Output" bitfld.byte 0x55 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x56 "GPDO127,SIUL2 GPIO Pad Data Output" bitfld.byte 0x56 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x57 "GPDO126,SIUL2 GPIO Pad Data Output" bitfld.byte 0x57 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x58 "GPDO125,SIUL2 GPIO Pad Data Output" bitfld.byte 0x58 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x59 "GPDO124,SIUL2 GPIO Pad Data Output" bitfld.byte 0x59 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x5A "GPDO131,SIUL2 GPIO Pad Data Output" bitfld.byte 0x5A 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x5B "GPDO130,SIUL2 GPIO Pad Data Output" bitfld.byte 0x5B 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x5C "GPDO129,SIUL2 GPIO Pad Data Output" bitfld.byte 0x5C 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x5D "GPDO128,SIUL2 GPIO Pad Data Output" bitfld.byte 0x5D 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x5E "GPDO135,SIUL2 GPIO Pad Data Output" bitfld.byte 0x5E 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x5F "GPDO134,SIUL2 GPIO Pad Data Output" bitfld.byte 0x5F 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x60 "GPDO133,SIUL2 GPIO Pad Data Output" bitfld.byte 0x60 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x61 "GPDO132,SIUL2 GPIO Pad Data Output" bitfld.byte 0x61 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x62 "GPDO139,SIUL2 GPIO Pad Data Output" bitfld.byte 0x62 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x63 "GPDO138,SIUL2 GPIO Pad Data Output" bitfld.byte 0x63 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x64 "GPDO137,SIUL2 GPIO Pad Data Output" bitfld.byte 0x64 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x65 "GPDO136,SIUL2 GPIO Pad Data Output" bitfld.byte 0x65 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x66 "GPDO143,SIUL2 GPIO Pad Data Output" bitfld.byte 0x66 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x67 "GPDO142,SIUL2 GPIO Pad Data Output" bitfld.byte 0x67 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" group.byte 0x138F++0x5C line.byte 0x0 "GPDO140,SIUL2 GPIO Pad Data Output" bitfld.byte 0x0 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1 "GPDO147,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x2 "GPDO146,SIUL2 GPIO Pad Data Output" bitfld.byte 0x2 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x3 "GPDO145,SIUL2 GPIO Pad Data Output" bitfld.byte 0x3 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x4 "GPDO144,SIUL2 GPIO Pad Data Output" bitfld.byte 0x4 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x5 "GPDO151,SIUL2 GPIO Pad Data Output" bitfld.byte 0x5 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x6 "GPDO150,SIUL2 GPIO Pad Data Output" bitfld.byte 0x6 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x7 "GPDO149,SIUL2 GPIO Pad Data Output" bitfld.byte 0x7 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x8 "GPDO148,SIUL2 GPIO Pad Data Output" bitfld.byte 0x8 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x9 "GPDO155,SIUL2 GPIO Pad Data Output" bitfld.byte 0x9 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0xA "GPDO154,SIUL2 GPIO Pad Data Output" bitfld.byte 0xA 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0xB "GPDO153,SIUL2 GPIO Pad Data Output" bitfld.byte 0xB 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0xC "GPDO152,SIUL2 GPIO Pad Data Output" bitfld.byte 0xC 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0xD "GPDO159,SIUL2 GPIO Pad Data Output" bitfld.byte 0xD 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0xE "GPDO158,SIUL2 GPIO Pad Data Output" bitfld.byte 0xE 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0xF "GPDO157,SIUL2 GPIO Pad Data Output" bitfld.byte 0xF 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x10 "GPDO156,SIUL2 GPIO Pad Data Output" bitfld.byte 0x10 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x11 "GPDO163,SIUL2 GPIO Pad Data Output" bitfld.byte 0x11 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x12 "GPDO162,SIUL2 GPIO Pad Data Output" bitfld.byte 0x12 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x13 "GPDO161,SIUL2 GPIO Pad Data Output" bitfld.byte 0x13 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x14 "GPDO160,SIUL2 GPIO Pad Data Output" bitfld.byte 0x14 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x15 "GPDO167,SIUL2 GPIO Pad Data Output" bitfld.byte 0x15 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x16 "GPDO166,SIUL2 GPIO Pad Data Output" bitfld.byte 0x16 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x17 "GPDO165,SIUL2 GPIO Pad Data Output" bitfld.byte 0x17 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x18 "GPDO164,SIUL2 GPIO Pad Data Output" bitfld.byte 0x18 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x19 "GPDO171,SIUL2 GPIO Pad Data Output" bitfld.byte 0x19 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1A "GPDO170,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1A 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1B "GPDO169,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1B 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1C "GPDO168,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1C 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1D "GPDO175,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1D 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1E "GPDO174,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1E 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x1F "GPDO173,SIUL2 GPIO Pad Data Output" bitfld.byte 0x1F 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x20 "GPDO172,SIUL2 GPIO Pad Data Output" bitfld.byte 0x20 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x21 "GPDO179,SIUL2 GPIO Pad Data Output" bitfld.byte 0x21 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x22 "GPDO178,SIUL2 GPIO Pad Data Output" bitfld.byte 0x22 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x23 "GPDO177,SIUL2 GPIO Pad Data Output" bitfld.byte 0x23 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x24 "GPDO176,SIUL2 GPIO Pad Data Output" bitfld.byte 0x24 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x25 "GPDO183,SIUL2 GPIO Pad Data Output" bitfld.byte 0x25 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x26 "GPDO182,SIUL2 GPIO Pad Data Output" bitfld.byte 0x26 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x27 "GPDO181,SIUL2 GPIO Pad Data Output" bitfld.byte 0x27 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x28 "GPDO180,SIUL2 GPIO Pad Data Output" bitfld.byte 0x28 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x29 "GPDO187,SIUL2 GPIO Pad Data Output" bitfld.byte 0x29 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x2A "GPDO186,SIUL2 GPIO Pad Data Output" bitfld.byte 0x2A 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x2B "GPDO185,SIUL2 GPIO Pad Data Output" bitfld.byte 0x2B 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x2C "GPDO184,SIUL2 GPIO Pad Data Output" bitfld.byte 0x2C 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x2D "GPDO191,SIUL2 GPIO Pad Data Output" bitfld.byte 0x2D 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x2E "GPDO190,SIUL2 GPIO Pad Data Output" bitfld.byte 0x2E 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x2F "GPDO189,SIUL2 GPIO Pad Data Output" bitfld.byte 0x2F 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x30 "GPDO188,SIUL2 GPIO Pad Data Output" bitfld.byte 0x30 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x31 "GPDO195,SIUL2 GPIO Pad Data Output" bitfld.byte 0x31 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x32 "GPDO194,SIUL2 GPIO Pad Data Output" bitfld.byte 0x32 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x33 "GPDO193,SIUL2 GPIO Pad Data Output" bitfld.byte 0x33 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x34 "GPDO192,SIUL2 GPIO Pad Data Output" bitfld.byte 0x34 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x35 "GPDO199,SIUL2 GPIO Pad Data Output" bitfld.byte 0x35 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x36 "GPDO198,SIUL2 GPIO Pad Data Output" bitfld.byte 0x36 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x37 "GPDO197,SIUL2 GPIO Pad Data Output" bitfld.byte 0x37 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x38 "GPDO196,SIUL2 GPIO Pad Data Output" bitfld.byte 0x38 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x39 "GPDO203,SIUL2 GPIO Pad Data Output" bitfld.byte 0x39 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x3A "GPDO202,SIUL2 GPIO Pad Data Output" bitfld.byte 0x3A 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x3B "GPDO201,SIUL2 GPIO Pad Data Output" bitfld.byte 0x3B 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x3C "GPDO200,SIUL2 GPIO Pad Data Output" bitfld.byte 0x3C 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x3D "GPDO207,SIUL2 GPIO Pad Data Output" bitfld.byte 0x3D 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x3E "GPDO206,SIUL2 GPIO Pad Data Output" bitfld.byte 0x3E 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x3F "GPDO205,SIUL2 GPIO Pad Data Output" bitfld.byte 0x3F 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x40 "GPDO204,SIUL2 GPIO Pad Data Output" bitfld.byte 0x40 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x41 "GPDO211,SIUL2 GPIO Pad Data Output" bitfld.byte 0x41 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x42 "GPDO210,SIUL2 GPIO Pad Data Output" bitfld.byte 0x42 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x43 "GPDO209,SIUL2 GPIO Pad Data Output" bitfld.byte 0x43 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x44 "GPDO208,SIUL2 GPIO Pad Data Output" bitfld.byte 0x44 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x45 "GPDO215,SIUL2 GPIO Pad Data Output" bitfld.byte 0x45 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x46 "GPDO214,SIUL2 GPIO Pad Data Output" bitfld.byte 0x46 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x47 "GPDO213,SIUL2 GPIO Pad Data Output" bitfld.byte 0x47 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x48 "GPDO212,SIUL2 GPIO Pad Data Output" bitfld.byte 0x48 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x49 "GPDO219,SIUL2 GPIO Pad Data Output" bitfld.byte 0x49 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x4A "GPDO218,SIUL2 GPIO Pad Data Output" bitfld.byte 0x4A 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x4B "GPDO217,SIUL2 GPIO Pad Data Output" bitfld.byte 0x4B 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x4C "GPDO216,SIUL2 GPIO Pad Data Output" bitfld.byte 0x4C 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x4D "GPDO223,SIUL2 GPIO Pad Data Output" bitfld.byte 0x4D 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x4E "GPDO222,SIUL2 GPIO Pad Data Output" bitfld.byte 0x4E 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x4F "GPDO221,SIUL2 GPIO Pad Data Output" bitfld.byte 0x4F 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x50 "GPDO220,SIUL2 GPIO Pad Data Output" bitfld.byte 0x50 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x51 "GPDO227,SIUL2 GPIO Pad Data Output" bitfld.byte 0x51 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x52 "GPDO226,SIUL2 GPIO Pad Data Output" bitfld.byte 0x52 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x53 "GPDO225,SIUL2 GPIO Pad Data Output" bitfld.byte 0x53 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x54 "GPDO224,SIUL2 GPIO Pad Data Output" bitfld.byte 0x54 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x55 "GPDO231,SIUL2 GPIO Pad Data Output" bitfld.byte 0x55 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x56 "GPDO230,SIUL2 GPIO Pad Data Output" bitfld.byte 0x56 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x57 "GPDO229,SIUL2 GPIO Pad Data Output" bitfld.byte 0x57 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x58 "GPDO228,SIUL2 GPIO Pad Data Output" bitfld.byte 0x58 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x59 "GPDO235,SIUL2 GPIO Pad Data Output" bitfld.byte 0x59 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x5A "GPDO234,SIUL2 GPIO Pad Data Output" bitfld.byte 0x5A 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x5B "GPDO233,SIUL2 GPIO Pad Data Output" bitfld.byte 0x5B 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" line.byte 0x5C "GPDO232,SIUL2 GPIO Pad Data Output" bitfld.byte 0x5C 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" group.byte 0x13EF++0x0 line.byte 0x0 "GPDO236,SIUL2 GPIO Pad Data Output" bitfld.byte 0x0 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High" rgroup.byte 0x1500++0x23 line.byte 0x0 "GPDI3,SIUL2 GPIO Pad Data Input" bitfld.byte 0x0 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1 "GPDI2,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x2 "GPDI1,SIUL2 GPIO Pad Data Input" bitfld.byte 0x2 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x3 "GPDI0,SIUL2 GPIO Pad Data Input" bitfld.byte 0x3 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x4 "GPDI7,SIUL2 GPIO Pad Data Input" bitfld.byte 0x4 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x5 "GPDI6,SIUL2 GPIO Pad Data Input" bitfld.byte 0x5 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x6 "GPDI5,SIUL2 GPIO Pad Data Input" bitfld.byte 0x6 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x7 "GPDI4,SIUL2 GPIO Pad Data Input" bitfld.byte 0x7 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x8 "GPDI11,SIUL2 GPIO Pad Data Input" bitfld.byte 0x8 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x9 "GPDI10,SIUL2 GPIO Pad Data Input" bitfld.byte 0x9 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0xA "GPDI9,SIUL2 GPIO Pad Data Input" bitfld.byte 0xA 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0xB "GPDI8,SIUL2 GPIO Pad Data Input" bitfld.byte 0xB 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0xC "GPDI15,SIUL2 GPIO Pad Data Input" bitfld.byte 0xC 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0xD "GPDI14,SIUL2 GPIO Pad Data Input" bitfld.byte 0xD 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0xE "GPDI13,SIUL2 GPIO Pad Data Input" bitfld.byte 0xE 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0xF "GPDI12,SIUL2 GPIO Pad Data Input" bitfld.byte 0xF 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x10 "GPDI19,SIUL2 GPIO Pad Data Input" bitfld.byte 0x10 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x11 "GPDI18,SIUL2 GPIO Pad Data Input" bitfld.byte 0x11 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x12 "GPDI17,SIUL2 GPIO Pad Data Input" bitfld.byte 0x12 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x13 "GPDI16,SIUL2 GPIO Pad Data Input" bitfld.byte 0x13 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x14 "GPDI23,SIUL2 GPIO Pad Data Input" bitfld.byte 0x14 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x15 "GPDI22,SIUL2 GPIO Pad Data Input" bitfld.byte 0x15 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x16 "GPDI21,SIUL2 GPIO Pad Data Input" bitfld.byte 0x16 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x17 "GPDI20,SIUL2 GPIO Pad Data Input" bitfld.byte 0x17 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x18 "GPDI27,SIUL2 GPIO Pad Data Input" bitfld.byte 0x18 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x19 "GPDI26,SIUL2 GPIO Pad Data Input" bitfld.byte 0x19 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1A "GPDI25,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1A 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1B "GPDI24,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1B 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1C "GPDI31,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1C 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1D "GPDI30,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1D 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1E "GPDI29,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1E 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1F "GPDI28,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1F 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x20 "GPDI35,SIUL2 GPIO Pad Data Input" bitfld.byte 0x20 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x21 "GPDI34,SIUL2 GPIO Pad Data Input" bitfld.byte 0x21 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x22 "GPDI33,SIUL2 GPIO Pad Data Input" bitfld.byte 0x22 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x23 "GPDI32,SIUL2 GPIO Pad Data Input" bitfld.byte 0x23 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" rgroup.byte 0x1526++0x67 line.byte 0x0 "GPDI37,SIUL2 GPIO Pad Data Input" bitfld.byte 0x0 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1 "GPDI36,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x2 "GPDI43,SIUL2 GPIO Pad Data Input" bitfld.byte 0x2 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x3 "GPDI42,SIUL2 GPIO Pad Data Input" bitfld.byte 0x3 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x4 "GPDI41,SIUL2 GPIO Pad Data Input" bitfld.byte 0x4 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x5 "GPDI40,SIUL2 GPIO Pad Data Input" bitfld.byte 0x5 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x6 "GPDI47,SIUL2 GPIO Pad Data Input" bitfld.byte 0x6 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x7 "GPDI46,SIUL2 GPIO Pad Data Input" bitfld.byte 0x7 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x8 "GPDI45,SIUL2 GPIO Pad Data Input" bitfld.byte 0x8 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x9 "GPDI44,SIUL2 GPIO Pad Data Input" bitfld.byte 0x9 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0xA "GPDI51,SIUL2 GPIO Pad Data Input" bitfld.byte 0xA 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0xB "GPDI50,SIUL2 GPIO Pad Data Input" bitfld.byte 0xB 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0xC "GPDI49,SIUL2 GPIO Pad Data Input" bitfld.byte 0xC 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0xD "GPDI48,SIUL2 GPIO Pad Data Input" bitfld.byte 0xD 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0xE "GPDI55,SIUL2 GPIO Pad Data Input" bitfld.byte 0xE 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0xF "GPDI54,SIUL2 GPIO Pad Data Input" bitfld.byte 0xF 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x10 "GPDI53,SIUL2 GPIO Pad Data Input" bitfld.byte 0x10 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x11 "GPDI52,SIUL2 GPIO Pad Data Input" bitfld.byte 0x11 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x12 "GPDI59,SIUL2 GPIO Pad Data Input" bitfld.byte 0x12 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x13 "GPDI58,SIUL2 GPIO Pad Data Input" bitfld.byte 0x13 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x14 "GPDI57,SIUL2 GPIO Pad Data Input" bitfld.byte 0x14 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x15 "GPDI56,SIUL2 GPIO Pad Data Input" bitfld.byte 0x15 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x16 "GPDI63,SIUL2 GPIO Pad Data Input" bitfld.byte 0x16 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x17 "GPDI62,SIUL2 GPIO Pad Data Input" bitfld.byte 0x17 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x18 "GPDI61,SIUL2 GPIO Pad Data Input" bitfld.byte 0x18 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x19 "GPDI60,SIUL2 GPIO Pad Data Input" bitfld.byte 0x19 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1A "GPDI67,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1A 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1B "GPDI66,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1B 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1C "GPDI65,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1C 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1D "GPDI64,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1D 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1E "GPDI71,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1E 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1F "GPDI70,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1F 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x20 "GPDI69,SIUL2 GPIO Pad Data Input" bitfld.byte 0x20 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x21 "GPDI68,SIUL2 GPIO Pad Data Input" bitfld.byte 0x21 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x22 "GPDI75,SIUL2 GPIO Pad Data Input" bitfld.byte 0x22 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x23 "GPDI74,SIUL2 GPIO Pad Data Input" bitfld.byte 0x23 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x24 "GPDI73,SIUL2 GPIO Pad Data Input" bitfld.byte 0x24 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x25 "GPDI72,SIUL2 GPIO Pad Data Input" bitfld.byte 0x25 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x26 "GPDI79,SIUL2 GPIO Pad Data Input" bitfld.byte 0x26 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x27 "GPDI78,SIUL2 GPIO Pad Data Input" bitfld.byte 0x27 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x28 "GPDI77,SIUL2 GPIO Pad Data Input" bitfld.byte 0x28 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x29 "GPDI76,SIUL2 GPIO Pad Data Input" bitfld.byte 0x29 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x2A "GPDI83,SIUL2 GPIO Pad Data Input" bitfld.byte 0x2A 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x2B "GPDI82,SIUL2 GPIO Pad Data Input" bitfld.byte 0x2B 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x2C "GPDI81,SIUL2 GPIO Pad Data Input" bitfld.byte 0x2C 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x2D "GPDI80,SIUL2 GPIO Pad Data Input" bitfld.byte 0x2D 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x2E "GPDI87,SIUL2 GPIO Pad Data Input" bitfld.byte 0x2E 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x2F "GPDI86,SIUL2 GPIO Pad Data Input" bitfld.byte 0x2F 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x30 "GPDI85,SIUL2 GPIO Pad Data Input" bitfld.byte 0x30 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x31 "GPDI84,SIUL2 GPIO Pad Data Input" bitfld.byte 0x31 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x32 "GPDI91,SIUL2 GPIO Pad Data Input" bitfld.byte 0x32 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x33 "GPDI90,SIUL2 GPIO Pad Data Input" bitfld.byte 0x33 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x34 "GPDI89,SIUL2 GPIO Pad Data Input" bitfld.byte 0x34 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x35 "GPDI88,SIUL2 GPIO Pad Data Input" bitfld.byte 0x35 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x36 "GPDI95,SIUL2 GPIO Pad Data Input" bitfld.byte 0x36 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x37 "GPDI94,SIUL2 GPIO Pad Data Input" bitfld.byte 0x37 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x38 "GPDI93,SIUL2 GPIO Pad Data Input" bitfld.byte 0x38 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x39 "GPDI92,SIUL2 GPIO Pad Data Input" bitfld.byte 0x39 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x3A "GPDI99,SIUL2 GPIO Pad Data Input" bitfld.byte 0x3A 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x3B "GPDI98,SIUL2 GPIO Pad Data Input" bitfld.byte 0x3B 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x3C "GPDI97,SIUL2 GPIO Pad Data Input" bitfld.byte 0x3C 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x3D "GPDI96,SIUL2 GPIO Pad Data Input" bitfld.byte 0x3D 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x3E "GPDI103,SIUL2 GPIO Pad Data Input" bitfld.byte 0x3E 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x3F "GPDI102,SIUL2 GPIO Pad Data Input" bitfld.byte 0x3F 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x40 "GPDI101,SIUL2 GPIO Pad Data Input" bitfld.byte 0x40 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x41 "GPDI100,SIUL2 GPIO Pad Data Input" bitfld.byte 0x41 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x42 "GPDI107,SIUL2 GPIO Pad Data Input" bitfld.byte 0x42 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x43 "GPDI106,SIUL2 GPIO Pad Data Input" bitfld.byte 0x43 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x44 "GPDI105,SIUL2 GPIO Pad Data Input" bitfld.byte 0x44 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x45 "GPDI104,SIUL2 GPIO Pad Data Input" bitfld.byte 0x45 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x46 "GPDI111,SIUL2 GPIO Pad Data Input" bitfld.byte 0x46 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x47 "GPDI110,SIUL2 GPIO Pad Data Input" bitfld.byte 0x47 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x48 "GPDI109,SIUL2 GPIO Pad Data Input" bitfld.byte 0x48 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x49 "GPDI108,SIUL2 GPIO Pad Data Input" bitfld.byte 0x49 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x4A "GPDI115,SIUL2 GPIO Pad Data Input" bitfld.byte 0x4A 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x4B "GPDI114,SIUL2 GPIO Pad Data Input" bitfld.byte 0x4B 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x4C "GPDI113,SIUL2 GPIO Pad Data Input" bitfld.byte 0x4C 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x4D "GPDI112,SIUL2 GPIO Pad Data Input" bitfld.byte 0x4D 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x4E "GPDI119,SIUL2 GPIO Pad Data Input" bitfld.byte 0x4E 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x4F "GPDI118,SIUL2 GPIO Pad Data Input" bitfld.byte 0x4F 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x50 "GPDI117,SIUL2 GPIO Pad Data Input" bitfld.byte 0x50 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x51 "GPDI116,SIUL2 GPIO Pad Data Input" bitfld.byte 0x51 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x52 "GPDI123,SIUL2 GPIO Pad Data Input" bitfld.byte 0x52 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x53 "GPDI122,SIUL2 GPIO Pad Data Input" bitfld.byte 0x53 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x54 "GPDI121,SIUL2 GPIO Pad Data Input" bitfld.byte 0x54 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x55 "GPDI120,SIUL2 GPIO Pad Data Input" bitfld.byte 0x55 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x56 "GPDI127,SIUL2 GPIO Pad Data Input" bitfld.byte 0x56 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x57 "GPDI126,SIUL2 GPIO Pad Data Input" bitfld.byte 0x57 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x58 "GPDI125,SIUL2 GPIO Pad Data Input" bitfld.byte 0x58 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x59 "GPDI124,SIUL2 GPIO Pad Data Input" bitfld.byte 0x59 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x5A "GPDI131,SIUL2 GPIO Pad Data Input" bitfld.byte 0x5A 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x5B "GPDI130,SIUL2 GPIO Pad Data Input" bitfld.byte 0x5B 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x5C "GPDI129,SIUL2 GPIO Pad Data Input" bitfld.byte 0x5C 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x5D "GPDI128,SIUL2 GPIO Pad Data Input" bitfld.byte 0x5D 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x5E "GPDI135,SIUL2 GPIO Pad Data Input" bitfld.byte 0x5E 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x5F "GPDI134,SIUL2 GPIO Pad Data Input" bitfld.byte 0x5F 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x60 "GPDI133,SIUL2 GPIO Pad Data Input" bitfld.byte 0x60 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x61 "GPDI132,SIUL2 GPIO Pad Data Input" bitfld.byte 0x61 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x62 "GPDI139,SIUL2 GPIO Pad Data Input" bitfld.byte 0x62 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x63 "GPDI138,SIUL2 GPIO Pad Data Input" bitfld.byte 0x63 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x64 "GPDI137,SIUL2 GPIO Pad Data Input" bitfld.byte 0x64 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x65 "GPDI136,SIUL2 GPIO Pad Data Input" bitfld.byte 0x65 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x66 "GPDI143,SIUL2 GPIO Pad Data Input" bitfld.byte 0x66 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x67 "GPDI142,SIUL2 GPIO Pad Data Input" bitfld.byte 0x67 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" rgroup.byte 0x158F++0x5C line.byte 0x0 "GPDI140,SIUL2 GPIO Pad Data Input" bitfld.byte 0x0 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1 "GPDI147,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x2 "GPDI146,SIUL2 GPIO Pad Data Input" bitfld.byte 0x2 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x3 "GPDI145,SIUL2 GPIO Pad Data Input" bitfld.byte 0x3 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x4 "GPDI144,SIUL2 GPIO Pad Data Input" bitfld.byte 0x4 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x5 "GPDI151,SIUL2 GPIO Pad Data Input" bitfld.byte 0x5 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x6 "GPDI150,SIUL2 GPIO Pad Data Input" bitfld.byte 0x6 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x7 "GPDI149,SIUL2 GPIO Pad Data Input" bitfld.byte 0x7 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x8 "GPDI148,SIUL2 GPIO Pad Data Input" bitfld.byte 0x8 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x9 "GPDI155,SIUL2 GPIO Pad Data Input" bitfld.byte 0x9 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0xA "GPDI154,SIUL2 GPIO Pad Data Input" bitfld.byte 0xA 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0xB "GPDI153,SIUL2 GPIO Pad Data Input" bitfld.byte 0xB 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0xC "GPDI152,SIUL2 GPIO Pad Data Input" bitfld.byte 0xC 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0xD "GPDI159,SIUL2 GPIO Pad Data Input" bitfld.byte 0xD 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0xE "GPDI158,SIUL2 GPIO Pad Data Input" bitfld.byte 0xE 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0xF "GPDI157,SIUL2 GPIO Pad Data Input" bitfld.byte 0xF 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x10 "GPDI156,SIUL2 GPIO Pad Data Input" bitfld.byte 0x10 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x11 "GPDI163,SIUL2 GPIO Pad Data Input" bitfld.byte 0x11 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x12 "GPDI162,SIUL2 GPIO Pad Data Input" bitfld.byte 0x12 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x13 "GPDI161,SIUL2 GPIO Pad Data Input" bitfld.byte 0x13 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x14 "GPDI160,SIUL2 GPIO Pad Data Input" bitfld.byte 0x14 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x15 "GPDI167,SIUL2 GPIO Pad Data Input" bitfld.byte 0x15 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x16 "GPDI166,SIUL2 GPIO Pad Data Input" bitfld.byte 0x16 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x17 "GPDI165,SIUL2 GPIO Pad Data Input" bitfld.byte 0x17 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x18 "GPDI164,SIUL2 GPIO Pad Data Input" bitfld.byte 0x18 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x19 "GPDI171,SIUL2 GPIO Pad Data Input" bitfld.byte 0x19 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1A "GPDI170,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1A 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1B "GPDI169,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1B 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1C "GPDI168,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1C 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1D "GPDI175,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1D 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1E "GPDI174,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1E 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x1F "GPDI173,SIUL2 GPIO Pad Data Input" bitfld.byte 0x1F 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x20 "GPDI172,SIUL2 GPIO Pad Data Input" bitfld.byte 0x20 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x21 "GPDI179,SIUL2 GPIO Pad Data Input" bitfld.byte 0x21 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x22 "GPDI178,SIUL2 GPIO Pad Data Input" bitfld.byte 0x22 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x23 "GPDI177,SIUL2 GPIO Pad Data Input" bitfld.byte 0x23 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x24 "GPDI176,SIUL2 GPIO Pad Data Input" bitfld.byte 0x24 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x25 "GPDI183,SIUL2 GPIO Pad Data Input" bitfld.byte 0x25 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x26 "GPDI182,SIUL2 GPIO Pad Data Input" bitfld.byte 0x26 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x27 "GPDI181,SIUL2 GPIO Pad Data Input" bitfld.byte 0x27 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x28 "GPDI180,SIUL2 GPIO Pad Data Input" bitfld.byte 0x28 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x29 "GPDI187,SIUL2 GPIO Pad Data Input" bitfld.byte 0x29 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x2A "GPDI186,SIUL2 GPIO Pad Data Input" bitfld.byte 0x2A 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x2B "GPDI185,SIUL2 GPIO Pad Data Input" bitfld.byte 0x2B 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x2C "GPDI184,SIUL2 GPIO Pad Data Input" bitfld.byte 0x2C 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x2D "GPDI191,SIUL2 GPIO Pad Data Input" bitfld.byte 0x2D 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x2E "GPDI190,SIUL2 GPIO Pad Data Input" bitfld.byte 0x2E 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x2F "GPDI189,SIUL2 GPIO Pad Data Input" bitfld.byte 0x2F 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x30 "GPDI188,SIUL2 GPIO Pad Data Input" bitfld.byte 0x30 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x31 "GPDI195,SIUL2 GPIO Pad Data Input" bitfld.byte 0x31 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x32 "GPDI194,SIUL2 GPIO Pad Data Input" bitfld.byte 0x32 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x33 "GPDI193,SIUL2 GPIO Pad Data Input" bitfld.byte 0x33 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x34 "GPDI192,SIUL2 GPIO Pad Data Input" bitfld.byte 0x34 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x35 "GPDI199,SIUL2 GPIO Pad Data Input" bitfld.byte 0x35 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x36 "GPDI198,SIUL2 GPIO Pad Data Input" bitfld.byte 0x36 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x37 "GPDI197,SIUL2 GPIO Pad Data Input" bitfld.byte 0x37 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x38 "GPDI196,SIUL2 GPIO Pad Data Input" bitfld.byte 0x38 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x39 "GPDI203,SIUL2 GPIO Pad Data Input" bitfld.byte 0x39 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x3A "GPDI202,SIUL2 GPIO Pad Data Input" bitfld.byte 0x3A 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x3B "GPDI201,SIUL2 GPIO Pad Data Input" bitfld.byte 0x3B 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x3C "GPDI200,SIUL2 GPIO Pad Data Input" bitfld.byte 0x3C 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x3D "GPDI207,SIUL2 GPIO Pad Data Input" bitfld.byte 0x3D 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x3E "GPDI206,SIUL2 GPIO Pad Data Input" bitfld.byte 0x3E 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x3F "GPDI205,SIUL2 GPIO Pad Data Input" bitfld.byte 0x3F 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x40 "GPDI204,SIUL2 GPIO Pad Data Input" bitfld.byte 0x40 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x41 "GPDI211,SIUL2 GPIO Pad Data Input" bitfld.byte 0x41 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x42 "GPDI210,SIUL2 GPIO Pad Data Input" bitfld.byte 0x42 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x43 "GPDI209,SIUL2 GPIO Pad Data Input" bitfld.byte 0x43 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x44 "GPDI208,SIUL2 GPIO Pad Data Input" bitfld.byte 0x44 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x45 "GPDI215,SIUL2 GPIO Pad Data Input" bitfld.byte 0x45 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x46 "GPDI214,SIUL2 GPIO Pad Data Input" bitfld.byte 0x46 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x47 "GPDI213,SIUL2 GPIO Pad Data Input" bitfld.byte 0x47 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x48 "GPDI212,SIUL2 GPIO Pad Data Input" bitfld.byte 0x48 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x49 "GPDI219,SIUL2 GPIO Pad Data Input" bitfld.byte 0x49 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x4A "GPDI218,SIUL2 GPIO Pad Data Input" bitfld.byte 0x4A 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x4B "GPDI217,SIUL2 GPIO Pad Data Input" bitfld.byte 0x4B 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x4C "GPDI216,SIUL2 GPIO Pad Data Input" bitfld.byte 0x4C 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x4D "GPDI223,SIUL2 GPIO Pad Data Input" bitfld.byte 0x4D 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x4E "GPDI222,SIUL2 GPIO Pad Data Input" bitfld.byte 0x4E 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x4F "GPDI221,SIUL2 GPIO Pad Data Input" bitfld.byte 0x4F 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x50 "GPDI220,SIUL2 GPIO Pad Data Input" bitfld.byte 0x50 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x51 "GPDI227,SIUL2 GPIO Pad Data Input" bitfld.byte 0x51 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x52 "GPDI226,SIUL2 GPIO Pad Data Input" bitfld.byte 0x52 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x53 "GPDI225,SIUL2 GPIO Pad Data Input" bitfld.byte 0x53 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x54 "GPDI224,SIUL2 GPIO Pad Data Input" bitfld.byte 0x54 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x55 "GPDI231,SIUL2 GPIO Pad Data Input" bitfld.byte 0x55 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x56 "GPDI230,SIUL2 GPIO Pad Data Input" bitfld.byte 0x56 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x57 "GPDI229,SIUL2 GPIO Pad Data Input" bitfld.byte 0x57 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x58 "GPDI228,SIUL2 GPIO Pad Data Input" bitfld.byte 0x58 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x59 "GPDI235,SIUL2 GPIO Pad Data Input" bitfld.byte 0x59 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x5A "GPDI234,SIUL2 GPIO Pad Data Input" bitfld.byte 0x5A 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x5B "GPDI233,SIUL2 GPIO Pad Data Input" bitfld.byte 0x5B 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" line.byte 0x5C "GPDI232,SIUL2 GPIO Pad Data Input" bitfld.byte 0x5C 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" rgroup.byte 0x15EF++0x0 line.byte 0x0 "GPDI236,SIUL2 GPIO Pad Data Input" bitfld.byte 0x0 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High" group.word 0x1700++0x1B line.word 0x0 "PGPDO1,SIUL2 Parallel GPIO Pad Data Out" bitfld.word 0x0 15. "PPDO15,Parallel Pad Data Out 15" "0: Logic low,1: Logic high" newline bitfld.word 0x0 14. "PPDO14,Parallel Pad Data Out 14" "0: Logic low,1: Logic high" newline bitfld.word 0x0 13. "PPDO13,Parallel Pad Data Out 13" "0: Logic low,1: Logic high" newline bitfld.word 0x0 12. "PPDO12,Parallel Pad Data Out 12" "0: Logic low,1: Logic high" newline bitfld.word 0x0 11. "PPDO11,Parallel Pad Data Out 11" "0: Logic low,1: Logic high" newline bitfld.word 0x0 10. "PPDO10,Parallel Pad Data Out 10" "0: Logic low,1: Logic high" newline bitfld.word 0x0 9. "PPDO9,Parallel Pad Data Out 9" "0: Logic low,1: Logic high" newline bitfld.word 0x0 8. "PPDO8,Parallel Pad Data Out 8" "0: Logic low,1: Logic high" newline bitfld.word 0x0 7. "PPDO7,Parallel Pad Data Out 7" "0: Logic low,1: Logic high" newline bitfld.word 0x0 6. "PPDO6,Parallel Pad Data Out 6" "0: Logic low,1: Logic high" newline bitfld.word 0x0 5. "PPDO5,Parallel Pad Data Out 5" "0: Logic low,1: Logic high" newline bitfld.word 0x0 4. "PPDO4,Parallel Pad Data Out 4" "0: Logic low,1: Logic high" newline bitfld.word 0x0 3. "PPDO3,Parallel Pad Data Out 3" "0: Logic low,1: Logic high" newline bitfld.word 0x0 2. "PPDO2,Parallel Pad Data Out 2" "0: Logic low,1: Logic high" newline bitfld.word 0x0 1. "PPDO1,Parallel Pad Data Out 1" "0: Logic low,1: Logic high" newline bitfld.word 0x0 0. "PPDO0,Parallel Pad Data Out 0" "0: Logic low,1: Logic high" line.word 0x2 "PGPDO0,SIUL2 Parallel GPIO Pad Data Out" bitfld.word 0x2 15. "PPDO15,Parallel Pad Data Out 15" "0: Logic low,1: Logic high" newline bitfld.word 0x2 14. "PPDO14,Parallel Pad Data Out 14" "0: Logic low,1: Logic high" newline bitfld.word 0x2 13. "PPDO13,Parallel Pad Data Out 13" "0: Logic low,1: Logic high" newline bitfld.word 0x2 12. "PPDO12,Parallel Pad Data Out 12" "0: Logic low,1: Logic high" newline bitfld.word 0x2 11. "PPDO11,Parallel Pad Data Out 11" "0: Logic low,1: Logic high" newline bitfld.word 0x2 10. "PPDO10,Parallel Pad Data Out 10" "0: Logic low,1: Logic high" newline bitfld.word 0x2 9. "PPDO9,Parallel Pad Data Out 9" "0: Logic low,1: Logic high" newline bitfld.word 0x2 8. "PPDO8,Parallel Pad Data Out 8" "0: Logic low,1: Logic high" newline bitfld.word 0x2 7. "PPDO7,Parallel Pad Data Out 7" "0: Logic low,1: Logic high" newline bitfld.word 0x2 6. "PPDO6,Parallel Pad Data Out 6" "0: Logic low,1: Logic high" newline bitfld.word 0x2 5. "PPDO5,Parallel Pad Data Out 5" "0: Logic low,1: Logic high" newline bitfld.word 0x2 4. "PPDO4,Parallel Pad Data Out 4" "0: Logic low,1: Logic high" newline bitfld.word 0x2 3. "PPDO3,Parallel Pad Data Out 3" "0: Logic low,1: Logic high" newline bitfld.word 0x2 2. "PPDO2,Parallel Pad Data Out 2" "0: Logic low,1: Logic high" newline bitfld.word 0x2 1. "PPDO1,Parallel Pad Data Out 1" "0: Logic low,1: Logic high" newline bitfld.word 0x2 0. "PPDO0,Parallel Pad Data Out 0" "0: Logic low,1: Logic high" line.word 0x4 "PGPDO3,SIUL2 Parallel GPIO Pad Data Out" bitfld.word 0x4 15. "PPDO15,Parallel Pad Data Out 15" "0: Logic low,1: Logic high" newline bitfld.word 0x4 14. "PPDO14,Parallel Pad Data Out 14" "0: Logic low,1: Logic high" newline bitfld.word 0x4 13. "PPDO13,Parallel Pad Data Out 13" "0: Logic low,1: Logic high" newline bitfld.word 0x4 12. "PPDO12,Parallel Pad Data Out 12" "0: Logic low,1: Logic high" newline bitfld.word 0x4 11. "PPDO11,Parallel Pad Data Out 11" "0: Logic low,1: Logic high" newline bitfld.word 0x4 10. "PPDO10,Parallel Pad Data Out 10" "0: Logic low,1: Logic high" newline bitfld.word 0x4 9. "PPDO9,Parallel Pad Data Out 9" "0: Logic low,1: Logic high" newline bitfld.word 0x4 8. "PPDO8,Parallel Pad Data Out 8" "0: Logic low,1: Logic high" newline bitfld.word 0x4 7. "PPDO7,Parallel Pad Data Out 7" "0: Logic low,1: Logic high" newline bitfld.word 0x4 6. "PPDO6,Parallel Pad Data Out 6" "0: Logic low,1: Logic high" newline bitfld.word 0x4 5. "PPDO5,Parallel Pad Data Out 5" "0: Logic low,1: Logic high" newline bitfld.word 0x4 4. "PPDO4,Parallel Pad Data Out 4" "0: Logic low,1: Logic high" newline bitfld.word 0x4 3. "PPDO3,Parallel Pad Data Out 3" "0: Logic low,1: Logic high" newline bitfld.word 0x4 2. "PPDO2,Parallel Pad Data Out 2" "0: Logic low,1: Logic high" newline bitfld.word 0x4 1. "PPDO1,Parallel Pad Data Out 1" "0: Logic low,1: Logic high" newline bitfld.word 0x4 0. "PPDO0,Parallel Pad Data Out 0" "0: Logic low,1: Logic high" line.word 0x6 "PGPDO2,SIUL2 Parallel GPIO Pad Data Out" bitfld.word 0x6 15. "PPDO15,Parallel Pad Data Out 15" "0: Logic low,1: Logic high" newline bitfld.word 0x6 14. "PPDO14,Parallel Pad Data Out 14" "0: Logic low,1: Logic high" newline bitfld.word 0x6 13. "PPDO13,Parallel Pad Data Out 13" "0: Logic low,1: Logic high" newline bitfld.word 0x6 12. "PPDO12,Parallel Pad Data Out 12" "0: Logic low,1: Logic high" newline bitfld.word 0x6 11. "PPDO11,Parallel Pad Data Out 11" "0: Logic low,1: Logic high" newline bitfld.word 0x6 10. "PPDO10,Parallel Pad Data Out 10" "0: Logic low,1: Logic high" newline bitfld.word 0x6 7. "PPDO7,Parallel Pad Data Out 7" "0: Logic low,1: Logic high" newline bitfld.word 0x6 6. "PPDO6,Parallel Pad Data Out 6" "0: Logic low,1: Logic high" newline bitfld.word 0x6 5. "PPDO5,Parallel Pad Data Out 5" "0: Logic low,1: Logic high" newline bitfld.word 0x6 4. "PPDO4,Parallel Pad Data Out 4" "0: Logic low,1: Logic high" newline bitfld.word 0x6 3. "PPDO3,Parallel Pad Data Out 3" "0: Logic low,1: Logic high" newline bitfld.word 0x6 2. "PPDO2,Parallel Pad Data Out 2" "0: Logic low,1: Logic high" newline bitfld.word 0x6 1. "PPDO1,Parallel Pad Data Out 1" "0: Logic low,1: Logic high" newline bitfld.word 0x6 0. "PPDO0,Parallel Pad Data Out 0" "0: Logic low,1: Logic high" line.word 0x8 "PGPDO5,SIUL2 Parallel GPIO Pad Data Out" bitfld.word 0x8 15. "PPDO15,Parallel Pad Data Out 15" "0: Logic low,1: Logic high" newline bitfld.word 0x8 14. "PPDO14,Parallel Pad Data Out 14" "0: Logic low,1: Logic high" newline bitfld.word 0x8 13. "PPDO13,Parallel Pad Data Out 13" "0: Logic low,1: Logic high" newline bitfld.word 0x8 12. "PPDO12,Parallel Pad Data Out 12" "0: Logic low,1: Logic high" newline bitfld.word 0x8 11. "PPDO11,Parallel Pad Data Out 11" "0: Logic low,1: Logic high" newline bitfld.word 0x8 10. "PPDO10,Parallel Pad Data Out 10" "0: Logic low,1: Logic high" newline bitfld.word 0x8 9. "PPDO9,Parallel Pad Data Out 9" "0: Logic low,1: Logic high" newline bitfld.word 0x8 8. "PPDO8,Parallel Pad Data Out 8" "0: Logic low,1: Logic high" newline bitfld.word 0x8 7. "PPDO7,Parallel Pad Data Out 7" "0: Logic low,1: Logic high" newline bitfld.word 0x8 6. "PPDO6,Parallel Pad Data Out 6" "0: Logic low,1: Logic high" newline bitfld.word 0x8 5. "PPDO5,Parallel Pad Data Out 5" "0: Logic low,1: Logic high" newline bitfld.word 0x8 4. "PPDO4,Parallel Pad Data Out 4" "0: Logic low,1: Logic high" newline bitfld.word 0x8 3. "PPDO3,Parallel Pad Data Out 3" "0: Logic low,1: Logic high" newline bitfld.word 0x8 2. "PPDO2,Parallel Pad Data Out 2" "0: Logic low,1: Logic high" newline bitfld.word 0x8 1. "PPDO1,Parallel Pad Data Out 1" "0: Logic low,1: Logic high" newline bitfld.word 0x8 0. "PPDO0,Parallel Pad Data Out 0" "0: Logic low,1: Logic high" line.word 0xA "PGPDO4,SIUL2 Parallel GPIO Pad Data Out" bitfld.word 0xA 15. "PPDO15,Parallel Pad Data Out 15" "0: Logic low,1: Logic high" newline bitfld.word 0xA 14. "PPDO14,Parallel Pad Data Out 14" "0: Logic low,1: Logic high" newline bitfld.word 0xA 13. "PPDO13,Parallel Pad Data Out 13" "0: Logic low,1: Logic high" newline bitfld.word 0xA 12. "PPDO12,Parallel Pad Data Out 12" "0: Logic low,1: Logic high" newline bitfld.word 0xA 11. "PPDO11,Parallel Pad Data Out 11" "0: Logic low,1: Logic high" newline bitfld.word 0xA 10. "PPDO10,Parallel Pad Data Out 10" "0: Logic low,1: Logic high" newline bitfld.word 0xA 9. "PPDO9,Parallel Pad Data Out 9" "0: Logic low,1: Logic high" newline bitfld.word 0xA 8. "PPDO8,Parallel Pad Data Out 8" "0: Logic low,1: Logic high" newline bitfld.word 0xA 7. "PPDO7,Parallel Pad Data Out 7" "0: Logic low,1: Logic high" newline bitfld.word 0xA 6. "PPDO6,Parallel Pad Data Out 6" "0: Logic low,1: Logic high" newline bitfld.word 0xA 5. "PPDO5,Parallel Pad Data Out 5" "0: Logic low,1: Logic high" newline bitfld.word 0xA 4. "PPDO4,Parallel Pad Data Out 4" "0: Logic low,1: Logic high" newline bitfld.word 0xA 3. "PPDO3,Parallel Pad Data Out 3" "0: Logic low,1: Logic high" newline bitfld.word 0xA 2. "PPDO2,Parallel Pad Data Out 2" "0: Logic low,1: Logic high" newline bitfld.word 0xA 1. "PPDO1,Parallel Pad Data Out 1" "0: Logic low,1: Logic high" newline bitfld.word 0xA 0. "PPDO0,Parallel Pad Data Out 0" "0: Logic low,1: Logic high" line.word 0xC "PGPDO7,SIUL2 Parallel GPIO Pad Data Out" bitfld.word 0xC 15. "PPDO15,Parallel Pad Data Out 15" "0: Logic low,1: Logic high" newline bitfld.word 0xC 14. "PPDO14,Parallel Pad Data Out 14" "0: Logic low,1: Logic high" newline bitfld.word 0xC 13. "PPDO13,Parallel Pad Data Out 13" "0: Logic low,1: Logic high" newline bitfld.word 0xC 12. "PPDO12,Parallel Pad Data Out 12" "0: Logic low,1: Logic high" newline bitfld.word 0xC 11. "PPDO11,Parallel Pad Data Out 11" "0: Logic low,1: Logic high" newline bitfld.word 0xC 10. "PPDO10,Parallel Pad Data Out 10" "0: Logic low,1: Logic high" newline bitfld.word 0xC 9. "PPDO9,Parallel Pad Data Out 9" "0: Logic low,1: Logic high" newline bitfld.word 0xC 8. "PPDO8,Parallel Pad Data Out 8" "0: Logic low,1: Logic high" newline bitfld.word 0xC 7. "PPDO7,Parallel Pad Data Out 7" "0: Logic low,1: Logic high" newline bitfld.word 0xC 6. "PPDO6,Parallel Pad Data Out 6" "0: Logic low,1: Logic high" newline bitfld.word 0xC 5. "PPDO5,Parallel Pad Data Out 5" "0: Logic low,1: Logic high" newline bitfld.word 0xC 4. "PPDO4,Parallel Pad Data Out 4" "0: Logic low,1: Logic high" newline bitfld.word 0xC 3. "PPDO3,Parallel Pad Data Out 3" "0: Logic low,1: Logic high" newline bitfld.word 0xC 2. "PPDO2,Parallel Pad Data Out 2" "0: Logic low,1: Logic high" newline bitfld.word 0xC 1. "PPDO1,Parallel Pad Data Out 1" "0: Logic low,1: Logic high" newline bitfld.word 0xC 0. "PPDO0,Parallel Pad Data Out 0" "0: Logic low,1: Logic high" line.word 0xE "PGPDO6,SIUL2 Parallel GPIO Pad Data Out" bitfld.word 0xE 15. "PPDO15,Parallel Pad Data Out 15" "0: Logic low,1: Logic high" newline bitfld.word 0xE 14. "PPDO14,Parallel Pad Data Out 14" "0: Logic low,1: Logic high" newline bitfld.word 0xE 13. "PPDO13,Parallel Pad Data Out 13" "0: Logic low,1: Logic high" newline bitfld.word 0xE 12. "PPDO12,Parallel Pad Data Out 12" "0: Logic low,1: Logic high" newline bitfld.word 0xE 11. "PPDO11,Parallel Pad Data Out 11" "0: Logic low,1: Logic high" newline bitfld.word 0xE 10. "PPDO10,Parallel Pad Data Out 10" "0: Logic low,1: Logic high" newline bitfld.word 0xE 9. "PPDO9,Parallel Pad Data Out 9" "0: Logic low,1: Logic high" newline bitfld.word 0xE 8. "PPDO8,Parallel Pad Data Out 8" "0: Logic low,1: Logic high" newline bitfld.word 0xE 7. "PPDO7,Parallel Pad Data Out 7" "0: Logic low,1: Logic high" newline bitfld.word 0xE 6. "PPDO6,Parallel Pad Data Out 6" "0: Logic low,1: Logic high" newline bitfld.word 0xE 5. "PPDO5,Parallel Pad Data Out 5" "0: Logic low,1: Logic high" newline bitfld.word 0xE 4. "PPDO4,Parallel Pad Data Out 4" "0: Logic low,1: Logic high" newline bitfld.word 0xE 3. "PPDO3,Parallel Pad Data Out 3" "0: Logic low,1: Logic high" newline bitfld.word 0xE 2. "PPDO2,Parallel Pad Data Out 2" "0: Logic low,1: Logic high" newline bitfld.word 0xE 1. "PPDO1,Parallel Pad Data Out 1" "0: Logic low,1: Logic high" newline bitfld.word 0xE 0. "PPDO0,Parallel Pad Data Out 0" "0: Logic low,1: Logic high" line.word 0x10 "PGPDO9,SIUL2 Parallel GPIO Pad Data Out" bitfld.word 0x10 15. "PPDO15,Parallel Pad Data Out 15" "0: Logic low,1: Logic high" newline bitfld.word 0x10 14. "PPDO14,Parallel Pad Data Out 14" "0: Logic low,1: Logic high" newline bitfld.word 0x10 13. "PPDO13,Parallel Pad Data Out 13" "0: Logic low,1: Logic high" newline bitfld.word 0x10 12. "PPDO12,Parallel Pad Data Out 12" "0: Logic low,1: Logic high" newline bitfld.word 0x10 11. "PPDO11,Parallel Pad Data Out 11" "0: Logic low,1: Logic high" newline bitfld.word 0x10 10. "PPDO10,Parallel Pad Data Out 10" "0: Logic low,1: Logic high" newline bitfld.word 0x10 9. "PPDO9,Parallel Pad Data Out 9" "0: Logic low,1: Logic high" newline bitfld.word 0x10 8. "PPDO8,Parallel Pad Data Out 8" "0: Logic low,1: Logic high" newline bitfld.word 0x10 7. "PPDO7,Parallel Pad Data Out 7" "0: Logic low,1: Logic high" newline bitfld.word 0x10 6. "PPDO6,Parallel Pad Data Out 6" "0: Logic low,1: Logic high" newline bitfld.word 0x10 5. "PPDO5,Parallel Pad Data Out 5" "0: Logic low,1: Logic high" newline bitfld.word 0x10 4. "PPDO4,Parallel Pad Data Out 4" "0: Logic low,1: Logic high" newline bitfld.word 0x10 3. "PPDO3,Parallel Pad Data Out 3" "0: Logic low,1: Logic high" newline bitfld.word 0x10 2. "PPDO2,Parallel Pad Data Out 2" "0: Logic low,1: Logic high" newline bitfld.word 0x10 1. "PPDO1,Parallel Pad Data Out 1" "0: Logic low,1: Logic high" newline bitfld.word 0x10 0. "PPDO0,Parallel Pad Data Out 0" "0: Logic low,1: Logic high" line.word 0x12 "PGPDO8,SIUL2 Parallel GPIO Pad Data Out" bitfld.word 0x12 15. "PPDO15,Parallel Pad Data Out 15" "0: Logic low,1: Logic high" newline bitfld.word 0x12 14. "PPDO14,Parallel Pad Data Out 14" "0: Logic low,1: Logic high" newline bitfld.word 0x12 13. "PPDO13,Parallel Pad Data Out 13" "0: Logic low,1: Logic high" newline bitfld.word 0x12 12. "PPDO12,Parallel Pad Data Out 12" "0: Logic low,1: Logic high" newline bitfld.word 0x12 11. "PPDO11,Parallel Pad Data Out 11" "0: Logic low,1: Logic high" newline bitfld.word 0x12 10. "PPDO10,Parallel Pad Data Out 10" "0: Logic low,1: Logic high" newline bitfld.word 0x12 9. "PPDO9,Parallel Pad Data Out 9" "0: Logic low,1: Logic high" newline bitfld.word 0x12 8. "PPDO8,Parallel Pad Data Out 8" "0: Logic low,1: Logic high" newline bitfld.word 0x12 7. "PPDO7,Parallel Pad Data Out 7" "0: Logic low,1: Logic high" newline bitfld.word 0x12 6. "PPDO6,Parallel Pad Data Out 6" "0: Logic low,1: Logic high" newline bitfld.word 0x12 5. "PPDO5,Parallel Pad Data Out 5" "0: Logic low,1: Logic high" newline bitfld.word 0x12 4. "PPDO4,Parallel Pad Data Out 4" "0: Logic low,1: Logic high" newline bitfld.word 0x12 3. "PPDO3,Parallel Pad Data Out 3" "0: Logic low,1: Logic high" newline bitfld.word 0x12 1. "PPDO1,Parallel Pad Data Out 1" "0: Logic low,1: Logic high" newline bitfld.word 0x12 0. "PPDO0,Parallel Pad Data Out 0" "0: Logic low,1: Logic high" line.word 0x14 "PGPDO11,SIUL2 Parallel GPIO Pad Data Out" bitfld.word 0x14 15. "PPDO15,Parallel Pad Data Out 15" "0: Logic low,1: Logic high" newline bitfld.word 0x14 14. "PPDO14,Parallel Pad Data Out 14" "0: Logic low,1: Logic high" newline bitfld.word 0x14 13. "PPDO13,Parallel Pad Data Out 13" "0: Logic low,1: Logic high" newline bitfld.word 0x14 12. "PPDO12,Parallel Pad Data Out 12" "0: Logic low,1: Logic high" newline bitfld.word 0x14 11. "PPDO11,Parallel Pad Data Out 11" "0: Logic low,1: Logic high" newline bitfld.word 0x14 10. "PPDO10,Parallel Pad Data Out 10" "0: Logic low,1: Logic high" newline bitfld.word 0x14 9. "PPDO9,Parallel Pad Data Out 9" "0: Logic low,1: Logic high" newline bitfld.word 0x14 8. "PPDO8,Parallel Pad Data Out 8" "0: Logic low,1: Logic high" newline bitfld.word 0x14 7. "PPDO7,Parallel Pad Data Out 7" "0: Logic low,1: Logic high" newline bitfld.word 0x14 6. "PPDO6,Parallel Pad Data Out 6" "0: Logic low,1: Logic high" newline bitfld.word 0x14 5. "PPDO5,Parallel Pad Data Out 5" "0: Logic low,1: Logic high" newline bitfld.word 0x14 4. "PPDO4,Parallel Pad Data Out 4" "0: Logic low,1: Logic high" newline bitfld.word 0x14 3. "PPDO3,Parallel Pad Data Out 3" "0: Logic low,1: Logic high" newline bitfld.word 0x14 2. "PPDO2,Parallel Pad Data Out 2" "0: Logic low,1: Logic high" newline bitfld.word 0x14 1. "PPDO1,Parallel Pad Data Out 1" "0: Logic low,1: Logic high" newline bitfld.word 0x14 0. "PPDO0,Parallel Pad Data Out 0" "0: Logic low,1: Logic high" line.word 0x16 "PGPDO10,SIUL2 Parallel GPIO Pad Data Out" bitfld.word 0x16 15. "PPDO15,Parallel Pad Data Out 15" "0: Logic low,1: Logic high" newline bitfld.word 0x16 14. "PPDO14,Parallel Pad Data Out 14" "0: Logic low,1: Logic high" newline bitfld.word 0x16 13. "PPDO13,Parallel Pad Data Out 13" "0: Logic low,1: Logic high" newline bitfld.word 0x16 12. "PPDO12,Parallel Pad Data Out 12" "0: Logic low,1: Logic high" newline bitfld.word 0x16 11. "PPDO11,Parallel Pad Data Out 11" "0: Logic low,1: Logic high" newline bitfld.word 0x16 10. "PPDO10,Parallel Pad Data Out 10" "0: Logic low,1: Logic high" newline bitfld.word 0x16 9. "PPDO9,Parallel Pad Data Out 9" "0: Logic low,1: Logic high" newline bitfld.word 0x16 8. "PPDO8,Parallel Pad Data Out 8" "0: Logic low,1: Logic high" newline bitfld.word 0x16 7. "PPDO7,Parallel Pad Data Out 7" "0: Logic low,1: Logic high" newline bitfld.word 0x16 6. "PPDO6,Parallel Pad Data Out 6" "0: Logic low,1: Logic high" newline bitfld.word 0x16 5. "PPDO5,Parallel Pad Data Out 5" "0: Logic low,1: Logic high" newline bitfld.word 0x16 4. "PPDO4,Parallel Pad Data Out 4" "0: Logic low,1: Logic high" newline bitfld.word 0x16 3. "PPDO3,Parallel Pad Data Out 3" "0: Logic low,1: Logic high" newline bitfld.word 0x16 2. "PPDO2,Parallel Pad Data Out 2" "0: Logic low,1: Logic high" newline bitfld.word 0x16 1. "PPDO1,Parallel Pad Data Out 1" "0: Logic low,1: Logic high" newline bitfld.word 0x16 0. "PPDO0,Parallel Pad Data Out 0" "0: Logic low,1: Logic high" line.word 0x18 "PGPDO13,SIUL2 Parallel GPIO Pad Data Out" bitfld.word 0x18 15. "PPDO15,Parallel Pad Data Out 15" "0: Logic low,1: Logic high" newline bitfld.word 0x18 14. "PPDO14,Parallel Pad Data Out 14" "0: Logic low,1: Logic high" newline bitfld.word 0x18 13. "PPDO13,Parallel Pad Data Out 13" "0: Logic low,1: Logic high" newline bitfld.word 0x18 12. "PPDO12,Parallel Pad Data Out 12" "0: Logic low,1: Logic high" newline bitfld.word 0x18 11. "PPDO11,Parallel Pad Data Out 11" "0: Logic low,1: Logic high" newline bitfld.word 0x18 10. "PPDO10,Parallel Pad Data Out 10" "0: Logic low,1: Logic high" newline bitfld.word 0x18 9. "PPDO9,Parallel Pad Data Out 9" "0: Logic low,1: Logic high" newline bitfld.word 0x18 8. "PPDO8,Parallel Pad Data Out 8" "0: Logic low,1: Logic high" newline bitfld.word 0x18 7. "PPDO7,Parallel Pad Data Out 7" "0: Logic low,1: Logic high" newline bitfld.word 0x18 6. "PPDO6,Parallel Pad Data Out 6" "0: Logic low,1: Logic high" newline bitfld.word 0x18 5. "PPDO5,Parallel Pad Data Out 5" "0: Logic low,1: Logic high" newline bitfld.word 0x18 4. "PPDO4,Parallel Pad Data Out 4" "0: Logic low,1: Logic high" newline bitfld.word 0x18 3. "PPDO3,Parallel Pad Data Out 3" "0: Logic low,1: Logic high" newline bitfld.word 0x18 2. "PPDO2,Parallel Pad Data Out 2" "0: Logic low,1: Logic high" newline bitfld.word 0x18 1. "PPDO1,Parallel Pad Data Out 1" "0: Logic low,1: Logic high" newline bitfld.word 0x18 0. "PPDO0,Parallel Pad Data Out 0" "0: Logic low,1: Logic high" line.word 0x1A "PGPDO12,SIUL2 Parallel GPIO Pad Data Out" bitfld.word 0x1A 15. "PPDO15,Parallel Pad Data Out 15" "0: Logic low,1: Logic high" newline bitfld.word 0x1A 14. "PPDO14,Parallel Pad Data Out 14" "0: Logic low,1: Logic high" newline bitfld.word 0x1A 13. "PPDO13,Parallel Pad Data Out 13" "0: Logic low,1: Logic high" newline bitfld.word 0x1A 12. "PPDO12,Parallel Pad Data Out 12" "0: Logic low,1: Logic high" newline bitfld.word 0x1A 11. "PPDO11,Parallel Pad Data Out 11" "0: Logic low,1: Logic high" newline bitfld.word 0x1A 10. "PPDO10,Parallel Pad Data Out 10" "0: Logic low,1: Logic high" newline bitfld.word 0x1A 9. "PPDO9,Parallel Pad Data Out 9" "0: Logic low,1: Logic high" newline bitfld.word 0x1A 8. "PPDO8,Parallel Pad Data Out 8" "0: Logic low,1: Logic high" newline bitfld.word 0x1A 7. "PPDO7,Parallel Pad Data Out 7" "0: Logic low,1: Logic high" newline bitfld.word 0x1A 6. "PPDO6,Parallel Pad Data Out 6" "0: Logic low,1: Logic high" newline bitfld.word 0x1A 5. "PPDO5,Parallel Pad Data Out 5" "0: Logic low,1: Logic high" newline bitfld.word 0x1A 4. "PPDO4,Parallel Pad Data Out 4" "0: Logic low,1: Logic high" newline bitfld.word 0x1A 3. "PPDO3,Parallel Pad Data Out 3" "0: Logic low,1: Logic high" newline bitfld.word 0x1A 2. "PPDO2,Parallel Pad Data Out 2" "0: Logic low,1: Logic high" newline bitfld.word 0x1A 1. "PPDO1,Parallel Pad Data Out 1" "0: Logic low,1: Logic high" newline bitfld.word 0x1A 0. "PPDO0,Parallel Pad Data Out 0" "0: Logic low,1: Logic high" group.word 0x171E++0x1 line.word 0x0 "PGPDO14,SIUL2 Parallel GPIO Pad Data Out" bitfld.word 0x0 15. "PPDO15,Parallel Pad Data Out 15" "0: Logic low,1: Logic high" newline bitfld.word 0x0 14. "PPDO14,Parallel Pad Data Out 14" "0: Logic low,1: Logic high" newline bitfld.word 0x0 13. "PPDO13,Parallel Pad Data Out 13" "0: Logic low,1: Logic high" newline bitfld.word 0x0 12. "PPDO12,Parallel Pad Data Out 12" "0: Logic low,1: Logic high" newline bitfld.word 0x0 11. "PPDO11,Parallel Pad Data Out 11" "0: Logic low,1: Logic high" newline bitfld.word 0x0 10. "PPDO10,Parallel Pad Data Out 10" "0: Logic low,1: Logic high" newline bitfld.word 0x0 9. "PPDO9,Parallel Pad Data Out 9" "0: Logic low,1: Logic high" newline bitfld.word 0x0 8. "PPDO8,Parallel Pad Data Out 8" "0: Logic low,1: Logic high" newline bitfld.word 0x0 7. "PPDO7,Parallel Pad Data Out 7" "0: Logic low,1: Logic high" newline bitfld.word 0x0 6. "PPDO6,Parallel Pad Data Out 6" "0: Logic low,1: Logic high" newline bitfld.word 0x0 5. "PPDO5,Parallel Pad Data Out 5" "0: Logic low,1: Logic high" newline bitfld.word 0x0 4. "PPDO4,Parallel Pad Data Out 4" "0: Logic low,1: Logic high" newline bitfld.word 0x0 3. "PPDO3,Parallel Pad Data Out 3" "0: Logic low,1: Logic high" rgroup.word 0x1740++0x1B line.word 0x0 "PGPDI1,SIUL2 Parallel GPIO Pad Data In" bitfld.word 0x0 15. "PPDI15,Parallel Pad Data In 15" "0: Logic low,1: Logic high" newline bitfld.word 0x0 14. "PPDI14,Parallel Pad Data In 14" "0: Logic low,1: Logic high" newline bitfld.word 0x0 13. "PPDI13,Parallel Pad Data In 13" "0: Logic low,1: Logic high" newline bitfld.word 0x0 12. "PPDI12,Parallel Pad Data In 12" "0: Logic low,1: Logic high" newline bitfld.word 0x0 11. "PPDI11,Parallel Pad Data In 11" "0: Logic low,1: Logic high" newline bitfld.word 0x0 10. "PPDI10,Parallel Pad Data In 10" "0: Logic low,1: Logic high" newline bitfld.word 0x0 9. "PPDI9,Parallel Pad Data In 9" "0: Logic low,1: Logic high" newline bitfld.word 0x0 8. "PPDI8,Parallel Pad Data In 8" "0: Logic low,1: Logic high" newline bitfld.word 0x0 7. "PPDI7,Parallel Pad Data In 7" "0: Logic low,1: Logic high" newline bitfld.word 0x0 6. "PPDI6,Parallel Pad Data In 6" "0: Logic low,1: Logic high" newline bitfld.word 0x0 5. "PPDI5,Parallel Pad Data In 5" "0: Logic low,1: Logic high" newline bitfld.word 0x0 4. "PPDI4,Parallel Pad Data In 4" "0: Logic low,1: Logic high" newline bitfld.word 0x0 3. "PPDI3,Parallel Pad Data In 3" "0: Logic low,1: Logic high" newline bitfld.word 0x0 2. "PPDI2,Parallel Pad Data In 2" "0: Logic low,1: Logic high" newline bitfld.word 0x0 1. "PPDI1,Parallel Pad Data In 1" "0: Logic low,1: Logic high" newline bitfld.word 0x0 0. "PPDI0,Parallel Pad Data In 0" "0: Logic low,1: Logic high" line.word 0x2 "PGPDI0,SIUL2 Parallel GPIO Pad Data In" bitfld.word 0x2 15. "PPDI15,Parallel Pad Data In 15" "0: Logic low,1: Logic high" newline bitfld.word 0x2 14. "PPDI14,Parallel Pad Data In 14" "0: Logic low,1: Logic high" newline bitfld.word 0x2 13. "PPDI13,Parallel Pad Data In 13" "0: Logic low,1: Logic high" newline bitfld.word 0x2 12. "PPDI12,Parallel Pad Data In 12" "0: Logic low,1: Logic high" newline bitfld.word 0x2 11. "PPDI11,Parallel Pad Data In 11" "0: Logic low,1: Logic high" newline bitfld.word 0x2 10. "PPDI10,Parallel Pad Data In 10" "0: Logic low,1: Logic high" newline bitfld.word 0x2 9. "PPDI9,Parallel Pad Data In 9" "0: Logic low,1: Logic high" newline bitfld.word 0x2 8. "PPDI8,Parallel Pad Data In 8" "0: Logic low,1: Logic high" newline bitfld.word 0x2 7. "PPDI7,Parallel Pad Data In 7" "0: Logic low,1: Logic high" newline bitfld.word 0x2 6. "PPDI6,Parallel Pad Data In 6" "0: Logic low,1: Logic high" newline bitfld.word 0x2 5. "PPDI5,Parallel Pad Data In 5" "0: Logic low,1: Logic high" newline bitfld.word 0x2 4. "PPDI4,Parallel Pad Data In 4" "0: Logic low,1: Logic high" newline bitfld.word 0x2 3. "PPDI3,Parallel Pad Data In 3" "0: Logic low,1: Logic high" newline bitfld.word 0x2 2. "PPDI2,Parallel Pad Data In 2" "0: Logic low,1: Logic high" newline bitfld.word 0x2 1. "PPDI1,Parallel Pad Data In 1" "0: Logic low,1: Logic high" newline bitfld.word 0x2 0. "PPDI0,Parallel Pad Data In 0" "0: Logic low,1: Logic high" line.word 0x4 "PGPDI3,SIUL2 Parallel GPIO Pad Data In" bitfld.word 0x4 15. "PPDI15,Parallel Pad Data In 15" "0: Logic low,1: Logic high" newline bitfld.word 0x4 14. "PPDI14,Parallel Pad Data In 14" "0: Logic low,1: Logic high" newline bitfld.word 0x4 13. "PPDI13,Parallel Pad Data In 13" "0: Logic low,1: Logic high" newline bitfld.word 0x4 12. "PPDI12,Parallel Pad Data In 12" "0: Logic low,1: Logic high" newline bitfld.word 0x4 11. "PPDI11,Parallel Pad Data In 11" "0: Logic low,1: Logic high" newline bitfld.word 0x4 10. "PPDI10,Parallel Pad Data In 10" "0: Logic low,1: Logic high" newline bitfld.word 0x4 9. "PPDI9,Parallel Pad Data In 9" "0: Logic low,1: Logic high" newline bitfld.word 0x4 8. "PPDI8,Parallel Pad Data In 8" "0: Logic low,1: Logic high" newline bitfld.word 0x4 7. "PPDI7,Parallel Pad Data In 7" "0: Logic low,1: Logic high" newline bitfld.word 0x4 6. "PPDI6,Parallel Pad Data In 6" "0: Logic low,1: Logic high" newline bitfld.word 0x4 5. "PPDI5,Parallel Pad Data In 5" "0: Logic low,1: Logic high" newline bitfld.word 0x4 4. "PPDI4,Parallel Pad Data In 4" "0: Logic low,1: Logic high" newline bitfld.word 0x4 3. "PPDI3,Parallel Pad Data In 3" "0: Logic low,1: Logic high" newline bitfld.word 0x4 2. "PPDI2,Parallel Pad Data In 2" "0: Logic low,1: Logic high" newline bitfld.word 0x4 1. "PPDI1,Parallel Pad Data In 1" "0: Logic low,1: Logic high" newline bitfld.word 0x4 0. "PPDI0,Parallel Pad Data In 0" "0: Logic low,1: Logic high" line.word 0x6 "PGPDI2,SIUL2 Parallel GPIO Pad Data In" bitfld.word 0x6 15. "PPDI15,Parallel Pad Data In 15" "0: Logic low,1: Logic high" newline bitfld.word 0x6 14. "PPDI14,Parallel Pad Data In 14" "0: Logic low,1: Logic high" newline bitfld.word 0x6 13. "PPDI13,Parallel Pad Data In 13" "0: Logic low,1: Logic high" newline bitfld.word 0x6 12. "PPDI12,Parallel Pad Data In 12" "0: Logic low,1: Logic high" newline bitfld.word 0x6 11. "PPDI11,Parallel Pad Data In 11" "0: Logic low,1: Logic high" newline bitfld.word 0x6 10. "PPDI10,Parallel Pad Data In 10" "0: Logic low,1: Logic high" newline bitfld.word 0x6 7. "PPDI7,Parallel Pad Data In 7" "0: Logic low,1: Logic high" newline bitfld.word 0x6 6. "PPDI6,Parallel Pad Data In 6" "0: Logic low,1: Logic high" newline bitfld.word 0x6 5. "PPDI5,Parallel Pad Data In 5" "0: Logic low,1: Logic high" newline bitfld.word 0x6 4. "PPDI4,Parallel Pad Data In 4" "0: Logic low,1: Logic high" newline bitfld.word 0x6 3. "PPDI3,Parallel Pad Data In 3" "0: Logic low,1: Logic high" newline bitfld.word 0x6 2. "PPDI2,Parallel Pad Data In 2" "0: Logic low,1: Logic high" newline bitfld.word 0x6 1. "PPDI1,Parallel Pad Data In 1" "0: Logic low,1: Logic high" newline bitfld.word 0x6 0. "PPDI0,Parallel Pad Data In 0" "0: Logic low,1: Logic high" line.word 0x8 "PGPDI5,SIUL2 Parallel GPIO Pad Data In" bitfld.word 0x8 15. "PPDI15,Parallel Pad Data In 15" "0: Logic low,1: Logic high" newline bitfld.word 0x8 14. "PPDI14,Parallel Pad Data In 14" "0: Logic low,1: Logic high" newline bitfld.word 0x8 13. "PPDI13,Parallel Pad Data In 13" "0: Logic low,1: Logic high" newline bitfld.word 0x8 12. "PPDI12,Parallel Pad Data In 12" "0: Logic low,1: Logic high" newline bitfld.word 0x8 11. "PPDI11,Parallel Pad Data In 11" "0: Logic low,1: Logic high" newline bitfld.word 0x8 10. "PPDI10,Parallel Pad Data In 10" "0: Logic low,1: Logic high" newline bitfld.word 0x8 9. "PPDI9,Parallel Pad Data In 9" "0: Logic low,1: Logic high" newline bitfld.word 0x8 8. "PPDI8,Parallel Pad Data In 8" "0: Logic low,1: Logic high" newline bitfld.word 0x8 7. "PPDI7,Parallel Pad Data In 7" "0: Logic low,1: Logic high" newline bitfld.word 0x8 6. "PPDI6,Parallel Pad Data In 6" "0: Logic low,1: Logic high" newline bitfld.word 0x8 5. "PPDI5,Parallel Pad Data In 5" "0: Logic low,1: Logic high" newline bitfld.word 0x8 4. "PPDI4,Parallel Pad Data In 4" "0: Logic low,1: Logic high" newline bitfld.word 0x8 3. "PPDI3,Parallel Pad Data In 3" "0: Logic low,1: Logic high" newline bitfld.word 0x8 2. "PPDI2,Parallel Pad Data In 2" "0: Logic low,1: Logic high" newline bitfld.word 0x8 1. "PPDI1,Parallel Pad Data In 1" "0: Logic low,1: Logic high" newline bitfld.word 0x8 0. "PPDI0,Parallel Pad Data In 0" "0: Logic low,1: Logic high" line.word 0xA "PGPDI4,SIUL2 Parallel GPIO Pad Data In" bitfld.word 0xA 15. "PPDI15,Parallel Pad Data In 15" "0: Logic low,1: Logic high" newline bitfld.word 0xA 14. "PPDI14,Parallel Pad Data In 14" "0: Logic low,1: Logic high" newline bitfld.word 0xA 13. "PPDI13,Parallel Pad Data In 13" "0: Logic low,1: Logic high" newline bitfld.word 0xA 12. "PPDI12,Parallel Pad Data In 12" "0: Logic low,1: Logic high" newline bitfld.word 0xA 11. "PPDI11,Parallel Pad Data In 11" "0: Logic low,1: Logic high" newline bitfld.word 0xA 10. "PPDI10,Parallel Pad Data In 10" "0: Logic low,1: Logic high" newline bitfld.word 0xA 9. "PPDI9,Parallel Pad Data In 9" "0: Logic low,1: Logic high" newline bitfld.word 0xA 8. "PPDI8,Parallel Pad Data In 8" "0: Logic low,1: Logic high" newline bitfld.word 0xA 7. "PPDI7,Parallel Pad Data In 7" "0: Logic low,1: Logic high" newline bitfld.word 0xA 6. "PPDI6,Parallel Pad Data In 6" "0: Logic low,1: Logic high" newline bitfld.word 0xA 5. "PPDI5,Parallel Pad Data In 5" "0: Logic low,1: Logic high" newline bitfld.word 0xA 4. "PPDI4,Parallel Pad Data In 4" "0: Logic low,1: Logic high" newline bitfld.word 0xA 3. "PPDI3,Parallel Pad Data In 3" "0: Logic low,1: Logic high" newline bitfld.word 0xA 2. "PPDI2,Parallel Pad Data In 2" "0: Logic low,1: Logic high" newline bitfld.word 0xA 1. "PPDI1,Parallel Pad Data In 1" "0: Logic low,1: Logic high" newline bitfld.word 0xA 0. "PPDI0,Parallel Pad Data In 0" "0: Logic low,1: Logic high" line.word 0xC "PGPDI7,SIUL2 Parallel GPIO Pad Data In" bitfld.word 0xC 15. "PPDI15,Parallel Pad Data In 15" "0: Logic low,1: Logic high" newline bitfld.word 0xC 14. "PPDI14,Parallel Pad Data In 14" "0: Logic low,1: Logic high" newline bitfld.word 0xC 13. "PPDI13,Parallel Pad Data In 13" "0: Logic low,1: Logic high" newline bitfld.word 0xC 12. "PPDI12,Parallel Pad Data In 12" "0: Logic low,1: Logic high" newline bitfld.word 0xC 11. "PPDI11,Parallel Pad Data In 11" "0: Logic low,1: Logic high" newline bitfld.word 0xC 10. "PPDI10,Parallel Pad Data In 10" "0: Logic low,1: Logic high" newline bitfld.word 0xC 9. "PPDI9,Parallel Pad Data In 9" "0: Logic low,1: Logic high" newline bitfld.word 0xC 8. "PPDI8,Parallel Pad Data In 8" "0: Logic low,1: Logic high" newline bitfld.word 0xC 7. "PPDI7,Parallel Pad Data In 7" "0: Logic low,1: Logic high" newline bitfld.word 0xC 6. "PPDI6,Parallel Pad Data In 6" "0: Logic low,1: Logic high" newline bitfld.word 0xC 5. "PPDI5,Parallel Pad Data In 5" "0: Logic low,1: Logic high" newline bitfld.word 0xC 4. "PPDI4,Parallel Pad Data In 4" "0: Logic low,1: Logic high" newline bitfld.word 0xC 3. "PPDI3,Parallel Pad Data In 3" "0: Logic low,1: Logic high" newline bitfld.word 0xC 2. "PPDI2,Parallel Pad Data In 2" "0: Logic low,1: Logic high" newline bitfld.word 0xC 1. "PPDI1,Parallel Pad Data In 1" "0: Logic low,1: Logic high" newline bitfld.word 0xC 0. "PPDI0,Parallel Pad Data In 0" "0: Logic low,1: Logic high" line.word 0xE "PGPDI6,SIUL2 Parallel GPIO Pad Data In" bitfld.word 0xE 15. "PPDI15,Parallel Pad Data In 15" "0: Logic low,1: Logic high" newline bitfld.word 0xE 14. "PPDI14,Parallel Pad Data In 14" "0: Logic low,1: Logic high" newline bitfld.word 0xE 13. "PPDI13,Parallel Pad Data In 13" "0: Logic low,1: Logic high" newline bitfld.word 0xE 12. "PPDI12,Parallel Pad Data In 12" "0: Logic low,1: Logic high" newline bitfld.word 0xE 11. "PPDI11,Parallel Pad Data In 11" "0: Logic low,1: Logic high" newline bitfld.word 0xE 10. "PPDI10,Parallel Pad Data In 10" "0: Logic low,1: Logic high" newline bitfld.word 0xE 9. "PPDI9,Parallel Pad Data In 9" "0: Logic low,1: Logic high" newline bitfld.word 0xE 8. "PPDI8,Parallel Pad Data In 8" "0: Logic low,1: Logic high" newline bitfld.word 0xE 7. "PPDI7,Parallel Pad Data In 7" "0: Logic low,1: Logic high" newline bitfld.word 0xE 6. "PPDI6,Parallel Pad Data In 6" "0: Logic low,1: Logic high" newline bitfld.word 0xE 5. "PPDI5,Parallel Pad Data In 5" "0: Logic low,1: Logic high" newline bitfld.word 0xE 4. "PPDI4,Parallel Pad Data In 4" "0: Logic low,1: Logic high" newline bitfld.word 0xE 3. "PPDI3,Parallel Pad Data In 3" "0: Logic low,1: Logic high" newline bitfld.word 0xE 2. "PPDI2,Parallel Pad Data In 2" "0: Logic low,1: Logic high" newline bitfld.word 0xE 1. "PPDI1,Parallel Pad Data In 1" "0: Logic low,1: Logic high" newline bitfld.word 0xE 0. "PPDI0,Parallel Pad Data In 0" "0: Logic low,1: Logic high" line.word 0x10 "PGPDI9,SIUL2 Parallel GPIO Pad Data In" bitfld.word 0x10 15. "PPDI15,Parallel Pad Data In 15" "0: Logic low,1: Logic high" newline bitfld.word 0x10 14. "PPDI14,Parallel Pad Data In 14" "0: Logic low,1: Logic high" newline bitfld.word 0x10 13. "PPDI13,Parallel Pad Data In 13" "0: Logic low,1: Logic high" newline bitfld.word 0x10 12. "PPDI12,Parallel Pad Data In 12" "0: Logic low,1: Logic high" newline bitfld.word 0x10 11. "PPDI11,Parallel Pad Data In 11" "0: Logic low,1: Logic high" newline bitfld.word 0x10 10. "PPDI10,Parallel Pad Data In 10" "0: Logic low,1: Logic high" newline bitfld.word 0x10 9. "PPDI9,Parallel Pad Data In 9" "0: Logic low,1: Logic high" newline bitfld.word 0x10 8. "PPDI8,Parallel Pad Data In 8" "0: Logic low,1: Logic high" newline bitfld.word 0x10 7. "PPDI7,Parallel Pad Data In 7" "0: Logic low,1: Logic high" newline bitfld.word 0x10 6. "PPDI6,Parallel Pad Data In 6" "0: Logic low,1: Logic high" newline bitfld.word 0x10 5. "PPDI5,Parallel Pad Data In 5" "0: Logic low,1: Logic high" newline bitfld.word 0x10 4. "PPDI4,Parallel Pad Data In 4" "0: Logic low,1: Logic high" newline bitfld.word 0x10 3. "PPDI3,Parallel Pad Data In 3" "0: Logic low,1: Logic high" newline bitfld.word 0x10 2. "PPDI2,Parallel Pad Data In 2" "0: Logic low,1: Logic high" newline bitfld.word 0x10 1. "PPDI1,Parallel Pad Data In 1" "0: Logic low,1: Logic high" newline bitfld.word 0x10 0. "PPDI0,Parallel Pad Data In 0" "0: Logic low,1: Logic high" line.word 0x12 "PGPDI8,SIUL2 Parallel GPIO Pad Data In" bitfld.word 0x12 15. "PPDI15,Parallel Pad Data In 15" "0: Logic low,1: Logic high" newline bitfld.word 0x12 14. "PPDI14,Parallel Pad Data In 14" "0: Logic low,1: Logic high" newline bitfld.word 0x12 13. "PPDI13,Parallel Pad Data In 13" "0: Logic low,1: Logic high" newline bitfld.word 0x12 12. "PPDI12,Parallel Pad Data In 12" "0: Logic low,1: Logic high" newline bitfld.word 0x12 11. "PPDI11,Parallel Pad Data In 11" "0: Logic low,1: Logic high" newline bitfld.word 0x12 10. "PPDI10,Parallel Pad Data In 10" "0: Logic low,1: Logic high" newline bitfld.word 0x12 9. "PPDI9,Parallel Pad Data In 9" "0: Logic low,1: Logic high" newline bitfld.word 0x12 8. "PPDI8,Parallel Pad Data In 8" "0: Logic low,1: Logic high" newline bitfld.word 0x12 7. "PPDI7,Parallel Pad Data In 7" "0: Logic low,1: Logic high" newline bitfld.word 0x12 6. "PPDI6,Parallel Pad Data In 6" "0: Logic low,1: Logic high" newline bitfld.word 0x12 5. "PPDI5,Parallel Pad Data In 5" "0: Logic low,1: Logic high" newline bitfld.word 0x12 4. "PPDI4,Parallel Pad Data In 4" "0: Logic low,1: Logic high" newline bitfld.word 0x12 3. "PPDI3,Parallel Pad Data In 3" "0: Logic low,1: Logic high" newline bitfld.word 0x12 1. "PPDI1,Parallel Pad Data In 1" "0: Logic low,1: Logic high" newline bitfld.word 0x12 0. "PPDI0,Parallel Pad Data In 0" "0: Logic low,1: Logic high" line.word 0x14 "PGPDI11,SIUL2 Parallel GPIO Pad Data In" bitfld.word 0x14 15. "PPDI15,Parallel Pad Data In 15" "0: Logic low,1: Logic high" newline bitfld.word 0x14 14. "PPDI14,Parallel Pad Data In 14" "0: Logic low,1: Logic high" newline bitfld.word 0x14 13. "PPDI13,Parallel Pad Data In 13" "0: Logic low,1: Logic high" newline bitfld.word 0x14 12. "PPDI12,Parallel Pad Data In 12" "0: Logic low,1: Logic high" newline bitfld.word 0x14 11. "PPDI11,Parallel Pad Data In 11" "0: Logic low,1: Logic high" newline bitfld.word 0x14 10. "PPDI10,Parallel Pad Data In 10" "0: Logic low,1: Logic high" newline bitfld.word 0x14 9. "PPDI9,Parallel Pad Data In 9" "0: Logic low,1: Logic high" newline bitfld.word 0x14 8. "PPDI8,Parallel Pad Data In 8" "0: Logic low,1: Logic high" newline bitfld.word 0x14 7. "PPDI7,Parallel Pad Data In 7" "0: Logic low,1: Logic high" newline bitfld.word 0x14 6. "PPDI6,Parallel Pad Data In 6" "0: Logic low,1: Logic high" newline bitfld.word 0x14 5. "PPDI5,Parallel Pad Data In 5" "0: Logic low,1: Logic high" newline bitfld.word 0x14 4. "PPDI4,Parallel Pad Data In 4" "0: Logic low,1: Logic high" newline bitfld.word 0x14 3. "PPDI3,Parallel Pad Data In 3" "0: Logic low,1: Logic high" newline bitfld.word 0x14 2. "PPDI2,Parallel Pad Data In 2" "0: Logic low,1: Logic high" newline bitfld.word 0x14 1. "PPDI1,Parallel Pad Data In 1" "0: Logic low,1: Logic high" newline bitfld.word 0x14 0. "PPDI0,Parallel Pad Data In 0" "0: Logic low,1: Logic high" line.word 0x16 "PGPDI10,SIUL2 Parallel GPIO Pad Data In" bitfld.word 0x16 15. "PPDI15,Parallel Pad Data In 15" "0: Logic low,1: Logic high" newline bitfld.word 0x16 14. "PPDI14,Parallel Pad Data In 14" "0: Logic low,1: Logic high" newline bitfld.word 0x16 13. "PPDI13,Parallel Pad Data In 13" "0: Logic low,1: Logic high" newline bitfld.word 0x16 12. "PPDI12,Parallel Pad Data In 12" "0: Logic low,1: Logic high" newline bitfld.word 0x16 11. "PPDI11,Parallel Pad Data In 11" "0: Logic low,1: Logic high" newline bitfld.word 0x16 10. "PPDI10,Parallel Pad Data In 10" "0: Logic low,1: Logic high" newline bitfld.word 0x16 9. "PPDI9,Parallel Pad Data In 9" "0: Logic low,1: Logic high" newline bitfld.word 0x16 8. "PPDI8,Parallel Pad Data In 8" "0: Logic low,1: Logic high" newline bitfld.word 0x16 7. "PPDI7,Parallel Pad Data In 7" "0: Logic low,1: Logic high" newline bitfld.word 0x16 6. "PPDI6,Parallel Pad Data In 6" "0: Logic low,1: Logic high" newline bitfld.word 0x16 5. "PPDI5,Parallel Pad Data In 5" "0: Logic low,1: Logic high" newline bitfld.word 0x16 4. "PPDI4,Parallel Pad Data In 4" "0: Logic low,1: Logic high" newline bitfld.word 0x16 3. "PPDI3,Parallel Pad Data In 3" "0: Logic low,1: Logic high" newline bitfld.word 0x16 2. "PPDI2,Parallel Pad Data In 2" "0: Logic low,1: Logic high" newline bitfld.word 0x16 1. "PPDI1,Parallel Pad Data In 1" "0: Logic low,1: Logic high" newline bitfld.word 0x16 0. "PPDI0,Parallel Pad Data In 0" "0: Logic low,1: Logic high" line.word 0x18 "PGPDI13,SIUL2 Parallel GPIO Pad Data In" bitfld.word 0x18 15. "PPDI15,Parallel Pad Data In 15" "0: Logic low,1: Logic high" newline bitfld.word 0x18 14. "PPDI14,Parallel Pad Data In 14" "0: Logic low,1: Logic high" newline bitfld.word 0x18 13. "PPDI13,Parallel Pad Data In 13" "0: Logic low,1: Logic high" newline bitfld.word 0x18 12. "PPDI12,Parallel Pad Data In 12" "0: Logic low,1: Logic high" newline bitfld.word 0x18 11. "PPDI11,Parallel Pad Data In 11" "0: Logic low,1: Logic high" newline bitfld.word 0x18 10. "PPDI10,Parallel Pad Data In 10" "0: Logic low,1: Logic high" newline bitfld.word 0x18 9. "PPDI9,Parallel Pad Data In 9" "0: Logic low,1: Logic high" newline bitfld.word 0x18 8. "PPDI8,Parallel Pad Data In 8" "0: Logic low,1: Logic high" newline bitfld.word 0x18 7. "PPDI7,Parallel Pad Data In 7" "0: Logic low,1: Logic high" newline bitfld.word 0x18 6. "PPDI6,Parallel Pad Data In 6" "0: Logic low,1: Logic high" newline bitfld.word 0x18 5. "PPDI5,Parallel Pad Data In 5" "0: Logic low,1: Logic high" newline bitfld.word 0x18 4. "PPDI4,Parallel Pad Data In 4" "0: Logic low,1: Logic high" newline bitfld.word 0x18 3. "PPDI3,Parallel Pad Data In 3" "0: Logic low,1: Logic high" newline bitfld.word 0x18 2. "PPDI2,Parallel Pad Data In 2" "0: Logic low,1: Logic high" newline bitfld.word 0x18 1. "PPDI1,Parallel Pad Data In 1" "0: Logic low,1: Logic high" newline bitfld.word 0x18 0. "PPDI0,Parallel Pad Data In 0" "0: Logic low,1: Logic high" line.word 0x1A "PGPDI12,SIUL2 Parallel GPIO Pad Data In" bitfld.word 0x1A 15. "PPDI15,Parallel Pad Data In 15" "0: Logic low,1: Logic high" newline bitfld.word 0x1A 14. "PPDI14,Parallel Pad Data In 14" "0: Logic low,1: Logic high" newline bitfld.word 0x1A 13. "PPDI13,Parallel Pad Data In 13" "0: Logic low,1: Logic high" newline bitfld.word 0x1A 12. "PPDI12,Parallel Pad Data In 12" "0: Logic low,1: Logic high" newline bitfld.word 0x1A 11. "PPDI11,Parallel Pad Data In 11" "0: Logic low,1: Logic high" newline bitfld.word 0x1A 10. "PPDI10,Parallel Pad Data In 10" "0: Logic low,1: Logic high" newline bitfld.word 0x1A 9. "PPDI9,Parallel Pad Data In 9" "0: Logic low,1: Logic high" newline bitfld.word 0x1A 8. "PPDI8,Parallel Pad Data In 8" "0: Logic low,1: Logic high" newline bitfld.word 0x1A 7. "PPDI7,Parallel Pad Data In 7" "0: Logic low,1: Logic high" newline bitfld.word 0x1A 6. "PPDI6,Parallel Pad Data In 6" "0: Logic low,1: Logic high" newline bitfld.word 0x1A 5. "PPDI5,Parallel Pad Data In 5" "0: Logic low,1: Logic high" newline bitfld.word 0x1A 4. "PPDI4,Parallel Pad Data In 4" "0: Logic low,1: Logic high" newline bitfld.word 0x1A 3. "PPDI3,Parallel Pad Data In 3" "0: Logic low,1: Logic high" newline bitfld.word 0x1A 2. "PPDI2,Parallel Pad Data In 2" "0: Logic low,1: Logic high" newline bitfld.word 0x1A 1. "PPDI1,Parallel Pad Data In 1" "0: Logic low,1: Logic high" newline bitfld.word 0x1A 0. "PPDI0,Parallel Pad Data In 0" "0: Logic low,1: Logic high" rgroup.word 0x175E++0x1 line.word 0x0 "PGPDI14,SIUL2 Parallel GPIO Pad Data In" bitfld.word 0x0 15. "PPDI15,Parallel Pad Data In 15" "0: Logic low,1: Logic high" newline bitfld.word 0x0 14. "PPDI14,Parallel Pad Data In 14" "0: Logic low,1: Logic high" newline bitfld.word 0x0 13. "PPDI13,Parallel Pad Data In 13" "0: Logic low,1: Logic high" newline bitfld.word 0x0 12. "PPDI12,Parallel Pad Data In 12" "0: Logic low,1: Logic high" newline bitfld.word 0x0 11. "PPDI11,Parallel Pad Data In 11" "0: Logic low,1: Logic high" newline bitfld.word 0x0 10. "PPDI10,Parallel Pad Data In 10" "0: Logic low,1: Logic high" newline bitfld.word 0x0 9. "PPDI9,Parallel Pad Data In 9" "0: Logic low,1: Logic high" newline bitfld.word 0x0 8. "PPDI8,Parallel Pad Data In 8" "0: Logic low,1: Logic high" newline bitfld.word 0x0 7. "PPDI7,Parallel Pad Data In 7" "0: Logic low,1: Logic high" newline bitfld.word 0x0 6. "PPDI6,Parallel Pad Data In 6" "0: Logic low,1: Logic high" newline bitfld.word 0x0 5. "PPDI5,Parallel Pad Data In 5" "0: Logic low,1: Logic high" newline bitfld.word 0x0 4. "PPDI4,Parallel Pad Data In 4" "0: Logic low,1: Logic high" newline bitfld.word 0x0 3. "PPDI3,Parallel Pad Data In 3" "0: Logic low,1: Logic high" group.long 0x1780++0x3B line.long 0x0 "MPGPDO0,SIUL2 Masked Parallel GPIO Pad Data Out" bitfld.long 0x0 31. "MASK15,Mask Field 15" "0: MPPDO15 is ignored,1: MPPDO15 is written" newline bitfld.long 0x0 30. "MASK14,Mask Field 14" "0: MPPDO14 is ignored,1: MPPDO14 is written" newline bitfld.long 0x0 29. "MASK13,Mask Field 13" "0: MPPDO13 is ignored,1: MPPDO13 is written" newline bitfld.long 0x0 28. "MASK12,Mask Field 12" "0: MPPDO12 is ignored,1: MPPDO12 is written" newline bitfld.long 0x0 27. "MASK11,Mask Field 11" "0: MPPDO11 is ignored,1: MPPDO11 is written" newline bitfld.long 0x0 26. "MASK10,Mask Field 10" "0: MPPDO10 is ignored,1: MPPDO10 is written" newline bitfld.long 0x0 25. "MASK9,Mask Field 9" "0: MPPDO9 is ignored,1: MPPDO9 is written" newline bitfld.long 0x0 24. "MASK8,Mask Field 8" "0: MPPDO8 is ignored,1: MPPDO8 is written" newline bitfld.long 0x0 23. "MASK7,Mask Field 7" "0: MPPDO7 is ignored,1: MPPDO7 is written" newline bitfld.long 0x0 22. "MASK6,Mask Field 6" "0: MPPDO6 is ignored,1: MPPDO6 is written" newline bitfld.long 0x0 21. "MASK5,Mask Field 5" "0: MPPDO5 is ignored,1: MPPDO5 is written" newline bitfld.long 0x0 20. "MASK4,Mask Field 4" "0: MPPDO4 is ignored,1: MPPDO4 is written" newline bitfld.long 0x0 19. "MASK3,Mask Field 3" "0: MPPDO3 is ignored,1: MPPDO3 is written" newline bitfld.long 0x0 18. "MASK2,Mask Field 2" "0: MPPDO2 is ignored,1: MPPDO2 is written" newline bitfld.long 0x0 17. "MASK1,Mask Field 1" "0: MPPDO1 is ignored,1: MPPDO1 is written" newline bitfld.long 0x0 16. "MASK0,Mask Field 0" "0: MPPDO0 is ignored,1: MPPDO0 is written" newline bitfld.long 0x0 15. "MPPDO15,Masked Parallel Pad Data Out 15" "0,1" newline bitfld.long 0x0 14. "MPPDO14,Masked Parallel Pad Data Out 14" "0,1" newline bitfld.long 0x0 13. "MPPDO13,Masked Parallel Pad Data Out 13" "0,1" newline bitfld.long 0x0 12. "MPPDO12,Masked Parallel Pad Data Out 12" "0,1" newline bitfld.long 0x0 11. "MPPDO11,Masked Parallel Pad Data Out 11" "0,1" newline bitfld.long 0x0 10. "MPPDO10,Masked Parallel Pad Data Out 10" "0,1" newline bitfld.long 0x0 9. "MPPDO9,Masked Parallel Pad Data Out 9" "0,1" newline bitfld.long 0x0 8. "MPPDO8,Masked Parallel Pad Data Out 8" "0,1" newline bitfld.long 0x0 7. "MPPDO7,Masked Parallel Pad Data Out 7" "0,1" newline bitfld.long 0x0 6. "MPPDO6,Masked Parallel Pad Data Out 6" "0,1" newline bitfld.long 0x0 5. "MPPDO5,Masked Parallel Pad Data Out 5" "0,1" newline bitfld.long 0x0 4. "MPPDO4,Masked Parallel Pad Data Out 4" "0,1" newline bitfld.long 0x0 3. "MPPDO3,Masked Parallel Pad Data Out 3" "0,1" newline bitfld.long 0x0 2. "MPPDO2,Masked Parallel Pad Data Out 2" "0,1" newline bitfld.long 0x0 1. "MPPDO1,Masked Parallel Pad Data Out 1" "0,1" newline bitfld.long 0x0 0. "MPPDO0,Masked Parallel Pad Data Out 0" "0,1" line.long 0x4 "MPGPDO1,SIUL2 Masked Parallel GPIO Pad Data Out" bitfld.long 0x4 31. "MASK15,Mask Field 15" "0: MPPDO15 is ignored,1: MPPDO15 is written" newline bitfld.long 0x4 30. "MASK14,Mask Field 14" "0: MPPDO14 is ignored,1: MPPDO14 is written" newline bitfld.long 0x4 29. "MASK13,Mask Field 13" "0: MPPDO13 is ignored,1: MPPDO13 is written" newline bitfld.long 0x4 28. "MASK12,Mask Field 12" "0: MPPDO12 is ignored,1: MPPDO12 is written" newline bitfld.long 0x4 27. "MASK11,Mask Field 11" "0: MPPDO11 is ignored,1: MPPDO11 is written" newline bitfld.long 0x4 26. "MASK10,Mask Field 10" "0: MPPDO10 is ignored,1: MPPDO10 is written" newline bitfld.long 0x4 25. "MASK9,Mask Field 9" "0: MPPDO9 is ignored,1: MPPDO9 is written" newline bitfld.long 0x4 24. "MASK8,Mask Field 8" "0: MPPDO8 is ignored,1: MPPDO8 is written" newline bitfld.long 0x4 23. "MASK7,Mask Field 7" "0: MPPDO7 is ignored,1: MPPDO7 is written" newline bitfld.long 0x4 22. "MASK6,Mask Field 6" "0: MPPDO6 is ignored,1: MPPDO6 is written" newline bitfld.long 0x4 21. "MASK5,Mask Field 5" "0: MPPDO5 is ignored,1: MPPDO5 is written" newline bitfld.long 0x4 20. "MASK4,Mask Field 4" "0: MPPDO4 is ignored,1: MPPDO4 is written" newline bitfld.long 0x4 19. "MASK3,Mask Field 3" "0: MPPDO3 is ignored,1: MPPDO3 is written" newline bitfld.long 0x4 18. "MASK2,Mask Field 2" "0: MPPDO2 is ignored,1: MPPDO2 is written" newline bitfld.long 0x4 17. "MASK1,Mask Field 1" "0: MPPDO1 is ignored,1: MPPDO1 is written" newline bitfld.long 0x4 16. "MASK0,Mask Field 0" "0: MPPDO0 is ignored,1: MPPDO0 is written" newline bitfld.long 0x4 15. "MPPDO15,Masked Parallel Pad Data Out 15" "0,1" newline bitfld.long 0x4 14. "MPPDO14,Masked Parallel Pad Data Out 14" "0,1" newline bitfld.long 0x4 13. "MPPDO13,Masked Parallel Pad Data Out 13" "0,1" newline bitfld.long 0x4 12. "MPPDO12,Masked Parallel Pad Data Out 12" "0,1" newline bitfld.long 0x4 11. "MPPDO11,Masked Parallel Pad Data Out 11" "0,1" newline bitfld.long 0x4 10. "MPPDO10,Masked Parallel Pad Data Out 10" "0,1" newline bitfld.long 0x4 9. "MPPDO9,Masked Parallel Pad Data Out 9" "0,1" newline bitfld.long 0x4 8. "MPPDO8,Masked Parallel Pad Data Out 8" "0,1" newline bitfld.long 0x4 7. "MPPDO7,Masked Parallel Pad Data Out 7" "0,1" newline bitfld.long 0x4 6. "MPPDO6,Masked Parallel Pad Data Out 6" "0,1" newline bitfld.long 0x4 5. "MPPDO5,Masked Parallel Pad Data Out 5" "0,1" newline bitfld.long 0x4 4. "MPPDO4,Masked Parallel Pad Data Out 4" "0,1" newline bitfld.long 0x4 3. "MPPDO3,Masked Parallel Pad Data Out 3" "0,1" newline bitfld.long 0x4 2. "MPPDO2,Masked Parallel Pad Data Out 2" "0,1" newline bitfld.long 0x4 1. "MPPDO1,Masked Parallel Pad Data Out 1" "0,1" newline bitfld.long 0x4 0. "MPPDO0,Masked Parallel Pad Data Out 0" "0,1" line.long 0x8 "MPGPDO2,SIUL2 Masked Parallel GPIO Pad Data Out" bitfld.long 0x8 31. "MASK15,Mask Field 15" "0: MPPDO15 is ignored,1: MPPDO15 is written" newline bitfld.long 0x8 30. "MASK14,Mask Field 14" "0: MPPDO14 is ignored,1: MPPDO14 is written" newline bitfld.long 0x8 29. "MASK13,Mask Field 13" "0: MPPDO13 is ignored,1: MPPDO13 is written" newline bitfld.long 0x8 28. "MASK12,Mask Field 12" "0: MPPDO12 is ignored,1: MPPDO12 is written" newline bitfld.long 0x8 27. "MASK11,Mask Field 11" "0: MPPDO11 is ignored,1: MPPDO11 is written" newline bitfld.long 0x8 26. "MASK10,Mask Field 10" "0: MPPDO10 is ignored,1: MPPDO10 is written" newline bitfld.long 0x8 23. "MASK7,Mask Field 7" "0: MPPDO7 is ignored,1: MPPDO7 is written" newline bitfld.long 0x8 22. "MASK6,Mask Field 6" "0: MPPDO6 is ignored,1: MPPDO6 is written" newline bitfld.long 0x8 21. "MASK5,Mask Field 5" "0: MPPDO5 is ignored,1: MPPDO5 is written" newline bitfld.long 0x8 20. "MASK4,Mask Field 4" "0: MPPDO4 is ignored,1: MPPDO4 is written" newline bitfld.long 0x8 19. "MASK3,Mask Field 3" "0: MPPDO3 is ignored,1: MPPDO3 is written" newline bitfld.long 0x8 18. "MASK2,Mask Field 2" "0: MPPDO2 is ignored,1: MPPDO2 is written" newline bitfld.long 0x8 17. "MASK1,Mask Field 1" "0: MPPDO1 is ignored,1: MPPDO1 is written" newline bitfld.long 0x8 16. "MASK0,Mask Field 0" "0: MPPDO0 is ignored,1: MPPDO0 is written" newline bitfld.long 0x8 15. "MPPDO15,Masked Parallel Pad Data Out 15" "0,1" newline bitfld.long 0x8 14. "MPPDO14,Masked Parallel Pad Data Out 14" "0,1" newline bitfld.long 0x8 13. "MPPDO13,Masked Parallel Pad Data Out 13" "0,1" newline bitfld.long 0x8 12. "MPPDO12,Masked Parallel Pad Data Out 12" "0,1" newline bitfld.long 0x8 11. "MPPDO11,Masked Parallel Pad Data Out 11" "0,1" newline bitfld.long 0x8 10. "MPPDO10,Masked Parallel Pad Data Out 10" "0,1" newline bitfld.long 0x8 7. "MPPDO7,Masked Parallel Pad Data Out 7" "0,1" newline bitfld.long 0x8 6. "MPPDO6,Masked Parallel Pad Data Out 6" "0,1" newline bitfld.long 0x8 5. "MPPDO5,Masked Parallel Pad Data Out 5" "0,1" newline bitfld.long 0x8 4. "MPPDO4,Masked Parallel Pad Data Out 4" "0,1" newline bitfld.long 0x8 3. "MPPDO3,Masked Parallel Pad Data Out 3" "0,1" newline bitfld.long 0x8 2. "MPPDO2,Masked Parallel Pad Data Out 2" "0,1" newline bitfld.long 0x8 1. "MPPDO1,Masked Parallel Pad Data Out 1" "0,1" newline bitfld.long 0x8 0. "MPPDO0,Masked Parallel Pad Data Out 0" "0,1" line.long 0xC "MPGPDO3,SIUL2 Masked Parallel GPIO Pad Data Out" bitfld.long 0xC 31. "MASK15,Mask Field 15" "0: MPPDO15 is ignored,1: MPPDO15 is written" newline bitfld.long 0xC 30. "MASK14,Mask Field 14" "0: MPPDO14 is ignored,1: MPPDO14 is written" newline bitfld.long 0xC 29. "MASK13,Mask Field 13" "0: MPPDO13 is ignored,1: MPPDO13 is written" newline bitfld.long 0xC 28. "MASK12,Mask Field 12" "0: MPPDO12 is ignored,1: MPPDO12 is written" newline bitfld.long 0xC 27. "MASK11,Mask Field 11" "0: MPPDO11 is ignored,1: MPPDO11 is written" newline bitfld.long 0xC 26. "MASK10,Mask Field 10" "0: MPPDO10 is ignored,1: MPPDO10 is written" newline bitfld.long 0xC 25. "MASK9,Mask Field 9" "0: MPPDO9 is ignored,1: MPPDO9 is written" newline bitfld.long 0xC 24. "MASK8,Mask Field 8" "0: MPPDO8 is ignored,1: MPPDO8 is written" newline bitfld.long 0xC 23. "MASK7,Mask Field 7" "0: MPPDO7 is ignored,1: MPPDO7 is written" newline bitfld.long 0xC 22. "MASK6,Mask Field 6" "0: MPPDO6 is ignored,1: MPPDO6 is written" newline bitfld.long 0xC 21. "MASK5,Mask Field 5" "0: MPPDO5 is ignored,1: MPPDO5 is written" newline bitfld.long 0xC 20. "MASK4,Mask Field 4" "0: MPPDO4 is ignored,1: MPPDO4 is written" newline bitfld.long 0xC 19. "MASK3,Mask Field 3" "0: MPPDO3 is ignored,1: MPPDO3 is written" newline bitfld.long 0xC 18. "MASK2,Mask Field 2" "0: MPPDO2 is ignored,1: MPPDO2 is written" newline bitfld.long 0xC 17. "MASK1,Mask Field 1" "0: MPPDO1 is ignored,1: MPPDO1 is written" newline bitfld.long 0xC 16. "MASK0,Mask Field 0" "0: MPPDO0 is ignored,1: MPPDO0 is written" newline bitfld.long 0xC 15. "MPPDO15,Masked Parallel Pad Data Out 15" "0,1" newline bitfld.long 0xC 14. "MPPDO14,Masked Parallel Pad Data Out 14" "0,1" newline bitfld.long 0xC 13. "MPPDO13,Masked Parallel Pad Data Out 13" "0,1" newline bitfld.long 0xC 12. "MPPDO12,Masked Parallel Pad Data Out 12" "0,1" newline bitfld.long 0xC 11. "MPPDO11,Masked Parallel Pad Data Out 11" "0,1" newline bitfld.long 0xC 10. "MPPDO10,Masked Parallel Pad Data Out 10" "0,1" newline bitfld.long 0xC 9. "MPPDO9,Masked Parallel Pad Data Out 9" "0,1" newline bitfld.long 0xC 8. "MPPDO8,Masked Parallel Pad Data Out 8" "0,1" newline bitfld.long 0xC 7. "MPPDO7,Masked Parallel Pad Data Out 7" "0,1" newline bitfld.long 0xC 6. "MPPDO6,Masked Parallel Pad Data Out 6" "0,1" newline bitfld.long 0xC 5. "MPPDO5,Masked Parallel Pad Data Out 5" "0,1" newline bitfld.long 0xC 4. "MPPDO4,Masked Parallel Pad Data Out 4" "0,1" newline bitfld.long 0xC 3. "MPPDO3,Masked Parallel Pad Data Out 3" "0,1" newline bitfld.long 0xC 2. "MPPDO2,Masked Parallel Pad Data Out 2" "0,1" newline bitfld.long 0xC 1. "MPPDO1,Masked Parallel Pad Data Out 1" "0,1" newline bitfld.long 0xC 0. "MPPDO0,Masked Parallel Pad Data Out 0" "0,1" line.long 0x10 "MPGPDO4,SIUL2 Masked Parallel GPIO Pad Data Out" bitfld.long 0x10 31. "MASK15,Mask Field 15" "0: MPPDO15 is ignored,1: MPPDO15 is written" newline bitfld.long 0x10 30. "MASK14,Mask Field 14" "0: MPPDO14 is ignored,1: MPPDO14 is written" newline bitfld.long 0x10 29. "MASK13,Mask Field 13" "0: MPPDO13 is ignored,1: MPPDO13 is written" newline bitfld.long 0x10 28. "MASK12,Mask Field 12" "0: MPPDO12 is ignored,1: MPPDO12 is written" newline bitfld.long 0x10 27. "MASK11,Mask Field 11" "0: MPPDO11 is ignored,1: MPPDO11 is written" newline bitfld.long 0x10 26. "MASK10,Mask Field 10" "0: MPPDO10 is ignored,1: MPPDO10 is written" newline bitfld.long 0x10 25. "MASK9,Mask Field 9" "0: MPPDO9 is ignored,1: MPPDO9 is written" newline bitfld.long 0x10 24. "MASK8,Mask Field 8" "0: MPPDO8 is ignored,1: MPPDO8 is written" newline bitfld.long 0x10 23. "MASK7,Mask Field 7" "0: MPPDO7 is ignored,1: MPPDO7 is written" newline bitfld.long 0x10 22. "MASK6,Mask Field 6" "0: MPPDO6 is ignored,1: MPPDO6 is written" newline bitfld.long 0x10 21. "MASK5,Mask Field 5" "0: MPPDO5 is ignored,1: MPPDO5 is written" newline bitfld.long 0x10 20. "MASK4,Mask Field 4" "0: MPPDO4 is ignored,1: MPPDO4 is written" newline bitfld.long 0x10 19. "MASK3,Mask Field 3" "0: MPPDO3 is ignored,1: MPPDO3 is written" newline bitfld.long 0x10 18. "MASK2,Mask Field 2" "0: MPPDO2 is ignored,1: MPPDO2 is written" newline bitfld.long 0x10 17. "MASK1,Mask Field 1" "0: MPPDO1 is ignored,1: MPPDO1 is written" newline bitfld.long 0x10 16. "MASK0,Mask Field 0" "0: MPPDO0 is ignored,1: MPPDO0 is written" newline bitfld.long 0x10 15. "MPPDO15,Masked Parallel Pad Data Out 15" "0,1" newline bitfld.long 0x10 14. "MPPDO14,Masked Parallel Pad Data Out 14" "0,1" newline bitfld.long 0x10 13. "MPPDO13,Masked Parallel Pad Data Out 13" "0,1" newline bitfld.long 0x10 12. "MPPDO12,Masked Parallel Pad Data Out 12" "0,1" newline bitfld.long 0x10 11. "MPPDO11,Masked Parallel Pad Data Out 11" "0,1" newline bitfld.long 0x10 10. "MPPDO10,Masked Parallel Pad Data Out 10" "0,1" newline bitfld.long 0x10 9. "MPPDO9,Masked Parallel Pad Data Out 9" "0,1" newline bitfld.long 0x10 8. "MPPDO8,Masked Parallel Pad Data Out 8" "0,1" newline bitfld.long 0x10 7. "MPPDO7,Masked Parallel Pad Data Out 7" "0,1" newline bitfld.long 0x10 6. "MPPDO6,Masked Parallel Pad Data Out 6" "0,1" newline bitfld.long 0x10 5. "MPPDO5,Masked Parallel Pad Data Out 5" "0,1" newline bitfld.long 0x10 4. "MPPDO4,Masked Parallel Pad Data Out 4" "0,1" newline bitfld.long 0x10 3. "MPPDO3,Masked Parallel Pad Data Out 3" "0,1" newline bitfld.long 0x10 2. "MPPDO2,Masked Parallel Pad Data Out 2" "0,1" newline bitfld.long 0x10 1. "MPPDO1,Masked Parallel Pad Data Out 1" "0,1" newline bitfld.long 0x10 0. "MPPDO0,Masked Parallel Pad Data Out 0" "0,1" line.long 0x14 "MPGPDO5,SIUL2 Masked Parallel GPIO Pad Data Out" bitfld.long 0x14 31. "MASK15,Mask Field 15" "0: MPPDO15 is ignored,1: MPPDO15 is written" newline bitfld.long 0x14 30. "MASK14,Mask Field 14" "0: MPPDO14 is ignored,1: MPPDO14 is written" newline bitfld.long 0x14 29. "MASK13,Mask Field 13" "0: MPPDO13 is ignored,1: MPPDO13 is written" newline bitfld.long 0x14 28. "MASK12,Mask Field 12" "0: MPPDO12 is ignored,1: MPPDO12 is written" newline bitfld.long 0x14 27. "MASK11,Mask Field 11" "0: MPPDO11 is ignored,1: MPPDO11 is written" newline bitfld.long 0x14 26. "MASK10,Mask Field 10" "0: MPPDO10 is ignored,1: MPPDO10 is written" newline bitfld.long 0x14 25. "MASK9,Mask Field 9" "0: MPPDO9 is ignored,1: MPPDO9 is written" newline bitfld.long 0x14 24. "MASK8,Mask Field 8" "0: MPPDO8 is ignored,1: MPPDO8 is written" newline bitfld.long 0x14 23. "MASK7,Mask Field 7" "0: MPPDO7 is ignored,1: MPPDO7 is written" newline bitfld.long 0x14 22. "MASK6,Mask Field 6" "0: MPPDO6 is ignored,1: MPPDO6 is written" newline bitfld.long 0x14 21. "MASK5,Mask Field 5" "0: MPPDO5 is ignored,1: MPPDO5 is written" newline bitfld.long 0x14 20. "MASK4,Mask Field 4" "0: MPPDO4 is ignored,1: MPPDO4 is written" newline bitfld.long 0x14 19. "MASK3,Mask Field 3" "0: MPPDO3 is ignored,1: MPPDO3 is written" newline bitfld.long 0x14 18. "MASK2,Mask Field 2" "0: MPPDO2 is ignored,1: MPPDO2 is written" newline bitfld.long 0x14 17. "MASK1,Mask Field 1" "0: MPPDO1 is ignored,1: MPPDO1 is written" newline bitfld.long 0x14 16. "MASK0,Mask Field 0" "0: MPPDO0 is ignored,1: MPPDO0 is written" newline bitfld.long 0x14 15. "MPPDO15,Masked Parallel Pad Data Out 15" "0,1" newline bitfld.long 0x14 14. "MPPDO14,Masked Parallel Pad Data Out 14" "0,1" newline bitfld.long 0x14 13. "MPPDO13,Masked Parallel Pad Data Out 13" "0,1" newline bitfld.long 0x14 12. "MPPDO12,Masked Parallel Pad Data Out 12" "0,1" newline bitfld.long 0x14 11. "MPPDO11,Masked Parallel Pad Data Out 11" "0,1" newline bitfld.long 0x14 10. "MPPDO10,Masked Parallel Pad Data Out 10" "0,1" newline bitfld.long 0x14 9. "MPPDO9,Masked Parallel Pad Data Out 9" "0,1" newline bitfld.long 0x14 8. "MPPDO8,Masked Parallel Pad Data Out 8" "0,1" newline bitfld.long 0x14 7. "MPPDO7,Masked Parallel Pad Data Out 7" "0,1" newline bitfld.long 0x14 6. "MPPDO6,Masked Parallel Pad Data Out 6" "0,1" newline bitfld.long 0x14 5. "MPPDO5,Masked Parallel Pad Data Out 5" "0,1" newline bitfld.long 0x14 4. "MPPDO4,Masked Parallel Pad Data Out 4" "0,1" newline bitfld.long 0x14 3. "MPPDO3,Masked Parallel Pad Data Out 3" "0,1" newline bitfld.long 0x14 2. "MPPDO2,Masked Parallel Pad Data Out 2" "0,1" newline bitfld.long 0x14 1. "MPPDO1,Masked Parallel Pad Data Out 1" "0,1" newline bitfld.long 0x14 0. "MPPDO0,Masked Parallel Pad Data Out 0" "0,1" line.long 0x18 "MPGPDO6,SIUL2 Masked Parallel GPIO Pad Data Out" bitfld.long 0x18 31. "MASK15,Mask Field 15" "0: MPPDO15 is ignored,1: MPPDO15 is written" newline bitfld.long 0x18 30. "MASK14,Mask Field 14" "0: MPPDO14 is ignored,1: MPPDO14 is written" newline bitfld.long 0x18 29. "MASK13,Mask Field 13" "0: MPPDO13 is ignored,1: MPPDO13 is written" newline bitfld.long 0x18 28. "MASK12,Mask Field 12" "0: MPPDO12 is ignored,1: MPPDO12 is written" newline bitfld.long 0x18 27. "MASK11,Mask Field 11" "0: MPPDO11 is ignored,1: MPPDO11 is written" newline bitfld.long 0x18 26. "MASK10,Mask Field 10" "0: MPPDO10 is ignored,1: MPPDO10 is written" newline bitfld.long 0x18 25. "MASK9,Mask Field 9" "0: MPPDO9 is ignored,1: MPPDO9 is written" newline bitfld.long 0x18 24. "MASK8,Mask Field 8" "0: MPPDO8 is ignored,1: MPPDO8 is written" newline bitfld.long 0x18 23. "MASK7,Mask Field 7" "0: MPPDO7 is ignored,1: MPPDO7 is written" newline bitfld.long 0x18 22. "MASK6,Mask Field 6" "0: MPPDO6 is ignored,1: MPPDO6 is written" newline bitfld.long 0x18 21. "MASK5,Mask Field 5" "0: MPPDO5 is ignored,1: MPPDO5 is written" newline bitfld.long 0x18 20. "MASK4,Mask Field 4" "0: MPPDO4 is ignored,1: MPPDO4 is written" newline bitfld.long 0x18 19. "MASK3,Mask Field 3" "0: MPPDO3 is ignored,1: MPPDO3 is written" newline bitfld.long 0x18 18. "MASK2,Mask Field 2" "0: MPPDO2 is ignored,1: MPPDO2 is written" newline bitfld.long 0x18 17. "MASK1,Mask Field 1" "0: MPPDO1 is ignored,1: MPPDO1 is written" newline bitfld.long 0x18 16. "MASK0,Mask Field 0" "0: MPPDO0 is ignored,1: MPPDO0 is written" newline bitfld.long 0x18 15. "MPPDO15,Masked Parallel Pad Data Out 15" "0,1" newline bitfld.long 0x18 14. "MPPDO14,Masked Parallel Pad Data Out 14" "0,1" newline bitfld.long 0x18 13. "MPPDO13,Masked Parallel Pad Data Out 13" "0,1" newline bitfld.long 0x18 12. "MPPDO12,Masked Parallel Pad Data Out 12" "0,1" newline bitfld.long 0x18 11. "MPPDO11,Masked Parallel Pad Data Out 11" "0,1" newline bitfld.long 0x18 10. "MPPDO10,Masked Parallel Pad Data Out 10" "0,1" newline bitfld.long 0x18 9. "MPPDO9,Masked Parallel Pad Data Out 9" "0,1" newline bitfld.long 0x18 8. "MPPDO8,Masked Parallel Pad Data Out 8" "0,1" newline bitfld.long 0x18 7. "MPPDO7,Masked Parallel Pad Data Out 7" "0,1" newline bitfld.long 0x18 6. "MPPDO6,Masked Parallel Pad Data Out 6" "0,1" newline bitfld.long 0x18 5. "MPPDO5,Masked Parallel Pad Data Out 5" "0,1" newline bitfld.long 0x18 4. "MPPDO4,Masked Parallel Pad Data Out 4" "0,1" newline bitfld.long 0x18 3. "MPPDO3,Masked Parallel Pad Data Out 3" "0,1" newline bitfld.long 0x18 2. "MPPDO2,Masked Parallel Pad Data Out 2" "0,1" newline bitfld.long 0x18 1. "MPPDO1,Masked Parallel Pad Data Out 1" "0,1" newline bitfld.long 0x18 0. "MPPDO0,Masked Parallel Pad Data Out 0" "0,1" line.long 0x1C "MPGPDO7,SIUL2 Masked Parallel GPIO Pad Data Out" bitfld.long 0x1C 31. "MASK15,Mask Field 15" "0: MPPDO15 is ignored,1: MPPDO15 is written" newline bitfld.long 0x1C 30. "MASK14,Mask Field 14" "0: MPPDO14 is ignored,1: MPPDO14 is written" newline bitfld.long 0x1C 29. "MASK13,Mask Field 13" "0: MPPDO13 is ignored,1: MPPDO13 is written" newline bitfld.long 0x1C 28. "MASK12,Mask Field 12" "0: MPPDO12 is ignored,1: MPPDO12 is written" newline bitfld.long 0x1C 27. "MASK11,Mask Field 11" "0: MPPDO11 is ignored,1: MPPDO11 is written" newline bitfld.long 0x1C 26. "MASK10,Mask Field 10" "0: MPPDO10 is ignored,1: MPPDO10 is written" newline bitfld.long 0x1C 25. "MASK9,Mask Field 9" "0: MPPDO9 is ignored,1: MPPDO9 is written" newline bitfld.long 0x1C 24. "MASK8,Mask Field 8" "0: MPPDO8 is ignored,1: MPPDO8 is written" newline bitfld.long 0x1C 23. "MASK7,Mask Field 7" "0: MPPDO7 is ignored,1: MPPDO7 is written" newline bitfld.long 0x1C 22. "MASK6,Mask Field 6" "0: MPPDO6 is ignored,1: MPPDO6 is written" newline bitfld.long 0x1C 21. "MASK5,Mask Field 5" "0: MPPDO5 is ignored,1: MPPDO5 is written" newline bitfld.long 0x1C 20. "MASK4,Mask Field 4" "0: MPPDO4 is ignored,1: MPPDO4 is written" newline bitfld.long 0x1C 19. "MASK3,Mask Field 3" "0: MPPDO3 is ignored,1: MPPDO3 is written" newline bitfld.long 0x1C 18. "MASK2,Mask Field 2" "0: MPPDO2 is ignored,1: MPPDO2 is written" newline bitfld.long 0x1C 17. "MASK1,Mask Field 1" "0: MPPDO1 is ignored,1: MPPDO1 is written" newline bitfld.long 0x1C 16. "MASK0,Mask Field 0" "0: MPPDO0 is ignored,1: MPPDO0 is written" newline bitfld.long 0x1C 15. "MPPDO15,Masked Parallel Pad Data Out 15" "0,1" newline bitfld.long 0x1C 14. "MPPDO14,Masked Parallel Pad Data Out 14" "0,1" newline bitfld.long 0x1C 13. "MPPDO13,Masked Parallel Pad Data Out 13" "0,1" newline bitfld.long 0x1C 12. "MPPDO12,Masked Parallel Pad Data Out 12" "0,1" newline bitfld.long 0x1C 11. "MPPDO11,Masked Parallel Pad Data Out 11" "0,1" newline bitfld.long 0x1C 10. "MPPDO10,Masked Parallel Pad Data Out 10" "0,1" newline bitfld.long 0x1C 9. "MPPDO9,Masked Parallel Pad Data Out 9" "0,1" newline bitfld.long 0x1C 8. "MPPDO8,Masked Parallel Pad Data Out 8" "0,1" newline bitfld.long 0x1C 7. "MPPDO7,Masked Parallel Pad Data Out 7" "0,1" newline bitfld.long 0x1C 6. "MPPDO6,Masked Parallel Pad Data Out 6" "0,1" newline bitfld.long 0x1C 5. "MPPDO5,Masked Parallel Pad Data Out 5" "0,1" newline bitfld.long 0x1C 4. "MPPDO4,Masked Parallel Pad Data Out 4" "0,1" newline bitfld.long 0x1C 3. "MPPDO3,Masked Parallel Pad Data Out 3" "0,1" newline bitfld.long 0x1C 2. "MPPDO2,Masked Parallel Pad Data Out 2" "0,1" newline bitfld.long 0x1C 1. "MPPDO1,Masked Parallel Pad Data Out 1" "0,1" newline bitfld.long 0x1C 0. "MPPDO0,Masked Parallel Pad Data Out 0" "0,1" line.long 0x20 "MPGPDO8,SIUL2 Masked Parallel GPIO Pad Data Out" bitfld.long 0x20 31. "MASK15,Mask Field 15" "0: MPPDO15 is ignored,1: MPPDO15 is written" newline bitfld.long 0x20 30. "MASK14,Mask Field 14" "0: MPPDO14 is ignored,1: MPPDO14 is written" newline bitfld.long 0x20 29. "MASK13,Mask Field 13" "0: MPPDO13 is ignored,1: MPPDO13 is written" newline bitfld.long 0x20 28. "MASK12,Mask Field 12" "0: MPPDO12 is ignored,1: MPPDO12 is written" newline bitfld.long 0x20 27. "MASK11,Mask Field 11" "0: MPPDO11 is ignored,1: MPPDO11 is written" newline bitfld.long 0x20 26. "MASK10,Mask Field 10" "0: MPPDO10 is ignored,1: MPPDO10 is written" newline bitfld.long 0x20 25. "MASK9,Mask Field 9" "0: MPPDO9 is ignored,1: MPPDO9 is written" newline bitfld.long 0x20 24. "MASK8,Mask Field 8" "0: MPPDO8 is ignored,1: MPPDO8 is written" newline bitfld.long 0x20 23. "MASK7,Mask Field 7" "0: MPPDO7 is ignored,1: MPPDO7 is written" newline bitfld.long 0x20 22. "MASK6,Mask Field 6" "0: MPPDO6 is ignored,1: MPPDO6 is written" newline bitfld.long 0x20 21. "MASK5,Mask Field 5" "0: MPPDO5 is ignored,1: MPPDO5 is written" newline bitfld.long 0x20 20. "MASK4,Mask Field 4" "0: MPPDO4 is ignored,1: MPPDO4 is written" newline bitfld.long 0x20 19. "MASK3,Mask Field 3" "0: MPPDO3 is ignored,1: MPPDO3 is written" newline bitfld.long 0x20 17. "MASK1,Mask Field 1" "0: MPPDO1 is ignored,1: MPPDO1 is written" newline bitfld.long 0x20 16. "MASK0,Mask Field 0" "0: MPPDO0 is ignored,1: MPPDO0 is written" newline bitfld.long 0x20 15. "MPPDO15,Masked Parallel Pad Data Out 15" "0,1" newline bitfld.long 0x20 14. "MPPDO14,Masked Parallel Pad Data Out 14" "0,1" newline bitfld.long 0x20 13. "MPPDO13,Masked Parallel Pad Data Out 13" "0,1" newline bitfld.long 0x20 12. "MPPDO12,Masked Parallel Pad Data Out 12" "0,1" newline bitfld.long 0x20 11. "MPPDO11,Masked Parallel Pad Data Out 11" "0,1" newline bitfld.long 0x20 10. "MPPDO10,Masked Parallel Pad Data Out 10" "0,1" newline bitfld.long 0x20 9. "MPPDO9,Masked Parallel Pad Data Out 9" "0,1" newline bitfld.long 0x20 8. "MPPDO8,Masked Parallel Pad Data Out 8" "0,1" newline bitfld.long 0x20 7. "MPPDO7,Masked Parallel Pad Data Out 7" "0,1" newline bitfld.long 0x20 6. "MPPDO6,Masked Parallel Pad Data Out 6" "0,1" newline bitfld.long 0x20 5. "MPPDO5,Masked Parallel Pad Data Out 5" "0,1" newline bitfld.long 0x20 4. "MPPDO4,Masked Parallel Pad Data Out 4" "0,1" newline bitfld.long 0x20 3. "MPPDO3,Masked Parallel Pad Data Out 3" "0,1" newline bitfld.long 0x20 1. "MPPDO1,Masked Parallel Pad Data Out 1" "0,1" newline bitfld.long 0x20 0. "MPPDO0,Masked Parallel Pad Data Out 0" "0,1" line.long 0x24 "MPGPDO9,SIUL2 Masked Parallel GPIO Pad Data Out" bitfld.long 0x24 31. "MASK15,Mask Field 15" "0: MPPDO15 is ignored,1: MPPDO15 is written" newline bitfld.long 0x24 30. "MASK14,Mask Field 14" "0: MPPDO14 is ignored,1: MPPDO14 is written" newline bitfld.long 0x24 29. "MASK13,Mask Field 13" "0: MPPDO13 is ignored,1: MPPDO13 is written" newline bitfld.long 0x24 28. "MASK12,Mask Field 12" "0: MPPDO12 is ignored,1: MPPDO12 is written" newline bitfld.long 0x24 27. "MASK11,Mask Field 11" "0: MPPDO11 is ignored,1: MPPDO11 is written" newline bitfld.long 0x24 26. "MASK10,Mask Field 10" "0: MPPDO10 is ignored,1: MPPDO10 is written" newline bitfld.long 0x24 25. "MASK9,Mask Field 9" "0: MPPDO9 is ignored,1: MPPDO9 is written" newline bitfld.long 0x24 24. "MASK8,Mask Field 8" "0: MPPDO8 is ignored,1: MPPDO8 is written" newline bitfld.long 0x24 23. "MASK7,Mask Field 7" "0: MPPDO7 is ignored,1: MPPDO7 is written" newline bitfld.long 0x24 22. "MASK6,Mask Field 6" "0: MPPDO6 is ignored,1: MPPDO6 is written" newline bitfld.long 0x24 21. "MASK5,Mask Field 5" "0: MPPDO5 is ignored,1: MPPDO5 is written" newline bitfld.long 0x24 20. "MASK4,Mask Field 4" "0: MPPDO4 is ignored,1: MPPDO4 is written" newline bitfld.long 0x24 19. "MASK3,Mask Field 3" "0: MPPDO3 is ignored,1: MPPDO3 is written" newline bitfld.long 0x24 18. "MASK2,Mask Field 2" "0: MPPDO2 is ignored,1: MPPDO2 is written" newline bitfld.long 0x24 17. "MASK1,Mask Field 1" "0: MPPDO1 is ignored,1: MPPDO1 is written" newline bitfld.long 0x24 16. "MASK0,Mask Field 0" "0: MPPDO0 is ignored,1: MPPDO0 is written" newline bitfld.long 0x24 15. "MPPDO15,Masked Parallel Pad Data Out 15" "0,1" newline bitfld.long 0x24 14. "MPPDO14,Masked Parallel Pad Data Out 14" "0,1" newline bitfld.long 0x24 13. "MPPDO13,Masked Parallel Pad Data Out 13" "0,1" newline bitfld.long 0x24 12. "MPPDO12,Masked Parallel Pad Data Out 12" "0,1" newline bitfld.long 0x24 11. "MPPDO11,Masked Parallel Pad Data Out 11" "0,1" newline bitfld.long 0x24 10. "MPPDO10,Masked Parallel Pad Data Out 10" "0,1" newline bitfld.long 0x24 9. "MPPDO9,Masked Parallel Pad Data Out 9" "0,1" newline bitfld.long 0x24 8. "MPPDO8,Masked Parallel Pad Data Out 8" "0,1" newline bitfld.long 0x24 7. "MPPDO7,Masked Parallel Pad Data Out 7" "0,1" newline bitfld.long 0x24 6. "MPPDO6,Masked Parallel Pad Data Out 6" "0,1" newline bitfld.long 0x24 5. "MPPDO5,Masked Parallel Pad Data Out 5" "0,1" newline bitfld.long 0x24 4. "MPPDO4,Masked Parallel Pad Data Out 4" "0,1" newline bitfld.long 0x24 3. "MPPDO3,Masked Parallel Pad Data Out 3" "0,1" newline bitfld.long 0x24 2. "MPPDO2,Masked Parallel Pad Data Out 2" "0,1" newline bitfld.long 0x24 1. "MPPDO1,Masked Parallel Pad Data Out 1" "0,1" newline bitfld.long 0x24 0. "MPPDO0,Masked Parallel Pad Data Out 0" "0,1" line.long 0x28 "MPGPDO10,SIUL2 Masked Parallel GPIO Pad Data Out" bitfld.long 0x28 31. "MASK15,Mask Field 15" "0: MPPDO15 is ignored,1: MPPDO15 is written" newline bitfld.long 0x28 30. "MASK14,Mask Field 14" "0: MPPDO14 is ignored,1: MPPDO14 is written" newline bitfld.long 0x28 29. "MASK13,Mask Field 13" "0: MPPDO13 is ignored,1: MPPDO13 is written" newline bitfld.long 0x28 28. "MASK12,Mask Field 12" "0: MPPDO12 is ignored,1: MPPDO12 is written" newline bitfld.long 0x28 27. "MASK11,Mask Field 11" "0: MPPDO11 is ignored,1: MPPDO11 is written" newline bitfld.long 0x28 26. "MASK10,Mask Field 10" "0: MPPDO10 is ignored,1: MPPDO10 is written" newline bitfld.long 0x28 25. "MASK9,Mask Field 9" "0: MPPDO9 is ignored,1: MPPDO9 is written" newline bitfld.long 0x28 24. "MASK8,Mask Field 8" "0: MPPDO8 is ignored,1: MPPDO8 is written" newline bitfld.long 0x28 23. "MASK7,Mask Field 7" "0: MPPDO7 is ignored,1: MPPDO7 is written" newline bitfld.long 0x28 22. "MASK6,Mask Field 6" "0: MPPDO6 is ignored,1: MPPDO6 is written" newline bitfld.long 0x28 21. "MASK5,Mask Field 5" "0: MPPDO5 is ignored,1: MPPDO5 is written" newline bitfld.long 0x28 20. "MASK4,Mask Field 4" "0: MPPDO4 is ignored,1: MPPDO4 is written" newline bitfld.long 0x28 19. "MASK3,Mask Field 3" "0: MPPDO3 is ignored,1: MPPDO3 is written" newline bitfld.long 0x28 18. "MASK2,Mask Field 2" "0: MPPDO2 is ignored,1: MPPDO2 is written" newline bitfld.long 0x28 17. "MASK1,Mask Field 1" "0: MPPDO1 is ignored,1: MPPDO1 is written" newline bitfld.long 0x28 16. "MASK0,Mask Field 0" "0: MPPDO0 is ignored,1: MPPDO0 is written" newline bitfld.long 0x28 15. "MPPDO15,Masked Parallel Pad Data Out 15" "0,1" newline bitfld.long 0x28 14. "MPPDO14,Masked Parallel Pad Data Out 14" "0,1" newline bitfld.long 0x28 13. "MPPDO13,Masked Parallel Pad Data Out 13" "0,1" newline bitfld.long 0x28 12. "MPPDO12,Masked Parallel Pad Data Out 12" "0,1" newline bitfld.long 0x28 11. "MPPDO11,Masked Parallel Pad Data Out 11" "0,1" newline bitfld.long 0x28 10. "MPPDO10,Masked Parallel Pad Data Out 10" "0,1" newline bitfld.long 0x28 9. "MPPDO9,Masked Parallel Pad Data Out 9" "0,1" newline bitfld.long 0x28 8. "MPPDO8,Masked Parallel Pad Data Out 8" "0,1" newline bitfld.long 0x28 7. "MPPDO7,Masked Parallel Pad Data Out 7" "0,1" newline bitfld.long 0x28 6. "MPPDO6,Masked Parallel Pad Data Out 6" "0,1" newline bitfld.long 0x28 5. "MPPDO5,Masked Parallel Pad Data Out 5" "0,1" newline bitfld.long 0x28 4. "MPPDO4,Masked Parallel Pad Data Out 4" "0,1" newline bitfld.long 0x28 3. "MPPDO3,Masked Parallel Pad Data Out 3" "0,1" newline bitfld.long 0x28 2. "MPPDO2,Masked Parallel Pad Data Out 2" "0,1" newline bitfld.long 0x28 1. "MPPDO1,Masked Parallel Pad Data Out 1" "0,1" newline bitfld.long 0x28 0. "MPPDO0,Masked Parallel Pad Data Out 0" "0,1" line.long 0x2C "MPGPDO11,SIUL2 Masked Parallel GPIO Pad Data Out" bitfld.long 0x2C 31. "MASK15,Mask Field 15" "0: MPPDO15 is ignored,1: MPPDO15 is written" newline bitfld.long 0x2C 30. "MASK14,Mask Field 14" "0: MPPDO14 is ignored,1: MPPDO14 is written" newline bitfld.long 0x2C 29. "MASK13,Mask Field 13" "0: MPPDO13 is ignored,1: MPPDO13 is written" newline bitfld.long 0x2C 28. "MASK12,Mask Field 12" "0: MPPDO12 is ignored,1: MPPDO12 is written" newline bitfld.long 0x2C 27. "MASK11,Mask Field 11" "0: MPPDO11 is ignored,1: MPPDO11 is written" newline bitfld.long 0x2C 26. "MASK10,Mask Field 10" "0: MPPDO10 is ignored,1: MPPDO10 is written" newline bitfld.long 0x2C 25. "MASK9,Mask Field 9" "0: MPPDO9 is ignored,1: MPPDO9 is written" newline bitfld.long 0x2C 24. "MASK8,Mask Field 8" "0: MPPDO8 is ignored,1: MPPDO8 is written" newline bitfld.long 0x2C 23. "MASK7,Mask Field 7" "0: MPPDO7 is ignored,1: MPPDO7 is written" newline bitfld.long 0x2C 22. "MASK6,Mask Field 6" "0: MPPDO6 is ignored,1: MPPDO6 is written" newline bitfld.long 0x2C 21. "MASK5,Mask Field 5" "0: MPPDO5 is ignored,1: MPPDO5 is written" newline bitfld.long 0x2C 20. "MASK4,Mask Field 4" "0: MPPDO4 is ignored,1: MPPDO4 is written" newline bitfld.long 0x2C 19. "MASK3,Mask Field 3" "0: MPPDO3 is ignored,1: MPPDO3 is written" newline bitfld.long 0x2C 18. "MASK2,Mask Field 2" "0: MPPDO2 is ignored,1: MPPDO2 is written" newline bitfld.long 0x2C 17. "MASK1,Mask Field 1" "0: MPPDO1 is ignored,1: MPPDO1 is written" newline bitfld.long 0x2C 16. "MASK0,Mask Field 0" "0: MPPDO0 is ignored,1: MPPDO0 is written" newline bitfld.long 0x2C 15. "MPPDO15,Masked Parallel Pad Data Out 15" "0,1" newline bitfld.long 0x2C 14. "MPPDO14,Masked Parallel Pad Data Out 14" "0,1" newline bitfld.long 0x2C 13. "MPPDO13,Masked Parallel Pad Data Out 13" "0,1" newline bitfld.long 0x2C 12. "MPPDO12,Masked Parallel Pad Data Out 12" "0,1" newline bitfld.long 0x2C 11. "MPPDO11,Masked Parallel Pad Data Out 11" "0,1" newline bitfld.long 0x2C 10. "MPPDO10,Masked Parallel Pad Data Out 10" "0,1" newline bitfld.long 0x2C 9. "MPPDO9,Masked Parallel Pad Data Out 9" "0,1" newline bitfld.long 0x2C 8. "MPPDO8,Masked Parallel Pad Data Out 8" "0,1" newline bitfld.long 0x2C 7. "MPPDO7,Masked Parallel Pad Data Out 7" "0,1" newline bitfld.long 0x2C 6. "MPPDO6,Masked Parallel Pad Data Out 6" "0,1" newline bitfld.long 0x2C 5. "MPPDO5,Masked Parallel Pad Data Out 5" "0,1" newline bitfld.long 0x2C 4. "MPPDO4,Masked Parallel Pad Data Out 4" "0,1" newline bitfld.long 0x2C 3. "MPPDO3,Masked Parallel Pad Data Out 3" "0,1" newline bitfld.long 0x2C 2. "MPPDO2,Masked Parallel Pad Data Out 2" "0,1" newline bitfld.long 0x2C 1. "MPPDO1,Masked Parallel Pad Data Out 1" "0,1" newline bitfld.long 0x2C 0. "MPPDO0,Masked Parallel Pad Data Out 0" "0,1" line.long 0x30 "MPGPDO12,SIUL2 Masked Parallel GPIO Pad Data Out" bitfld.long 0x30 31. "MASK15,Mask Field 15" "0: MPPDO15 is ignored,1: MPPDO15 is written" newline bitfld.long 0x30 30. "MASK14,Mask Field 14" "0: MPPDO14 is ignored,1: MPPDO14 is written" newline bitfld.long 0x30 29. "MASK13,Mask Field 13" "0: MPPDO13 is ignored,1: MPPDO13 is written" newline bitfld.long 0x30 28. "MASK12,Mask Field 12" "0: MPPDO12 is ignored,1: MPPDO12 is written" newline bitfld.long 0x30 27. "MASK11,Mask Field 11" "0: MPPDO11 is ignored,1: MPPDO11 is written" newline bitfld.long 0x30 26. "MASK10,Mask Field 10" "0: MPPDO10 is ignored,1: MPPDO10 is written" newline bitfld.long 0x30 25. "MASK9,Mask Field 9" "0: MPPDO9 is ignored,1: MPPDO9 is written" newline bitfld.long 0x30 24. "MASK8,Mask Field 8" "0: MPPDO8 is ignored,1: MPPDO8 is written" newline bitfld.long 0x30 23. "MASK7,Mask Field 7" "0: MPPDO7 is ignored,1: MPPDO7 is written" newline bitfld.long 0x30 22. "MASK6,Mask Field 6" "0: MPPDO6 is ignored,1: MPPDO6 is written" newline bitfld.long 0x30 21. "MASK5,Mask Field 5" "0: MPPDO5 is ignored,1: MPPDO5 is written" newline bitfld.long 0x30 20. "MASK4,Mask Field 4" "0: MPPDO4 is ignored,1: MPPDO4 is written" newline bitfld.long 0x30 19. "MASK3,Mask Field 3" "0: MPPDO3 is ignored,1: MPPDO3 is written" newline bitfld.long 0x30 18. "MASK2,Mask Field 2" "0: MPPDO2 is ignored,1: MPPDO2 is written" newline bitfld.long 0x30 17. "MASK1,Mask Field 1" "0: MPPDO1 is ignored,1: MPPDO1 is written" newline bitfld.long 0x30 16. "MASK0,Mask Field 0" "0: MPPDO0 is ignored,1: MPPDO0 is written" newline bitfld.long 0x30 15. "MPPDO15,Masked Parallel Pad Data Out 15" "0,1" newline bitfld.long 0x30 14. "MPPDO14,Masked Parallel Pad Data Out 14" "0,1" newline bitfld.long 0x30 13. "MPPDO13,Masked Parallel Pad Data Out 13" "0,1" newline bitfld.long 0x30 12. "MPPDO12,Masked Parallel Pad Data Out 12" "0,1" newline bitfld.long 0x30 11. "MPPDO11,Masked Parallel Pad Data Out 11" "0,1" newline bitfld.long 0x30 10. "MPPDO10,Masked Parallel Pad Data Out 10" "0,1" newline bitfld.long 0x30 9. "MPPDO9,Masked Parallel Pad Data Out 9" "0,1" newline bitfld.long 0x30 8. "MPPDO8,Masked Parallel Pad Data Out 8" "0,1" newline bitfld.long 0x30 7. "MPPDO7,Masked Parallel Pad Data Out 7" "0,1" newline bitfld.long 0x30 6. "MPPDO6,Masked Parallel Pad Data Out 6" "0,1" newline bitfld.long 0x30 5. "MPPDO5,Masked Parallel Pad Data Out 5" "0,1" newline bitfld.long 0x30 4. "MPPDO4,Masked Parallel Pad Data Out 4" "0,1" newline bitfld.long 0x30 3. "MPPDO3,Masked Parallel Pad Data Out 3" "0,1" newline bitfld.long 0x30 2. "MPPDO2,Masked Parallel Pad Data Out 2" "0,1" newline bitfld.long 0x30 1. "MPPDO1,Masked Parallel Pad Data Out 1" "0,1" newline bitfld.long 0x30 0. "MPPDO0,Masked Parallel Pad Data Out 0" "0,1" line.long 0x34 "MPGPDO13,SIUL2 Masked Parallel GPIO Pad Data Out" bitfld.long 0x34 31. "MASK15,Mask Field 15" "0: MPPDO15 is ignored,1: MPPDO15 is written" newline bitfld.long 0x34 30. "MASK14,Mask Field 14" "0: MPPDO14 is ignored,1: MPPDO14 is written" newline bitfld.long 0x34 29. "MASK13,Mask Field 13" "0: MPPDO13 is ignored,1: MPPDO13 is written" newline bitfld.long 0x34 28. "MASK12,Mask Field 12" "0: MPPDO12 is ignored,1: MPPDO12 is written" newline bitfld.long 0x34 27. "MASK11,Mask Field 11" "0: MPPDO11 is ignored,1: MPPDO11 is written" newline bitfld.long 0x34 26. "MASK10,Mask Field 10" "0: MPPDO10 is ignored,1: MPPDO10 is written" newline bitfld.long 0x34 25. "MASK9,Mask Field 9" "0: MPPDO9 is ignored,1: MPPDO9 is written" newline bitfld.long 0x34 24. "MASK8,Mask Field 8" "0: MPPDO8 is ignored,1: MPPDO8 is written" newline bitfld.long 0x34 23. "MASK7,Mask Field 7" "0: MPPDO7 is ignored,1: MPPDO7 is written" newline bitfld.long 0x34 22. "MASK6,Mask Field 6" "0: MPPDO6 is ignored,1: MPPDO6 is written" newline bitfld.long 0x34 21. "MASK5,Mask Field 5" "0: MPPDO5 is ignored,1: MPPDO5 is written" newline bitfld.long 0x34 20. "MASK4,Mask Field 4" "0: MPPDO4 is ignored,1: MPPDO4 is written" newline bitfld.long 0x34 19. "MASK3,Mask Field 3" "0: MPPDO3 is ignored,1: MPPDO3 is written" newline bitfld.long 0x34 18. "MASK2,Mask Field 2" "0: MPPDO2 is ignored,1: MPPDO2 is written" newline bitfld.long 0x34 17. "MASK1,Mask Field 1" "0: MPPDO1 is ignored,1: MPPDO1 is written" newline bitfld.long 0x34 16. "MASK0,Mask Field 0" "0: MPPDO0 is ignored,1: MPPDO0 is written" newline bitfld.long 0x34 15. "MPPDO15,Masked Parallel Pad Data Out 15" "0,1" newline bitfld.long 0x34 14. "MPPDO14,Masked Parallel Pad Data Out 14" "0,1" newline bitfld.long 0x34 13. "MPPDO13,Masked Parallel Pad Data Out 13" "0,1" newline bitfld.long 0x34 12. "MPPDO12,Masked Parallel Pad Data Out 12" "0,1" newline bitfld.long 0x34 11. "MPPDO11,Masked Parallel Pad Data Out 11" "0,1" newline bitfld.long 0x34 10. "MPPDO10,Masked Parallel Pad Data Out 10" "0,1" newline bitfld.long 0x34 9. "MPPDO9,Masked Parallel Pad Data Out 9" "0,1" newline bitfld.long 0x34 8. "MPPDO8,Masked Parallel Pad Data Out 8" "0,1" newline bitfld.long 0x34 7. "MPPDO7,Masked Parallel Pad Data Out 7" "0,1" newline bitfld.long 0x34 6. "MPPDO6,Masked Parallel Pad Data Out 6" "0,1" newline bitfld.long 0x34 5. "MPPDO5,Masked Parallel Pad Data Out 5" "0,1" newline bitfld.long 0x34 4. "MPPDO4,Masked Parallel Pad Data Out 4" "0,1" newline bitfld.long 0x34 3. "MPPDO3,Masked Parallel Pad Data Out 3" "0,1" newline bitfld.long 0x34 2. "MPPDO2,Masked Parallel Pad Data Out 2" "0,1" newline bitfld.long 0x34 1. "MPPDO1,Masked Parallel Pad Data Out 1" "0,1" newline bitfld.long 0x34 0. "MPPDO0,Masked Parallel Pad Data Out 0" "0,1" line.long 0x38 "MPGPDO14,SIUL2 Masked Parallel GPIO Pad Data Out" bitfld.long 0x38 31. "MASK15,Mask Field 15" "0: MPPDO15 is ignored,1: MPPDO15 is written" newline bitfld.long 0x38 30. "MASK14,Mask Field 14" "0: MPPDO14 is ignored,1: MPPDO14 is written" newline bitfld.long 0x38 29. "MASK13,Mask Field 13" "0: MPPDO13 is ignored,1: MPPDO13 is written" newline bitfld.long 0x38 28. "MASK12,Mask Field 12" "0: MPPDO12 is ignored,1: MPPDO12 is written" newline bitfld.long 0x38 27. "MASK11,Mask Field 11" "0: MPPDO11 is ignored,1: MPPDO11 is written" newline bitfld.long 0x38 26. "MASK10,Mask Field 10" "0: MPPDO10 is ignored,1: MPPDO10 is written" newline bitfld.long 0x38 25. "MASK9,Mask Field 9" "0: MPPDO9 is ignored,1: MPPDO9 is written" newline bitfld.long 0x38 24. "MASK8,Mask Field 8" "0: MPPDO8 is ignored,1: MPPDO8 is written" newline bitfld.long 0x38 23. "MASK7,Mask Field 7" "0: MPPDO7 is ignored,1: MPPDO7 is written" newline bitfld.long 0x38 22. "MASK6,Mask Field 6" "0: MPPDO6 is ignored,1: MPPDO6 is written" newline bitfld.long 0x38 21. "MASK5,Mask Field 5" "0: MPPDO5 is ignored,1: MPPDO5 is written" newline bitfld.long 0x38 20. "MASK4,Mask Field 4" "0: MPPDO4 is ignored,1: MPPDO4 is written" newline bitfld.long 0x38 19. "MASK3,Mask Field 3" "0: MPPDO3 is ignored,1: MPPDO3 is written" newline bitfld.long 0x38 15. "MPPDO15,Masked Parallel Pad Data Out 15" "0,1" newline bitfld.long 0x38 14. "MPPDO14,Masked Parallel Pad Data Out 14" "0,1" newline bitfld.long 0x38 13. "MPPDO13,Masked Parallel Pad Data Out 13" "0,1" newline bitfld.long 0x38 12. "MPPDO12,Masked Parallel Pad Data Out 12" "0,1" newline bitfld.long 0x38 11. "MPPDO11,Masked Parallel Pad Data Out 11" "0,1" newline bitfld.long 0x38 10. "MPPDO10,Masked Parallel Pad Data Out 10" "0,1" newline bitfld.long 0x38 9. "MPPDO9,Masked Parallel Pad Data Out 9" "0,1" newline bitfld.long 0x38 8. "MPPDO8,Masked Parallel Pad Data Out 8" "0,1" newline bitfld.long 0x38 7. "MPPDO7,Masked Parallel Pad Data Out 7" "0,1" newline bitfld.long 0x38 6. "MPPDO6,Masked Parallel Pad Data Out 6" "0,1" newline bitfld.long 0x38 5. "MPPDO5,Masked Parallel Pad Data Out 5" "0,1" newline bitfld.long 0x38 4. "MPPDO4,Masked Parallel Pad Data Out 4" "0,1" newline bitfld.long 0x38 3. "MPPDO3,Masked Parallel Pad Data Out 3" "0,1" tree.end tree "STCU (Self-Test Control Unit)" base ad:0x403A0000 group.long 0x4++0x3 line.long 0x0 "RUNSW,STCU2 Run Software" bitfld.long 0x0 9. "MBSWPLLEN,Online MBIST with PLL Enabled" "0: Online MBIST is executed without using the..,1: Online MBIST is executed using the PLL.." bitfld.long 0x0 8. "LBSWPLLEN,Online LBIST with PLL Enabled" "0: Online LBIST is executed without using the..,1: Online LBIST is executed using the PLL.." newline bitfld.long 0x0 0. "RUNSW,The RUNSW bit is automatically cleared by STCU2 when the online self-testing procedure is complete." "0: Idle,1: Online self-testing procedure is running" wgroup.long 0x8++0x3 line.long 0x0 "SKC,STCU2 SK Code" hexmask.long 0x0 0.--31. 1. "SKC,STCU2 SK Code" group.long 0xC++0x3 line.long 0x0 "CFG,STCU2 Configuration" hexmask.long.word 0x0 21.--30. 1. "PTR,First LBIST or MBIST pointer PTR defines the logical pointer to the first LBIST or MBIST to be scheduled when the self-testing procedure is enabled" hexmask.long.byte 0x0 13.--20. 1. "LB_DELAY,Delay LBIST run LB_DELAY defines the delay between the LBIST starts when more than a single LBIST is selected to be executed concurrently with the purpose of smoothing the power consumption transient" newline bitfld.long 0x0 8. "WRP,Write Protection 0: Specific STCU2 registers can be written through IPS bus interface 1: STCU2 registers cannot be written through IPS preventing any user application write operation" "0: Specific STCU2 registers can be written through..,1: STCU2 registers cannot be written through IPS" bitfld.long 0x0 0.--2. "CLK_CFG,Logic Memory BIST and STCU2 CORE_CLK configuration CLK_CFG defines the ratio between the sys_clk and the internal clock used to program both the LBIST and the MBIST and the STCU2 CORE_CLK" "0: sys_clk/1,1: sys_clk/2,2: sys_clk/3,3: sys_clk/4,4: sys_clk/5,5: sys_clk/6,6: sys_clk/7,7: sys_clk/8" group.long 0x14++0x3 line.long 0x0 "WDG,STCU2 Watchdog Granularity" hexmask.long 0x0 0.--31. 1. "WDGEOC,Watchdog End of Count Timer This value has to be set to define the time budget related to the online self-test execution and check that everything is correctly working within this slot of time" group.long 0x24++0x7 line.long 0x0 "ERR_STAT,STCU2 Error" rbitfld.long 0x0 20. "LOCKESW,Online LOCK error You can always read this field" "0: In case PLL is enabled it is correctly locked..,1: When the PLL is enabled this flag highlights.." rbitfld.long 0x0 19. "WDTOSW,Online watchdog timeout You can always read this field" "0: LBIST and MBIST time slots completed within the..,1: LBIST and MBIST time slots not completed within.." newline rbitfld.long 0x0 17. "ENGESW,Online engine error You can always read this field" "0: Valid engine execution,1: Invalid engine execution. The error conditions.." rbitfld.long 0x0 16. "INVPSW,Online invalid pointer You can always read this field" "0: Valid linked pointer list,1: Invalid linked pointer list. The following.." newline bitfld.long 0x0 9. "UFSF,Unrecoverable Faults Status Flag This flag reports the global status of the Unrecoverable Faults(UF)" "0: No errors that trigger the UF condition.,1: There are errors that trigger the UF condition." bitfld.long 0x0 8. "RFSF,Recoverable Faults Status Flag This flag reports the global status of the Recoverable Fault (RF)" "0: No errors that trigger the Recoverable Faults..,1: There are errors that trigger the Recoverable.." line.long 0x4 "ERR_FM,STCU2 Error FM" bitfld.long 0x4 4. "LOCKEUFM,PLL LOCK Unrecoverable Fault Mapping" "0: Recoverable Fault Mapping,1: Unrecoverable Fault Mapping" bitfld.long 0x4 3. "WDTOUFM,Watchdog Timeout Unrecoverable Fault Mapping" "0: Recoverable Fault Mapping,1: Unrecoverable Fault Mapping" newline bitfld.long 0x4 1. "ENGEUFM,Engine Error Unrecoverable Fault Mapping" "0: Recoverable Fault Mapping,1: Unrecoverable Fault Mapping" bitfld.long 0x4 0. "INVPUFM,Invalid Pointer Unrecoverable Fault Mapping" "0: Recoverable Fault Mapping,1: Unrecoverable Mapping" rgroup.long 0x4C++0x3 line.long 0x0 "LBSSW0,STCU2 Online LBIST Status" bitfld.long 0x0 0. "LBSSW0,LBSSW0" "0: Failed LBIST execution,1: Successful LBIST execution" rgroup.long 0x5C++0x3 line.long 0x0 "LBESW0,STCU2 Online LBIST End Flag" bitfld.long 0x0 0. "LBESW0,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished" group.long 0x7C++0x3 line.long 0x0 "LBUFM0,STCU2 Online LBIST Unrecoverable FM" bitfld.long 0x0 0. "LBUFM0,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping" rgroup.long 0x10C++0x3 line.long 0x0 "MBSSW0,STCU2 Online MBIST Status" bitfld.long 0x0 17. "MBSSW17,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x0 16. "MBSSW16,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x0 15. "MBSSW15,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x0 14. "MBSSW14,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x0 13. "MBSSW13,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x0 12. "MBSSW12,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x0 11. "MBSSW11,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x0 10. "MBSSW10,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x0 9. "MBSSW9,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x0 8. "MBSSW8,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x0 7. "MBSSW7,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x0 6. "MBSSW6,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x0 5. "MBSSW5,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x0 4. "MBSSW4,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x0 3. "MBSSW3,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x0 2. "MBSSW2,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" newline bitfld.long 0x0 1. "MBSSW1,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" bitfld.long 0x0 0. "MBSSW0,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution" rgroup.long 0x14C++0x3 line.long 0x0 "MBESW0,STCU2 Online MBIST End Flag" bitfld.long 0x0 17. "MBESW17,Online end status of MBISTn (where n = 17:0)." "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x0 16. "MBESW16,Online end status of MBISTn (where n = 17:0)." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 15. "MBESW15,Online end status of MBISTn (where n = 17:0)." "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x0 14. "MBESW14,Online end status of MBISTn (where n = 17:0)." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 13. "MBESW13,Online end status of MBISTn (where n = 17:0)." "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x0 12. "MBESW12,Online end status of MBISTn (where n = 17:0)." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 11. "MBESW11,Online end status of MBISTn (where n = 17:0)." "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x0 10. "MBESW10,Online end status of MBISTn (where n = 17:0)." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 9. "MBESW9,Online end status of MBISTn (where n = 17:0)." "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x0 8. "MBESW8,Online end status of MBISTn (where n = 17:0)." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 7. "MBESW7,Online end status of MBISTn (where n = 17:0)." "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x0 6. "MBESW6,Online end status of MBISTn (where n = 17:0)." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 5. "MBESW5,Online end status of MBISTn (where n = 17:0)." "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x0 4. "MBESW4,Online end status of MBISTn (where n = 17:0)." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 3. "MBESW3,Online end status of MBISTn (where n = 17:0)." "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x0 2. "MBESW2,Online end status of MBISTn (where n = 17:0)." "0: MBIST execution still ongoing,1: MBIST execution finished" newline bitfld.long 0x0 1. "MBESW1,Online end status of MBISTn (where n = 17:0)." "0: MBIST execution still ongoing,1: MBIST execution finished" bitfld.long 0x0 0. "MBESW0,Online end status of MBISTn (where n = 17:0)." "0: MBIST execution still ongoing,1: MBIST execution finished" group.long 0x18C++0x3 line.long 0x0 "MBUFM0,STCU2 MBIST Unrecoverable FM" bitfld.long 0x0 17. "MBUFM17,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x0 16. "MBUFM16,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 15. "MBUFM15,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x0 14. "MBUFM14,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 13. "MBUFM13,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x0 12. "MBUFM12,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 11. "MBUFM11,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x0 10. "MBUFM10,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 9. "MBUFM9,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x0 8. "MBUFM8,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 7. "MBUFM7,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x0 6. "MBUFM6,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 5. "MBUFM5,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x0 4. "MBUFM4,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 3. "MBUFM3,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x0 2. "MBUFM2,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" newline bitfld.long 0x0 1. "MBUFM1,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" bitfld.long 0x0 0. "MBUFM0,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping" group.long 0x200++0x7 line.long 0x0 "LB_CTRL0,STCU2 LBIST Control" bitfld.long 0x0 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1; otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x0 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled" newline bitfld.long 0x0 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock).,1: Shift at 1/2 rate (BIST clock).,2: Shift at 1/3 rate (BIST clock).,3: Shift at 1/4 rate (BIST clock).,4: Shift at 1/5 rate (BIST clock).,5: Shift at 1/6 rate (BIST clock).,6: Shift at 1/7 rate (BIST clock).,7: Shift at 1/8 rate (BIST clock)." hexmask.long.byte 0x0 12.--15. 1. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" newline hexmask.long.byte 0x0 8.--11. 1. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" hexmask.long.byte 0x0 0.--5. 1. "CWS,Capture window size CWS defines the capture window size." line.long 0x4 "LB_PCS0,STCU2 LBIST PC Stop" hexmask.long 0x4 0.--25. 1. "PCS,PCS" group.long 0x220++0x7 line.long 0x0 "LB_MISRELSW0,STCU2 Online LBIST MISR Expected Low" hexmask.long 0x0 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR." line.long 0x4 "LB_MISREHSW0,STCU2 Online LBIST MISR Expected High" hexmask.long 0x4 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR." rgroup.long 0x228++0x7 line.long 0x0 "LB_MISRRLSW0,STCU2 Online LBIST MISR Read Low" hexmask.long 0x0 0.--31. 1. "MISRRSWx,MISRRSWx" line.long 0x4 "LB_MISRRHSW0,STCU2 Online LBIST MISR Read High" hexmask.long 0x4 0.--31. 1. "MISRRSWx,MISRRSWx" group.long 0x2200++0x3 line.long 0x0 "ALGOSEL,STCU2 Algorithm Select" bitfld.long 0x0 31. "ALGOSEL31,Algorithm Select" "0,1" bitfld.long 0x0 30. "ALGOSEL30,Algorithm Select" "0,1" newline bitfld.long 0x0 29. "ALGOSEL29,Algorithm Select" "0,1" bitfld.long 0x0 28. "ALGOSEL28,Algorithm Select" "0,1" newline bitfld.long 0x0 27. "ALGOSEL27,Algorithm Select" "0,1" bitfld.long 0x0 26. "ALGOSEL26,Algorithm Select" "0,1" newline bitfld.long 0x0 25. "ALGOSEL25,Algorithm Select" "0,1" bitfld.long 0x0 24. "ALGOSEL24,Algorithm Select" "0,1" newline bitfld.long 0x0 23. "ALGOSEL23,Algorithm Select" "0,1" bitfld.long 0x0 22. "ALGOSEL22,Algorithm Select" "0,1" newline bitfld.long 0x0 21. "ALGOSEL21,Algorithm Select" "0,1" bitfld.long 0x0 20. "ALGOSEL20,Algorithm Select" "0,1" newline bitfld.long 0x0 19. "ALGOSEL19,Algorithm Select" "0,1" bitfld.long 0x0 18. "ALGOSEL18,Algorithm Select" "0,1" newline bitfld.long 0x0 17. "ALGOSEL17,Algorithm Select" "0,1" bitfld.long 0x0 16. "ALGOSEL16,Algorithm Select" "0,1" newline bitfld.long 0x0 15. "ALGOSEL15,Algorithm Select" "0,1" bitfld.long 0x0 14. "ALGOSEL14,Algorithm Select" "0,1" newline bitfld.long 0x0 13. "ALGOSEL13,Algorithm Select" "0,1" bitfld.long 0x0 12. "ALGOSEL12,Algorithm Select" "0,1" newline bitfld.long 0x0 11. "ALGOSEL11,Algorithm Select" "0,1" bitfld.long 0x0 10. "ALGOSEL10,Algorithm Select" "0,1" newline bitfld.long 0x0 9. "ALGOSEL9,Algorithm Select" "0,1" bitfld.long 0x0 8. "ALGOSEL8,Algorithm Select" "0,1" newline bitfld.long 0x0 7. "ALGOSEL7,Algorithm Select" "0,1" bitfld.long 0x0 6. "ALGOSEL6,Algorithm Select" "0,1" newline bitfld.long 0x0 5. "ALGOSEL5,Algorithm Select" "0,1" bitfld.long 0x0 4. "ALGOSEL4,Algorithm Select" "0,1" newline bitfld.long 0x0 3. "ALGOSEL3,Algorithm Select" "0,1" bitfld.long 0x0 2. "ALGOSEL2,Algorithm Select" "0,1" newline bitfld.long 0x0 1. "ALGOSEL1,Algorithm Select" "0,1" bitfld.long 0x0 0. "ALGOSEL0,Algorithm Select" "0,1" group.long 0x220C++0x4F line.long 0x0 "STGGR,STCU2 MBIST Stagger" hexmask.long 0x0 0.--31. 1. "STAG,STAG" line.long 0x4 "BSTART,STCU2 BIST Start" bitfld.long 0x4 31. "BSTART31,BIST Start" "0,1" bitfld.long 0x4 30. "BSTART30,BIST Start" "0,1" newline bitfld.long 0x4 29. "BSTART29,BIST Start" "0,1" bitfld.long 0x4 28. "BSTART28,BIST Start" "0,1" newline bitfld.long 0x4 27. "BSTART27,BIST Start" "0,1" bitfld.long 0x4 26. "BSTART26,BIST Start" "0,1" newline bitfld.long 0x4 25. "BSTART25,BIST Start" "0,1" bitfld.long 0x4 24. "BSTART24,BIST Start" "0,1" newline bitfld.long 0x4 23. "BSTART23,BIST Start" "0,1" bitfld.long 0x4 22. "BSTART22,BIST Start" "0,1" newline bitfld.long 0x4 21. "BSTART21,BIST Start" "0,1" bitfld.long 0x4 20. "BSTART20,BIST Start" "0,1" newline bitfld.long 0x4 19. "BSTART19,BIST Start" "0,1" bitfld.long 0x4 18. "BSTART18,BIST Start" "0,1" newline bitfld.long 0x4 17. "BSTART17,BIST Start" "0,1" bitfld.long 0x4 16. "BSTART16,BIST Start" "0,1" newline bitfld.long 0x4 15. "BSTART15,BIST Start" "0,1" bitfld.long 0x4 14. "BSTART14,BIST Start" "0,1" newline bitfld.long 0x4 13. "BSTART13,BIST Start" "0,1" bitfld.long 0x4 12. "BSTART12,BIST Start" "0,1" newline bitfld.long 0x4 11. "BSTART11,BIST Start" "0,1" bitfld.long 0x4 10. "BSTART10,BIST Start" "0,1" newline bitfld.long 0x4 9. "BSTART9,BIST Start" "0,1" bitfld.long 0x4 8. "BSTART8,BIST Start" "0,1" newline bitfld.long 0x4 7. "BSTART7,BIST Start" "0,1" bitfld.long 0x4 6. "BSTART6,BIST Start" "0,1" newline bitfld.long 0x4 5. "BSTART5,BIST Start" "0,1" bitfld.long 0x4 4. "BSTART4,BIST Start" "0,1" newline bitfld.long 0x4 3. "BSTART3,BIST Start" "0,1" bitfld.long 0x4 2. "BSTART2,BIST Start" "0,1" newline bitfld.long 0x4 1. "BSTART1,BIST Start" "0,1" bitfld.long 0x4 0. "BSTART0,BIST Start" "0,1" line.long 0x8 "MB_CTRL0,STCU2 MBIST Control" bitfld.long 0x8 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x8 21.--30. 1. "PTR,PTR" newline bitfld.long 0x8 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0xC "MB_CTRL1,STCU2 MBIST Control" bitfld.long 0xC 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0xC 21.--30. 1. "PTR,PTR" newline bitfld.long 0xC 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x10 "MB_CTRL2,STCU2 MBIST Control" bitfld.long 0x10 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x10 21.--30. 1. "PTR,PTR" newline bitfld.long 0x10 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x14 "MB_CTRL3,STCU2 MBIST Control" bitfld.long 0x14 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x14 21.--30. 1. "PTR,PTR" newline bitfld.long 0x14 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x18 "MB_CTRL4,STCU2 MBIST Control" bitfld.long 0x18 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x18 21.--30. 1. "PTR,PTR" newline bitfld.long 0x18 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x1C "MB_CTRL5,STCU2 MBIST Control" bitfld.long 0x1C 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x1C 21.--30. 1. "PTR,PTR" newline bitfld.long 0x1C 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x20 "MB_CTRL6,STCU2 MBIST Control" bitfld.long 0x20 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x20 21.--30. 1. "PTR,PTR" newline bitfld.long 0x20 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x24 "MB_CTRL7,STCU2 MBIST Control" bitfld.long 0x24 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x24 21.--30. 1. "PTR,PTR" newline bitfld.long 0x24 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x28 "MB_CTRL8,STCU2 MBIST Control" bitfld.long 0x28 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x28 21.--30. 1. "PTR,PTR" newline bitfld.long 0x28 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x2C "MB_CTRL9,STCU2 MBIST Control" bitfld.long 0x2C 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x2C 21.--30. 1. "PTR,PTR" newline bitfld.long 0x2C 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x30 "MB_CTRL10,STCU2 MBIST Control" bitfld.long 0x30 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x30 21.--30. 1. "PTR,PTR" newline bitfld.long 0x30 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x34 "MB_CTRL11,STCU2 MBIST Control" bitfld.long 0x34 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x34 21.--30. 1. "PTR,PTR" newline bitfld.long 0x34 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x38 "MB_CTRL12,STCU2 MBIST Control" bitfld.long 0x38 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x38 21.--30. 1. "PTR,PTR" newline bitfld.long 0x38 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x3C "MB_CTRL13,STCU2 MBIST Control" bitfld.long 0x3C 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x3C 21.--30. 1. "PTR,PTR" newline bitfld.long 0x3C 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x40 "MB_CTRL14,STCU2 MBIST Control" bitfld.long 0x40 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x40 21.--30. 1. "PTR,PTR" newline bitfld.long 0x40 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x44 "MB_CTRL15,STCU2 MBIST Control" bitfld.long 0x44 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x44 21.--30. 1. "PTR,PTR" newline bitfld.long 0x44 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x48 "MB_CTRL16,STCU2 MBIST Control" bitfld.long 0x48 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x48 21.--30. 1. "PTR,PTR" newline bitfld.long 0x48 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." line.long 0x4C "MB_CTRL17,STCU2 MBIST Control" bitfld.long 0x4C 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode" hexmask.long.word 0x4C 21.--30. 1. "PTR,PTR" newline bitfld.long 0x4C 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution.,1: Selected BIST is selected for execution." tree.end tree "STM (System Timer Module)" base ad:0x0 tree "STM_0" base ad:0x40274000 group.long 0x0++0x7 line.long 0x0 "CR,Control" hexmask.long.byte 0x0 8.--15. 1. "CPS,Counter Prescaler" bitfld.long 0x0 1. "FRZ,Freeze" "0: Timer runs in Debug mode,1: Timer stops in Debug mode" bitfld.long 0x0 0. "TEN,Timer Enable" "0: Disabled,1: Enabled" line.long 0x4 "CNT,Count" hexmask.long 0x4 0.--31. 1. "CNT,Timer Count" repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x40274010 ad:0x40274020 ad:0x40274030 ad:0x40274040) tree "CHANNEL[$1]" base $2 group.long ($2)++0xB line.long 0x0 "CCR,Channel Control" bitfld.long 0x0 0. "CEN,Channel Enable" "0: Disabled,1: Enabled" line.long 0x4 "CIR,Channel Interrupt" eventfld.long 0x4 0. "CIF,Channel Interrupt Flag" "0: Read: IRQ is not asserted. Write: No effect.,1: Read: IRQ is asserted. Write: Clear the flag." line.long 0x8 "CMP,Channel Compare" hexmask.long 0x8 0.--31. 1. "CMP,Channel Compare" tree.end repeat.end tree.end tree "STM_1" base ad:0x40474000 group.long 0x0++0x7 line.long 0x0 "CR,Control" hexmask.long.byte 0x0 8.--15. 1. "CPS,Counter Prescaler" bitfld.long 0x0 1. "FRZ,Freeze" "0: Timer runs in Debug mode,1: Timer stops in Debug mode" bitfld.long 0x0 0. "TEN,Timer Enable" "0: Disabled,1: Enabled" line.long 0x4 "CNT,Count" hexmask.long 0x4 0.--31. 1. "CNT,Timer Count" repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x40474010 ad:0x40474020 ad:0x40474030 ad:0x40474040) tree "CHANNEL[$1]" base $2 group.long ($2)++0xB line.long 0x0 "CCR,Channel Control" bitfld.long 0x0 0. "CEN,Channel Enable" "0: Disabled,1: Enabled" line.long 0x4 "CIR,Channel Interrupt" eventfld.long 0x4 0. "CIF,Channel Interrupt Flag" "0: Read: IRQ is not asserted. Write: No effect.,1: Read: IRQ is asserted. Write: Clear the flag." line.long 0x8 "CMP,Channel Compare" hexmask.long 0x8 0.--31. 1. "CMP,Channel Compare" tree.end repeat.end tree.end tree "STM_2" base ad:0x40478000 group.long 0x0++0x7 line.long 0x0 "CR,Control" hexmask.long.byte 0x0 8.--15. 1. "CPS,Counter Prescaler" bitfld.long 0x0 1. "FRZ,Freeze" "0: Timer runs in Debug mode,1: Timer stops in Debug mode" bitfld.long 0x0 0. "TEN,Timer Enable" "0: Disabled,1: Enabled" line.long 0x4 "CNT,Count" hexmask.long 0x4 0.--31. 1. "CNT,Timer Count" repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x40478010 ad:0x40478020 ad:0x40478030 ad:0x40478040) tree "CHANNEL[$1]" base $2 group.long ($2)++0xB line.long 0x0 "CCR,Channel Control" bitfld.long 0x0 0. "CEN,Channel Enable" "0: Disabled,1: Enabled" line.long 0x4 "CIR,Channel Interrupt" eventfld.long 0x4 0. "CIF,Channel Interrupt Flag" "0: Read: IRQ is not asserted. Write: No effect.,1: Read: IRQ is asserted. Write: Clear the flag." line.long 0x8 "CMP,Channel Compare" hexmask.long 0x8 0.--31. 1. "CMP,Channel Compare" tree.end repeat.end tree.end tree "STM_3" base ad:0x4047C000 group.long 0x0++0x7 line.long 0x0 "CR,Control" hexmask.long.byte 0x0 8.--15. 1. "CPS,Counter Prescaler" bitfld.long 0x0 1. "FRZ,Freeze" "0: Timer runs in Debug mode,1: Timer stops in Debug mode" bitfld.long 0x0 0. "TEN,Timer Enable" "0: Disabled,1: Enabled" line.long 0x4 "CNT,Count" hexmask.long 0x4 0.--31. 1. "CNT,Timer Count" repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x4047C010 ad:0x4047C020 ad:0x4047C030 ad:0x4047C040) tree "CHANNEL[$1]" base $2 group.long ($2)++0xB line.long 0x0 "CCR,Channel Control" bitfld.long 0x0 0. "CEN,Channel Enable" "0: Disabled,1: Enabled" line.long 0x4 "CIR,Channel Interrupt" eventfld.long 0x4 0. "CIF,Channel Interrupt Flag" "0: Read: IRQ is not asserted. Write: No effect.,1: Read: IRQ is asserted. Write: Clear the flag." line.long 0x8 "CMP,Channel Compare" hexmask.long 0x8 0.--31. 1. "CMP,Channel Compare" tree.end repeat.end tree.end tree.end tree "SWT (Software Watchdog Timer)" base ad:0x0 tree "SWT_0" base ad:0x40270000 group.long 0x0++0x13 line.long 0x0 "CR,Control" bitfld.long 0x0 31. "MAP0,Master Access Protection 0" "0: Access disabled,1: Access enabled" bitfld.long 0x0 30. "MAP1,Master Access Protection 1" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 29. "MAP2,Master Access Protection 2" "0: Access disabled,1: Access enabled" bitfld.long 0x0 28. "MAP3,Master Access Protection 3" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 27. "MAP4,Master Access Protection 4" "0: Access disabled,1: Access enabled" bitfld.long 0x0 26. "MAP5,Master Access Protection 5" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 25. "MAP6,Master Access Protection 6" "0: Access disabled,1: Access enabled" bitfld.long 0x0 24. "MAP7,Master Access Protection 7" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 9.--10. "SMD,Service Mode" "0: Fixed Service Sequence,1: Keyed Service Sequence,?,?" bitfld.long 0x0 8. "RIA,Reset on Invalid Access" "0: Generate a bus error,1: Generate a bus error and reset request" newline bitfld.long 0x0 7. "WND,Window Mode" "0: Regular mode,1: Window mode" bitfld.long 0x0 6. "ITR,Interrupt Then Reset Request" "0: Generate a reset request on a timeout,1: Generate an interrupt on an initial timeout;.." newline bitfld.long 0x0 5. "HLK,Hard Lock" "0: CR TO WN and SK are read/write registers if SLK..,1: CR TO WN and SK are read-only registers" bitfld.long 0x0 4. "SLK,Soft Lock" "0: CR TO WN and SK are read/write registers if HLK..,1: CR TO WN and SK are read-only registers" newline bitfld.long 0x0 1. "FRZ,Debug Mode Control" "0: Timer continues,1: Timer stops" bitfld.long 0x0 0. "WEN,Watchdog Enable" "0: Disabled,1: Enabled" line.long 0x4 "IR,Interrupt" eventfld.long 0x4 0. "TIF,Timeout Interrupt Flag" "0: No interrupt request,1: Interrupt request due to an initial timeout" line.long 0x8 "TO,Timeout" hexmask.long 0x8 0.--31. 1. "WTO,Watchdog Timeout" line.long 0xC "WN,Window" hexmask.long 0xC 0.--31. 1. "WST,Window Start Value" line.long 0x10 "SR,Service" hexmask.long.word 0x10 0.--15. 1. "WSC,Watchdog Service Code" rgroup.long 0x14++0x3 line.long 0x0 "CO,Counter Output" hexmask.long 0x0 0.--31. 1. "CNT,Watchdog Count" group.long 0x18++0x7 line.long 0x0 "SK,Service Key" hexmask.long.word 0x0 0.--15. 1. "SK,Service Key" line.long 0x4 "RRR,Event Request" eventfld.long 0x4 0. "RRF,Reset Request Flag" "0: No reset request,1: Any reset request initiated" tree.end tree "SWT_1" base ad:0x4046C000 group.long 0x0++0x13 line.long 0x0 "CR,Control" bitfld.long 0x0 31. "MAP0,Master Access Protection 0" "0: Access disabled,1: Access enabled" bitfld.long 0x0 30. "MAP1,Master Access Protection 1" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 29. "MAP2,Master Access Protection 2" "0: Access disabled,1: Access enabled" bitfld.long 0x0 28. "MAP3,Master Access Protection 3" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 27. "MAP4,Master Access Protection 4" "0: Access disabled,1: Access enabled" bitfld.long 0x0 26. "MAP5,Master Access Protection 5" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 25. "MAP6,Master Access Protection 6" "0: Access disabled,1: Access enabled" bitfld.long 0x0 24. "MAP7,Master Access Protection 7" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 9.--10. "SMD,Service Mode" "0: Fixed Service Sequence,1: Keyed Service Sequence,?,?" bitfld.long 0x0 8. "RIA,Reset on Invalid Access" "0: Generate a bus error,1: Generate a bus error and reset request" newline bitfld.long 0x0 7. "WND,Window Mode" "0: Regular mode,1: Window mode" bitfld.long 0x0 6. "ITR,Interrupt Then Reset Request" "0: Generate a reset request on a timeout,1: Generate an interrupt on an initial timeout;.." newline bitfld.long 0x0 5. "HLK,Hard Lock" "0: CR TO WN and SK are read/write registers if SLK..,1: CR TO WN and SK are read-only registers" bitfld.long 0x0 4. "SLK,Soft Lock" "0: CR TO WN and SK are read/write registers if HLK..,1: CR TO WN and SK are read-only registers" newline bitfld.long 0x0 1. "FRZ,Debug Mode Control" "0: Timer continues,1: Timer stops" bitfld.long 0x0 0. "WEN,Watchdog Enable" "0: Disabled,1: Enabled" line.long 0x4 "IR,Interrupt" eventfld.long 0x4 0. "TIF,Timeout Interrupt Flag" "0: No interrupt request,1: Interrupt request due to an initial timeout" line.long 0x8 "TO,Timeout" hexmask.long 0x8 0.--31. 1. "WTO,Watchdog Timeout" line.long 0xC "WN,Window" hexmask.long 0xC 0.--31. 1. "WST,Window Start Value" line.long 0x10 "SR,Service" hexmask.long.word 0x10 0.--15. 1. "WSC,Watchdog Service Code" rgroup.long 0x14++0x3 line.long 0x0 "CO,Counter Output" hexmask.long 0x0 0.--31. 1. "CNT,Watchdog Count" group.long 0x18++0x7 line.long 0x0 "SK,Service Key" hexmask.long.word 0x0 0.--15. 1. "SK,Service Key" line.long 0x4 "RRR,Event Request" eventfld.long 0x4 0. "RRF,Reset Request Flag" "0: No reset request,1: Any reset request initiated" tree.end tree "SWT_2" base ad:0x40470000 group.long 0x0++0x13 line.long 0x0 "CR,Control" bitfld.long 0x0 31. "MAP0,Master Access Protection 0" "0: Access disabled,1: Access enabled" bitfld.long 0x0 30. "MAP1,Master Access Protection 1" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 29. "MAP2,Master Access Protection 2" "0: Access disabled,1: Access enabled" bitfld.long 0x0 28. "MAP3,Master Access Protection 3" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 27. "MAP4,Master Access Protection 4" "0: Access disabled,1: Access enabled" bitfld.long 0x0 26. "MAP5,Master Access Protection 5" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 25. "MAP6,Master Access Protection 6" "0: Access disabled,1: Access enabled" bitfld.long 0x0 24. "MAP7,Master Access Protection 7" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 9.--10. "SMD,Service Mode" "0: Fixed Service Sequence,1: Keyed Service Sequence,?,?" bitfld.long 0x0 8. "RIA,Reset on Invalid Access" "0: Generate a bus error,1: Generate a bus error and reset request" newline bitfld.long 0x0 7. "WND,Window Mode" "0: Regular mode,1: Window mode" bitfld.long 0x0 6. "ITR,Interrupt Then Reset Request" "0: Generate a reset request on a timeout,1: Generate an interrupt on an initial timeout;.." newline bitfld.long 0x0 5. "HLK,Hard Lock" "0: CR TO WN and SK are read/write registers if SLK..,1: CR TO WN and SK are read-only registers" bitfld.long 0x0 4. "SLK,Soft Lock" "0: CR TO WN and SK are read/write registers if HLK..,1: CR TO WN and SK are read-only registers" newline bitfld.long 0x0 1. "FRZ,Debug Mode Control" "0: Timer continues,1: Timer stops" bitfld.long 0x0 0. "WEN,Watchdog Enable" "0: Disabled,1: Enabled" line.long 0x4 "IR,Interrupt" eventfld.long 0x4 0. "TIF,Timeout Interrupt Flag" "0: No interrupt request,1: Interrupt request due to an initial timeout" line.long 0x8 "TO,Timeout" hexmask.long 0x8 0.--31. 1. "WTO,Watchdog Timeout" line.long 0xC "WN,Window" hexmask.long 0xC 0.--31. 1. "WST,Window Start Value" line.long 0x10 "SR,Service" hexmask.long.word 0x10 0.--15. 1. "WSC,Watchdog Service Code" rgroup.long 0x14++0x3 line.long 0x0 "CO,Counter Output" hexmask.long 0x0 0.--31. 1. "CNT,Watchdog Count" group.long 0x18++0x7 line.long 0x0 "SK,Service Key" hexmask.long.word 0x0 0.--15. 1. "SK,Service Key" line.long 0x4 "RRR,Event Request" eventfld.long 0x4 0. "RRF,Reset Request Flag" "0: No reset request,1: Any reset request initiated" tree.end tree "SWT_3" base ad:0x40070000 group.long 0x0++0x13 line.long 0x0 "CR,Control" bitfld.long 0x0 31. "MAP0,Master Access Protection 0" "0: Access disabled,1: Access enabled" bitfld.long 0x0 30. "MAP1,Master Access Protection 1" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 29. "MAP2,Master Access Protection 2" "0: Access disabled,1: Access enabled" bitfld.long 0x0 28. "MAP3,Master Access Protection 3" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 27. "MAP4,Master Access Protection 4" "0: Access disabled,1: Access enabled" bitfld.long 0x0 26. "MAP5,Master Access Protection 5" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 25. "MAP6,Master Access Protection 6" "0: Access disabled,1: Access enabled" bitfld.long 0x0 24. "MAP7,Master Access Protection 7" "0: Access disabled,1: Access enabled" newline bitfld.long 0x0 9.--10. "SMD,Service Mode" "0: Fixed Service Sequence,1: Keyed Service Sequence,?,?" bitfld.long 0x0 8. "RIA,Reset on Invalid Access" "0: Generate a bus error,1: Generate a bus error and reset request" newline bitfld.long 0x0 7. "WND,Window Mode" "0: Regular mode,1: Window mode" bitfld.long 0x0 6. "ITR,Interrupt Then Reset Request" "0: Generate a reset request on a timeout,1: Generate an interrupt on an initial timeout;.." newline bitfld.long 0x0 5. "HLK,Hard Lock" "0: CR TO WN and SK are read/write registers if SLK..,1: CR TO WN and SK are read-only registers" bitfld.long 0x0 4. "SLK,Soft Lock" "0: CR TO WN and SK are read/write registers if HLK..,1: CR TO WN and SK are read-only registers" newline bitfld.long 0x0 1. "FRZ,Debug Mode Control" "0: Timer continues,1: Timer stops" bitfld.long 0x0 0. "WEN,Watchdog Enable" "0: Disabled,1: Enabled" line.long 0x4 "IR,Interrupt" eventfld.long 0x4 0. "TIF,Timeout Interrupt Flag" "0: No interrupt request,1: Interrupt request due to an initial timeout" line.long 0x8 "TO,Timeout" hexmask.long 0x8 0.--31. 1. "WTO,Watchdog Timeout" line.long 0xC "WN,Window" hexmask.long 0xC 0.--31. 1. "WST,Window Start Value" line.long 0x10 "SR,Service" hexmask.long.word 0x10 0.--15. 1. "WSC,Watchdog Service Code" rgroup.long 0x14++0x3 line.long 0x0 "CO,Counter Output" hexmask.long 0x0 0.--31. 1. "CNT,Watchdog Count" group.long 0x18++0x7 line.long 0x0 "SK,Service Key" hexmask.long.word 0x0 0.--15. 1. "SK,Service Key" line.long 0x4 "RRR,Event Request" eventfld.long 0x4 0. "RRF,Reset Request Flag" "0: No reset request,1: Any reset request initiated" tree.end tree.end tree "SXOSC (Slow Crystal Oscillator)" base ad:0x402CC000 group.long 0x0++0x3 line.long 0x0 "SXOSC_CTRL,Oscillator Control Register" bitfld.long 0x0 26.--27. "CURR_PRG_SF,These bits specify programmability of level shifter current." "0: 3x,1: 2x,2: 3.5x,3: 4x" bitfld.long 0x0 24.--25. "CURR_PRG_COMP,These bits specify programmability of comparator current." "0: 1x,1: 2x,2: 3x,3: 4x" hexmask.long.byte 0x0 16.--23. 1. "EOCV,End of count value" newline bitfld.long 0x0 6.--7. "GM_SEL,Crystal overdrive protection This field setting decides the trans-conductance applied by SXOSC amplifier and it will depend on crystal specification." "0: 1x,1: 1.25x,2: 1.3x,3: 1.6x" bitfld.long 0x0 0. "OSCON,Crystal oscillator power-down control" "0: Crystal oscillator is switched OFF,1: Crystal oscillator is switched ON" rgroup.long 0x4++0x3 line.long 0x0 "SXOSC_STAT,Oscillator Status Register" bitfld.long 0x0 31. "OSC_STAT,Crystal oscillator status" "0: Crystal oscillator output clock is not stable.,1: Crystal oscillator is providing a stable clock." tree.end tree "TEMPSENSE (Temperature Sensor)" base ad:0x4037C000 group.long 0x0++0x3 line.long 0x0 "ETSCTL,ETS Control" bitfld.long 0x0 1. "GNDSEL,Ground selection" "0: No exposure of the ground,1: Expose ground on the ADC output if ETS_EN=1" bitfld.long 0x0 0. "ETS_EN,Temperature Sensor enable" "0: Power down,1: Functional mode" rgroup.long 0x8++0xB line.long 0x0 "TCA0,Temperature Coefficient" hexmask.long.word 0x0 0.--15. 1. "TCA0,Temperature coefficient A0" line.long 0x4 "TCA1,Temperature Coefficient" hexmask.long.word 0x4 0.--15. 1. "TCA1,Temperature coefficient A1" line.long 0x8 "TCA2,Temperature Coefficient" hexmask.long.word 0x8 0.--15. 1. "TCA2,Temperature coefficient A2" tree.end tree "TRGMUX (Trigger MUX)" base ad:0x40080000 group.long 0x0++0x9F line.long 0x0 "ADC12_0,TRGMUX ADC12_0" bitfld.long 0x0 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x0 16.--22. 1. "SEL2,TRGMUX Source Select 2" hexmask.long.byte 0x0 8.--14. 1. "SEL1,TRGMUX Source Select 1" hexmask.long.byte 0x0 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0x4 "ADC12_1,TRGMUX ADC12_1" bitfld.long 0x4 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x4 16.--22. 1. "SEL2,TRGMUX Source Select 2" hexmask.long.byte 0x4 8.--14. 1. "SEL1,TRGMUX Source Select 1" hexmask.long.byte 0x4 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0x8 "ADC12_2,TRGMUX ADC12_2" bitfld.long 0x8 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x8 16.--22. 1. "SEL2,TRGMUX Source Select 2" hexmask.long.byte 0x8 8.--14. 1. "SEL1,TRGMUX Source Select 1" hexmask.long.byte 0x8 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0xC "LPCMP_0,TRGMUX LPCMP_0" bitfld.long 0xC 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0xC 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0x10 "LPCMP_1,TRGMUX LPCMP_1" bitfld.long 0x10 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x10 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0x14 "LPCMP_2,TRGMUX LPCMP_2" bitfld.long 0x14 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x14 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0x18 "BCTU,TRGMUX BCTU" bitfld.long 0x18 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x18 16.--22. 1. "SEL2,TRGMUX Source Select 2" hexmask.long.byte 0x18 8.--14. 1. "SEL1,TRGMUX Source Select 1" hexmask.long.byte 0x18 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0x1C "eMIOS012_ODIS,TRGMUX eMIOS012_ODIS" bitfld.long 0x1C 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x1C 24.--30. 1. "SEL3,TRGMUX Source Select 3" hexmask.long.byte 0x1C 16.--22. 1. "SEL2,TRGMUX Source Select 2" hexmask.long.byte 0x1C 8.--14. 1. "SEL1,TRGMUX Source Select 1" hexmask.long.byte 0x1C 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0x20 "eMIOS0_0,TRGMUX eMIOS0_0" bitfld.long 0x20 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x20 24.--30. 1. "SEL3,TRGMUX Source Select 3" hexmask.long.byte 0x20 16.--22. 1. "SEL2,TRGMUX Source Select 2" hexmask.long.byte 0x20 8.--14. 1. "SEL1,TRGMUX Source Select 1" hexmask.long.byte 0x20 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0x24 "eMIOS0_1,TRGMUX eMIOS0_1" bitfld.long 0x24 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x24 24.--30. 1. "SEL3,TRGMUX Source Select 3" hexmask.long.byte 0x24 16.--22. 1. "SEL2,TRGMUX Source Select 2" hexmask.long.byte 0x24 8.--14. 1. "SEL1,TRGMUX Source Select 1" hexmask.long.byte 0x24 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0x28 "eMIOS0_2,TRGMUX eMIOS0_2" bitfld.long 0x28 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x28 24.--30. 1. "SEL3,TRGMUX Source Select 3" hexmask.long.byte 0x28 16.--22. 1. "SEL2,TRGMUX Source Select 2" hexmask.long.byte 0x28 8.--14. 1. "SEL1,TRGMUX Source Select 1" hexmask.long.byte 0x28 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0x2C "eMIOS0_3,TRGMUX eMIOS0_3" bitfld.long 0x2C 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x2C 8.--14. 1. "SEL1,TRGMUX Source Select 1" hexmask.long.byte 0x2C 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0x30 "eMIOS1_0,TRGMUX eMIOS1_0" bitfld.long 0x30 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x30 24.--30. 1. "SEL3,TRGMUX Source Select 3" hexmask.long.byte 0x30 16.--22. 1. "SEL2,TRGMUX Source Select 2" hexmask.long.byte 0x30 8.--14. 1. "SEL1,TRGMUX Source Select 1" hexmask.long.byte 0x30 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0x34 "eMIOS1_1,TRGMUX eMIOS1_1" bitfld.long 0x34 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x34 24.--30. 1. "SEL3,TRGMUX Source Select 3" hexmask.long.byte 0x34 16.--22. 1. "SEL2,TRGMUX Source Select 2" hexmask.long.byte 0x34 8.--14. 1. "SEL1,TRGMUX Source Select 1" hexmask.long.byte 0x34 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0x38 "eMIOS1_2,TRGMUX eMIOS1_2" bitfld.long 0x38 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x38 24.--30. 1. "SEL3,TRGMUX Source Select 3" hexmask.long.byte 0x38 16.--22. 1. "SEL2,TRGMUX Source Select 2" hexmask.long.byte 0x38 8.--14. 1. "SEL1,TRGMUX Source Select 1" hexmask.long.byte 0x38 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0x3C "eMIOS1_3,TRGMUX eMIOS1_3" bitfld.long 0x3C 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x3C 8.--14. 1. "SEL1,TRGMUX Source Select 1" hexmask.long.byte 0x3C 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0x40 "FlexIO,TRGMUX FlexIO" bitfld.long 0x40 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x40 24.--30. 1. "SEL3,TRGMUX Source Select 3" hexmask.long.byte 0x40 16.--22. 1. "SEL2,TRGMUX Source Select 2" hexmask.long.byte 0x40 8.--14. 1. "SEL1,TRGMUX Source Select 1" hexmask.long.byte 0x40 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0x44 "SIUL_OUT0,TRGMUX SIUL_OUT0" bitfld.long 0x44 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x44 24.--30. 1. "SEL3,TRGMUX Source Select 3" hexmask.long.byte 0x44 16.--22. 1. "SEL2,TRGMUX Source Select 2" hexmask.long.byte 0x44 8.--14. 1. "SEL1,TRGMUX Source Select 1" hexmask.long.byte 0x44 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0x48 "SIUL_OUT1,TRGMUX SIUL_OUT1" bitfld.long 0x48 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x48 24.--30. 1. "SEL3,TRGMUX Source Select 3" hexmask.long.byte 0x48 16.--22. 1. "SEL2,TRGMUX Source Select 2" hexmask.long.byte 0x48 8.--14. 1. "SEL1,TRGMUX Source Select 1" hexmask.long.byte 0x48 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0x4C "SIUL_OUT2,TRGMUX SIUL_OUT2" bitfld.long 0x4C 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x4C 24.--30. 1. "SEL3,TRGMUX Source Select 3" hexmask.long.byte 0x4C 16.--22. 1. "SEL2,TRGMUX Source Select 2" hexmask.long.byte 0x4C 8.--14. 1. "SEL1,TRGMUX Source Select 1" hexmask.long.byte 0x4C 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0x50 "SIUL_OUT3,TRGMUX SIUL_OUT3" bitfld.long 0x50 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x50 24.--30. 1. "SEL3,TRGMUX Source Select 3" hexmask.long.byte 0x50 16.--22. 1. "SEL2,TRGMUX Source Select 2" hexmask.long.byte 0x50 8.--14. 1. "SEL1,TRGMUX Source Select 1" hexmask.long.byte 0x50 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0x54 "LPI2C_0,TRGMUX LPI2C_0" bitfld.long 0x54 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x54 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0x58 "LPSPI_0,TRGMUX LPSPI_0" bitfld.long 0x58 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x58 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0x5C "LPSPI_1,TRGMUX LPSPI_1" bitfld.long 0x5C 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x5C 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0x60 "LPSPI_2,TRGMUX LPSPI_2" bitfld.long 0x60 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x60 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0x64 "LPUART_0,TRGMUX LPUART_0" bitfld.long 0x64 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x64 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0x68 "LPUART_1,TRGMUX LPUART_1" bitfld.long 0x68 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x68 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0x6C "LPUART_2,TRGMUX LPUART_2" bitfld.long 0x6C 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x6C 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0x70 "LPUART_3,TRGMUX LPUART_3" bitfld.long 0x70 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x70 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0x74 "LCU0_SYNC,TRGMUX LCU0_SYNC" bitfld.long 0x74 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x74 8.--14. 1. "SEL1,TRGMUX Source Select 1" hexmask.long.byte 0x74 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0x78 "LCU0_FORCE,TRGMUX LCU0_FORCE" bitfld.long 0x78 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x78 16.--22. 1. "SEL2,TRGMUX Source Select 2" hexmask.long.byte 0x78 8.--14. 1. "SEL1,TRGMUX Source Select 1" hexmask.long.byte 0x78 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0x7C "LCU0_0,TRGMUX LCU0_0" bitfld.long 0x7C 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x7C 24.--30. 1. "SEL3,TRGMUX Source Select 3" hexmask.long.byte 0x7C 16.--22. 1. "SEL2,TRGMUX Source Select 2" hexmask.long.byte 0x7C 8.--14. 1. "SEL1,TRGMUX Source Select 1" hexmask.long.byte 0x7C 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0x80 "LCU0_1,TRGMUX LCU0_1" bitfld.long 0x80 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x80 24.--30. 1. "SEL3,TRGMUX Source Select 3" hexmask.long.byte 0x80 16.--22. 1. "SEL2,TRGMUX Source Select 2" hexmask.long.byte 0x80 8.--14. 1. "SEL1,TRGMUX Source Select 1" hexmask.long.byte 0x80 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0x84 "LCU0_2,TRGMUX LCU0_2" bitfld.long 0x84 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x84 24.--30. 1. "SEL3,TRGMUX Source Select 3" hexmask.long.byte 0x84 16.--22. 1. "SEL2,TRGMUX Source Select 2" hexmask.long.byte 0x84 8.--14. 1. "SEL1,TRGMUX Source Select 1" hexmask.long.byte 0x84 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0x88 "LCU1_SYNC,TRGMUX LCU1_SYNC" bitfld.long 0x88 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x88 8.--14. 1. "SEL1,TRGMUX Source Select 1" hexmask.long.byte 0x88 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0x8C "LCU1_FORCE,TRGMUX LCU1_FORCE" bitfld.long 0x8C 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x8C 16.--22. 1. "SEL2,TRGMUX Source Select 2" hexmask.long.byte 0x8C 8.--14. 1. "SEL1,TRGMUX Source Select 1" hexmask.long.byte 0x8C 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0x90 "LCU1_0,TRGMUX LCU1_0" bitfld.long 0x90 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x90 24.--30. 1. "SEL3,TRGMUX Source Select 3" hexmask.long.byte 0x90 16.--22. 1. "SEL2,TRGMUX Source Select 2" hexmask.long.byte 0x90 8.--14. 1. "SEL1,TRGMUX Source Select 1" hexmask.long.byte 0x90 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0x94 "LCU1_1,TRGMUX LCU1_1" bitfld.long 0x94 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x94 24.--30. 1. "SEL3,TRGMUX Source Select 3" hexmask.long.byte 0x94 16.--22. 1. "SEL2,TRGMUX Source Select 2" hexmask.long.byte 0x94 8.--14. 1. "SEL1,TRGMUX Source Select 1" hexmask.long.byte 0x94 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0x98 "LCU1_2,TRGMUX LCU1_2" bitfld.long 0x98 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x98 24.--30. 1. "SEL3,TRGMUX Source Select 3" hexmask.long.byte 0x98 16.--22. 1. "SEL2,TRGMUX Source Select 2" hexmask.long.byte 0x98 8.--14. 1. "SEL1,TRGMUX Source Select 1" hexmask.long.byte 0x98 0.--6. 1. "SEL0,TRGMUX Source Select 0" line.long 0x9C "CM7_RXEV,TRGMUX CM7_RXEV" bitfld.long 0x9C 31. "LK,TRGMUX Register Lock" "0: Register is writable,1: Register is not writable until the next system.." hexmask.long.byte 0x9C 24.--30. 1. "SEL3,TRGMUX Source Select 3" hexmask.long.byte 0x9C 16.--22. 1. "SEL2,TRGMUX Source Select 2" hexmask.long.byte 0x9C 8.--14. 1. "SEL1,TRGMUX Source Select 1" hexmask.long.byte 0x9C 0.--6. 1. "SEL0,TRGMUX Source Select 0" tree.end tree "TSPC" base ad:0x402C4000 group.long 0x0++0x3 line.long 0x0 "GRP_EN,Group Enable" bitfld.long 0x0 1. "GRP2_EN,Enable for GRP2_OBEn Register" "0: Disable,1: Enable" bitfld.long 0x0 0. "GRP1_EN,Enable for GRP1_OBEn Register" "0: Disable,1: Enable" group.long 0x50++0x7 line.long 0x0 "GRP1_OBE1,Group OBE" bitfld.long 0x0 31. "OBE31,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x0 30. "OBE30,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." newline bitfld.long 0x0 29. "OBE29,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x0 28. "OBE28,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." newline bitfld.long 0x0 27. "OBE27,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x0 26. "OBE26,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." newline bitfld.long 0x0 25. "OBE25,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x0 24. "OBE24,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." newline bitfld.long 0x0 23. "OBE23,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x0 22. "OBE22,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." newline bitfld.long 0x0 21. "OBE21,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x0 20. "OBE20,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." newline bitfld.long 0x0 19. "OBE19,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x0 18. "OBE18,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." newline bitfld.long 0x0 17. "OBE17,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x0 16. "OBE16,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." newline bitfld.long 0x0 15. "OBE15,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x0 14. "OBE14,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." newline bitfld.long 0x0 13. "OBE13,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x0 12. "OBE12,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." newline bitfld.long 0x0 11. "OBE11,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x0 10. "OBE10,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." newline bitfld.long 0x0 9. "OBE9,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x0 8. "OBE8,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." newline bitfld.long 0x0 7. "OBE7,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x0 6. "OBE6,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." newline bitfld.long 0x0 5. "OBE5,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x0 4. "OBE4,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." newline bitfld.long 0x0 3. "OBE3,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x0 2. "OBE2,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." newline bitfld.long 0x0 1. "OBE1,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x0 0. "OBE0,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." line.long 0x4 "GRP1_OBE2,Group OBE" bitfld.long 0x4 13. "OBE45,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x4 12. "OBE44,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." newline bitfld.long 0x4 11. "OBE43,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x4 10. "OBE42,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." newline bitfld.long 0x4 9. "OBE41,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x4 8. "OBE40,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." newline bitfld.long 0x4 7. "OBE39,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x4 6. "OBE38,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." newline bitfld.long 0x4 5. "OBE37,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x4 4. "OBE36,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." newline bitfld.long 0x4 3. "OBE35,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x4 2. "OBE34,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." newline bitfld.long 0x4 1. "OBE33,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x4 0. "OBE32,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." group.long 0xA0++0x7 line.long 0x0 "GRP2_OBE1,Group OBE" bitfld.long 0x0 31. "OBE31,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x0 30. "OBE30,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." newline bitfld.long 0x0 29. "OBE29,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x0 28. "OBE28,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." newline bitfld.long 0x0 27. "OBE27,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x0 26. "OBE26,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." newline bitfld.long 0x0 25. "OBE25,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x0 24. "OBE24,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." newline bitfld.long 0x0 23. "OBE23,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x0 22. "OBE22,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." newline bitfld.long 0x0 21. "OBE21,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x0 20. "OBE20,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." newline bitfld.long 0x0 19. "OBE19,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x0 18. "OBE18,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." newline bitfld.long 0x0 17. "OBE17,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x0 16. "OBE16,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." newline bitfld.long 0x0 15. "OBE15,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x0 14. "OBE14,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." newline bitfld.long 0x0 13. "OBE13,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x0 12. "OBE12,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." newline bitfld.long 0x0 11. "OBE11,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x0 10. "OBE10,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." newline bitfld.long 0x0 9. "OBE9,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x0 8. "OBE8,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." newline bitfld.long 0x0 7. "OBE7,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x0 6. "OBE6,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." newline bitfld.long 0x0 5. "OBE5,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x0 4. "OBE4,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." newline bitfld.long 0x0 3. "OBE3,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x0 2. "OBE2,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." newline bitfld.long 0x0 1. "OBE1,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x0 0. "OBE0,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." line.long 0x4 "GRP2_OBE2,Group OBE" bitfld.long 0x4 5. "OBE37,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x4 4. "OBE36,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." newline bitfld.long 0x4 3. "OBE35,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x4 2. "OBE34,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." newline bitfld.long 0x4 1. "OBE33,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." bitfld.long 0x4 0. "OBE32,Output Buffer Enable" "0: OBE pad does not transition if any OBE in group..,1: OBE pad transitions from high to low if any OBE.." tree.end tree "VIRT_WRAPPER (Virtualization Wrapper)" base ad:0x402A8000 group.long 0x0++0xEF line.long 0x0 "REG_A3_0,Parameter_n Register" bitfld.long 0x0 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x0 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x0 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x0 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x4 "REG_A7_4,Parameter_n Register" bitfld.long 0x4 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x4 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x4 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x4 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x8 "REG_A11_8,Parameter_n Register" bitfld.long 0x8 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x8 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x8 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x8 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0xC "REG_A15_12,Parameter_n Register" bitfld.long 0xC 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xC 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xC 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0xC 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x10 "REG_A19_16,Parameter_n Register" bitfld.long 0x10 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x10 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x10 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x10 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x14 "REG_A23_20,Parameter_n Register" bitfld.long 0x14 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x14 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x14 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x14 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x18 "REG_A27_24,Parameter_n Register" bitfld.long 0x18 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x18 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x18 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x18 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x1C "REG_A31_28,Parameter_n Register" bitfld.long 0x1C 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x1C 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x1C 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x1C 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x20 "REG_A35_32,Parameter_n Register" bitfld.long 0x20 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x20 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x20 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x20 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x24 "REG_A39_36,Parameter_n Register" bitfld.long 0x24 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x24 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x28 "REG_A43_40,Parameter_n Register" bitfld.long 0x28 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x28 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x28 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x28 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x2C "REG_A47_44,Parameter_n Register" bitfld.long 0x2C 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x2C 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x2C 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x2C 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x30 "REG_A51_48,Parameter_n Register" bitfld.long 0x30 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x30 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x30 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x30 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x34 "REG_A55_52,Parameter_n Register" bitfld.long 0x34 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x34 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x34 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x34 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x38 "REG_A59_56,Parameter_n Register" bitfld.long 0x38 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x38 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x38 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x38 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x3C "REG_A63_60,Parameter_n Register" bitfld.long 0x3C 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x3C 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x3C 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x3C 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x40 "REG_A67_64,Parameter_n Register" bitfld.long 0x40 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x40 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x40 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x40 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x44 "REG_A71_68,Parameter_n Register" bitfld.long 0x44 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x44 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x44 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x44 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x48 "REG_A75_72,Parameter_n Register" bitfld.long 0x48 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x48 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x48 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x48 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x4C "REG_A79_76,Parameter_n Register" bitfld.long 0x4C 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x4C 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x4C 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x4C 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x50 "REG_A83_80,Parameter_n Register" bitfld.long 0x50 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x50 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x50 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x50 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x54 "REG_A87_84,Parameter_n Register" bitfld.long 0x54 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x54 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x54 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x54 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x58 "REG_A91_88,Parameter_n Register" bitfld.long 0x58 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x58 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x58 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x58 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x5C "REG_A95_92,Parameter_n Register" bitfld.long 0x5C 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x5C 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x5C 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x5C 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x60 "REG_A99_96,Parameter_n Register" bitfld.long 0x60 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x60 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x60 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x60 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x64 "REG_A103_100,Parameter_n Register" bitfld.long 0x64 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x64 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x64 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x64 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x68 "REG_A107_104,Parameter_n Register" bitfld.long 0x68 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x68 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x68 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x68 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x6C "REG_A111_108,Parameter_n Register" bitfld.long 0x6C 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x6C 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x6C 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x6C 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x70 "REG_A115_112,Parameter_n Register" bitfld.long 0x70 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x70 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x70 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x70 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x74 "REG_A119_116,Parameter_n Register" bitfld.long 0x74 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x74 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x74 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x74 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x78 "REG_A123_120,Parameter_n Register" bitfld.long 0x78 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x78 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x78 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x78 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x7C "REG_A127_124,Parameter_n Register" bitfld.long 0x7C 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x7C 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x7C 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x7C 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x80 "REG_A131_128,Parameter_n Register" bitfld.long 0x80 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x80 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x80 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x80 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x84 "REG_A135_132,Parameter_n Register" bitfld.long 0x84 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x84 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x84 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x84 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x88 "REG_A139_136,Parameter_n Register" bitfld.long 0x88 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x88 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x88 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x88 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x8C "REG_A143_140,Parameter_n Register" bitfld.long 0x8C 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x8C 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x8C 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x90 "REG_A147_144,Parameter_n Register" bitfld.long 0x90 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x90 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x90 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x90 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x94 "REG_A151_148,Parameter_n Register" bitfld.long 0x94 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x94 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x94 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x94 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x98 "REG_A155_152,Parameter_n Register" bitfld.long 0x98 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x98 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x98 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x98 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x9C "REG_A159_156,Parameter_n Register" bitfld.long 0x9C 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x9C 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x9C 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x9C 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0xA0 "REG_A163_160,Parameter_n Register" bitfld.long 0xA0 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xA0 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xA0 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0xA0 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0xA4 "REG_A167_164,Parameter_n Register" bitfld.long 0xA4 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xA4 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xA4 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0xA4 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0xA8 "REG_A171_168,Parameter_n Register" bitfld.long 0xA8 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xA8 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xA8 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0xA8 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0xAC "REG_A175_172,Parameter_n Register" bitfld.long 0xAC 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xAC 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xAC 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0xAC 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0xB0 "REG_A179_176,Parameter_n Register" bitfld.long 0xB0 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xB0 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xB0 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0xB0 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0xB4 "REG_A183_180,Parameter_n Register" bitfld.long 0xB4 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xB4 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xB4 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0xB4 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0xB8 "REG_A187_184,Parameter_n Register" bitfld.long 0xB8 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xB8 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xB8 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0xB8 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0xBC "REG_A191_188,Parameter_n Register" bitfld.long 0xBC 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xBC 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xBC 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0xBC 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0xC0 "REG_A195_192,Parameter_n Register" bitfld.long 0xC0 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xC0 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xC0 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0xC0 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0xC4 "REG_A199_196,Parameter_n Register" bitfld.long 0xC4 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xC4 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xC4 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0xC4 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0xC8 "REG_A203_200,Parameter_n Register" bitfld.long 0xC8 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xC8 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xC8 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0xC8 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0xCC "REG_A207_204,Parameter_n Register" bitfld.long 0xCC 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xCC 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xCC 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0xCC 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0xD0 "REG_A211_208,Parameter_n Register" bitfld.long 0xD0 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xD0 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xD0 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0xD0 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0xD4 "REG_A215_212,Parameter_n Register" bitfld.long 0xD4 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xD4 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xD4 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0xD4 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0xD8 "REG_A219_216,Parameter_n Register" bitfld.long 0xD8 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xD8 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xD8 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0xD8 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0xDC "REG_A223_220,Parameter_n Register" bitfld.long 0xDC 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xDC 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xDC 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0xDC 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0xE0 "REG_A227_224,Parameter_n Register" bitfld.long 0xE0 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xE0 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xE0 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0xE0 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0xE4 "REG_A231_228,Parameter_n Register" bitfld.long 0xE4 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xE4 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xE4 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0xE4 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0xE8 "REG_A235_232,Parameter_n Register" bitfld.long 0xE8 24.--26. "PAD_3,PAD_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xE8 16.--18. "PAD_2,PAD_2" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xE8 8.--10. "PAD_1,PAD_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0xE8 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0xEC "REG_A239_236,Parameter_n Register" bitfld.long 0xEC 0.--2. "PAD_0,PAD_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" group.long 0x400++0x7 line.long 0x0 "REG_B3_0,Parameter_n Register" bitfld.long 0x0 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x0 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x0 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x4 "REG_B7_4,Parameter_n Register" bitfld.long 0x4 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x4 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" group.long 0x410++0x37 line.long 0x0 "REG_B19_16,Parameter_n Register" bitfld.long 0x0 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x0 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x0 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x4 "REG_B23_20,Parameter_n Register" bitfld.long 0x4 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x4 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x4 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x8 "REG_B27_24,Parameter_n Register" bitfld.long 0x8 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x8 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x8 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0xC "REG_B31_28,Parameter_n Register" bitfld.long 0xC 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xC 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0xC 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x10 "REG_B35_32,Parameter_n Register" bitfld.long 0x10 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x10 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x10 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x10 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x14 "REG_B39_36,Parameter_n Register" bitfld.long 0x14 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x14 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x14 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x14 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x18 "REG_B43_40,Parameter_n Register" bitfld.long 0x18 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x18 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x18 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x18 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x1C "REG_B47_44,Parameter_n Register" bitfld.long 0x1C 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x1C 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x1C 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x20 "REG_B51_48,Parameter_n Register" bitfld.long 0x20 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x20 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x20 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x20 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x24 "REG_B55_52,Parameter_n Register" bitfld.long 0x24 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x24 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x24 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x24 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x28 "REG_B59_56,Parameter_n Register" bitfld.long 0x28 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x28 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x28 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x28 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x2C "REG_B63_60,Parameter_n Register" bitfld.long 0x2C 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x2C 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x2C 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x2C 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x30 "REG_B67_64,Parameter_n Register" bitfld.long 0x30 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x30 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x30 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x30 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x34 "REG_B71_68,Parameter_n Register" bitfld.long 0x34 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x34 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x34 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x34 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" group.long 0x450++0x17 line.long 0x0 "REG_B83_80,Parameter_n Register" bitfld.long 0x0 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x0 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x0 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x4 "REG_B87_84,Parameter_n Register" bitfld.long 0x4 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x4 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x4 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x8 "REG_B91_88,Parameter_n Register" bitfld.long 0x8 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x8 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x8 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0xC "REG_B95_92,Parameter_n Register" bitfld.long 0xC 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xC 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0xC 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x10 "REG_B99_96,Parameter_n Register" bitfld.long 0x10 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x10 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x10 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x10 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x14 "REG_B103_100,Parameter_n Register" bitfld.long 0x14 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x14 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x14 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x14 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" group.long 0x470++0x17 line.long 0x0 "REG_B115_112,Parameter_n Register" bitfld.long 0x0 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x0 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x0 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x4 "REG_B119_116,Parameter_n Register" bitfld.long 0x4 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x4 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x4 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x8 "REG_B123_120,Parameter_n Register" bitfld.long 0x8 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x8 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x8 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0xC "REG_B127_124,Parameter_n Register" bitfld.long 0xC 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xC 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0xC 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x10 "REG_B131_128,Parameter_n Register" bitfld.long 0x10 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x10 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x10 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x10 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x14 "REG_B135_132,Parameter_n Register" bitfld.long 0x14 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x14 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x14 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x14 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" group.long 0x490++0x3B line.long 0x0 "REG_B147_144,Parameter_n Register" bitfld.long 0x0 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x0 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x0 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x4 "REG_B151_148,Parameter_n Register" bitfld.long 0x4 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x4 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x8 "REG_B155_152,Parameter_n Register" bitfld.long 0x8 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x8 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x8 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0xC "REG_B159_156,Parameter_n Register" bitfld.long 0xC 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xC 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0xC 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x10 "REG_B163_160,Parameter_n Register" bitfld.long 0x10 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x10 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x10 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x10 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x14 "REG_B167_164,Parameter_n Register" bitfld.long 0x14 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x14 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x14 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x14 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x18 "REG_B171_168,Parameter_n Register" bitfld.long 0x18 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x18 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x18 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x18 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x1C "REG_B175_172,Parameter_n Register" bitfld.long 0x1C 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x1C 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x1C 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x20 "REG_B179_176,Parameter_n Register" bitfld.long 0x20 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x20 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x20 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x20 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x24 "REG_B183_180,Parameter_n Register" bitfld.long 0x24 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x24 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x24 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x24 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x28 "REG_B187_184,Parameter_n Register" bitfld.long 0x28 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x28 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x28 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x28 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x2C "REG_B191_188,Parameter_n Register" bitfld.long 0x2C 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x2C 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x2C 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x2C 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x30 "REG_B195_192,Parameter_n Register" bitfld.long 0x30 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x30 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x30 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x30 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x34 "REG_B199_196,Parameter_n Register" bitfld.long 0x34 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x34 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x34 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x34 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x38 "REG_B203_200,Parameter_n Register" bitfld.long 0x38 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x38 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x38 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" group.long 0x4D0++0x3F line.long 0x0 "REG_B211_208,Parameter_n Register" bitfld.long 0x0 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x4 "REG_B215_212,Parameter_n Register" bitfld.long 0x4 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x4 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x4 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x8 "REG_B219_216,Parameter_n Register" bitfld.long 0x8 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x8 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x8 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0xC "REG_B223_220,Parameter_n Register" bitfld.long 0xC 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xC 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0xC 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x10 "REG_B227_224,Parameter_n Register" bitfld.long 0x10 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x10 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x10 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x10 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x14 "REG_B231_228,Parameter_n Register" bitfld.long 0x14 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x14 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x14 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x14 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x18 "REG_B235_232,Parameter_n Register" bitfld.long 0x18 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x18 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x18 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x18 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x1C "REG_B239_236,Parameter_n Register" bitfld.long 0x1C 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x1C 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x1C 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x20 "REG_B243_240,Parameter_n Register" bitfld.long 0x20 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x20 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x20 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x20 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x24 "REG_B247_244,Parameter_n Register" bitfld.long 0x24 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x24 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x24 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x24 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x28 "REG_B251_248,Parameter_n Register" bitfld.long 0x28 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x28 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x28 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x28 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x2C "REG_B255_252,Parameter_n Register" bitfld.long 0x2C 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x2C 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x2C 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x2C 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x30 "REG_B259_256,Parameter_n Register" bitfld.long 0x30 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x30 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x30 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x30 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x34 "REG_B263_260,Parameter_n Register" bitfld.long 0x34 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x34 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x34 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x34 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x38 "REG_B267_264,Parameter_n Register" bitfld.long 0x38 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x38 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x38 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x38 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x3C "REG_B271_268,Parameter_n Register" bitfld.long 0x3C 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" group.long 0x520++0x27 line.long 0x0 "REG_B291_288,Parameter_n Register" bitfld.long 0x0 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x0 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x4 "REG_B295_292,Parameter_n Register" bitfld.long 0x4 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x4 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x4 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x8 "REG_B299_296,Parameter_n Register" bitfld.long 0x8 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x8 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x8 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0xC "REG_B303_300,Parameter_n Register" bitfld.long 0xC 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xC 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0xC 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x10 "REG_B307_304,Parameter_n Register" bitfld.long 0x10 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x10 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x10 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x10 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x14 "REG_B311_308,Parameter_n Register" bitfld.long 0x14 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x14 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x18 "REG_B315_312,Parameter_n Register" bitfld.long 0x18 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x1C "REG_B319_316,Parameter_n Register" bitfld.long 0x1C 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x1C 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x1C 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x20 "REG_B323_320,Parameter_n Register" bitfld.long 0x20 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x20 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x20 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x20 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x24 "REG_B327_324,Parameter_n Register" bitfld.long 0x24 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x24 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" group.long 0x554++0x27 line.long 0x0 "REG_B343_340,Parameter_n Register" bitfld.long 0x0 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x4 "REG_B347_344,Parameter_n Register" bitfld.long 0x4 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x4 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x4 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x8 "REG_B351_348,Parameter_n Register" bitfld.long 0x8 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x8 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x8 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0xC "REG_B355_352,Parameter_n Register" bitfld.long 0xC 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xC 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0xC 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x10 "REG_B359_356,Parameter_n Register" bitfld.long 0x10 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x10 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x10 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x10 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x14 "REG_B363_360,Parameter_n Register" bitfld.long 0x14 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x14 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x14 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x14 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x18 "REG_B367_364,Parameter_n Register" bitfld.long 0x18 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x18 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x18 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x18 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x1C "REG_B371_368,Parameter_n Register" bitfld.long 0x1C 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x1C 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x20 "REG_B375_372,Parameter_n Register" bitfld.long 0x20 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x20 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x20 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x24 "REG_B379_376,Parameter_n Register" bitfld.long 0x24 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x24 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x24 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" group.long 0x584++0x3 line.long 0x0 "REG_B391_388,Parameter_n Register" bitfld.long 0x0 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" group.long 0x58C++0x3 line.long 0x0 "REG_B399_396,Parameter_n Register" bitfld.long 0x0 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x0 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" group.long 0x598++0xB line.long 0x0 "REG_B411_408,Parameter_n Register" bitfld.long 0x0 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x0 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x4 "REG_B415_412,Parameter_n Register" bitfld.long 0x4 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x4 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x4 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x8 "REG_B419_416,Parameter_n Register" bitfld.long 0x8 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x8 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" group.long 0x5B8++0x3 line.long 0x0 "REG_B443_440,Parameter_n Register" bitfld.long 0x0 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" group.long 0x5C0++0x17 line.long 0x0 "REG_B451_448,Parameter_n Register" bitfld.long 0x0 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x0 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x0 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x4 "REG_B455_452,Parameter_n Register" bitfld.long 0x4 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x4 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x4 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x8 "REG_B459_456,Parameter_n Register" bitfld.long 0x8 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x8 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x8 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0xC "REG_B463_460,Parameter_n Register" bitfld.long 0xC 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0xC 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0xC 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x10 "REG_B467_464,Parameter_n Register" bitfld.long 0x10 24.--26. "INMUX_3,INMUX_3" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x10 16.--18. "INMUX_2,no description available" "0,1,2,3,4,5,6,7" bitfld.long 0x10 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" newline bitfld.long 0x10 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" line.long 0x14 "REG_B471_468,Parameter_n Register" bitfld.long 0x14 8.--10. "INMUX_1,INMUX_1" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" bitfld.long 0x14 0.--2. "INMUX_0,INMUX_0" "0: SIUL2_VIRTWRAPPER_PDAC1,1: SIUL2_VIRTWRAPPER_PDAC2,2: SIUL2_VIRTWRAPPER_PDAC4,3: SIUL2_VIRTWRAPPER_PDAC5,?,?,?,7: SIUL2_VIRTWRAPPER_PDAC0" group.long 0x800++0x3 line.long 0x0 "REG_C,Parameter_n Register" bitfld.long 0x0 0.--2. "INTC_CTRL,Interrupt register control" "0,1,2,3,4,5,6,7" group.long 0xC00++0x3 line.long 0x0 "REG_D,Parameter_n Register" bitfld.long 0x0 0.--2. "REG_GCR,GCR Register Of REG_PROT" "0,1,2,3,4,5,6,7" tree.end tree "WKPU (Wakeup Unit)" base ad:0x402B4000 group.long 0x0++0x3 line.long 0x0 "NSR,NMI Status Flag Register" eventfld.long 0x0 31. "NIF0,NMI Status Flag 0" "0: No event has occurred on the pad,1: An event as defined by NREE0 and NFEE0 has.." eventfld.long 0x0 30. "NOVF0,NMI Overrun Status Flag 0" "0: No overrun has occurred on NMI input 0,1: An overrun has occurred on NMI input 0" newline eventfld.long 0x0 23. "NIF1,NMI Status Flag 1" "0: No event has occurred on the pad,1: An event as defined by NREE1 and NFEE1 has.." eventfld.long 0x0 22. "NOVF1,NMI Overrun Status Flag 1" "0: No overrun has occurred on NMI input 1,1: An overrun has occurred on NMI input 1" newline eventfld.long 0x0 15. "NIF2,NMI Status Flag 2" "0: No event has occurred on the pad,1: An event as defined by NREE2 and NFEE2 has.." eventfld.long 0x0 14. "NOVF2,NMI Overrun Status Flag 2" "0: No overrun has occurred on NMI input 2,1: An overrun has occurred on NMI input 2" newline eventfld.long 0x0 7. "NIF3,NMI Status Flag 3" "0: No event has occurred on the pad,1: An event as defined by NREE3 and NFEE3 has.." eventfld.long 0x0 6. "NOVF3,NMI Overrun Status Flag 3" "0: No overrun has occurred on NMI input 3,1: An overrun has occurred on NMI input 3" group.long 0x8++0x3 line.long 0x0 "NCR,NMI Configuration Register" bitfld.long 0x0 31. "NLOCK0,NMI Configuration Lock Register 0" "0,1" bitfld.long 0x0 29.--30. "NDSS0,NMI Destination Source Select 0" "0: Non-maskable interrupt,?,?,?" newline bitfld.long 0x0 28. "NWRE0,NMI Wakeup Request Enable 0" "0: System wakeup requests from the corresponding..,1: Causes a system wakeup request when NIF0 = 1 or.." bitfld.long 0x0 26. "NREE0,NMI Rising-Edge Events Enable 0" "0: Rising-edge event is disabled,1: Rising-edge event is enabled" newline bitfld.long 0x0 25. "NFEE0,NMI Falling-edge Events Enable 0" "0,1" bitfld.long 0x0 24. "NFE0,NMI Filter Enable 0" "0: Filter is disabled,1: Filter is enabled" newline bitfld.long 0x0 23. "NLOCK1,NMI Configuration Lock Register 1" "0,1" bitfld.long 0x0 21.--22. "NDSS1,NMI Destination Source Select 1" "0: Non-maskable interrupt,?,?,?" newline bitfld.long 0x0 20. "NWRE1,NMI Wakeup Request Enable 1" "0: System wakeup requests from the corresponding..,1: Causes a system wakeup request when NIF1 = 1 or.." bitfld.long 0x0 18. "NREE1,NMI Rising-Edge Events Enable 1" "0: Rising-edge event is disabled,1: Rising-edge event is enabled" newline bitfld.long 0x0 17. "NFEE1,NMI Falling-Edge Events Enable 1" "0,1" bitfld.long 0x0 16. "NFE1,NMI Filter Enable 1" "0: Filter is disabled,1: Filter is enabled" newline bitfld.long 0x0 15. "NLOCK2,NMI Configuration Lock Register 2" "0,1" bitfld.long 0x0 13.--14. "NDSS2,NMI Destination Source Select 2" "0: Non-maskable interrupt,?,?,?" newline bitfld.long 0x0 12. "NWRE2,NMI Wakeup Request Enable 2" "0: System wakeup requests from the corresponding..,1: Causes a system wakeup request when NIF2 = 1 or.." bitfld.long 0x0 10. "NREE2,NMI Rising-Edge Events Enable 2" "0: Rising-edge event is disabled,1: Rising-edge event is enabled" newline bitfld.long 0x0 9. "NFEE2,NMI Falling-Edge Events Enable 2" "0: Falling-edge event is disabled,1: Falling-edge event is enabled" bitfld.long 0x0 8. "NFE2,NMI Filter Enable 2" "0: Filter is disabled,1: Filter is enabled" newline bitfld.long 0x0 7. "NLOCK3_RLOCK,NMI Configuration Lock Register 3" "0,1" bitfld.long 0x0 5.--6. "NDSS3_RDSS,NMI Destination Source Select 3. ." "0: Non-maskable interrupt,?,?,?" newline bitfld.long 0x0 4. "NWRE3_RWRE,NMI Wakeup Request Enable 3" "0: System wakeup requests from the corresponding..,1: A set NIF3 bit or set NOVF3 bit causes a system.." bitfld.long 0x0 2. "NREE3_RREE,NMI Rising-Edge Events Enable 3." "0: Rising-edge event is disabled,1: Rising-edge event is enabled" newline bitfld.long 0x0 1. "NFEE3_RFEE,NMI Falling-Edge Events Enable 3" "0: Falling-edge event is disabled,1: Falling-edge event is enabled" bitfld.long 0x0 0. "NFE3,NMI Filter Enable 3" "0: Filter is disabled,1: Filter is enabled" group.long 0x14++0xB line.long 0x0 "WISR,Wakeup/Interrupt Status Flag Register" hexmask.long 0x0 0.--31. 1. "EIF,External Wakeup/Interrupt Status Flag x" line.long 0x4 "IRER,Interrupt Request Enable Register" hexmask.long 0x4 0.--31. 1. "EIRE,External Interrupt Request Enable x" line.long 0x8 "WRER,Wakeup Request Enable Register" hexmask.long 0x8 0.--31. 1. "WRE,External Wakeup Request Enable x" group.long 0x28++0xB line.long 0x0 "WIREER,Wakeup/Interrupt Rising-Edge Event Enable Register" hexmask.long 0x0 0.--31. 1. "IREE,External Interrupt Rising-edge Events Enable x" line.long 0x4 "WIFEER,Wakeup/Interrupt Falling-Edge Event Enable Register" hexmask.long 0x4 0.--31. 1. "IFEEx,External Interrupt Falling-edge Events Enable x" line.long 0x8 "WIFER,Wakeup/Interrupt Filter Enable Register" hexmask.long 0x8 0.--31. 1. "IFE,External Interrupt Filter Enable x" group.long 0x54++0xB line.long 0x0 "WISR_64,Wakeup/Interrupt Status Flag Register" hexmask.long 0x0 0.--31. 1. "EIF_1,External Wakeup/Interrupt Status Flag x" line.long 0x4 "IRER_64,Interrupt Request Enable Register" hexmask.long 0x4 0.--31. 1. "EIRE_1,External Interrupt Request Enable x" line.long 0x8 "WRER_64,Wakeup Request Enable Register" hexmask.long 0x8 0.--31. 1. "WRE_1,External Wakeup Request Enable x" group.long 0x68++0xB line.long 0x0 "WIREER_64,Wakeup/Interrupt Rising-Edge Event Enable Register" hexmask.long 0x0 0.--31. 1. "IREE_1,External Interrupt Rising-edge Events Enable x" line.long 0x4 "WIFEER_64,Wakeup/Interrupt Falling-Edge Event Enable Register" hexmask.long 0x4 0.--31. 1. "IFEEx_1,External Interrupt Falling-edge Events Enable x" line.long 0x8 "WIFER_64,Wakeup/Interrupt Filter Enable Register" hexmask.long 0x8 0.--31. 1. "IFE_1,External Interrupt Filter Enable x" tree.end tree "XBIC (Crossbar Integrity Checker)" base ad:0x0 tree "XBIC_AXBS" base ad:0x40204000 group.long 0x0++0xB line.long 0x0 "MCR,XBIC Module Control" bitfld.long 0x0 31. "SE0,Slave port EDC Error Detection Enable" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." bitfld.long 0x0 30. "SE1,Slave port EDC Error Detection Enable" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." newline bitfld.long 0x0 29. "SE2,Slave port EDC Error Detection Enable" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." bitfld.long 0x0 28. "SE3,Slave port EDC Error Detection Enable" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." newline bitfld.long 0x0 27. "SE4,Slave port EDC Error Detection Enable" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." bitfld.long 0x0 26. "SE5,Slave port EDC Error Detection Enable" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." newline bitfld.long 0x0 25. "SE6,Slave port EDC Error Detection Enable" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." bitfld.long 0x0 24. "SE7,Slave Port EDC Error Detection Enable" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." newline bitfld.long 0x0 23. "ME0,Master Port Enable For Feedback Integrity Check" "0: Feedback integrity checking disabled for master..,1: Feedback integrity checking enabled for master.." bitfld.long 0x0 22. "ME1,Master Port Enable For Feedback Integrity Check" "0: Feedback integrity checking disabled for master..,1: Feedback integrity checking enabled for master.." newline bitfld.long 0x0 21. "ME2,Master Port Enable For Feedback Integrity Check" "0: Feedback integrity checking disabled for master..,1: Feedback integrity checking enabled for master.." bitfld.long 0x0 20. "ME3,Master Port Enable For Feedback Integrity Check" "0: Feedback integrity checking disabled for master..,1: Feedback integrity checking enabled for master.." newline bitfld.long 0x0 19. "ME4,Master Port Enable For Feedback Integrity Check" "0: Feedback integrity checking disabled for master..,1: Feedback integrity checking enabled for master.." bitfld.long 0x0 18. "ME5,Master Port Enable For Feedback Integrity Check" "0: Feedback integrity checking disabled for master..,1: Feedback integrity checking enabled for master.." newline bitfld.long 0x0 17. "ME6,Master Port Enable For Feedback Integrity Check" "0: Feedback integrity checking disabled for master..,1: Feedback integrity checking enabled for master.." bitfld.long 0x0 16. "ME7,Master Port Enable For Feedback Integrity Check" "0: Feedback integrity checking disabled for master..,1: Feedback integrity checking enabled for master.." line.long 0x4 "EIR,XBIC Error Injection" bitfld.long 0x4 31. "EIE,Error Injection Enable" "0: Error injection disabled,1: Error injection enabled" bitfld.long 0x4 12.--14. "SLV,Target Slave Port" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--11. 1. "MST,Target Master ID" hexmask.long.byte 0x4 0.--7. 1. "SYN,Syndrome" line.long 0x8 "ESR,XBIC Error Status" eventfld.long 0x8 31. "VLD,Error Status Valid" "0: No error detected-other fields of the ESR and..,1: Error detected-all fields of the ESR and EAR.." rbitfld.long 0x8 30. "DPSE0,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 0" newline rbitfld.long 0x8 29. "DPSE1,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 1" rbitfld.long 0x8 28. "DPSE2,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 2" newline rbitfld.long 0x8 27. "DPSE3,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 3" rbitfld.long 0x8 26. "DPSE4,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 4" newline rbitfld.long 0x8 25. "DPSE5,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 5" rbitfld.long 0x8 24. "DPSE6,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 6" newline rbitfld.long 0x8 23. "DPSE7,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 7" rbitfld.long 0x8 22. "DPME0,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 0" newline rbitfld.long 0x8 21. "DPME1,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 1" rbitfld.long 0x8 20. "DPME2,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 2" newline rbitfld.long 0x8 19. "DPME3,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 3" rbitfld.long 0x8 18. "DPME4,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 4" newline rbitfld.long 0x8 17. "DPME5,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 5" rbitfld.long 0x8 16. "DPME6,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 6" newline rbitfld.long 0x8 15. "DPME7,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 7" rbitfld.long 0x8 12.--14. "SLV,Slave Port" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "MST,Master ID" hexmask.long.byte 0x8 0.--7. 1. "SYN,Syndrome" rgroup.long 0xC++0x3 line.long 0x0 "EAR,XBIC Error Address" hexmask.long 0x0 0.--31. 1. "ADDR,Error Address" tree.end tree "XBIC_AXBS_ACE" base ad:0x4040C000 group.long 0x0++0xB line.long 0x0 "MCR,XBIC Module Control" bitfld.long 0x0 31. "SE0,Slave port EDC Error Detection Enable" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." bitfld.long 0x0 23. "ME0,Master Port Enable For Feedback Integrity Check" "0: Feedback integrity checking disabled for master..,1: Feedback integrity checking enabled for master.." newline bitfld.long 0x0 22. "ME1,Master Port Enable For Feedback Integrity Check" "0: Feedback integrity checking disabled for master..,1: Feedback integrity checking enabled for master.." line.long 0x4 "EIR,XBIC Error Injection" bitfld.long 0x4 31. "EIE,Error Injection Enable" "0: Error injection disabled,1: Error injection enabled" bitfld.long 0x4 12.--14. "SLV,Target Slave Port" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--11. 1. "MST,Target Master ID" hexmask.long.byte 0x4 0.--7. 1. "SYN,Syndrome" line.long 0x8 "ESR,XBIC Error Status" eventfld.long 0x8 31. "VLD,Error Status Valid" "0: No error detected-other fields of the ESR and..,1: Error detected-all fields of the ESR and EAR.." rbitfld.long 0x8 30. "DPSE0,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 0" newline rbitfld.long 0x8 29. "DPSE1,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 1" rbitfld.long 0x8 28. "DPSE2,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 2" newline rbitfld.long 0x8 27. "DPSE3,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 3" rbitfld.long 0x8 26. "DPSE4,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 4" newline rbitfld.long 0x8 25. "DPSE5,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 5" rbitfld.long 0x8 24. "DPSE6,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 6" newline rbitfld.long 0x8 23. "DPSE7,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 7" rbitfld.long 0x8 22. "DPME0,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 0" newline rbitfld.long 0x8 21. "DPME1,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 1" rbitfld.long 0x8 20. "DPME2,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 2" newline rbitfld.long 0x8 19. "DPME3,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 3" rbitfld.long 0x8 18. "DPME4,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 4" newline rbitfld.long 0x8 17. "DPME5,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 5" rbitfld.long 0x8 16. "DPME6,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 6" newline rbitfld.long 0x8 15. "DPME7,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 7" rbitfld.long 0x8 12.--14. "SLV,Slave Port" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "MST,Master ID" hexmask.long.byte 0x8 0.--7. 1. "SYN,Syndrome" rgroup.long 0xC++0x3 line.long 0x0 "EAR,XBIC Error Address" hexmask.long 0x0 0.--31. 1. "ADDR,Error Address" tree.end tree "XBIC_AXBS_ACE_HSE" base ad:0x40008000 group.long 0x0++0xB line.long 0x0 "MCR,XBIC Module Control" bitfld.long 0x0 31. "SE0,Slave port EDC Error Detection Enable" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." bitfld.long 0x0 30. "SE1,Slave port EDC Error Detection Enable" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." newline bitfld.long 0x0 23. "ME0,Master Port Enable For Feedback Integrity Check" "0: Feedback integrity checking disabled for master..,1: Feedback integrity checking enabled for master.." bitfld.long 0x0 22. "ME1,Master Port Enable For Feedback Integrity Check" "0: Feedback integrity checking disabled for master..,1: Feedback integrity checking enabled for master.." line.long 0x4 "EIR,XBIC Error Injection" bitfld.long 0x4 31. "EIE,Error Injection Enable" "0: Error injection disabled,1: Error injection enabled" bitfld.long 0x4 12.--14. "SLV,Target Slave Port" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--11. 1. "MST,Target Master ID" hexmask.long.byte 0x4 0.--7. 1. "SYN,Syndrome" line.long 0x8 "ESR,XBIC Error Status" eventfld.long 0x8 31. "VLD,Error Status Valid" "0: No error detected-other fields of the ESR and..,1: Error detected-all fields of the ESR and EAR.." rbitfld.long 0x8 30. "DPSE0,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 0" newline rbitfld.long 0x8 29. "DPSE1,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 1" rbitfld.long 0x8 28. "DPSE2,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 2" newline rbitfld.long 0x8 27. "DPSE3,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 3" rbitfld.long 0x8 26. "DPSE4,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 4" newline rbitfld.long 0x8 25. "DPSE5,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 5" rbitfld.long 0x8 24. "DPSE6,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 6" newline rbitfld.long 0x8 23. "DPSE7,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 7" rbitfld.long 0x8 22. "DPME0,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 0" newline rbitfld.long 0x8 21. "DPME1,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 1" rbitfld.long 0x8 20. "DPME2,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 2" newline rbitfld.long 0x8 19. "DPME3,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 3" rbitfld.long 0x8 18. "DPME4,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 4" newline rbitfld.long 0x8 17. "DPME5,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 5" rbitfld.long 0x8 16. "DPME6,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 6" newline rbitfld.long 0x8 15. "DPME7,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 7" rbitfld.long 0x8 12.--14. "SLV,Slave Port" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "MST,Master ID" hexmask.long.byte 0x8 0.--7. 1. "SYN,Syndrome" rgroup.long 0xC++0x3 line.long 0x0 "EAR,XBIC Error Address" hexmask.long 0x0 0.--31. 1. "ADDR,Error Address" tree.end tree "XBIC_AXBS_EDMA" base ad:0x40404000 group.long 0x0++0xB line.long 0x0 "MCR,XBIC Module Control" bitfld.long 0x0 31. "SE0,Slave port EDC Error Detection Enable" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." bitfld.long 0x0 30. "SE1,Slave port EDC Error Detection Enable" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." newline bitfld.long 0x0 23. "ME0,Master Port Enable For Feedback Integrity Check" "0: Feedback integrity checking disabled for master..,1: Feedback integrity checking enabled for master.." bitfld.long 0x0 22. "ME1,Master Port Enable For Feedback Integrity Check" "0: Feedback integrity checking disabled for master..,1: Feedback integrity checking enabled for master.." line.long 0x4 "EIR,XBIC Error Injection" bitfld.long 0x4 31. "EIE,Error Injection Enable" "0: Error injection disabled,1: Error injection enabled" bitfld.long 0x4 12.--14. "SLV,Target Slave Port" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--11. 1. "MST,Target Master ID" hexmask.long.byte 0x4 0.--7. 1. "SYN,Syndrome" line.long 0x8 "ESR,XBIC Error Status" eventfld.long 0x8 31. "VLD,Error Status Valid" "0: No error detected-other fields of the ESR and..,1: Error detected-all fields of the ESR and EAR.." rbitfld.long 0x8 30. "DPSE0,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 0" newline rbitfld.long 0x8 29. "DPSE1,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 1" rbitfld.long 0x8 28. "DPSE2,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 2" newline rbitfld.long 0x8 27. "DPSE3,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 3" rbitfld.long 0x8 26. "DPSE4,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 4" newline rbitfld.long 0x8 25. "DPSE5,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 5" rbitfld.long 0x8 24. "DPSE6,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 6" newline rbitfld.long 0x8 23. "DPSE7,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 7" rbitfld.long 0x8 22. "DPME0,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 0" newline rbitfld.long 0x8 21. "DPME1,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 1" rbitfld.long 0x8 20. "DPME2,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 2" newline rbitfld.long 0x8 19. "DPME3,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 3" rbitfld.long 0x8 18. "DPME4,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 4" newline rbitfld.long 0x8 17. "DPME5,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 5" rbitfld.long 0x8 16. "DPME6,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 6" newline rbitfld.long 0x8 15. "DPME7,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 7" rbitfld.long 0x8 12.--14. "SLV,Slave Port" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "MST,Master ID" hexmask.long.byte 0x8 0.--7. 1. "SYN,Syndrome" rgroup.long 0xC++0x3 line.long 0x0 "EAR,XBIC Error Address" hexmask.long 0x0 0.--31. 1. "ADDR,Error Address" tree.end tree "XBIC_AXBS_PERI" base ad:0x40208000 group.long 0x0++0xB line.long 0x0 "MCR,XBIC Module Control" bitfld.long 0x0 31. "SE0,Slave port EDC Error Detection Enable" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." bitfld.long 0x0 30. "SE1,Slave port EDC Error Detection Enable" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." newline bitfld.long 0x0 29. "SE2,Slave port EDC Error Detection Enable" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." bitfld.long 0x0 28. "SE3,Slave port EDC Error Detection Enable" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." newline bitfld.long 0x0 23. "ME0,Master Port Enable For Feedback Integrity Check" "0: Feedback integrity checking disabled for master..,1: Feedback integrity checking enabled for master.." bitfld.long 0x0 22. "ME1,Master Port Enable For Feedback Integrity Check" "0: Feedback integrity checking disabled for master..,1: Feedback integrity checking enabled for master.." newline bitfld.long 0x0 21. "ME2,Master Port Enable For Feedback Integrity Check" "0: Feedback integrity checking disabled for master..,1: Feedback integrity checking enabled for master.." bitfld.long 0x0 20. "ME3,Master Port Enable For Feedback Integrity Check" "0: Feedback integrity checking disabled for master..,1: Feedback integrity checking enabled for master.." newline bitfld.long 0x0 19. "ME4,Master Port Enable For Feedback Integrity Check" "0: Feedback integrity checking disabled for master..,1: Feedback integrity checking enabled for master.." bitfld.long 0x0 18. "ME5,Master Port Enable For Feedback Integrity Check" "0: Feedback integrity checking disabled for master..,1: Feedback integrity checking enabled for master.." line.long 0x4 "EIR,XBIC Error Injection" bitfld.long 0x4 31. "EIE,Error Injection Enable" "0: Error injection disabled,1: Error injection enabled" bitfld.long 0x4 12.--14. "SLV,Target Slave Port" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--11. 1. "MST,Target Master ID" hexmask.long.byte 0x4 0.--7. 1. "SYN,Syndrome" line.long 0x8 "ESR,XBIC Error Status" eventfld.long 0x8 31. "VLD,Error Status Valid" "0: No error detected-other fields of the ESR and..,1: Error detected-all fields of the ESR and EAR.." rbitfld.long 0x8 30. "DPSE0,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 0" newline rbitfld.long 0x8 29. "DPSE1,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 1" rbitfld.long 0x8 28. "DPSE2,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 2" newline rbitfld.long 0x8 27. "DPSE3,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 3" rbitfld.long 0x8 26. "DPSE4,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 4" newline rbitfld.long 0x8 25. "DPSE5,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 5" rbitfld.long 0x8 24. "DPSE6,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 6" newline rbitfld.long 0x8 23. "DPSE7,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 7" rbitfld.long 0x8 22. "DPME0,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 0" newline rbitfld.long 0x8 21. "DPME1,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 1" rbitfld.long 0x8 20. "DPME2,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 2" newline rbitfld.long 0x8 19. "DPME3,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 3" rbitfld.long 0x8 18. "DPME4,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 4" newline rbitfld.long 0x8 17. "DPME5,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 5" rbitfld.long 0x8 16. "DPME6,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 6" newline rbitfld.long 0x8 15. "DPME7,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 7" rbitfld.long 0x8 12.--14. "SLV,Slave Port" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "MST,Master ID" hexmask.long.byte 0x8 0.--7. 1. "SYN,Syndrome" rgroup.long 0xC++0x3 line.long 0x0 "EAR,XBIC Error Address" hexmask.long 0x0 0.--31. 1. "ADDR,Error Address" tree.end tree "XBIC_AXBS_PRAM_TCM" base ad:0x40408000 group.long 0x0++0xB line.long 0x0 "MCR,XBIC Module Control" bitfld.long 0x0 31. "SE0,Slave port EDC Error Detection Enable" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." bitfld.long 0x0 30. "SE1,Slave port EDC Error Detection Enable" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." newline bitfld.long 0x0 23. "ME0,Master Port Enable For Feedback Integrity Check" "0: Feedback integrity checking disabled for master..,1: Feedback integrity checking enabled for master.." line.long 0x4 "EIR,XBIC Error Injection" bitfld.long 0x4 31. "EIE,Error Injection Enable" "0: Error injection disabled,1: Error injection enabled" bitfld.long 0x4 12.--14. "SLV,Target Slave Port" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--11. 1. "MST,Target Master ID" hexmask.long.byte 0x4 0.--7. 1. "SYN,Syndrome" line.long 0x8 "ESR,XBIC Error Status" eventfld.long 0x8 31. "VLD,Error Status Valid" "0: No error detected-other fields of the ESR and..,1: Error detected-all fields of the ESR and EAR.." rbitfld.long 0x8 30. "DPSE0,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 0" newline rbitfld.long 0x8 29. "DPSE1,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 1" rbitfld.long 0x8 28. "DPSE2,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 2" newline rbitfld.long 0x8 27. "DPSE3,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 3" rbitfld.long 0x8 26. "DPSE4,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 4" newline rbitfld.long 0x8 25. "DPSE5,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 5" rbitfld.long 0x8 24. "DPSE6,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 6" newline rbitfld.long 0x8 23. "DPSE7,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 7" rbitfld.long 0x8 22. "DPME0,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 0" newline rbitfld.long 0x8 21. "DPME1,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 1" rbitfld.long 0x8 20. "DPME2,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 2" newline rbitfld.long 0x8 19. "DPME3,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 3" rbitfld.long 0x8 18. "DPME4,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 4" newline rbitfld.long 0x8 17. "DPME5,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 5" rbitfld.long 0x8 16. "DPME6,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 6" newline rbitfld.long 0x8 15. "DPME7,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 7" rbitfld.long 0x8 12.--14. "SLV,Slave Port" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "MST,Master ID" hexmask.long.byte 0x8 0.--7. 1. "SYN,Syndrome" rgroup.long 0xC++0x3 line.long 0x0 "EAR,XBIC Error Address" hexmask.long 0x0 0.--31. 1. "ADDR,Error Address" tree.end tree "XBIC_AXBS_TCM" base ad:0x40400000 group.long 0x0++0xB line.long 0x0 "MCR,XBIC Module Control" bitfld.long 0x0 31. "SE0,Slave port EDC Error Detection Enable" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." bitfld.long 0x0 30. "SE1,Slave port EDC Error Detection Enable" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." newline bitfld.long 0x0 29. "SE2,Slave port EDC Error Detection Enable" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." bitfld.long 0x0 28. "SE3,Slave port EDC Error Detection Enable" "0: Attribute integrity checking disabled for slave..,1: Attribute integrity checking enabled for slave.." newline bitfld.long 0x0 23. "ME0,Master Port Enable For Feedback Integrity Check" "0: Feedback integrity checking disabled for master..,1: Feedback integrity checking enabled for master.." line.long 0x4 "EIR,XBIC Error Injection" bitfld.long 0x4 31. "EIE,Error Injection Enable" "0: Error injection disabled,1: Error injection enabled" bitfld.long 0x4 12.--14. "SLV,Target Slave Port" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--11. 1. "MST,Target Master ID" hexmask.long.byte 0x4 0.--7. 1. "SYN,Syndrome" line.long 0x8 "ESR,XBIC Error Status" eventfld.long 0x8 31. "VLD,Error Status Valid" "0: No error detected-other fields of the ESR and..,1: Error detected-all fields of the ESR and EAR.." rbitfld.long 0x8 30. "DPSE0,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 0" newline rbitfld.long 0x8 29. "DPSE1,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 1" rbitfld.long 0x8 28. "DPSE2,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 2" newline rbitfld.long 0x8 27. "DPSE3,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 3" rbitfld.long 0x8 26. "DPSE4,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 4" newline rbitfld.long 0x8 25. "DPSE5,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 5" rbitfld.long 0x8 24. "DPSE6,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 6" newline rbitfld.long 0x8 23. "DPSE7,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave port 7" rbitfld.long 0x8 22. "DPME0,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 0" newline rbitfld.long 0x8 21. "DPME1,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 1" rbitfld.long 0x8 20. "DPME2,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 2" newline rbitfld.long 0x8 19. "DPME3,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 3" rbitfld.long 0x8 18. "DPME4,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 4" newline rbitfld.long 0x8 17. "DPME5,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 5" rbitfld.long 0x8 16. "DPME6,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 6" newline rbitfld.long 0x8 15. "DPME7,Data Phase Master Port Error" "0: No feedback integrity error detected on master..,1: Feedback integrity error detected on master port 7" rbitfld.long 0x8 12.--14. "SLV,Slave Port" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "MST,Master ID" hexmask.long.byte 0x8 0.--7. 1. "SYN,Syndrome" rgroup.long 0xC++0x3 line.long 0x0 "EAR,XBIC Error Address" hexmask.long 0x0 0.--31. 1. "ADDR,Error Address" tree.end tree.end tree "XRDC (Extended Resource Domain Controller)" base ad:0x40278000 group.long 0x0++0x3 line.long 0x0 "CR,Control" bitfld.long 0x0 30. "LK1,Lock" "0: Unlocked,1: Locks" rbitfld.long 0x0 8. "VAW,Virtualization Aware" "0: Not virtualization-aware,1: Virtualization-aware" newline rbitfld.long 0x0 7. "MRF,Memory Region Format" "?,1: SMPU family format" hexmask.long.byte 0x0 1.--4. 1. "HRL,Hardware Revision Level" newline bitfld.long 0x0 0. "GVLD,Global Valid (XRDC Global Enable/Disable)" "0: Disables,1: Enables" rgroup.long 0xF0++0xB line.long 0x0 "HWCFG0,Hardware Configuration 0" hexmask.long.byte 0x0 28.--31. 1. "MID,Module ID" hexmask.long.byte 0x0 24.--27. 1. "NPAC,Number Of PACs" newline hexmask.long.byte 0x0 16.--23. 1. "NMRC,Number of MRCs" hexmask.long.byte 0x0 8.--15. 1. "NMSTR,Number Of Bus Masters" newline hexmask.long.byte 0x0 0.--7. 1. "NDID,Number Of DIDs" line.long 0x4 "HWCFG1,Hardware Configuration 1" hexmask.long.byte 0x4 0.--3. 1. "DID,Domain Identifier" line.long 0x8 "HWCFG2,Hardware Configuration 2" bitfld.long 0x8 31. "PIDP31,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 30. "PIDP30,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 29. "PIDP29,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 28. "PIDP28,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 27. "PIDP27,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 26. "PIDP26,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 25. "PIDP25,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 24. "PIDP24,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 23. "PIDP23,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 22. "PIDP22,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 21. "PIDP21,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 20. "PIDP20,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 19. "PIDP19,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 18. "PIDP18,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 17. "PIDP17,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 16. "PIDP16,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 15. "PIDP15,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 14. "PIDP14,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 13. "PIDP13,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 12. "PIDP12,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 11. "PIDP11,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 10. "PIDP10,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 9. "PIDP9,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 8. "PIDP8,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 7. "PIDP7,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 6. "PIDP6,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 5. "PIDP5,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 4. "PIDP4,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 3. "PIDP3,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 2. "PIDP2,Process Identifier Present" "0: Does not have PID register,1: Has PID register" newline bitfld.long 0x8 1. "PIDP1,Process Identifier Present" "0: Does not have PID register,1: Has PID register" bitfld.long 0x8 0. "PIDP0,Process Identifier Present" "0: Does not have PID register,1: Has PID register" rgroup.byte 0x100++0x9 line.byte 0x0 "MDACFG0,Master Domain Assignment Configuration" bitfld.byte 0x0 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master" hexmask.byte 0x0 0.--3. 1. "NMDAR,Number Of Master Domain Assignment Registers" line.byte 0x1 "MDACFG1,Master Domain Assignment Configuration" bitfld.byte 0x1 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master" hexmask.byte 0x1 0.--3. 1. "NMDAR,Number Of Master Domain Assignment Registers" line.byte 0x2 "MDACFG2,Master Domain Assignment Configuration" bitfld.byte 0x2 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master" hexmask.byte 0x2 0.--3. 1. "NMDAR,Number Of Master Domain Assignment Registers" line.byte 0x3 "MDACFG3,Master Domain Assignment Configuration" bitfld.byte 0x3 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master" hexmask.byte 0x3 0.--3. 1. "NMDAR,Number Of Master Domain Assignment Registers" line.byte 0x4 "MDACFG4,Master Domain Assignment Configuration" bitfld.byte 0x4 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master" hexmask.byte 0x4 0.--3. 1. "NMDAR,Number Of Master Domain Assignment Registers" line.byte 0x5 "MDACFG5,Master Domain Assignment Configuration" bitfld.byte 0x5 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master" hexmask.byte 0x5 0.--3. 1. "NMDAR,Number Of Master Domain Assignment Registers" line.byte 0x6 "MDACFG6,Master Domain Assignment Configuration" bitfld.byte 0x6 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master" hexmask.byte 0x6 0.--3. 1. "NMDAR,Number Of Master Domain Assignment Registers" line.byte 0x7 "MDACFG7,Master Domain Assignment Configuration" bitfld.byte 0x7 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master" hexmask.byte 0x7 0.--3. 1. "NMDAR,Number Of Master Domain Assignment Registers" line.byte 0x8 "MDACFG8,Master Domain Assignment Configuration" bitfld.byte 0x8 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master" hexmask.byte 0x8 0.--3. 1. "NMDAR,Number Of Master Domain Assignment Registers" line.byte 0x9 "MDACFG9,Master Domain Assignment Configuration" bitfld.byte 0x9 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master" hexmask.byte 0x9 0.--3. 1. "NMDAR,Number Of Master Domain Assignment Registers" rgroup.byte 0x140++0x4 line.byte 0x0 "MRCFG0,Memory Region Configuration" hexmask.byte 0x0 0.--4. 1. "NMRGD,Number Of Memory Region Descriptors" line.byte 0x1 "MRCFG1,Memory Region Configuration" hexmask.byte 0x1 0.--4. 1. "NMRGD,Number Of Memory Region Descriptors" line.byte 0x2 "MRCFG2,Memory Region Configuration" hexmask.byte 0x2 0.--4. 1. "NMRGD,Number Of Memory Region Descriptors" line.byte 0x3 "MRCFG3,Memory Region Configuration" hexmask.byte 0x3 0.--4. 1. "NMRGD,Number Of Memory Region Descriptors" line.byte 0x4 "MRCFG4,Memory Region Configuration" hexmask.byte 0x4 0.--4. 1. "NMRGD,Number Of Memory Region Descriptors" repeat 5. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x200)++0x3 line.long 0x0 "DERRLOC[$1],Domain Error Location" hexmask.long.byte 0x0 16.--19. 1. "PACINST,PAC Instance" hexmask.long.word 0x0 0.--15. 1. "MRCINST,MRC Instance" repeat.end rgroup.long 0x400++0x7 line.long 0x0 "DERR_W0_0,Domain Error Word 0" hexmask.long 0x0 0.--31. 1. "EADDR,Error Address" line.long 0x4 "DERR_W1_0,Domain Error Word 1" bitfld.long 0x4 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected" bitfld.long 0x4 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 11. "ERW,Error Read Or Write" "0: Read access,1: Write access" bitfld.long 0x4 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch access,7: Nonsecure privileged mode data access" newline hexmask.long.byte 0x4 0.--3. 1. "EDID,Error Domain Identifier" group.long 0x40C++0x3 line.long 0x0 "DERR_W3_0,Domain Error Word 3" bitfld.long 0x0 30.--31. "RECR,Rearm Error Capture Registers" "0: No effect,1: Rearms error capture resets error capture..,2: No effect,3: No effect" rgroup.long 0x410++0x7 line.long 0x0 "DERR_W0_1,Domain Error Word 0" hexmask.long 0x0 0.--31. 1. "EADDR,Error Address" line.long 0x4 "DERR_W1_1,Domain Error Word 1" bitfld.long 0x4 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected" bitfld.long 0x4 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 11. "ERW,Error Read Or Write" "0: Read access,1: Write access" bitfld.long 0x4 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch access,7: Nonsecure privileged mode data access" newline hexmask.long.byte 0x4 0.--3. 1. "EDID,Error Domain Identifier" group.long 0x41C++0x3 line.long 0x0 "DERR_W3_1,Domain Error Word 3" bitfld.long 0x0 30.--31. "RECR,Rearm Error Capture Registers" "0: No effect,1: Rearms error capture resets error capture..,2: No effect,3: No effect" rgroup.long 0x420++0x7 line.long 0x0 "DERR_W0_2,Domain Error Word 0" hexmask.long 0x0 0.--31. 1. "EADDR,Error Address" line.long 0x4 "DERR_W1_2,Domain Error Word 1" bitfld.long 0x4 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected" bitfld.long 0x4 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 11. "ERW,Error Read Or Write" "0: Read access,1: Write access" bitfld.long 0x4 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch access,7: Nonsecure privileged mode data access" newline hexmask.long.byte 0x4 0.--3. 1. "EDID,Error Domain Identifier" group.long 0x42C++0x3 line.long 0x0 "DERR_W3_2,Domain Error Word 3" bitfld.long 0x0 30.--31. "RECR,Rearm Error Capture Registers" "0: No effect,1: Rearms error capture resets error capture..,2: No effect,3: No effect" rgroup.long 0x430++0x7 line.long 0x0 "DERR_W0_3,Domain Error Word 0" hexmask.long 0x0 0.--31. 1. "EADDR,Error Address" line.long 0x4 "DERR_W1_3,Domain Error Word 1" bitfld.long 0x4 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected" bitfld.long 0x4 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 11. "ERW,Error Read Or Write" "0: Read access,1: Write access" bitfld.long 0x4 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch access,7: Nonsecure privileged mode data access" newline hexmask.long.byte 0x4 0.--3. 1. "EDID,Error Domain Identifier" group.long 0x43C++0x3 line.long 0x0 "DERR_W3_3,Domain Error Word 3" bitfld.long 0x0 30.--31. "RECR,Rearm Error Capture Registers" "0: No effect,1: Rearms error capture resets error capture..,2: No effect,3: No effect" rgroup.long 0x440++0x7 line.long 0x0 "DERR_W0_4,Domain Error Word 0" hexmask.long 0x0 0.--31. 1. "EADDR,Error Address" line.long 0x4 "DERR_W1_4,Domain Error Word 1" bitfld.long 0x4 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected" bitfld.long 0x4 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 11. "ERW,Error Read Or Write" "0: Read access,1: Write access" bitfld.long 0x4 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch access,7: Nonsecure privileged mode data access" newline hexmask.long.byte 0x4 0.--3. 1. "EDID,Error Domain Identifier" group.long 0x44C++0x3 line.long 0x0 "DERR_W3_4,Domain Error Word 3" bitfld.long 0x0 30.--31. "RECR,Rearm Error Capture Registers" "0: No effect,1: Rearms error capture resets error capture..,2: No effect,3: No effect" rgroup.long 0x500++0x7 line.long 0x0 "DERR_W0_16,Domain Error Word 0" hexmask.long 0x0 0.--31. 1. "EADDR,Error Address" line.long 0x4 "DERR_W1_16,Domain Error Word 1" bitfld.long 0x4 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected" bitfld.long 0x4 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 11. "ERW,Error Read Or Write" "0: Read access,1: Write access" bitfld.long 0x4 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch access,7: Nonsecure privileged mode data access" newline hexmask.long.byte 0x4 0.--3. 1. "EDID,Error Domain Identifier" group.long 0x50C++0x3 line.long 0x0 "DERR_W3_16,Domain Error Word 3" bitfld.long 0x0 30.--31. "RECR,Rearm Error Capture Registers" "0: No effect,1: Rearms error capture resets error capture..,2: No effect,3: No effect" rgroup.long 0x510++0x7 line.long 0x0 "DERR_W0_17,Domain Error Word 0" hexmask.long 0x0 0.--31. 1. "EADDR,Error Address" line.long 0x4 "DERR_W1_17,Domain Error Word 1" bitfld.long 0x4 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected" bitfld.long 0x4 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 11. "ERW,Error Read Or Write" "0: Read access,1: Write access" bitfld.long 0x4 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch access,7: Nonsecure privileged mode data access" newline hexmask.long.byte 0x4 0.--3. 1. "EDID,Error Domain Identifier" group.long 0x51C++0x3 line.long 0x0 "DERR_W3_17,Domain Error Word 3" bitfld.long 0x0 30.--31. "RECR,Rearm Error Capture Registers" "0: No effect,1: Rearms error capture resets error capture..,2: No effect,3: No effect" rgroup.long 0x520++0x7 line.long 0x0 "DERR_W0_18,Domain Error Word 0" hexmask.long 0x0 0.--31. 1. "EADDR,Error Address" line.long 0x4 "DERR_W1_18,Domain Error Word 1" bitfld.long 0x4 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected" bitfld.long 0x4 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 11. "ERW,Error Read Or Write" "0: Read access,1: Write access" bitfld.long 0x4 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch access,7: Nonsecure privileged mode data access" newline hexmask.long.byte 0x4 0.--3. 1. "EDID,Error Domain Identifier" group.long 0x52C++0x3 line.long 0x0 "DERR_W3_18,Domain Error Word 3" bitfld.long 0x0 30.--31. "RECR,Rearm Error Capture Registers" "0: No effect,1: Rearms error capture resets error capture..,2: No effect,3: No effect" group.long 0x700++0x3 line.long 0x0 "PID0,Process Identifier" bitfld.long 0x0 29.--30. "LK2,Lock" "0: Any secure privileged write,1: Any secure privileged write,2: Secure privileged writes from master only,3: Locks" bitfld.long 0x0 28. "TSM,Three-State Model" "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "PID,Process Identifier" group.long 0x70C++0x7 line.long 0x0 "PID3,Process Identifier" bitfld.long 0x0 29.--30. "LK2,Lock" "0: Any secure privileged write,1: Any secure privileged write,2: Secure privileged writes from master only,3: Locks" bitfld.long 0x0 28. "TSM,Three-State Model" "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "PID,Process Identifier" line.long 0x4 "PID4,Process Identifier" bitfld.long 0x4 29.--30. "LK2,Lock" "0: Any secure privileged write,1: Any secure privileged write,2: Secure privileged writes from master only,3: Locks" bitfld.long 0x4 28. "TSM,Three-State Model" "0,1" newline hexmask.long.byte 0x4 0.--5. 1. "PID,Process Identifier" group.long 0x718++0x3 line.long 0x0 "PID6,Process Identifier" bitfld.long 0x0 29.--30. "LK2,Lock" "0: Any secure privileged write,1: Any secure privileged write,2: Secure privileged writes from master only,3: Locks" bitfld.long 0x0 28. "TSM,Three-State Model" "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "PID,Process Identifier" group.long 0x720++0x3 line.long 0x0 "PID8,Process Identifier" bitfld.long 0x0 29.--30. "LK2,Lock" "0: Any secure privileged write,1: Any secure privileged write,2: Secure privileged writes from master only,3: Locks" bitfld.long 0x0 28. "TSM,Three-State Model" "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "PID,Process Identifier" group.long 0x800++0x3 line.long 0x0 "MDA_W0_0_DFMT0,Master Domain Assignment" bitfld.long 0x0 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x0 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x0 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x0 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x0 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x0 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x0 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x0 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" group.long 0x820++0x3 line.long 0x0 "MDA_W0_1_DFMT1,Master Domain Assignment" bitfld.long 0x0 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x0 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x0 29. "DFMT,Domain Format" "?,1: Bus master domain assignment (DFMT1)" bitfld.long 0x0 8. "DIDB,DID Bypass" "0: Bypass DID input,1: Use DID input" newline bitfld.long 0x0 6.--7. "SA,Secure Attribute" "0: Use secure attribute from the master,1: Force to nonsecure,2: Use secure attribute from the master,3: Use secure attribute from the master" bitfld.long 0x0 4.--5. "PA,Privileged Attribute" "0: Use privileged attribute from the master,1: Force to privileged,2: Use privileged attribute from the master,3: Use privileged attribute from the master" newline bitfld.long 0x0 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" group.long 0x840++0x3 line.long 0x0 "MDA_W0_2_DFMT1,Master Domain Assignment" bitfld.long 0x0 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x0 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x0 29. "DFMT,Domain Format" "?,1: Bus master domain assignment (DFMT1)" bitfld.long 0x0 8. "DIDB,DID Bypass" "0: Bypass DID input,1: Use DID input" newline bitfld.long 0x0 6.--7. "SA,Secure Attribute" "0: Use secure attribute from the master,1: Force to nonsecure,2: Use secure attribute from the master,3: Use secure attribute from the master" bitfld.long 0x0 4.--5. "PA,Privileged Attribute" "0: Use privileged attribute from the master,1: Force to privileged,2: Use privileged attribute from the master,3: Use privileged attribute from the master" newline bitfld.long 0x0 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" group.long 0x860++0x3 line.long 0x0 "MDA_W0_3_DFMT0,Master Domain Assignment" bitfld.long 0x0 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x0 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x0 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x0 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x0 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x0 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x0 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x0 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" group.long 0x880++0x3 line.long 0x0 "MDA_W0_4_DFMT0,Master Domain Assignment" bitfld.long 0x0 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x0 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x0 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x0 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x0 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x0 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x0 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x0 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" group.long 0x8A0++0x3 line.long 0x0 "MDA_W0_5_DFMT1,Master Domain Assignment" bitfld.long 0x0 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x0 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x0 29. "DFMT,Domain Format" "?,1: Bus master domain assignment (DFMT1)" bitfld.long 0x0 8. "DIDB,DID Bypass" "0: Bypass DID input,1: Use DID input" newline bitfld.long 0x0 6.--7. "SA,Secure Attribute" "0: Use secure attribute from the master,1: Force to nonsecure,2: Use secure attribute from the master,3: Use secure attribute from the master" bitfld.long 0x0 4.--5. "PA,Privileged Attribute" "0: Use privileged attribute from the master,1: Force to privileged,2: Use privileged attribute from the master,3: Use privileged attribute from the master" newline bitfld.long 0x0 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" group.long 0x8C0++0x3 line.long 0x0 "MDA_W0_6_DFMT0,Master Domain Assignment" bitfld.long 0x0 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x0 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x0 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x0 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x0 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x0 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x0 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x0 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" group.long 0x8E0++0x3 line.long 0x0 "MDA_W0_7_DFMT1,Master Domain Assignment" bitfld.long 0x0 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x0 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x0 29. "DFMT,Domain Format" "?,1: Bus master domain assignment (DFMT1)" bitfld.long 0x0 8. "DIDB,DID Bypass" "0: Bypass DID input,1: Use DID input" newline bitfld.long 0x0 6.--7. "SA,Secure Attribute" "0: Use secure attribute from the master,1: Force to nonsecure,2: Use secure attribute from the master,3: Use secure attribute from the master" bitfld.long 0x0 4.--5. "PA,Privileged Attribute" "0: Use privileged attribute from the master,1: Force to privileged,2: Use privileged attribute from the master,3: Use privileged attribute from the master" newline bitfld.long 0x0 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" group.long 0x900++0x3 line.long 0x0 "MDA_W0_8_DFMT0,Master Domain Assignment" bitfld.long 0x0 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x0 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x0 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?" hexmask.long.byte 0x0 16.--21. 1. "PID,Process Identifier" newline hexmask.long.byte 0x0 8.--13. 1. "PIDM,Process Identifier Mask" bitfld.long 0x0 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) == (PIDm[PID]..,3: Partial domain hit = ~((PID & ~PIDM) ==.." newline bitfld.long 0x0 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with the..,?" bitfld.long 0x0 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" group.long 0x920++0x3 line.long 0x0 "MDA_W0_9_DFMT1,Master Domain Assignment" bitfld.long 0x0 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x0 30. "LK1,Lock" "0: Unlocked,1: Locks" newline rbitfld.long 0x0 29. "DFMT,Domain Format" "?,1: Bus master domain assignment (DFMT1)" bitfld.long 0x0 8. "DIDB,DID Bypass" "0: Bypass DID input,1: Use DID input" newline bitfld.long 0x0 6.--7. "SA,Secure Attribute" "0: Use secure attribute from the master,1: Force to nonsecure,2: Use secure attribute from the master,3: Use secure attribute from the master" bitfld.long 0x0 4.--5. "PA,Privileged Attribute" "0: Use privileged attribute from the master,1: Force to privileged,2: Use privileged attribute from the master,3: Use privileged attribute from the master" newline bitfld.long 0x0 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7" group.long 0x1010++0xF line.long 0x0 "PDAC_W0_2,Peripheral Domain Access Control Word 0" bitfld.long 0x0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4 "PDAC_W1_2,Peripheral Domain Access Control Word 1" bitfld.long 0x4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x8 "PDAC_W0_3,Peripheral Domain Access Control Word 0" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "PDAC_W1_3,Peripheral Domain Access Control Word 1" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" group.long 0x10E0++0x7 line.long 0x0 "PDAC_W0_28,Peripheral Domain Access Control Word 0" bitfld.long 0x0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4 "PDAC_W1_28,Peripheral Domain Access Control Word 1" bitfld.long 0x4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" group.long 0x1100++0x27 line.long 0x0 "PDAC_W0_32,Peripheral Domain Access Control Word 0" bitfld.long 0x0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4 "PDAC_W1_32,Peripheral Domain Access Control Word 1" bitfld.long 0x4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x8 "PDAC_W0_33,Peripheral Domain Access Control Word 0" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "PDAC_W1_33,Peripheral Domain Access Control Word 1" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x10 "PDAC_W0_34,Peripheral Domain Access Control Word 0" bitfld.long 0x10 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x10 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x10 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x14 "PDAC_W1_34,Peripheral Domain Access Control Word 1" bitfld.long 0x14 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x14 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x18 "PDAC_W0_35,Peripheral Domain Access Control Word 0" bitfld.long 0x18 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x18 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x18 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x1C "PDAC_W1_35,Peripheral Domain Access Control Word 1" bitfld.long 0x1C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x1C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x20 "PDAC_W0_36,Peripheral Domain Access Control Word 0" bitfld.long 0x20 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x20 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x20 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x24 "PDAC_W1_36,Peripheral Domain Access Control Word 1" bitfld.long 0x24 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x24 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" group.long 0x1130++0x27 line.long 0x0 "PDAC_W0_38,Peripheral Domain Access Control Word 0" bitfld.long 0x0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4 "PDAC_W1_38,Peripheral Domain Access Control Word 1" bitfld.long 0x4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x8 "PDAC_W0_39,Peripheral Domain Access Control Word 0" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "PDAC_W1_39,Peripheral Domain Access Control Word 1" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x10 "PDAC_W0_40,Peripheral Domain Access Control Word 0" bitfld.long 0x10 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x10 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x10 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x14 "PDAC_W1_40,Peripheral Domain Access Control Word 1" bitfld.long 0x14 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x14 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x18 "PDAC_W0_41,Peripheral Domain Access Control Word 0" bitfld.long 0x18 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x18 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x18 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x1C "PDAC_W1_41,Peripheral Domain Access Control Word 1" bitfld.long 0x1C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x1C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x20 "PDAC_W0_42,Peripheral Domain Access Control Word 0" bitfld.long 0x20 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x20 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x20 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x24 "PDAC_W1_42,Peripheral Domain Access Control Word 1" bitfld.long 0x24 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x24 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" group.long 0x1160++0x1F line.long 0x0 "PDAC_W0_44,Peripheral Domain Access Control Word 0" bitfld.long 0x0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4 "PDAC_W1_44,Peripheral Domain Access Control Word 1" bitfld.long 0x4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x8 "PDAC_W0_45,Peripheral Domain Access Control Word 0" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "PDAC_W1_45,Peripheral Domain Access Control Word 1" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x10 "PDAC_W0_46,Peripheral Domain Access Control Word 0" bitfld.long 0x10 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x10 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x10 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x14 "PDAC_W1_46,Peripheral Domain Access Control Word 1" bitfld.long 0x14 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x14 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x18 "PDAC_W0_47,Peripheral Domain Access Control Word 0" bitfld.long 0x18 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x18 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x18 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x1C "PDAC_W1_47,Peripheral Domain Access Control Word 1" bitfld.long 0x1C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x1C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" group.long 0x1188++0x1F line.long 0x0 "PDAC_W0_49,Peripheral Domain Access Control Word 0" bitfld.long 0x0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4 "PDAC_W1_49,Peripheral Domain Access Control Word 1" bitfld.long 0x4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x8 "PDAC_W0_50,Peripheral Domain Access Control Word 0" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "PDAC_W1_50,Peripheral Domain Access Control Word 1" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x10 "PDAC_W0_51,Peripheral Domain Access Control Word 0" bitfld.long 0x10 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x10 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x10 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x14 "PDAC_W1_51,Peripheral Domain Access Control Word 1" bitfld.long 0x14 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x14 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x18 "PDAC_W0_52,Peripheral Domain Access Control Word 0" bitfld.long 0x18 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x18 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x18 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x1C "PDAC_W1_52,Peripheral Domain Access Control Word 1" bitfld.long 0x1C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x1C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" group.long 0x1400++0xAF line.long 0x0 "PDAC_W0_128,Peripheral Domain Access Control Word 0" bitfld.long 0x0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4 "PDAC_W1_128,Peripheral Domain Access Control Word 1" bitfld.long 0x4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x8 "PDAC_W0_129,Peripheral Domain Access Control Word 0" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "PDAC_W1_129,Peripheral Domain Access Control Word 1" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x10 "PDAC_W0_130,Peripheral Domain Access Control Word 0" bitfld.long 0x10 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x10 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x10 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x14 "PDAC_W1_130,Peripheral Domain Access Control Word 1" bitfld.long 0x14 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x14 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x18 "PDAC_W0_131,Peripheral Domain Access Control Word 0" bitfld.long 0x18 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x18 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x18 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x1C "PDAC_W1_131,Peripheral Domain Access Control Word 1" bitfld.long 0x1C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x1C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x20 "PDAC_W0_132,Peripheral Domain Access Control Word 0" bitfld.long 0x20 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x20 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x20 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x24 "PDAC_W1_132,Peripheral Domain Access Control Word 1" bitfld.long 0x24 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x24 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x28 "PDAC_W0_133,Peripheral Domain Access Control Word 0" bitfld.long 0x28 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x28 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x28 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x28 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x28 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x2C "PDAC_W1_133,Peripheral Domain Access Control Word 1" bitfld.long 0x2C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x2C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x30 "PDAC_W0_134,Peripheral Domain Access Control Word 0" bitfld.long 0x30 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x30 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x30 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x30 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x30 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x34 "PDAC_W1_134,Peripheral Domain Access Control Word 1" bitfld.long 0x34 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x34 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x38 "PDAC_W0_135,Peripheral Domain Access Control Word 0" bitfld.long 0x38 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x38 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x38 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x38 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x38 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x3C "PDAC_W1_135,Peripheral Domain Access Control Word 1" bitfld.long 0x3C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x3C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x40 "PDAC_W0_136,Peripheral Domain Access Control Word 0" bitfld.long 0x40 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x40 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x40 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x40 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x40 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x44 "PDAC_W1_136,Peripheral Domain Access Control Word 1" bitfld.long 0x44 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x44 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x48 "PDAC_W0_137,Peripheral Domain Access Control Word 0" bitfld.long 0x48 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x48 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x48 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x48 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x48 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4C "PDAC_W1_137,Peripheral Domain Access Control Word 1" bitfld.long 0x4C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x50 "PDAC_W0_138,Peripheral Domain Access Control Word 0" bitfld.long 0x50 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x50 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x50 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x50 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x50 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x54 "PDAC_W1_138,Peripheral Domain Access Control Word 1" bitfld.long 0x54 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x54 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x58 "PDAC_W0_139,Peripheral Domain Access Control Word 0" bitfld.long 0x58 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x58 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x58 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x58 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x58 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x5C "PDAC_W1_139,Peripheral Domain Access Control Word 1" bitfld.long 0x5C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x5C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x60 "PDAC_W0_140,Peripheral Domain Access Control Word 0" bitfld.long 0x60 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x60 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x60 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x60 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x60 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x64 "PDAC_W1_140,Peripheral Domain Access Control Word 1" bitfld.long 0x64 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x64 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x68 "PDAC_W0_141,Peripheral Domain Access Control Word 0" bitfld.long 0x68 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x68 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x68 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x68 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x68 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x6C "PDAC_W1_141,Peripheral Domain Access Control Word 1" bitfld.long 0x6C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x6C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x70 "PDAC_W0_142,Peripheral Domain Access Control Word 0" bitfld.long 0x70 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x70 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x70 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x70 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x70 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x74 "PDAC_W1_142,Peripheral Domain Access Control Word 1" bitfld.long 0x74 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x74 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x78 "PDAC_W0_143,Peripheral Domain Access Control Word 0" bitfld.long 0x78 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x78 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x78 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x78 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x78 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x78 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x78 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x7C "PDAC_W1_143,Peripheral Domain Access Control Word 1" bitfld.long 0x7C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x7C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x80 "PDAC_W0_144,Peripheral Domain Access Control Word 0" bitfld.long 0x80 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x80 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x80 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x80 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x80 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x84 "PDAC_W1_144,Peripheral Domain Access Control Word 1" bitfld.long 0x84 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x84 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x88 "PDAC_W0_145,Peripheral Domain Access Control Word 0" bitfld.long 0x88 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x88 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x88 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x88 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x88 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x88 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x88 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x8C "PDAC_W1_145,Peripheral Domain Access Control Word 1" bitfld.long 0x8C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x8C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x90 "PDAC_W0_146,Peripheral Domain Access Control Word 0" bitfld.long 0x90 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x90 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x90 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x90 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x90 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x90 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x90 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x94 "PDAC_W1_146,Peripheral Domain Access Control Word 1" bitfld.long 0x94 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x94 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x98 "PDAC_W0_147,Peripheral Domain Access Control Word 0" bitfld.long 0x98 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x98 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x98 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x98 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x98 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x98 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x98 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x9C "PDAC_W1_147,Peripheral Domain Access Control Word 1" bitfld.long 0x9C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x9C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xA0 "PDAC_W0_148,Peripheral Domain Access Control Word 0" bitfld.long 0xA0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xA0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xA0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xA0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xA0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xA4 "PDAC_W1_148,Peripheral Domain Access Control Word 1" bitfld.long 0xA4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xA4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xA8 "PDAC_W0_149,Peripheral Domain Access Control Word 0" bitfld.long 0xA8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xA8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xA8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xA8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xA8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xAC "PDAC_W1_149,Peripheral Domain Access Control Word 1" bitfld.long 0xAC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xAC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" group.long 0x14B8++0xA7 line.long 0x0 "PDAC_W0_151,Peripheral Domain Access Control Word 0" bitfld.long 0x0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4 "PDAC_W1_151,Peripheral Domain Access Control Word 1" bitfld.long 0x4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x8 "PDAC_W0_152,Peripheral Domain Access Control Word 0" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "PDAC_W1_152,Peripheral Domain Access Control Word 1" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x10 "PDAC_W0_153,Peripheral Domain Access Control Word 0" bitfld.long 0x10 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x10 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x10 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x14 "PDAC_W1_153,Peripheral Domain Access Control Word 1" bitfld.long 0x14 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x14 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x18 "PDAC_W0_154,Peripheral Domain Access Control Word 0" bitfld.long 0x18 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x18 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x18 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x1C "PDAC_W1_154,Peripheral Domain Access Control Word 1" bitfld.long 0x1C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x1C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x20 "PDAC_W0_155,Peripheral Domain Access Control Word 0" bitfld.long 0x20 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x20 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x20 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x24 "PDAC_W1_155,Peripheral Domain Access Control Word 1" bitfld.long 0x24 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x24 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x28 "PDAC_W0_156,Peripheral Domain Access Control Word 0" bitfld.long 0x28 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x28 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x28 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x28 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x28 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x2C "PDAC_W1_156,Peripheral Domain Access Control Word 1" bitfld.long 0x2C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x2C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x30 "PDAC_W0_157,Peripheral Domain Access Control Word 0" bitfld.long 0x30 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x30 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x30 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x30 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x30 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x34 "PDAC_W1_157,Peripheral Domain Access Control Word 1" bitfld.long 0x34 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x34 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x38 "PDAC_W0_158,Peripheral Domain Access Control Word 0" bitfld.long 0x38 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x38 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x38 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x38 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x38 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x3C "PDAC_W1_158,Peripheral Domain Access Control Word 1" bitfld.long 0x3C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x3C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x40 "PDAC_W0_159,Peripheral Domain Access Control Word 0" bitfld.long 0x40 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x40 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x40 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x40 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x40 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x44 "PDAC_W1_159,Peripheral Domain Access Control Word 1" bitfld.long 0x44 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x44 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x48 "PDAC_W0_160,Peripheral Domain Access Control Word 0" bitfld.long 0x48 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x48 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x48 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x48 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x48 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4C "PDAC_W1_160,Peripheral Domain Access Control Word 1" bitfld.long 0x4C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x50 "PDAC_W0_161,Peripheral Domain Access Control Word 0" bitfld.long 0x50 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x50 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x50 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x50 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x50 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x54 "PDAC_W1_161,Peripheral Domain Access Control Word 1" bitfld.long 0x54 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x54 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x58 "PDAC_W0_162,Peripheral Domain Access Control Word 0" bitfld.long 0x58 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x58 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x58 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x58 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x58 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x5C "PDAC_W1_162,Peripheral Domain Access Control Word 1" bitfld.long 0x5C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x5C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x60 "PDAC_W0_163,Peripheral Domain Access Control Word 0" bitfld.long 0x60 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x60 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x60 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x60 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x60 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x64 "PDAC_W1_163,Peripheral Domain Access Control Word 1" bitfld.long 0x64 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x64 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x68 "PDAC_W0_164,Peripheral Domain Access Control Word 0" bitfld.long 0x68 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x68 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x68 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x68 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x68 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x6C "PDAC_W1_164,Peripheral Domain Access Control Word 1" bitfld.long 0x6C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x6C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x70 "PDAC_W0_165,Peripheral Domain Access Control Word 0" bitfld.long 0x70 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x70 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x70 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x70 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x70 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x74 "PDAC_W1_165,Peripheral Domain Access Control Word 1" bitfld.long 0x74 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x74 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x78 "PDAC_W0_166,Peripheral Domain Access Control Word 0" bitfld.long 0x78 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x78 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x78 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x78 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x78 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x78 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x78 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x7C "PDAC_W1_166,Peripheral Domain Access Control Word 1" bitfld.long 0x7C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x7C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x80 "PDAC_W0_167,Peripheral Domain Access Control Word 0" bitfld.long 0x80 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x80 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x80 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x80 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x80 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x84 "PDAC_W1_167,Peripheral Domain Access Control Word 1" bitfld.long 0x84 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x84 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x88 "PDAC_W0_168,Peripheral Domain Access Control Word 0" bitfld.long 0x88 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x88 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x88 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x88 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x88 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x88 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x88 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x8C "PDAC_W1_168,Peripheral Domain Access Control Word 1" bitfld.long 0x8C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x8C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x90 "PDAC_W0_169,Peripheral Domain Access Control Word 0" bitfld.long 0x90 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x90 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x90 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x90 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x90 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x90 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x90 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x94 "PDAC_W1_169,Peripheral Domain Access Control Word 1" bitfld.long 0x94 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x94 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x98 "PDAC_W0_170,Peripheral Domain Access Control Word 0" bitfld.long 0x98 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x98 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x98 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x98 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x98 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x98 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x98 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x9C "PDAC_W1_170,Peripheral Domain Access Control Word 1" bitfld.long 0x9C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x9C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xA0 "PDAC_W0_171,Peripheral Domain Access Control Word 0" bitfld.long 0xA0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xA0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xA0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xA0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xA0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xA4 "PDAC_W1_171,Peripheral Domain Access Control Word 1" bitfld.long 0xA4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xA4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" group.long 0x1568++0x7 line.long 0x0 "PDAC_W0_173,Peripheral Domain Access Control Word 0" bitfld.long 0x0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4 "PDAC_W1_173,Peripheral Domain Access Control Word 1" bitfld.long 0x4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" group.long 0x1578++0x7 line.long 0x0 "PDAC_W0_175,Peripheral Domain Access Control Word 0" bitfld.long 0x0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4 "PDAC_W1_175,Peripheral Domain Access Control Word 1" bitfld.long 0x4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" group.long 0x1588++0x147 line.long 0x0 "PDAC_W0_177,Peripheral Domain Access Control Word 0" bitfld.long 0x0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4 "PDAC_W1_177,Peripheral Domain Access Control Word 1" bitfld.long 0x4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x8 "PDAC_W0_178,Peripheral Domain Access Control Word 0" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "PDAC_W1_178,Peripheral Domain Access Control Word 1" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x10 "PDAC_W0_179,Peripheral Domain Access Control Word 0" bitfld.long 0x10 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x10 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x10 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x14 "PDAC_W1_179,Peripheral Domain Access Control Word 1" bitfld.long 0x14 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x14 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x18 "PDAC_W0_180,Peripheral Domain Access Control Word 0" bitfld.long 0x18 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x18 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x18 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x1C "PDAC_W1_180,Peripheral Domain Access Control Word 1" bitfld.long 0x1C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x1C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x20 "PDAC_W0_181,Peripheral Domain Access Control Word 0" bitfld.long 0x20 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x20 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x20 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x24 "PDAC_W1_181,Peripheral Domain Access Control Word 1" bitfld.long 0x24 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x24 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x28 "PDAC_W0_182,Peripheral Domain Access Control Word 0" bitfld.long 0x28 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x28 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x28 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x28 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x28 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x2C "PDAC_W1_182,Peripheral Domain Access Control Word 1" bitfld.long 0x2C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x2C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x30 "PDAC_W0_183,Peripheral Domain Access Control Word 0" bitfld.long 0x30 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x30 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x30 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x30 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x30 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x34 "PDAC_W1_183,Peripheral Domain Access Control Word 1" bitfld.long 0x34 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x34 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x38 "PDAC_W0_184,Peripheral Domain Access Control Word 0" bitfld.long 0x38 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x38 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x38 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x38 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x38 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x3C "PDAC_W1_184,Peripheral Domain Access Control Word 1" bitfld.long 0x3C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x3C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x40 "PDAC_W0_185,Peripheral Domain Access Control Word 0" bitfld.long 0x40 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x40 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x40 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x40 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x40 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x44 "PDAC_W1_185,Peripheral Domain Access Control Word 1" bitfld.long 0x44 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x44 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x48 "PDAC_W0_186,Peripheral Domain Access Control Word 0" bitfld.long 0x48 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x48 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x48 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x48 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x48 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4C "PDAC_W1_186,Peripheral Domain Access Control Word 1" bitfld.long 0x4C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x50 "PDAC_W0_187,Peripheral Domain Access Control Word 0" bitfld.long 0x50 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x50 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x50 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x50 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x50 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x54 "PDAC_W1_187,Peripheral Domain Access Control Word 1" bitfld.long 0x54 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x54 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x58 "PDAC_W0_188,Peripheral Domain Access Control Word 0" bitfld.long 0x58 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x58 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x58 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x58 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x58 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x5C "PDAC_W1_188,Peripheral Domain Access Control Word 1" bitfld.long 0x5C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x5C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x60 "PDAC_W0_189,Peripheral Domain Access Control Word 0" bitfld.long 0x60 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x60 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x60 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x60 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x60 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x64 "PDAC_W1_189,Peripheral Domain Access Control Word 1" bitfld.long 0x64 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x64 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x68 "PDAC_W0_190,Peripheral Domain Access Control Word 0" bitfld.long 0x68 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x68 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x68 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x68 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x68 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x6C "PDAC_W1_190,Peripheral Domain Access Control Word 1" bitfld.long 0x6C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x6C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x70 "PDAC_W0_191,Peripheral Domain Access Control Word 0" bitfld.long 0x70 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x70 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x70 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x70 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x70 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x74 "PDAC_W1_191,Peripheral Domain Access Control Word 1" bitfld.long 0x74 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x74 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x78 "PDAC_W0_192,Peripheral Domain Access Control Word 0" bitfld.long 0x78 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x78 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x78 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x78 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x78 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x78 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x78 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x7C "PDAC_W1_192,Peripheral Domain Access Control Word 1" bitfld.long 0x7C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x7C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x80 "PDAC_W0_193,Peripheral Domain Access Control Word 0" bitfld.long 0x80 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x80 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x80 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x80 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x80 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x84 "PDAC_W1_193,Peripheral Domain Access Control Word 1" bitfld.long 0x84 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x84 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x88 "PDAC_W0_194,Peripheral Domain Access Control Word 0" bitfld.long 0x88 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x88 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x88 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x88 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x88 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x88 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x88 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x8C "PDAC_W1_194,Peripheral Domain Access Control Word 1" bitfld.long 0x8C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x8C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x90 "PDAC_W0_195,Peripheral Domain Access Control Word 0" bitfld.long 0x90 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x90 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x90 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x90 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x90 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x90 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x90 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x94 "PDAC_W1_195,Peripheral Domain Access Control Word 1" bitfld.long 0x94 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x94 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x98 "PDAC_W0_196,Peripheral Domain Access Control Word 0" bitfld.long 0x98 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x98 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x98 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x98 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x98 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x98 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x98 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x9C "PDAC_W1_196,Peripheral Domain Access Control Word 1" bitfld.long 0x9C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x9C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xA0 "PDAC_W0_197,Peripheral Domain Access Control Word 0" bitfld.long 0xA0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xA0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xA0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xA0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xA0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xA4 "PDAC_W1_197,Peripheral Domain Access Control Word 1" bitfld.long 0xA4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xA4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xA8 "PDAC_W0_198,Peripheral Domain Access Control Word 0" bitfld.long 0xA8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xA8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xA8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xA8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xA8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xAC "PDAC_W1_198,Peripheral Domain Access Control Word 1" bitfld.long 0xAC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xAC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xB0 "PDAC_W0_199,Peripheral Domain Access Control Word 0" bitfld.long 0xB0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xB0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xB0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xB0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xB0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xB0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xB0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xB4 "PDAC_W1_199,Peripheral Domain Access Control Word 1" bitfld.long 0xB4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xB4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xB8 "PDAC_W0_200,Peripheral Domain Access Control Word 0" bitfld.long 0xB8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xB8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xB8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xB8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xB8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xB8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xB8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xBC "PDAC_W1_200,Peripheral Domain Access Control Word 1" bitfld.long 0xBC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xBC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xC0 "PDAC_W0_201,Peripheral Domain Access Control Word 0" bitfld.long 0xC0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xC0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xC0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xC0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xC0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC4 "PDAC_W1_201,Peripheral Domain Access Control Word 1" bitfld.long 0xC4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xC8 "PDAC_W0_202,Peripheral Domain Access Control Word 0" bitfld.long 0xC8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xC8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xC8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xC8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xC8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xCC "PDAC_W1_202,Peripheral Domain Access Control Word 1" bitfld.long 0xCC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xCC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xD0 "PDAC_W0_203,Peripheral Domain Access Control Word 0" bitfld.long 0xD0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xD0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xD0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xD0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xD0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xD0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xD0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xD4 "PDAC_W1_203,Peripheral Domain Access Control Word 1" bitfld.long 0xD4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xD4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xD8 "PDAC_W0_204,Peripheral Domain Access Control Word 0" bitfld.long 0xD8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xD8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xD8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xD8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xD8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xD8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xD8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xDC "PDAC_W1_204,Peripheral Domain Access Control Word 1" bitfld.long 0xDC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xDC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xE0 "PDAC_W0_205,Peripheral Domain Access Control Word 0" bitfld.long 0xE0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xE0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xE0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xE0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xE0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xE0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xE0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xE4 "PDAC_W1_205,Peripheral Domain Access Control Word 1" bitfld.long 0xE4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xE4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xE8 "PDAC_W0_206,Peripheral Domain Access Control Word 0" bitfld.long 0xE8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xE8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xE8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xE8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xE8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xE8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xE8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xEC "PDAC_W1_206,Peripheral Domain Access Control Word 1" bitfld.long 0xEC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xEC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xF0 "PDAC_W0_207,Peripheral Domain Access Control Word 0" bitfld.long 0xF0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xF0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xF0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xF0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xF0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xF0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xF0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xF4 "PDAC_W1_207,Peripheral Domain Access Control Word 1" bitfld.long 0xF4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xF4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xF8 "PDAC_W0_208,Peripheral Domain Access Control Word 0" bitfld.long 0xF8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xF8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xF8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xF8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xF8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xF8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xF8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xFC "PDAC_W1_208,Peripheral Domain Access Control Word 1" bitfld.long 0xFC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xFC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x100 "PDAC_W0_209,Peripheral Domain Access Control Word 0" bitfld.long 0x100 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x100 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x100 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x100 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x100 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x100 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x100 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x104 "PDAC_W1_209,Peripheral Domain Access Control Word 1" bitfld.long 0x104 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x104 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x108 "PDAC_W0_210,Peripheral Domain Access Control Word 0" bitfld.long 0x108 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x108 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x108 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x108 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x108 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x108 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x108 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x10C "PDAC_W1_210,Peripheral Domain Access Control Word 1" bitfld.long 0x10C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x10C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x110 "PDAC_W0_211,Peripheral Domain Access Control Word 0" bitfld.long 0x110 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x110 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x110 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x110 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x110 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x110 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x110 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x114 "PDAC_W1_211,Peripheral Domain Access Control Word 1" bitfld.long 0x114 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x114 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x118 "PDAC_W0_212,Peripheral Domain Access Control Word 0" bitfld.long 0x118 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x118 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x118 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x118 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x118 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x118 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x118 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x11C "PDAC_W1_212,Peripheral Domain Access Control Word 1" bitfld.long 0x11C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x11C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x120 "PDAC_W0_213,Peripheral Domain Access Control Word 0" bitfld.long 0x120 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x120 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x120 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x120 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x120 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x120 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x120 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x124 "PDAC_W1_213,Peripheral Domain Access Control Word 1" bitfld.long 0x124 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x124 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x128 "PDAC_W0_214,Peripheral Domain Access Control Word 0" bitfld.long 0x128 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x128 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x128 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x128 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x128 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x128 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x128 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x12C "PDAC_W1_214,Peripheral Domain Access Control Word 1" bitfld.long 0x12C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x12C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x130 "PDAC_W0_215,Peripheral Domain Access Control Word 0" bitfld.long 0x130 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x130 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x130 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x130 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x130 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x130 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x130 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x134 "PDAC_W1_215,Peripheral Domain Access Control Word 1" bitfld.long 0x134 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x134 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x138 "PDAC_W0_216,Peripheral Domain Access Control Word 0" bitfld.long 0x138 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x138 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x138 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x138 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x138 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x138 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x138 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x13C "PDAC_W1_216,Peripheral Domain Access Control Word 1" bitfld.long 0x13C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x13C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x140 "PDAC_W0_217,Peripheral Domain Access Control Word 0" bitfld.long 0x140 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x140 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x140 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x140 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x140 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x140 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x140 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x144 "PDAC_W1_217,Peripheral Domain Access Control Word 1" bitfld.long 0x144 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x144 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" group.long 0x16D8++0x17 line.long 0x0 "PDAC_W0_219,Peripheral Domain Access Control Word 0" bitfld.long 0x0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4 "PDAC_W1_219,Peripheral Domain Access Control Word 1" bitfld.long 0x4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x8 "PDAC_W0_220,Peripheral Domain Access Control Word 0" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "PDAC_W1_220,Peripheral Domain Access Control Word 1" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x10 "PDAC_W0_221,Peripheral Domain Access Control Word 0" bitfld.long 0x10 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x10 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x10 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x14 "PDAC_W1_221,Peripheral Domain Access Control Word 1" bitfld.long 0x14 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x14 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" group.long 0x16F8++0x27 line.long 0x0 "PDAC_W0_223,Peripheral Domain Access Control Word 0" bitfld.long 0x0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4 "PDAC_W1_223,Peripheral Domain Access Control Word 1" bitfld.long 0x4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x8 "PDAC_W0_224,Peripheral Domain Access Control Word 0" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "PDAC_W1_224,Peripheral Domain Access Control Word 1" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x10 "PDAC_W0_225,Peripheral Domain Access Control Word 0" bitfld.long 0x10 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x10 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x10 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x14 "PDAC_W1_225,Peripheral Domain Access Control Word 1" bitfld.long 0x14 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x14 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x18 "PDAC_W0_226,Peripheral Domain Access Control Word 0" bitfld.long 0x18 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x18 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x18 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x1C "PDAC_W1_226,Peripheral Domain Access Control Word 1" bitfld.long 0x1C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x1C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x20 "PDAC_W0_227,Peripheral Domain Access Control Word 0" bitfld.long 0x20 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x20 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x20 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x24 "PDAC_W1_227,Peripheral Domain Access Control Word 1" bitfld.long 0x24 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x24 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" group.long 0x1728++0x3F line.long 0x0 "PDAC_W0_229,Peripheral Domain Access Control Word 0" bitfld.long 0x0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4 "PDAC_W1_229,Peripheral Domain Access Control Word 1" bitfld.long 0x4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x8 "PDAC_W0_230,Peripheral Domain Access Control Word 0" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "PDAC_W1_230,Peripheral Domain Access Control Word 1" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x10 "PDAC_W0_231,Peripheral Domain Access Control Word 0" bitfld.long 0x10 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x10 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x10 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x14 "PDAC_W1_231,Peripheral Domain Access Control Word 1" bitfld.long 0x14 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x14 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x18 "PDAC_W0_232,Peripheral Domain Access Control Word 0" bitfld.long 0x18 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x18 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x18 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x1C "PDAC_W1_232,Peripheral Domain Access Control Word 1" bitfld.long 0x1C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x1C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x20 "PDAC_W0_233,Peripheral Domain Access Control Word 0" bitfld.long 0x20 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x20 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x20 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x24 "PDAC_W1_233,Peripheral Domain Access Control Word 1" bitfld.long 0x24 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x24 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x28 "PDAC_W0_234,Peripheral Domain Access Control Word 0" bitfld.long 0x28 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x28 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x28 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x28 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x28 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x2C "PDAC_W1_234,Peripheral Domain Access Control Word 1" bitfld.long 0x2C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x2C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x30 "PDAC_W0_235,Peripheral Domain Access Control Word 0" bitfld.long 0x30 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x30 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x30 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x30 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x30 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x34 "PDAC_W1_235,Peripheral Domain Access Control Word 1" bitfld.long 0x34 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x34 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x38 "PDAC_W0_236,Peripheral Domain Access Control Word 0" bitfld.long 0x38 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x38 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x38 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x38 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x38 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x3C "PDAC_W1_236,Peripheral Domain Access Control Word 1" bitfld.long 0x3C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x3C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" group.long 0x1770++0x7 line.long 0x0 "PDAC_W0_238,Peripheral Domain Access Control Word 0" bitfld.long 0x0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4 "PDAC_W1_238,Peripheral Domain Access Control Word 1" bitfld.long 0x4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" group.long 0x1780++0x17F line.long 0x0 "PDAC_W0_240,Peripheral Domain Access Control Word 0" bitfld.long 0x0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4 "PDAC_W1_240,Peripheral Domain Access Control Word 1" bitfld.long 0x4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x8 "PDAC_W0_241,Peripheral Domain Access Control Word 0" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "PDAC_W1_241,Peripheral Domain Access Control Word 1" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x10 "PDAC_W0_242,Peripheral Domain Access Control Word 0" bitfld.long 0x10 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x10 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x10 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x14 "PDAC_W1_242,Peripheral Domain Access Control Word 1" bitfld.long 0x14 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x14 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x18 "PDAC_W0_243,Peripheral Domain Access Control Word 0" bitfld.long 0x18 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x18 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x18 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x1C "PDAC_W1_243,Peripheral Domain Access Control Word 1" bitfld.long 0x1C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x1C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x20 "PDAC_W0_244,Peripheral Domain Access Control Word 0" bitfld.long 0x20 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x20 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x20 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x24 "PDAC_W1_244,Peripheral Domain Access Control Word 1" bitfld.long 0x24 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x24 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x28 "PDAC_W0_245,Peripheral Domain Access Control Word 0" bitfld.long 0x28 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x28 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x28 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x28 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x28 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x2C "PDAC_W1_245,Peripheral Domain Access Control Word 1" bitfld.long 0x2C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x2C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x30 "PDAC_W0_246,Peripheral Domain Access Control Word 0" bitfld.long 0x30 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x30 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x30 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x30 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x30 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x34 "PDAC_W1_246,Peripheral Domain Access Control Word 1" bitfld.long 0x34 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x34 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x38 "PDAC_W0_247,Peripheral Domain Access Control Word 0" bitfld.long 0x38 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x38 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x38 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x38 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x38 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x3C "PDAC_W1_247,Peripheral Domain Access Control Word 1" bitfld.long 0x3C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x3C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x40 "PDAC_W0_248,Peripheral Domain Access Control Word 0" bitfld.long 0x40 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x40 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x40 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x40 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x40 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x44 "PDAC_W1_248,Peripheral Domain Access Control Word 1" bitfld.long 0x44 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x44 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x48 "PDAC_W0_249,Peripheral Domain Access Control Word 0" bitfld.long 0x48 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x48 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x48 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x48 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x48 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4C "PDAC_W1_249,Peripheral Domain Access Control Word 1" bitfld.long 0x4C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x50 "PDAC_W0_250,Peripheral Domain Access Control Word 0" bitfld.long 0x50 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x50 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x50 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x50 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x50 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x54 "PDAC_W1_250,Peripheral Domain Access Control Word 1" bitfld.long 0x54 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x54 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x58 "PDAC_W0_251,Peripheral Domain Access Control Word 0" bitfld.long 0x58 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x58 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x58 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x58 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x58 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x5C "PDAC_W1_251,Peripheral Domain Access Control Word 1" bitfld.long 0x5C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x5C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x60 "PDAC_W0_252,Peripheral Domain Access Control Word 0" bitfld.long 0x60 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x60 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x60 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x60 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x60 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x64 "PDAC_W1_252,Peripheral Domain Access Control Word 1" bitfld.long 0x64 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x64 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x68 "PDAC_W0_253,Peripheral Domain Access Control Word 0" bitfld.long 0x68 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x68 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x68 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x68 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x68 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x6C "PDAC_W1_253,Peripheral Domain Access Control Word 1" bitfld.long 0x6C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x6C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x70 "PDAC_W0_254,Peripheral Domain Access Control Word 0" bitfld.long 0x70 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x70 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x70 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x70 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x70 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x74 "PDAC_W1_254,Peripheral Domain Access Control Word 1" bitfld.long 0x74 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x74 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x78 "PDAC_W0_255,Peripheral Domain Access Control Word 0" bitfld.long 0x78 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x78 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x78 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x78 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x78 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x78 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x78 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x7C "PDAC_W1_255,Peripheral Domain Access Control Word 1" bitfld.long 0x7C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x7C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x80 "PDAC_W0_256,Peripheral Domain Access Control Word 0" bitfld.long 0x80 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x80 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x80 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x80 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x80 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x84 "PDAC_W1_256,Peripheral Domain Access Control Word 1" bitfld.long 0x84 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x84 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x88 "PDAC_W0_257,Peripheral Domain Access Control Word 0" bitfld.long 0x88 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x88 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x88 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x88 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x88 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x88 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x88 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x8C "PDAC_W1_257,Peripheral Domain Access Control Word 1" bitfld.long 0x8C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x8C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x90 "PDAC_W0_258,Peripheral Domain Access Control Word 0" bitfld.long 0x90 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x90 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x90 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x90 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x90 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x90 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x90 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x94 "PDAC_W1_258,Peripheral Domain Access Control Word 1" bitfld.long 0x94 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x94 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x98 "PDAC_W0_259,Peripheral Domain Access Control Word 0" bitfld.long 0x98 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x98 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x98 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x98 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x98 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x98 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x98 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x9C "PDAC_W1_259,Peripheral Domain Access Control Word 1" bitfld.long 0x9C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x9C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xA0 "PDAC_W0_260,Peripheral Domain Access Control Word 0" bitfld.long 0xA0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xA0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xA0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xA0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xA0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xA4 "PDAC_W1_260,Peripheral Domain Access Control Word 1" bitfld.long 0xA4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xA4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xA8 "PDAC_W0_261,Peripheral Domain Access Control Word 0" bitfld.long 0xA8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xA8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xA8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xA8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xA8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xA8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xAC "PDAC_W1_261,Peripheral Domain Access Control Word 1" bitfld.long 0xAC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xAC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xB0 "PDAC_W0_262,Peripheral Domain Access Control Word 0" bitfld.long 0xB0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xB0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xB0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xB0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xB0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xB0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xB0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xB4 "PDAC_W1_262,Peripheral Domain Access Control Word 1" bitfld.long 0xB4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xB4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xB8 "PDAC_W0_263,Peripheral Domain Access Control Word 0" bitfld.long 0xB8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xB8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xB8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xB8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xB8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xB8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xB8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xBC "PDAC_W1_263,Peripheral Domain Access Control Word 1" bitfld.long 0xBC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xBC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xC0 "PDAC_W0_264,Peripheral Domain Access Control Word 0" bitfld.long 0xC0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xC0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xC0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xC0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xC0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC4 "PDAC_W1_264,Peripheral Domain Access Control Word 1" bitfld.long 0xC4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xC8 "PDAC_W0_265,Peripheral Domain Access Control Word 0" bitfld.long 0xC8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xC8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xC8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xC8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xC8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xCC "PDAC_W1_265,Peripheral Domain Access Control Word 1" bitfld.long 0xCC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xCC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xD0 "PDAC_W0_266,Peripheral Domain Access Control Word 0" bitfld.long 0xD0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xD0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xD0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xD0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xD0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xD0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xD0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xD4 "PDAC_W1_266,Peripheral Domain Access Control Word 1" bitfld.long 0xD4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xD4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xD8 "PDAC_W0_267,Peripheral Domain Access Control Word 0" bitfld.long 0xD8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xD8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xD8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xD8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xD8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xD8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xD8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xDC "PDAC_W1_267,Peripheral Domain Access Control Word 1" bitfld.long 0xDC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xDC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xE0 "PDAC_W0_268,Peripheral Domain Access Control Word 0" bitfld.long 0xE0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xE0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xE0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xE0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xE0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xE0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xE0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xE4 "PDAC_W1_268,Peripheral Domain Access Control Word 1" bitfld.long 0xE4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xE4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xE8 "PDAC_W0_269,Peripheral Domain Access Control Word 0" bitfld.long 0xE8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xE8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xE8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xE8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xE8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xE8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xE8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xEC "PDAC_W1_269,Peripheral Domain Access Control Word 1" bitfld.long 0xEC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xEC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xF0 "PDAC_W0_270,Peripheral Domain Access Control Word 0" bitfld.long 0xF0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xF0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xF0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xF0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xF0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xF0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xF0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xF4 "PDAC_W1_270,Peripheral Domain Access Control Word 1" bitfld.long 0xF4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xF4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0xF8 "PDAC_W0_271,Peripheral Domain Access Control Word 0" bitfld.long 0xF8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0xF8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0xF8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xF8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xF8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0xF8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0xF8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xFC "PDAC_W1_271,Peripheral Domain Access Control Word 1" bitfld.long 0xFC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xFC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x100 "PDAC_W0_272,Peripheral Domain Access Control Word 0" bitfld.long 0x100 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x100 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x100 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x100 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x100 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x100 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x100 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x104 "PDAC_W1_272,Peripheral Domain Access Control Word 1" bitfld.long 0x104 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x104 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x108 "PDAC_W0_273,Peripheral Domain Access Control Word 0" bitfld.long 0x108 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x108 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x108 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x108 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x108 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x108 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x108 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x10C "PDAC_W1_273,Peripheral Domain Access Control Word 1" bitfld.long 0x10C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x10C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x110 "PDAC_W0_274,Peripheral Domain Access Control Word 0" bitfld.long 0x110 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x110 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x110 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x110 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x110 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x110 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x110 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x114 "PDAC_W1_274,Peripheral Domain Access Control Word 1" bitfld.long 0x114 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x114 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x118 "PDAC_W0_275,Peripheral Domain Access Control Word 0" bitfld.long 0x118 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x118 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x118 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x118 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x118 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x118 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x118 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x11C "PDAC_W1_275,Peripheral Domain Access Control Word 1" bitfld.long 0x11C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x11C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x120 "PDAC_W0_276,Peripheral Domain Access Control Word 0" bitfld.long 0x120 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x120 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x120 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x120 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x120 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x120 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x120 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x124 "PDAC_W1_276,Peripheral Domain Access Control Word 1" bitfld.long 0x124 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x124 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x128 "PDAC_W0_277,Peripheral Domain Access Control Word 0" bitfld.long 0x128 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x128 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x128 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x128 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x128 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x128 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x128 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x12C "PDAC_W1_277,Peripheral Domain Access Control Word 1" bitfld.long 0x12C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x12C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x130 "PDAC_W0_278,Peripheral Domain Access Control Word 0" bitfld.long 0x130 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x130 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x130 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x130 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x130 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x130 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x130 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x134 "PDAC_W1_278,Peripheral Domain Access Control Word 1" bitfld.long 0x134 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x134 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x138 "PDAC_W0_279,Peripheral Domain Access Control Word 0" bitfld.long 0x138 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x138 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x138 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x138 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x138 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x138 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x138 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x13C "PDAC_W1_279,Peripheral Domain Access Control Word 1" bitfld.long 0x13C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x13C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x140 "PDAC_W0_280,Peripheral Domain Access Control Word 0" bitfld.long 0x140 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x140 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x140 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x140 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x140 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x140 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x140 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x144 "PDAC_W1_280,Peripheral Domain Access Control Word 1" bitfld.long 0x144 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x144 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x148 "PDAC_W0_281,Peripheral Domain Access Control Word 0" bitfld.long 0x148 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x148 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x148 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x148 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x148 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x148 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x148 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x14C "PDAC_W1_281,Peripheral Domain Access Control Word 1" bitfld.long 0x14C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x14C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x150 "PDAC_W0_282,Peripheral Domain Access Control Word 0" bitfld.long 0x150 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x150 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x150 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x150 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x150 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x150 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x150 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x154 "PDAC_W1_282,Peripheral Domain Access Control Word 1" bitfld.long 0x154 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x154 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x158 "PDAC_W0_283,Peripheral Domain Access Control Word 0" bitfld.long 0x158 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x158 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x158 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x158 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x158 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x158 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x158 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x15C "PDAC_W1_283,Peripheral Domain Access Control Word 1" bitfld.long 0x15C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x15C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x160 "PDAC_W0_284,Peripheral Domain Access Control Word 0" bitfld.long 0x160 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x160 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x160 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x160 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x160 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x160 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x160 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x164 "PDAC_W1_284,Peripheral Domain Access Control Word 1" bitfld.long 0x164 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x164 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x168 "PDAC_W0_285,Peripheral Domain Access Control Word 0" bitfld.long 0x168 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x168 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x168 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x168 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x168 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x168 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x168 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x16C "PDAC_W1_285,Peripheral Domain Access Control Word 1" bitfld.long 0x16C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x16C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x170 "PDAC_W0_286,Peripheral Domain Access Control Word 0" bitfld.long 0x170 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x170 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x170 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x170 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x170 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x170 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x170 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x174 "PDAC_W1_286,Peripheral Domain Access Control Word 1" bitfld.long 0x174 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x174 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x178 "PDAC_W0_287,Peripheral Domain Access Control Word 0" bitfld.long 0x178 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x178 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x178 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x178 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x178 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x178 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x178 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x17C "PDAC_W1_287,Peripheral Domain Access Control Word 1" bitfld.long 0x17C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x17C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" group.long 0x1908++0x4F line.long 0x0 "PDAC_W0_289,Peripheral Domain Access Control Word 0" bitfld.long 0x0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4 "PDAC_W1_289,Peripheral Domain Access Control Word 1" bitfld.long 0x4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x8 "PDAC_W0_290,Peripheral Domain Access Control Word 0" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "PDAC_W1_290,Peripheral Domain Access Control Word 1" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x10 "PDAC_W0_291,Peripheral Domain Access Control Word 0" bitfld.long 0x10 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x10 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x10 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x14 "PDAC_W1_291,Peripheral Domain Access Control Word 1" bitfld.long 0x14 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x14 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x18 "PDAC_W0_292,Peripheral Domain Access Control Word 0" bitfld.long 0x18 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x18 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x18 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x1C "PDAC_W1_292,Peripheral Domain Access Control Word 1" bitfld.long 0x1C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x1C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x20 "PDAC_W0_293,Peripheral Domain Access Control Word 0" bitfld.long 0x20 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x20 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x20 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x24 "PDAC_W1_293,Peripheral Domain Access Control Word 1" bitfld.long 0x24 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x24 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x28 "PDAC_W0_294,Peripheral Domain Access Control Word 0" bitfld.long 0x28 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x28 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x28 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x28 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x28 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x2C "PDAC_W1_294,Peripheral Domain Access Control Word 1" bitfld.long 0x2C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x2C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x30 "PDAC_W0_295,Peripheral Domain Access Control Word 0" bitfld.long 0x30 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x30 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x30 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x30 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x30 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x34 "PDAC_W1_295,Peripheral Domain Access Control Word 1" bitfld.long 0x34 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x34 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x38 "PDAC_W0_296,Peripheral Domain Access Control Word 0" bitfld.long 0x38 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x38 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x38 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x38 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x38 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x3C "PDAC_W1_296,Peripheral Domain Access Control Word 1" bitfld.long 0x3C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x3C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x40 "PDAC_W0_297,Peripheral Domain Access Control Word 0" bitfld.long 0x40 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x40 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x40 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x40 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x40 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x44 "PDAC_W1_297,Peripheral Domain Access Control Word 1" bitfld.long 0x44 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x44 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x48 "PDAC_W0_298,Peripheral Domain Access Control Word 0" bitfld.long 0x48 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x48 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x48 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x48 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x48 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4C "PDAC_W1_298,Peripheral Domain Access Control Word 1" bitfld.long 0x4C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" group.long 0x1978++0xF line.long 0x0 "PDAC_W0_303,Peripheral Domain Access Control Word 0" bitfld.long 0x0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4 "PDAC_W1_303,Peripheral Domain Access Control Word 1" bitfld.long 0x4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x8 "PDAC_W0_304,Peripheral Domain Access Control Word 0" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "PDAC_W1_304,Peripheral Domain Access Control Word 1" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" group.long 0x1998++0x7 line.long 0x0 "PDAC_W0_307,Peripheral Domain Access Control Word 0" bitfld.long 0x0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4 "PDAC_W1_307,Peripheral Domain Access Control Word 1" bitfld.long 0x4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" group.long 0x19B8++0x7 line.long 0x0 "PDAC_W0_311,Peripheral Domain Access Control Word 0" bitfld.long 0x0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4 "PDAC_W1_311,Peripheral Domain Access Control Word 1" bitfld.long 0x4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" group.long 0x19D0++0xF line.long 0x0 "PDAC_W0_314,Peripheral Domain Access Control Word 0" bitfld.long 0x0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4 "PDAC_W1_314,Peripheral Domain Access Control Word 1" bitfld.long 0x4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x8 "PDAC_W0_315,Peripheral Domain Access Control Word 0" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "PDAC_W1_315,Peripheral Domain Access Control Word 1" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" group.long 0x19F0++0x1F line.long 0x0 "PDAC_W0_318,Peripheral Domain Access Control Word 0" bitfld.long 0x0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4 "PDAC_W1_318,Peripheral Domain Access Control Word 1" bitfld.long 0x4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x8 "PDAC_W0_319,Peripheral Domain Access Control Word 0" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "PDAC_W1_319,Peripheral Domain Access Control Word 1" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x10 "PDAC_W0_320,Peripheral Domain Access Control Word 0" bitfld.long 0x10 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x10 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x10 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x14 "PDAC_W1_320,Peripheral Domain Access Control Word 1" bitfld.long 0x14 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x14 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x18 "PDAC_W0_321,Peripheral Domain Access Control Word 0" bitfld.long 0x18 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x18 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x18 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x1C "PDAC_W1_321,Peripheral Domain Access Control Word 1" bitfld.long 0x1C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x1C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" group.long 0x1A18++0x1F line.long 0x0 "PDAC_W0_323,Peripheral Domain Access Control Word 0" bitfld.long 0x0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4 "PDAC_W1_323,Peripheral Domain Access Control Word 1" bitfld.long 0x4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x8 "PDAC_W0_324,Peripheral Domain Access Control Word 0" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "PDAC_W1_324,Peripheral Domain Access Control Word 1" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x10 "PDAC_W0_325,Peripheral Domain Access Control Word 0" bitfld.long 0x10 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x10 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x10 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x14 "PDAC_W1_325,Peripheral Domain Access Control Word 1" bitfld.long 0x14 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x14 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x18 "PDAC_W0_326,Peripheral Domain Access Control Word 0" bitfld.long 0x18 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x18 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x18 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x1C "PDAC_W1_326,Peripheral Domain Access Control Word 1" bitfld.long 0x1C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x1C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" group.long 0x1A40++0x3F line.long 0x0 "PDAC_W0_328,Peripheral Domain Access Control Word 0" bitfld.long 0x0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4 "PDAC_W1_328,Peripheral Domain Access Control Word 1" bitfld.long 0x4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x8 "PDAC_W0_329,Peripheral Domain Access Control Word 0" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "PDAC_W1_329,Peripheral Domain Access Control Word 1" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x10 "PDAC_W0_330,Peripheral Domain Access Control Word 0" bitfld.long 0x10 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x10 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x10 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x14 "PDAC_W1_330,Peripheral Domain Access Control Word 1" bitfld.long 0x14 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x14 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x18 "PDAC_W0_331,Peripheral Domain Access Control Word 0" bitfld.long 0x18 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x18 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x18 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x1C "PDAC_W1_331,Peripheral Domain Access Control Word 1" bitfld.long 0x1C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x1C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x20 "PDAC_W0_332,Peripheral Domain Access Control Word 0" bitfld.long 0x20 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x20 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x20 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x24 "PDAC_W1_332,Peripheral Domain Access Control Word 1" bitfld.long 0x24 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x24 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x28 "PDAC_W0_333,Peripheral Domain Access Control Word 0" bitfld.long 0x28 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x28 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x28 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x28 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x28 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x2C "PDAC_W1_333,Peripheral Domain Access Control Word 1" bitfld.long 0x2C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x2C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x30 "PDAC_W0_334,Peripheral Domain Access Control Word 0" bitfld.long 0x30 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x30 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x30 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x30 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x30 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x34 "PDAC_W1_334,Peripheral Domain Access Control Word 1" bitfld.long 0x34 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x34 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x38 "PDAC_W0_335,Peripheral Domain Access Control Word 0" bitfld.long 0x38 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x38 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x38 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x38 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x38 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x3C "PDAC_W1_335,Peripheral Domain Access Control Word 1" bitfld.long 0x3C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x3C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" group.long 0x1A88++0x57 line.long 0x0 "PDAC_W0_337,Peripheral Domain Access Control Word 0" bitfld.long 0x0 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x0 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x0 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4 "PDAC_W1_337,Peripheral Domain Access Control Word 1" bitfld.long 0x4 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x8 "PDAC_W0_338,Peripheral Domain Access Control Word 0" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "PDAC_W1_338,Peripheral Domain Access Control Word 1" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x10 "PDAC_W0_339,Peripheral Domain Access Control Word 0" bitfld.long 0x10 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x10 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x10 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x10 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x14 "PDAC_W1_339,Peripheral Domain Access Control Word 1" bitfld.long 0x14 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x14 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x18 "PDAC_W0_340,Peripheral Domain Access Control Word 0" bitfld.long 0x18 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x18 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x18 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x1C "PDAC_W1_340,Peripheral Domain Access Control Word 1" bitfld.long 0x1C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x1C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x20 "PDAC_W0_341,Peripheral Domain Access Control Word 0" bitfld.long 0x20 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x20 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x20 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x20 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x24 "PDAC_W1_341,Peripheral Domain Access Control Word 1" bitfld.long 0x24 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x24 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x28 "PDAC_W0_342,Peripheral Domain Access Control Word 0" bitfld.long 0x28 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x28 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x28 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x28 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x28 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x2C "PDAC_W1_342,Peripheral Domain Access Control Word 1" bitfld.long 0x2C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x2C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x30 "PDAC_W0_343,Peripheral Domain Access Control Word 0" bitfld.long 0x30 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x30 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x30 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x30 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x30 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x34 "PDAC_W1_343,Peripheral Domain Access Control Word 1" bitfld.long 0x34 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x34 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x38 "PDAC_W0_344,Peripheral Domain Access Control Word 0" bitfld.long 0x38 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x38 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x38 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x38 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x38 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x3C "PDAC_W1_344,Peripheral Domain Access Control Word 1" bitfld.long 0x3C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x3C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x40 "PDAC_W0_345,Peripheral Domain Access Control Word 0" bitfld.long 0x40 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x40 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x40 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x40 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x40 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x44 "PDAC_W1_345,Peripheral Domain Access Control Word 1" bitfld.long 0x44 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x44 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x48 "PDAC_W0_346,Peripheral Domain Access Control Word 0" bitfld.long 0x48 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x48 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x48 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x48 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x48 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x4C "PDAC_W1_346,Peripheral Domain Access Control Word 1" bitfld.long 0x4C 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x4C 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" line.long 0x50 "PDAC_W0_347,Peripheral Domain Access Control Word 0" bitfld.long 0x50 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x50 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x50 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x50 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x50 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0x54 "PDAC_W1_347,Peripheral Domain Access Control Word 1" bitfld.long 0x54 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0x54 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)" group.long 0x2000++0xF line.long 0x0 "MRGD_W0_0,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_0,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_0,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_0,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2020++0xF line.long 0x0 "MRGD_W0_1,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_1,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_1,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_1,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2040++0xF line.long 0x0 "MRGD_W0_2,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_2,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_2,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_2,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2060++0xF line.long 0x0 "MRGD_W0_3,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_3,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_3,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_3,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2080++0xF line.long 0x0 "MRGD_W0_4,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_4,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_4,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_4,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x20A0++0xF line.long 0x0 "MRGD_W0_5,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_5,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_5,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_5,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x20C0++0xF line.long 0x0 "MRGD_W0_6,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_6,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_6,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_6,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x20E0++0xF line.long 0x0 "MRGD_W0_7,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_7,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_7,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_7,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2100++0xF line.long 0x0 "MRGD_W0_8,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_8,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_8,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_8,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2120++0xF line.long 0x0 "MRGD_W0_9,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_9,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_9,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_9,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2140++0xF line.long 0x0 "MRGD_W0_10,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_10,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_10,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_10,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2160++0xF line.long 0x0 "MRGD_W0_11,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_11,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_11,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_11,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2180++0xF line.long 0x0 "MRGD_W0_12,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_12,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_12,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_12,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x21A0++0xF line.long 0x0 "MRGD_W0_13,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_13,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_13,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_13,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x21C0++0xF line.long 0x0 "MRGD_W0_14,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_14,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_14,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_14,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x21E0++0xF line.long 0x0 "MRGD_W0_15,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_15,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_15,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_15,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2200++0xF line.long 0x0 "MRGD_W0_16,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_16,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_16,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_16,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2220++0xF line.long 0x0 "MRGD_W0_17,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_17,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_17,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_17,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2240++0xF line.long 0x0 "MRGD_W0_18,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_18,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_18,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_18,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2260++0xF line.long 0x0 "MRGD_W0_19,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_19,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_19,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_19,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2280++0xF line.long 0x0 "MRGD_W0_20,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_20,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_20,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_20,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x22A0++0xF line.long 0x0 "MRGD_W0_21,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_21,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_21,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_21,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x22C0++0xF line.long 0x0 "MRGD_W0_22,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_22,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_22,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_22,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x22E0++0xF line.long 0x0 "MRGD_W0_23,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_23,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_23,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_23,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2300++0xF line.long 0x0 "MRGD_W0_24,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_24,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_24,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_24,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2320++0xF line.long 0x0 "MRGD_W0_25,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_25,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_25,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_25,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2340++0xF line.long 0x0 "MRGD_W0_26,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_26,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_26,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_26,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2360++0xF line.long 0x0 "MRGD_W0_27,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_27,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_27,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_27,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2380++0xF line.long 0x0 "MRGD_W0_28,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_28,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_28,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_28,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x23A0++0xF line.long 0x0 "MRGD_W0_29,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_29,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_29,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_29,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x23C0++0xF line.long 0x0 "MRGD_W0_30,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_30,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_30,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_30,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x23E0++0xF line.long 0x0 "MRGD_W0_31,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_31,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_31,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_31,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2400++0xF line.long 0x0 "MRGD_W0_32,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_32,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_32,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_32,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2420++0xF line.long 0x0 "MRGD_W0_33,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_33,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_33,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_33,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2440++0xF line.long 0x0 "MRGD_W0_34,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_34,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_34,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_34,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2460++0xF line.long 0x0 "MRGD_W0_35,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_35,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_35,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_35,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2600++0xF line.long 0x0 "MRGD_W0_48,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_48,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_48,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_48,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2620++0xF line.long 0x0 "MRGD_W0_49,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_49,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_49,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_49,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2640++0xF line.long 0x0 "MRGD_W0_50,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_50,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_50,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_50,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2660++0xF line.long 0x0 "MRGD_W0_51,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_51,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_51,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_51,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2680++0xF line.long 0x0 "MRGD_W0_52,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_52,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_52,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_52,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x26A0++0xF line.long 0x0 "MRGD_W0_53,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_53,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_53,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_53,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x26C0++0xF line.long 0x0 "MRGD_W0_54,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_54,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_54,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_54,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x26E0++0xF line.long 0x0 "MRGD_W0_55,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_55,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_55,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_55,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2700++0xF line.long 0x0 "MRGD_W0_56,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_56,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_56,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_56,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2720++0xF line.long 0x0 "MRGD_W0_57,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_57,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_57,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_57,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2740++0xF line.long 0x0 "MRGD_W0_58,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_58,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_58,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_58,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2760++0xF line.long 0x0 "MRGD_W0_59,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_59,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_59,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_59,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2780++0xF line.long 0x0 "MRGD_W0_60,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_60,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_60,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_60,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x27A0++0xF line.long 0x0 "MRGD_W0_61,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_61,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_61,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_61,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x27C0++0xF line.long 0x0 "MRGD_W0_62,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_62,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_62,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_62,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x27E0++0xF line.long 0x0 "MRGD_W0_63,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_63,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_63,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_63,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2800++0xF line.long 0x0 "MRGD_W0_64,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_64,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_64,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_64,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2820++0xF line.long 0x0 "MRGD_W0_65,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_65,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_65,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_65,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2840++0xF line.long 0x0 "MRGD_W0_66,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_66,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_66,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_66,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" group.long 0x2860++0xF line.long 0x0 "MRGD_W0_67,Memory Region Descriptor Word 0" hexmask.long 0x0 5.--31. 1. "SRTADDR,Start Address" line.long 0x4 "MRGD_W1_67,Memory Region Descriptor Word 1" hexmask.long 0x4 5.--31. 1. "ENDADDR,End Address" line.long 0x8 "MRGD_W2_67,Memory Region Descriptor Word 2" bitfld.long 0x8 30. "SE,Semaphore Enable" "0: Disables,1: Enables" hexmask.long.byte 0x8 24.--27. 1. "SNUM,Semaphore Number" newline bitfld.long 0x8 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7" line.long 0xC "MRGD_W3_67,Memory Region Descriptor Word 3" bitfld.long 0xC 31. "VLD,Valid" "0: Invalid,1: Valid" bitfld.long 0xC 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)" tree.end AUTOINDENT.OFF